From patchwork Fri Feb 7 15:53:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lei Wei X-Patchwork-Id: 863341 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 931C223C8AF; Fri, 7 Feb 2025 15:58:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738943937; cv=none; b=IcRtaUhLkLMnX6B75siYjHYOqwjef1xXjAA0Z6/evmj+zMhni4dOrlgUBnTl79idXCldpsSnYVoTcIAtOdQei8zTdsF/eceAJ7uENrfqedaBQyJgaiiiLHq9gvXWOArc5QoqHCqVXrYh8Y5gEnHM5AqA70jRA5Sh1HXg1l7q3NE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738943937; c=relaxed/simple; bh=ojXkiotBHQ9rAaYBnRCdE1xocadVCqvahUxximuBPGM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=ImnVqxmyIguTbTjXH9JcBJIm7rxH0E3Qvj6LAxy6ykcnTmM4v/dgI5VE12g/I4e7JIekctf3k+1QU8L+MBfWQ++y8PYbWpqtTGDDOdwAu3c9MvTZWFPX++bpUbkE+VjfKBzA6FbTlCcobd5n60BIp5hOvUBY+ODlb7OzaRVNxsQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=nbUtE1WP; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="nbUtE1WP" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 517Fri5M002543; Fri, 7 Feb 2025 15:58:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= TuHRJ7541Wr5H9B90tSRVYLZAZ1RhIehA4GQ1nrsq8U=; b=nbUtE1WP+EA8448+ j8gr6H4o1OE90GmY3mQ+KvUEN9ILkDo+cVnHQqy/FsZtSOTdcUw/ha8z2NFNR68a 5cDGZWbyF0BpGKS3u5bAvmot3bIJQARWRhqMRG/uY5X5nRTr9rQMSQbTZNi5k+xm R0N3WhgTSLm68woL1r+iN5v1DzmOqMDGpRTT0wPs2R7lHYGARuyevuxqE80gc44H +cSlB7KRc6exFJcC59y3aKVzvFdpM8AyvIGD7vicnRVlQNmCzXYbEsqwFUMbTgmC Nj5/wI47yBxHRQr7AJyMUd072iIjEheZ4bS6AXWAk9vKd0CkyQHMpZxG1VdMlI5A JBF1uw== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44nn7fr0bq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Feb 2025 15:58:40 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 517FwdUR018844 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Feb 2025 15:58:39 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 7 Feb 2025 07:58:33 -0800 From: Lei Wei Date: Fri, 7 Feb 2025 23:53:12 +0800 Subject: [PATCH net-next v5 1/5] dt-bindings: net: pcs: Add Ethernet PCS for Qualcomm IPQ9574 SoC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250207-ipq_pcs_6-14_rc1-v5-1-be2ebec32921@quicinc.com> References: <20250207-ipq_pcs_6-14_rc1-v5-0-be2ebec32921@quicinc.com> In-Reply-To: <20250207-ipq_pcs_6-14_rc1-v5-0-be2ebec32921@quicinc.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Heiner Kallweit , Russell King CC: , , , , , , , , , , , , , , Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738943908; l=8737; i=quic_leiwei@quicinc.com; s=20240829; h=from:subject:message-id; bh=ojXkiotBHQ9rAaYBnRCdE1xocadVCqvahUxximuBPGM=; b=kx8LhlQjAaD4TIDNjRUMHZU/fgI0ZFDoYjHO31+CYz5mZ0PXpuQlzmBcs5kheccFFn3f/QYgz dENHMmTydFpDFVrIDhYk/UVUMUyvIKejwiAdWcRD9Y+ZtWKIScGJaWl X-Developer-Key: i=quic_leiwei@quicinc.com; a=ed25519; pk=uFXBHtxtDjtIrTKpDEZlMLSn1i/sonZepYO8yioKACM= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 60uPnGKKjZ0fZHVmO_p093Bo4Dwd2DvE X-Proofpoint-ORIG-GUID: 60uPnGKKjZ0fZHVmO_p093Bo4Dwd2DvE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-07_07,2025-02-07_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 spamscore=0 priorityscore=1501 bulkscore=0 mlxscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 impostorscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502070121 The 'UNIPHY' PCS block in the IPQ9574 SoC includes PCS and SerDes functions. It supports different interface modes to enable Ethernet MAC connections to different types of external PHYs/switch. It includes PCS functions for 1Gbps and 2.5Gbps interface modes and XPCS functions for 10Gbps interface modes. There are three UNIPHY (PCS) instances in IPQ9574 SoC which provide PCS/XPCS functions to the six Ethernet ports. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Lei Wei --- .../bindings/net/pcs/qcom,ipq9574-pcs.yaml | 190 +++++++++++++++++++++ include/dt-bindings/net/qcom,ipq9574-pcs.h | 15 ++ 2 files changed, 205 insertions(+) diff --git a/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml b/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml new file mode 100644 index 000000000000..74573c28d6fe --- /dev/null +++ b/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pcs/qcom,ipq9574-pcs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ethernet PCS for Qualcomm IPQ9574 SoC + +maintainers: + - Lei Wei + +description: + The UNIPHY hardware blocks in the Qualcomm IPQ SoC include PCS and SerDes + functions. They enable connectivity between the Ethernet MAC inside the + PPE (packet processing engine) and external Ethernet PHY/switch. There are + three UNIPHY instances in IPQ9574 SoC which provide PCS functions to the + six Ethernet ports. + + For SGMII (1Gbps PHY) or 2500BASE-X (2.5Gbps PHY) interface modes, the PCS + function is enabled by using the PCS block inside UNIPHY. For USXGMII (10Gbps + PHY), the XPCS block in UNIPHY is used. + + The SerDes provides 125M (1Gbps mode) or 312.5M (2.5Gbps and 10Gbps modes) + RX and TX clocks to the NSSCC (Networking Sub System Clock Controller). The + NSSCC divides these clocks and generates the MII RX and TX clocks to each + of the MII interfaces between the PCS and MAC, as per the link speeds and + interface modes. + + Different IPQ SoC may support different number of UNIPHYs (PCSes) since the + number of ports and their capabilities can be different between these SoCs + + Below diagram depicts the UNIPHY (PCS) connections for an IPQ9574 SoC based + board. In this example, the PCS0 has four GMIIs/XGMIIs, which can connect + with four MACs to support QSGMII (4 x 1Gbps) or 10G_QXGMII (4 x 2.5Gbps) + interface modes. + + - +-------+ +---------+ +-------------------------+ + +---------+CMN PLL| | GCC | | NSSCC (Divider) | + | +----+--+ +----+----+ +--+-------+--------------+ + | | | ^ | + | 31.25M | SYS/AHB|clk RX/TX|clk +------------+ + | ref clk| | | | | + | | v | MII RX|TX clk MAC| RX/TX clk + |25/50M +--+---------+----------+-------+---+ +-+---------+ + |ref clk | | +----------------+ | | | | PPE | + v | | | UNIPHY0 V | | V | + +-------+ | v | +-----------+ (X)GMII| | | + | | | +---+---+ | |--------|------|-- MAC0 | + | | | | | | | (X)GMII| | | + | Quad | | |SerDes | | PCS/XPCS |--------|------|-- MAC1 | + | +<----+ | | | | (X)GMII| | | + |(X)GPHY| | | | | |--------|------|-- MAC2 | + | | | | | | | (X)GMII| | | + | | | +-------+ | |--------|------|-- MAC3 | + +-------+ | | | | | | + | +-----------+ | | | + +-----------------------------------+ | | + +--+---------+----------+-------+---+ | | + +-------+ | UNIPHY1 | | | + | | | +-----------+ | | | + |(X)GPHY| | +-------+ | | (X)GMII| | | + | +<----+ |SerDes | | PCS/XPCS |--------|------|- MAC4 | + | | | | | | | | | | + +-------+ | +-------+ | | | | | + | +-----------+ | | | + +-----------------------------------+ | | + +--+---------+----------+-------+---+ | | + +-------+ | UNIPHY2 | | | + | | | +-----------+ | | | + |(X)GPHY| | +-------+ | | (X)GMII| | | + | +<----+ |SerDes | | PCS/XPCS |--------|------|- MAC5 | + | | | | | | | | | | + +-------+ | +-------+ | | | | | + | +-----------+ | | | + +-----------------------------------+ +-----------+ + +properties: + compatible: + enum: + - qcom,ipq9574-pcs + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + clocks: + items: + - description: System clock + - description: AHB clock needed for register interface access + + clock-names: + items: + - const: sys + - const: ahb + + '#clock-cells': + const: 1 + description: See include/dt-bindings/net/qcom,ipq9574-pcs.h for constants + +patternProperties: + '^pcs-mii@[0-4]$': + type: object + description: PCS MII interface. + + properties: + reg: + minimum: 0 + maximum: 4 + description: MII index + + clocks: + items: + - description: PCS MII RX clock + - description: PCS MII TX clock + + clock-names: + items: + - const: rx + - const: tx + + required: + - reg + - clocks + - clock-names + + additionalProperties: false + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + ethernet-pcs@7a00000 { + compatible = "qcom,ipq9574-pcs"; + reg = <0x7a00000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_UNIPHY0_SYS_CLK>, + <&gcc GCC_UNIPHY0_AHB_CLK>; + clock-names = "sys", + "ahb"; + #clock-cells = <1>; + + pcs-mii@0 { + reg = <0>; + clocks = <&nsscc 116>, + <&nsscc 117>; + clock-names = "rx", + "tx"; + }; + + pcs-mii@1 { + reg = <1>; + clocks = <&nsscc 118>, + <&nsscc 119>; + clock-names = "rx", + "tx"; + }; + + pcs-mii@2 { + reg = <2>; + clocks = <&nsscc 120>, + <&nsscc 121>; + clock-names = "rx", + "tx"; + }; + + pcs-mii@3 { + reg = <3>; + clocks = <&nsscc 122>, + <&nsscc 123>; + clock-names = "rx", + "tx"; + }; + }; diff --git a/include/dt-bindings/net/qcom,ipq9574-pcs.h b/include/dt-bindings/net/qcom,ipq9574-pcs.h new file mode 100644 index 000000000000..96bd036aaa70 --- /dev/null +++ b/include/dt-bindings/net/qcom,ipq9574-pcs.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Device Tree constants for the Qualcomm IPQ9574 PCS + */ + +#ifndef _DT_BINDINGS_PCS_QCOM_IPQ9574_H +#define _DT_BINDINGS_PCS_QCOM_IPQ9574_H + +/* The RX and TX clocks which are provided from the SerDes to NSSCC. */ +#define PCS_RX_CLK 0 +#define PCS_TX_CLK 1 + +#endif /* _DT_BINDINGS_PCS_QCOM_IPQ9574_H */ From patchwork Fri Feb 7 15:53:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lei Wei X-Patchwork-Id: 863340 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41774225386; Fri, 7 Feb 2025 15:58:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738943941; cv=none; b=UNHc00zV1D7rGn7bNq/0AlJcdjFvw4sJeMkQ+2KfB3kvrlQPYosmyCXn563oDnQpWWn4wFb3tSamTVfLRpE6ZdkRimlNBgEM8L2tbVgILyrpzp0mZf4Yh9pvYMYzVKwrDl7UNkvww1xo1l9UJ6XgvbhGZVMZ3Jkg/HoVvHpBZRw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738943941; c=relaxed/simple; bh=yh/EFtq4AEREolC1RTUq+ZIPrwr6SoOQEDByc4CktBI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=lKssD4GPD0jZ9555kBhWO4PKqd74/YZsMwzenJFHkAi4DjVZ3gXRgcUdP1momPxMq/50dnuNi0S7dLSaFaobtZmFunmngs7Budi+PfmzvwfdoOUhpeENKlxLB16RZlQ+PivHlM/z7oXlG4N0+raUifzh7IxV9xCp6lKmcqcfRmo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=N39jeNcA; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="N39jeNcA" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 517FNTL6007775; Fri, 7 Feb 2025 15:58:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= kgdDMWAsrDNaPNt4LS2FlIrvOkc8XUW0vXtsWIgYbko=; b=N39jeNcAJaiOl5Ec a0SRNjBMJB0zoD24P+zBefCQOgqLhIqEQJPx5YS/pfDJHe5+RBszpRBfLdD95QhW SlBIaK+OmiseFQTEi72EjJ6X2ujkCDLgTzV1W6812UPCkT2x30YruRCD2tgBFOSV 6f3COPWJ8ixC5jGQRJK0m9YozWoQ+4yrbWzDJ8L54LkpldgoaaVk9kA4mcBvTZ8W vJkSf9m2AZ/rHL2CPde5FqH0esHcxT+dQzD+nyoDduZGoh9U9UtPmP1HC/+Ds8cy CgRn+TgXhZAB3t3vmFGxMXBOY9wfo8zZC/Gn5gH5lVghz1dNZcIX5esdnshoNVcp PwTYkg== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44nmsbg3nn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Feb 2025 15:58:45 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 517FwiSl005309 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Feb 2025 15:58:44 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 7 Feb 2025 07:58:39 -0800 From: Lei Wei Date: Fri, 7 Feb 2025 23:53:13 +0800 Subject: [PATCH net-next v5 2/5] net: pcs: Add PCS driver for Qualcomm IPQ9574 SoC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250207-ipq_pcs_6-14_rc1-v5-2-be2ebec32921@quicinc.com> References: <20250207-ipq_pcs_6-14_rc1-v5-0-be2ebec32921@quicinc.com> In-Reply-To: <20250207-ipq_pcs_6-14_rc1-v5-0-be2ebec32921@quicinc.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Heiner Kallweit , Russell King CC: , , , , , , , , , , , , , X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738943908; l=9186; i=quic_leiwei@quicinc.com; s=20240829; h=from:subject:message-id; bh=yh/EFtq4AEREolC1RTUq+ZIPrwr6SoOQEDByc4CktBI=; b=LvHvpt4BBiKqLTd3q7m5mhP6hS5A6/VWboiIFyOCf9VMlLUndhWD4L+YJ6XQ3uMZzDL6+Hlyz qOhMpDZx1feAJzUdcAhWvLeh0flaQUKzSx1r5XoOasEhTXh0lUbmKO4 X-Developer-Key: i=quic_leiwei@quicinc.com; a=ed25519; pk=uFXBHtxtDjtIrTKpDEZlMLSn1i/sonZepYO8yioKACM= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: whBtx7Z1nB0QEbp_hrXQ-zC31J1lm-iK X-Proofpoint-GUID: whBtx7Z1nB0QEbp_hrXQ-zC31J1lm-iK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-07_07,2025-02-07_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 phishscore=0 mlxlogscore=999 malwarescore=0 spamscore=0 mlxscore=0 adultscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502070121 The 'UNIPHY' PCS hardware block in Qualcomm's IPQ SoC supports different interface modes to enable Ethernet MAC connections for different types of external PHYs/switch. Each UNIPHY block includes a SerDes and PCS/XPCS blocks, and can operate in either PCS or XPCS modes. It supports 1Gbps and 2.5Gbps interface modes (Ex: SGMII) using the PCS, and 10Gbps interface modes (Ex: USXGMII) using the XPCS. There are three UNIPHY (PCS) instances in IPQ9574 SoC which support the six Ethernet ports in the SoC. This patch adds support for the platform driver, probe and clock registrations for the PCS driver. The platform driver creates an 'ipq_pcs' instance for each of the UNIPHY used on the given board. Signed-off-by: Lei Wei --- drivers/net/pcs/Kconfig | 9 ++ drivers/net/pcs/Makefile | 1 + drivers/net/pcs/pcs-qcom-ipq9574.c | 245 +++++++++++++++++++++++++++++++++++++ 3 files changed, 255 insertions(+) diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig index f6aa437473de..f1f5669f501a 100644 --- a/drivers/net/pcs/Kconfig +++ b/drivers/net/pcs/Kconfig @@ -25,6 +25,15 @@ config PCS_MTK_LYNXI This module provides helpers to phylink for managing the LynxI PCS which is part of MediaTek's SoC and Ethernet switch ICs. +config PCS_QCOM_IPQ9574 + tristate "Qualcomm IPQ9574 PCS" + depends on OF && (ARCH_QCOM || COMPILE_TEST) + depends on HAS_IOMEM && COMMON_CLK + help + This module provides driver for UNIPHY PCS available on Qualcomm + IPQ9574 SoC. The UNIPHY PCS supports both PCS and XPCS functions + to support different interface modes for MAC to PHY connections. + config PCS_RZN1_MIIC tristate "Renesas RZ/N1 MII converter" depends on OF && (ARCH_RZN1 || COMPILE_TEST) diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile index 4f7920618b90..2fa3faf8a5db 100644 --- a/drivers/net/pcs/Makefile +++ b/drivers/net/pcs/Makefile @@ -7,4 +7,5 @@ pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \ obj-$(CONFIG_PCS_XPCS) += pcs_xpcs.o obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o obj-$(CONFIG_PCS_MTK_LYNXI) += pcs-mtk-lynxi.o +obj-$(CONFIG_PCS_QCOM_IPQ9574) += pcs-qcom-ipq9574.o obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o diff --git a/drivers/net/pcs/pcs-qcom-ipq9574.c b/drivers/net/pcs/pcs-qcom-ipq9574.c new file mode 100644 index 000000000000..ea90c1902b61 --- /dev/null +++ b/drivers/net/pcs/pcs-qcom-ipq9574.c @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define XPCS_INDIRECT_ADDR 0x8000 +#define XPCS_INDIRECT_AHB_ADDR 0x83fc +#define XPCS_INDIRECT_ADDR_H GENMASK(20, 8) +#define XPCS_INDIRECT_ADDR_L GENMASK(7, 0) +#define XPCS_INDIRECT_DATA_ADDR(reg) (FIELD_PREP(GENMASK(15, 10), 0x20) | \ + FIELD_PREP(GENMASK(9, 2), \ + FIELD_GET(XPCS_INDIRECT_ADDR_L, reg))) + +/* PCS private data */ +struct ipq_pcs { + struct device *dev; + void __iomem *base; + struct regmap *regmap; + phy_interface_t interface; + + /* RX clock supplied to NSSCC */ + struct clk_hw rx_hw; + /* TX clock supplied to NSSCC */ + struct clk_hw tx_hw; +}; + +static unsigned long ipq_pcs_clk_rate_get(struct ipq_pcs *qpcs) +{ + switch (qpcs->interface) { + case PHY_INTERFACE_MODE_USXGMII: + return 312500000; + default: + return 125000000; + } +} + +/* Return clock rate for the RX clock supplied to NSSCC + * as per the interface mode. + */ +static unsigned long ipq_pcs_rx_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ipq_pcs *qpcs = container_of(hw, struct ipq_pcs, rx_hw); + + return ipq_pcs_clk_rate_get(qpcs); +} + +/* Return clock rate for the TX clock supplied to NSSCC + * as per the interface mode. + */ +static unsigned long ipq_pcs_tx_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ipq_pcs *qpcs = container_of(hw, struct ipq_pcs, tx_hw); + + return ipq_pcs_clk_rate_get(qpcs); +} + +static int ipq_pcs_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + switch (req->rate) { + case 125000000: + case 312500000: + return 0; + default: + return -EINVAL; + } +} + +/* Clock ops for the RX clock supplied to NSSCC */ +static const struct clk_ops ipq_pcs_rx_clk_ops = { + .determine_rate = ipq_pcs_clk_determine_rate, + .recalc_rate = ipq_pcs_rx_clk_recalc_rate, +}; + +/* Clock ops for the TX clock supplied to NSSCC */ +static const struct clk_ops ipq_pcs_tx_clk_ops = { + .determine_rate = ipq_pcs_clk_determine_rate, + .recalc_rate = ipq_pcs_tx_clk_recalc_rate, +}; + +static struct clk_hw *ipq_pcs_clk_hw_get(struct of_phandle_args *clkspec, + void *data) +{ + struct ipq_pcs *qpcs = data; + + switch (clkspec->args[0]) { + case PCS_RX_CLK: + return &qpcs->rx_hw; + case PCS_TX_CLK: + return &qpcs->tx_hw; + } + + return ERR_PTR(-EINVAL); +} + +/* Register the RX and TX clock which are output from SerDes to + * the NSSCC. The NSSCC driver assigns the RX and TX clock as + * parent, divides them to generate the MII RX and TX clock to + * each MII interface of the PCS as per the link speeds and + * interface modes. + */ +static int ipq_pcs_clk_register(struct ipq_pcs *qpcs) +{ + struct clk_init_data init = { }; + int ret; + + init.ops = &ipq_pcs_rx_clk_ops; + init.name = devm_kasprintf(qpcs->dev, GFP_KERNEL, "%s::rx_clk", + dev_name(qpcs->dev)); + if (!init.name) + return -ENOMEM; + + qpcs->rx_hw.init = &init; + ret = devm_clk_hw_register(qpcs->dev, &qpcs->rx_hw); + if (ret) + return ret; + + init.ops = &ipq_pcs_tx_clk_ops; + init.name = devm_kasprintf(qpcs->dev, GFP_KERNEL, "%s::tx_clk", + dev_name(qpcs->dev)); + if (!init.name) + return -ENOMEM; + + qpcs->tx_hw.init = &init; + ret = devm_clk_hw_register(qpcs->dev, &qpcs->tx_hw); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(qpcs->dev, ipq_pcs_clk_hw_get, qpcs); +} + +static int ipq_pcs_regmap_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct ipq_pcs *qpcs = context; + + /* PCS uses direct AHB access while XPCS uses indirect AHB access */ + if (reg >= XPCS_INDIRECT_ADDR) { + writel(FIELD_GET(XPCS_INDIRECT_ADDR_H, reg), + qpcs->base + XPCS_INDIRECT_AHB_ADDR); + *val = readl(qpcs->base + XPCS_INDIRECT_DATA_ADDR(reg)); + } else { + *val = readl(qpcs->base + reg); + } + + return 0; +} + +static int ipq_pcs_regmap_write(void *context, unsigned int reg, + unsigned int val) +{ + struct ipq_pcs *qpcs = context; + + /* PCS uses direct AHB access while XPCS uses indirect AHB access */ + if (reg >= XPCS_INDIRECT_ADDR) { + writel(FIELD_GET(XPCS_INDIRECT_ADDR_H, reg), + qpcs->base + XPCS_INDIRECT_AHB_ADDR); + writel(val, qpcs->base + XPCS_INDIRECT_DATA_ADDR(reg)); + } else { + writel(val, qpcs->base + reg); + } + + return 0; +} + +static const struct regmap_config ipq_pcs_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_read = ipq_pcs_regmap_read, + .reg_write = ipq_pcs_regmap_write, + .fast_io = true, +}; + +static int ipq9574_pcs_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ipq_pcs *qpcs; + struct clk *clk; + int ret; + + qpcs = devm_kzalloc(dev, sizeof(*qpcs), GFP_KERNEL); + if (!qpcs) + return -ENOMEM; + + qpcs->dev = dev; + + qpcs->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(qpcs->base)) + return dev_err_probe(dev, PTR_ERR(qpcs->base), + "Failed to ioremap resource\n"); + + qpcs->regmap = devm_regmap_init(dev, NULL, qpcs, &ipq_pcs_regmap_cfg); + if (IS_ERR(qpcs->regmap)) + return dev_err_probe(dev, PTR_ERR(qpcs->regmap), + "Failed to allocate register map\n"); + + clk = devm_clk_get_enabled(dev, "sys"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to enable SYS clock\n"); + + clk = devm_clk_get_enabled(dev, "ahb"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to enable AHB clock\n"); + + ret = ipq_pcs_clk_register(qpcs); + if (ret) + return ret; + + platform_set_drvdata(pdev, qpcs); + + return 0; +} + +static const struct of_device_id ipq9574_pcs_of_mtable[] = { + { .compatible = "qcom,ipq9574-pcs" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, ipq9574_pcs_of_mtable); + +static struct platform_driver ipq9574_pcs_driver = { + .driver = { + .name = "ipq9574_pcs", + .suppress_bind_attrs = true, + .of_match_table = ipq9574_pcs_of_mtable, + }, + .probe = ipq9574_pcs_probe, +}; +module_platform_driver(ipq9574_pcs_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Qualcomm IPQ9574 PCS driver"); +MODULE_AUTHOR("Lei Wei "); From patchwork Fri Feb 7 15:53:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lei Wei X-Patchwork-Id: 863048 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD81023F283; Fri, 7 Feb 2025 15:59:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; 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Fri, 07 Feb 2025 15:58:50 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 517Fwnlh007271 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Feb 2025 15:58:49 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 7 Feb 2025 07:58:44 -0800 From: Lei Wei Date: Fri, 7 Feb 2025 23:53:14 +0800 Subject: [PATCH net-next v5 3/5] net: pcs: qcom-ipq9574: Add PCS instantiation and phylink operations Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250207-ipq_pcs_6-14_rc1-v5-3-be2ebec32921@quicinc.com> References: <20250207-ipq_pcs_6-14_rc1-v5-0-be2ebec32921@quicinc.com> In-Reply-To: <20250207-ipq_pcs_6-14_rc1-v5-0-be2ebec32921@quicinc.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Heiner Kallweit , Russell King CC: , , , , , , , , , , , , , X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738943908; l=14874; i=quic_leiwei@quicinc.com; s=20240829; h=from:subject:message-id; bh=mmjdpeFVaChf9LUz7wm75RSIZpBASvOmbpdNU55SMvM=; b=GsCbxc++uB40y4Hhv3gBHPN9xCFdyMHbIb4YUSpFS/klp/Q7ewhLJ/FCD30Ee/M9ycCi3gVEb 3lxWeuUVWmfCxQNTTCN8LK7weFTp1yPpjIsyRSObAlouKIjxU2y9+TY X-Developer-Key: i=quic_leiwei@quicinc.com; a=ed25519; pk=uFXBHtxtDjtIrTKpDEZlMLSn1i/sonZepYO8yioKACM= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: hz5KVNi0KqeqIk73WslTUszlz2pkoys1 X-Proofpoint-GUID: hz5KVNi0KqeqIk73WslTUszlz2pkoys1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-07_07,2025-02-07_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 bulkscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 suspectscore=0 clxscore=1015 mlxlogscore=999 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502070121 This patch adds the following PCS functionality for the PCS driver for IPQ9574 SoC: a.) Parses PCS MII DT nodes and instantiate each MII PCS instance. b.) Exports PCS instance get and put APIs. The network driver calls the PCS get API to get and associate the PCS instance with the port MAC. c.) PCS phylink operations for SGMII/QSGMII interface modes. Signed-off-by: Lei Wei --- drivers/net/pcs/pcs-qcom-ipq9574.c | 469 +++++++++++++++++++++++++++++++++++ include/linux/pcs/pcs-qcom-ipq9574.h | 15 ++ 2 files changed, 484 insertions(+) diff --git a/drivers/net/pcs/pcs-qcom-ipq9574.c b/drivers/net/pcs/pcs-qcom-ipq9574.c index ea90c1902b61..2bb55814d2fb 100644 --- a/drivers/net/pcs/pcs-qcom-ipq9574.c +++ b/drivers/net/pcs/pcs-qcom-ipq9574.c @@ -6,12 +6,46 @@ #include #include #include +#include +#include +#include #include +#include #include #include #include +/* Maximum number of MIIs per PCS instance. There are 5 MIIs for PSGMII. */ +#define PCS_MAX_MII_NRS 5 + +#define PCS_CALIBRATION 0x1e0 +#define PCS_CALIBRATION_DONE BIT(7) + +#define PCS_MODE_CTRL 0x46c +#define PCS_MODE_SEL_MASK GENMASK(12, 8) +#define PCS_MODE_SGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x4) +#define PCS_MODE_QSGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x1) + +#define PCS_MII_CTRL(x) (0x480 + 0x18 * (x)) +#define PCS_MII_ADPT_RESET BIT(11) +#define PCS_MII_FORCE_MODE BIT(3) +#define PCS_MII_SPEED_MASK GENMASK(2, 1) +#define PCS_MII_SPEED_1000 FIELD_PREP(PCS_MII_SPEED_MASK, 0x2) +#define PCS_MII_SPEED_100 FIELD_PREP(PCS_MII_SPEED_MASK, 0x1) +#define PCS_MII_SPEED_10 FIELD_PREP(PCS_MII_SPEED_MASK, 0x0) + +#define PCS_MII_STS(x) (0x488 + 0x18 * (x)) +#define PCS_MII_LINK_STS BIT(7) +#define PCS_MII_STS_DUPLEX_FULL BIT(6) +#define PCS_MII_STS_SPEED_MASK GENMASK(5, 4) +#define PCS_MII_STS_SPEED_10 0 +#define PCS_MII_STS_SPEED_100 1 +#define PCS_MII_STS_SPEED_1000 2 + +#define PCS_PLL_RESET 0x780 +#define PCS_ANA_SW_RESET BIT(6) + #define XPCS_INDIRECT_ADDR 0x8000 #define XPCS_INDIRECT_AHB_ADDR 0x83fc #define XPCS_INDIRECT_ADDR_H GENMASK(20, 8) @@ -20,6 +54,18 @@ FIELD_PREP(GENMASK(9, 2), \ FIELD_GET(XPCS_INDIRECT_ADDR_L, reg))) +/* Per PCS MII private data */ +struct ipq_pcs_mii { + struct ipq_pcs *qpcs; + struct phylink_pcs pcs; + int index; + + /* RX clock from NSSCC to PCS MII */ + struct clk *rx_clk; + /* TX clock from NSSCC to PCS MII */ + struct clk *tx_clk; +}; + /* PCS private data */ struct ipq_pcs { struct device *dev; @@ -31,8 +77,359 @@ struct ipq_pcs { struct clk_hw rx_hw; /* TX clock supplied to NSSCC */ struct clk_hw tx_hw; + + struct ipq_pcs_mii *qpcs_mii[PCS_MAX_MII_NRS]; }; +#define phylink_pcs_to_qpcs_mii(_pcs) \ + container_of(_pcs, struct ipq_pcs_mii, pcs) + +static void ipq_pcs_get_state_sgmii(struct ipq_pcs *qpcs, + int index, + struct phylink_link_state *state) +{ + unsigned int val; + int ret; + + ret = regmap_read(qpcs->regmap, PCS_MII_STS(index), &val); + if (ret) { + state->link = 0; + return; + } + + state->link = !!(val & PCS_MII_LINK_STS); + + if (!state->link) + return; + + switch (FIELD_GET(PCS_MII_STS_SPEED_MASK, val)) { + case PCS_MII_STS_SPEED_1000: + state->speed = SPEED_1000; + break; + case PCS_MII_STS_SPEED_100: + state->speed = SPEED_100; + break; + case PCS_MII_STS_SPEED_10: + state->speed = SPEED_10; + break; + default: + state->link = false; + return; + } + + if (val & PCS_MII_STS_DUPLEX_FULL) + state->duplex = DUPLEX_FULL; + else + state->duplex = DUPLEX_HALF; +} + +static int ipq_pcs_config_mode(struct ipq_pcs *qpcs, + phy_interface_t interface) +{ + unsigned int val; + int ret; + + /* Configure PCS interface mode */ + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + val = PCS_MODE_SGMII; + break; + case PHY_INTERFACE_MODE_QSGMII: + val = PCS_MODE_QSGMII; + break; + default: + return -EOPNOTSUPP; + } + + ret = regmap_update_bits(qpcs->regmap, PCS_MODE_CTRL, + PCS_MODE_SEL_MASK, val); + if (ret) + return ret; + + /* PCS PLL reset */ + ret = regmap_clear_bits(qpcs->regmap, PCS_PLL_RESET, PCS_ANA_SW_RESET); + if (ret) + return ret; + + fsleep(1000); + ret = regmap_set_bits(qpcs->regmap, PCS_PLL_RESET, PCS_ANA_SW_RESET); + if (ret) + return ret; + + /* Wait for calibration completion */ + ret = regmap_read_poll_timeout(qpcs->regmap, PCS_CALIBRATION, + val, val & PCS_CALIBRATION_DONE, + 1000, 100000); + if (ret) { + dev_err(qpcs->dev, "PCS calibration timed-out\n"); + return ret; + } + + qpcs->interface = interface; + + return 0; +} + +static int ipq_pcs_config_sgmii(struct ipq_pcs *qpcs, + int index, + unsigned int neg_mode, + phy_interface_t interface) +{ + int ret; + + /* Configure the PCS mode if required */ + if (qpcs->interface != interface) { + ret = ipq_pcs_config_mode(qpcs, interface); + if (ret) + return ret; + } + + /* Nothing to do here as in-band autoneg mode is enabled + * by default for each PCS MII port. + */ + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) + return 0; + + /* Set force speed mode */ + return regmap_set_bits(qpcs->regmap, + PCS_MII_CTRL(index), PCS_MII_FORCE_MODE); +} + +static int ipq_pcs_link_up_config_sgmii(struct ipq_pcs *qpcs, + int index, + unsigned int neg_mode, + int speed) +{ + unsigned int val; + int ret; + + /* PCS speed need not be configured if in-band autoneg is enabled */ + if (neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) { + /* PCS speed set for force mode */ + switch (speed) { + case SPEED_1000: + val = PCS_MII_SPEED_1000; + break; + case SPEED_100: + val = PCS_MII_SPEED_100; + break; + case SPEED_10: + val = PCS_MII_SPEED_10; + break; + default: + dev_err(qpcs->dev, "Invalid SGMII speed %d\n", speed); + return -EINVAL; + } + + ret = regmap_update_bits(qpcs->regmap, PCS_MII_CTRL(index), + PCS_MII_SPEED_MASK, val); + if (ret) + return ret; + } + + /* PCS adapter reset */ + ret = regmap_clear_bits(qpcs->regmap, + PCS_MII_CTRL(index), PCS_MII_ADPT_RESET); + if (ret) + return ret; + + return regmap_set_bits(qpcs->regmap, + PCS_MII_CTRL(index), PCS_MII_ADPT_RESET); +} + +static int ipq_pcs_validate(struct phylink_pcs *pcs, unsigned long *supported, + const struct phylink_link_state *state) +{ + switch (state->interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + return 0; + default: + return -EINVAL; + } +} + +static unsigned int ipq_pcs_inband_caps(struct phylink_pcs *pcs, + phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; + default: + return 0; + } +} + +static int ipq_pcs_enable(struct phylink_pcs *pcs) +{ + struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); + struct ipq_pcs *qpcs = qpcs_mii->qpcs; + int index = qpcs_mii->index; + int ret; + + ret = clk_prepare_enable(qpcs_mii->rx_clk); + if (ret) { + dev_err(qpcs->dev, "Failed to enable MII %d RX clock\n", index); + return ret; + } + + ret = clk_prepare_enable(qpcs_mii->tx_clk); + if (ret) { + /* This is a fatal event since phylink does not support unwinding + * the state back for this error. So, we only report the error + * and do not disable the clocks. + */ + dev_err(qpcs->dev, "Failed to enable MII %d TX clock\n", index); + return ret; + } + + return 0; +} + +static void ipq_pcs_disable(struct phylink_pcs *pcs) +{ + struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); + + clk_disable_unprepare(qpcs_mii->rx_clk); + clk_disable_unprepare(qpcs_mii->tx_clk); +} + +static void ipq_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, + struct phylink_link_state *state) +{ + struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); + struct ipq_pcs *qpcs = qpcs_mii->qpcs; + int index = qpcs_mii->index; + + switch (state->interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + ipq_pcs_get_state_sgmii(qpcs, index, state); + break; + default: + break; + } + + dev_dbg_ratelimited(qpcs->dev, + "mode=%s/%s/%s link=%u\n", + phy_modes(state->interface), + phy_speed_to_str(state->speed), + phy_duplex_to_str(state->duplex), + state->link); +} + +static int ipq_pcs_config(struct phylink_pcs *pcs, + unsigned int neg_mode, + phy_interface_t interface, + const unsigned long *advertising, + bool permit) +{ + struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); + struct ipq_pcs *qpcs = qpcs_mii->qpcs; + int index = qpcs_mii->index; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + return ipq_pcs_config_sgmii(qpcs, index, neg_mode, interface); + default: + return -EOPNOTSUPP; + }; +} + +static void ipq_pcs_link_up(struct phylink_pcs *pcs, + unsigned int neg_mode, + phy_interface_t interface, + int speed, int duplex) +{ + struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); + struct ipq_pcs *qpcs = qpcs_mii->qpcs; + int index = qpcs_mii->index; + int ret; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + ret = ipq_pcs_link_up_config_sgmii(qpcs, index, + neg_mode, speed); + break; + default: + return; + } + + if (ret) + dev_err(qpcs->dev, "PCS link up fail for interface %s\n", + phy_modes(interface)); +} + +static const struct phylink_pcs_ops ipq_pcs_phylink_ops = { + .pcs_validate = ipq_pcs_validate, + .pcs_inband_caps = ipq_pcs_inband_caps, + .pcs_enable = ipq_pcs_enable, + .pcs_disable = ipq_pcs_disable, + .pcs_get_state = ipq_pcs_get_state, + .pcs_config = ipq_pcs_config, + .pcs_link_up = ipq_pcs_link_up, +}; + +/* Parse the PCS MII DT nodes which are child nodes of the PCS node, + * and instantiate each MII PCS instance. + */ +static int ipq_pcs_create_miis(struct ipq_pcs *qpcs) +{ + struct device *dev = qpcs->dev; + struct ipq_pcs_mii *qpcs_mii; + struct device_node *mii_np; + u32 index; + int ret; + + for_each_available_child_of_node(dev->of_node, mii_np) { + ret = of_property_read_u32(mii_np, "reg", &index); + if (ret) { + dev_err(dev, "Failed to read MII index\n"); + of_node_put(mii_np); + return ret; + } + + if (index >= PCS_MAX_MII_NRS) { + dev_err(dev, "Invalid MII index\n"); + of_node_put(mii_np); + return -EINVAL; + } + + qpcs_mii = devm_kzalloc(dev, sizeof(*qpcs_mii), GFP_KERNEL); + if (!qpcs_mii) { + of_node_put(mii_np); + return -ENOMEM; + } + + qpcs_mii->qpcs = qpcs; + qpcs_mii->index = index; + qpcs_mii->pcs.ops = &ipq_pcs_phylink_ops; + qpcs_mii->pcs.neg_mode = true; + qpcs_mii->pcs.poll = true; + + qpcs_mii->rx_clk = devm_get_clk_from_child(dev, mii_np, "rx"); + if (IS_ERR(qpcs_mii->rx_clk)) { + of_node_put(mii_np); + return dev_err_probe(dev, PTR_ERR(qpcs_mii->rx_clk), + "Failed to get MII %d RX clock\n", index); + } + + qpcs_mii->tx_clk = devm_get_clk_from_child(dev, mii_np, "tx"); + if (IS_ERR(qpcs_mii->tx_clk)) { + of_node_put(mii_np); + return dev_err_probe(dev, PTR_ERR(qpcs_mii->tx_clk), + "Failed to get MII %d TX clock\n", index); + } + + qpcs->qpcs_mii[index] = qpcs_mii; + } + + return 0; +} + static unsigned long ipq_pcs_clk_rate_get(struct ipq_pcs *qpcs) { switch (qpcs->interface) { @@ -219,6 +616,10 @@ static int ipq9574_pcs_probe(struct platform_device *pdev) if (ret) return ret; + ret = ipq_pcs_create_miis(qpcs); + if (ret) + return ret; + platform_set_drvdata(pdev, qpcs); return 0; @@ -230,6 +631,74 @@ static const struct of_device_id ipq9574_pcs_of_mtable[] = { }; MODULE_DEVICE_TABLE(of, ipq9574_pcs_of_mtable); +/** + * ipq_pcs_get() - Get the IPQ PCS MII instance + * @np: Device tree node to the PCS MII + * + * Description: Get the phylink PCS instance for the given PCS MII node @np. + * This instance is associated with the specific MII of the PCS and the + * corresponding Ethernet netdevice. + * + * Return: A pointer to the phylink PCS instance or an error-pointer value. + */ +struct phylink_pcs *ipq_pcs_get(struct device_node *np) +{ + struct platform_device *pdev; + struct ipq_pcs_mii *qpcs_mii; + struct ipq_pcs *qpcs; + u32 index; + + if (of_property_read_u32(np, "reg", &index)) + return ERR_PTR(-EINVAL); + + if (index >= PCS_MAX_MII_NRS) + return ERR_PTR(-EINVAL); + + if (!of_match_node(ipq9574_pcs_of_mtable, np->parent)) + return ERR_PTR(-EINVAL); + + /* Get the parent device */ + pdev = of_find_device_by_node(np->parent); + if (!pdev) + return ERR_PTR(-ENODEV); + + qpcs = platform_get_drvdata(pdev); + if (!qpcs) { + put_device(&pdev->dev); + + /* If probe is not yet completed, return DEFER to + * the dependent driver. + */ + return ERR_PTR(-EPROBE_DEFER); + } + + qpcs_mii = qpcs->qpcs_mii[index]; + if (!qpcs_mii) { + put_device(&pdev->dev); + return ERR_PTR(-ENOENT); + } + + return &qpcs_mii->pcs; +} +EXPORT_SYMBOL(ipq_pcs_get); + +/** + * ipq_pcs_put() - Release the IPQ PCS MII instance + * @pcs: PCS instance + * + * Description: Release a phylink PCS instance. + */ +void ipq_pcs_put(struct phylink_pcs *pcs) +{ + struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); + + /* Put reference taken by of_find_device_by_node() in + * ipq_pcs_get(). + */ + put_device(qpcs_mii->qpcs->dev); +} +EXPORT_SYMBOL(ipq_pcs_put); + static struct platform_driver ipq9574_pcs_driver = { .driver = { .name = "ipq9574_pcs", diff --git a/include/linux/pcs/pcs-qcom-ipq9574.h b/include/linux/pcs/pcs-qcom-ipq9574.h new file mode 100644 index 000000000000..8daff8fa5a00 --- /dev/null +++ b/include/linux/pcs/pcs-qcom-ipq9574.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __LINUX_PCS_QCOM_IPQ9574_H +#define __LINUX_PCS_QCOM_IPQ9574_H + +struct device_node; +struct phylink_pcs; + +struct phylink_pcs *ipq_pcs_get(struct device_node *np); +void ipq_pcs_put(struct phylink_pcs *pcs); + +#endif /* __LINUX_PCS_QCOM_IPQ9574_H */ From patchwork Fri Feb 7 15:53:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lei Wei X-Patchwork-Id: 863339 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F54823FC70; Fri, 7 Feb 2025 15:59:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738943951; cv=none; b=br2hJgZH8tIfi6fprP7uiyDWCsUjbD9lORrJtxBSKW89jebLwJB4S7bfBcji9NEKOJDajv5ZFc1OfbHq0u2WKZGSt03QmOe/P3BhoGutDHjGwPt68dZYt9dShduWR51dAM96ZltB/SiWIYVE9cMsbsOz+83SSdlvz4TMSJHJ1vM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738943951; c=relaxed/simple; bh=fxqCdraWBnnIJZPN5xLPPSvURBBX8lMHMmoEO1NhZhc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Ilf9JVzKycuAQvstRURATiJpRCK3rFBX+JmLh4GkAORKOj9AQ87mOfDwRtVbIqf9CkV4J39evqBTD91iiQv77KhiPuNyKsg6e5sACYqbzd9CdJSvhdiyWLALb5AIDWanoTPrTwUCBJtCJMH4gCk+qOUn1czin3Fqqx8Uhn3qkSM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=lhiClJdO; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="lhiClJdO" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 517BNWwE032176; Fri, 7 Feb 2025 15:58:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ZNz99dhMzCuKVYN8cfdJRUp/3EeOJSuncQmxCrYlLz0=; b=lhiClJdOx6+w1Jdg PQwfYvnmIyBNJB1UkHZrtd/d68y0Cb7dDFxKkJemh9Hh/BYHfSNkdv5n7IgyUifd PvUcyz/QLFV7rcsa6mSZBAI+Aa/AbIV596u9UxutvPuIFARdaoVSTY8jO9ZJDliF tQEbMuSZOjS0RArCJUIsnAS973NoJBvqMfmiuHCGCjFJLvsIJK/EmRLT2Eqp1Nq3 WDNdP9Vov8MbEtlA+Wys/B7QNrbPxgamq1aYPXJTOiakf6FwSh4ZO/gF+TnwHKfg oyZEnuWeJGDYHppL3CeWIyRwIx5OShB7ru6Z/oe+UwB2mVAWDbCiYbIYHJjhNQ0F iCQdDw== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44nh8urp5f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Feb 2025 15:58:54 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 517FwsXJ007320 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Feb 2025 15:58:54 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 7 Feb 2025 07:58:49 -0800 From: Lei Wei Date: Fri, 7 Feb 2025 23:53:15 +0800 Subject: [PATCH net-next v5 4/5] net: pcs: qcom-ipq9574: Add USXGMII interface mode support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250207-ipq_pcs_6-14_rc1-v5-4-be2ebec32921@quicinc.com> References: <20250207-ipq_pcs_6-14_rc1-v5-0-be2ebec32921@quicinc.com> In-Reply-To: <20250207-ipq_pcs_6-14_rc1-v5-0-be2ebec32921@quicinc.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Heiner Kallweit , Russell King CC: , , , , , , , , , , , , , X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738943908; l=7629; i=quic_leiwei@quicinc.com; s=20240829; h=from:subject:message-id; bh=fxqCdraWBnnIJZPN5xLPPSvURBBX8lMHMmoEO1NhZhc=; b=TJR0u/H5vTDgaXvUtgGSSvrqPVSOrgnu4efKJVrwhIv0ZriMjrTMMmXqoXFzy6aIRN9E9yf4R laBsyG0U1MeCz6f9Fgtuft7AcaH0Ym3s06Bb708qvzL+2LZeSyjQVwX X-Developer-Key: i=quic_leiwei@quicinc.com; a=ed25519; pk=uFXBHtxtDjtIrTKpDEZlMLSn1i/sonZepYO8yioKACM= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: TxvIGz8sR1L2g4r7AxOeTqL-wZDIRTS- X-Proofpoint-ORIG-GUID: TxvIGz8sR1L2g4r7AxOeTqL-wZDIRTS- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-07_07,2025-02-07_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 mlxscore=0 bulkscore=0 adultscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502070121 USXGMII mode is enabled by PCS when 10Gbps PHYs are connected, such as Aquantia 10Gbps PHY. Signed-off-by: Lei Wei --- drivers/net/pcs/pcs-qcom-ipq9574.c | 170 +++++++++++++++++++++++++++++++++++++ 1 file changed, 170 insertions(+) diff --git a/drivers/net/pcs/pcs-qcom-ipq9574.c b/drivers/net/pcs/pcs-qcom-ipq9574.c index 2bb55814d2fb..c35281c9397b 100644 --- a/drivers/net/pcs/pcs-qcom-ipq9574.c +++ b/drivers/net/pcs/pcs-qcom-ipq9574.c @@ -26,6 +26,7 @@ #define PCS_MODE_SEL_MASK GENMASK(12, 8) #define PCS_MODE_SGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x4) #define PCS_MODE_QSGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x1) +#define PCS_MODE_XPCS FIELD_PREP(PCS_MODE_SEL_MASK, 0x10) #define PCS_MII_CTRL(x) (0x480 + 0x18 * (x)) #define PCS_MII_ADPT_RESET BIT(11) @@ -54,6 +55,34 @@ FIELD_PREP(GENMASK(9, 2), \ FIELD_GET(XPCS_INDIRECT_ADDR_L, reg))) +#define XPCS_DIG_CTRL 0x38000 +#define XPCS_USXG_ADPT_RESET BIT(10) +#define XPCS_USXG_EN BIT(9) + +#define XPCS_MII_CTRL 0x1f0000 +#define XPCS_MII_AN_EN BIT(12) +#define XPCS_DUPLEX_FULL BIT(8) +#define XPCS_SPEED_MASK (BIT(13) | BIT(6) | BIT(5)) +#define XPCS_SPEED_10000 (BIT(13) | BIT(6)) +#define XPCS_SPEED_5000 (BIT(13) | BIT(5)) +#define XPCS_SPEED_2500 BIT(5) +#define XPCS_SPEED_1000 BIT(6) +#define XPCS_SPEED_100 BIT(13) +#define XPCS_SPEED_10 0 + +#define XPCS_MII_AN_CTRL 0x1f8001 +#define XPCS_MII_AN_8BIT BIT(8) + +#define XPCS_MII_AN_INTR_STS 0x1f8002 +#define XPCS_USXG_AN_LINK_STS BIT(14) +#define XPCS_USXG_AN_SPEED_MASK GENMASK(12, 10) +#define XPCS_USXG_AN_SPEED_10 0 +#define XPCS_USXG_AN_SPEED_100 1 +#define XPCS_USXG_AN_SPEED_1000 2 +#define XPCS_USXG_AN_SPEED_2500 4 +#define XPCS_USXG_AN_SPEED_5000 5 +#define XPCS_USXG_AN_SPEED_10000 3 + /* Per PCS MII private data */ struct ipq_pcs_mii { struct ipq_pcs *qpcs; @@ -123,9 +152,54 @@ static void ipq_pcs_get_state_sgmii(struct ipq_pcs *qpcs, state->duplex = DUPLEX_HALF; } +static void ipq_pcs_get_state_usxgmii(struct ipq_pcs *qpcs, + struct phylink_link_state *state) +{ + unsigned int val; + int ret; + + ret = regmap_read(qpcs->regmap, XPCS_MII_AN_INTR_STS, &val); + if (ret) { + state->link = 0; + return; + } + + state->link = !!(val & XPCS_USXG_AN_LINK_STS); + + if (!state->link) + return; + + switch (FIELD_GET(XPCS_USXG_AN_SPEED_MASK, val)) { + case XPCS_USXG_AN_SPEED_10000: + state->speed = SPEED_10000; + break; + case XPCS_USXG_AN_SPEED_5000: + state->speed = SPEED_5000; + break; + case XPCS_USXG_AN_SPEED_2500: + state->speed = SPEED_2500; + break; + case XPCS_USXG_AN_SPEED_1000: + state->speed = SPEED_1000; + break; + case XPCS_USXG_AN_SPEED_100: + state->speed = SPEED_100; + break; + case XPCS_USXG_AN_SPEED_10: + state->speed = SPEED_10; + break; + default: + state->link = false; + return; + } + + state->duplex = DUPLEX_FULL; +} + static int ipq_pcs_config_mode(struct ipq_pcs *qpcs, phy_interface_t interface) { + unsigned long rate = 125000000; unsigned int val; int ret; @@ -137,6 +211,10 @@ static int ipq_pcs_config_mode(struct ipq_pcs *qpcs, case PHY_INTERFACE_MODE_QSGMII: val = PCS_MODE_QSGMII; break; + case PHY_INTERFACE_MODE_USXGMII: + val = PCS_MODE_XPCS; + rate = 312500000; + break; default: return -EOPNOTSUPP; } @@ -167,6 +245,21 @@ static int ipq_pcs_config_mode(struct ipq_pcs *qpcs, qpcs->interface = interface; + /* Configure the RX and TX clock to NSSCC as 125M or 312.5M based + * on current interface mode. + */ + ret = clk_set_rate(qpcs->rx_hw.clk, rate); + if (ret) { + dev_err(qpcs->dev, "Failed to set RX clock rate\n"); + return ret; + } + + ret = clk_set_rate(qpcs->tx_hw.clk, rate); + if (ret) { + dev_err(qpcs->dev, "Failed to set TX clock rate\n"); + return ret; + } + return 0; } @@ -195,6 +288,29 @@ static int ipq_pcs_config_sgmii(struct ipq_pcs *qpcs, PCS_MII_CTRL(index), PCS_MII_FORCE_MODE); } +static int ipq_pcs_config_usxgmii(struct ipq_pcs *qpcs) +{ + int ret; + + /* Configure the XPCS for USXGMII mode if required */ + if (qpcs->interface == PHY_INTERFACE_MODE_USXGMII) + return 0; + + ret = ipq_pcs_config_mode(qpcs, PHY_INTERFACE_MODE_USXGMII); + if (ret) + return ret; + + ret = regmap_set_bits(qpcs->regmap, XPCS_DIG_CTRL, XPCS_USXG_EN); + if (ret) + return ret; + + ret = regmap_set_bits(qpcs->regmap, XPCS_MII_AN_CTRL, XPCS_MII_AN_8BIT); + if (ret) + return ret; + + return regmap_set_bits(qpcs->regmap, XPCS_MII_CTRL, XPCS_MII_AN_EN); +} + static int ipq_pcs_link_up_config_sgmii(struct ipq_pcs *qpcs, int index, unsigned int neg_mode, @@ -237,6 +353,46 @@ static int ipq_pcs_link_up_config_sgmii(struct ipq_pcs *qpcs, PCS_MII_CTRL(index), PCS_MII_ADPT_RESET); } +static int ipq_pcs_link_up_config_usxgmii(struct ipq_pcs *qpcs, int speed) +{ + unsigned int val; + int ret; + + switch (speed) { + case SPEED_10000: + val = XPCS_SPEED_10000; + break; + case SPEED_5000: + val = XPCS_SPEED_5000; + break; + case SPEED_2500: + val = XPCS_SPEED_2500; + break; + case SPEED_1000: + val = XPCS_SPEED_1000; + break; + case SPEED_100: + val = XPCS_SPEED_100; + break; + case SPEED_10: + val = XPCS_SPEED_10; + break; + default: + dev_err(qpcs->dev, "Invalid USXGMII speed %d\n", speed); + return -EINVAL; + } + + /* Configure XPCS speed */ + ret = regmap_update_bits(qpcs->regmap, XPCS_MII_CTRL, + XPCS_SPEED_MASK, val | XPCS_DUPLEX_FULL); + if (ret) + return ret; + + /* XPCS adapter reset */ + return regmap_set_bits(qpcs->regmap, + XPCS_DIG_CTRL, XPCS_USXG_ADPT_RESET); +} + static int ipq_pcs_validate(struct phylink_pcs *pcs, unsigned long *supported, const struct phylink_link_state *state) { @@ -244,6 +400,11 @@ static int ipq_pcs_validate(struct phylink_pcs *pcs, unsigned long *supported, case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: return 0; + case PHY_INTERFACE_MODE_USXGMII: + /* USXGMII only supports full duplex mode */ + phylink_clear(supported, 100baseT_Half); + phylink_clear(supported, 10baseT_Half); + return 0; default: return -EINVAL; } @@ -255,6 +416,7 @@ static unsigned int ipq_pcs_inband_caps(struct phylink_pcs *pcs, switch (interface) { case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_USXGMII: return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; default: return 0; @@ -307,6 +469,9 @@ static void ipq_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, case PHY_INTERFACE_MODE_QSGMII: ipq_pcs_get_state_sgmii(qpcs, index, state); break; + case PHY_INTERFACE_MODE_USXGMII: + ipq_pcs_get_state_usxgmii(qpcs, state); + break; default: break; } @@ -333,6 +498,8 @@ static int ipq_pcs_config(struct phylink_pcs *pcs, case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: return ipq_pcs_config_sgmii(qpcs, index, neg_mode, interface); + case PHY_INTERFACE_MODE_USXGMII: + return ipq_pcs_config_usxgmii(qpcs); default: return -EOPNOTSUPP; }; @@ -354,6 +521,9 @@ static void ipq_pcs_link_up(struct phylink_pcs *pcs, ret = ipq_pcs_link_up_config_sgmii(qpcs, index, neg_mode, speed); break; + case PHY_INTERFACE_MODE_USXGMII: + ret = ipq_pcs_link_up_config_usxgmii(qpcs, speed); + break; default: return; } From patchwork Fri Feb 7 15:53:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lei Wei X-Patchwork-Id: 863047 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED18F1EB18D; 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Signed-off-by: Lei Wei --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 896a307fa065..60c340a2de5e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19525,6 +19525,15 @@ S: Maintained F: Documentation/devicetree/bindings/regulator/vqmmc-ipq4019-regulator.yaml F: drivers/regulator/vqmmc-ipq4019-regulator.c +QUALCOMM IPQ9574 Ethernet PCS DRIVER +M: Lei Wei +L: netdev@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml +F: drivers/net/pcs/pcs-qcom-ipq9574.c +F: include/dt-bindings/net/qcom,ipq9574-pcs.h +F: include/linux/pcs/pcs-qcom-ipq9574.h + QUALCOMM NAND CONTROLLER DRIVER M: Manivannan Sadhasivam L: linux-mtd@lists.infradead.org