From patchwork Sun Feb 9 21:42:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 863607 Received: from m-r1.th.seeweb.it (m-r1.th.seeweb.it [5.144.164.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3ADA81E5721 for ; Sun, 9 Feb 2025 21:43:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.144.164.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739137385; cv=none; b=fgxwzkOaejfO5gMa9FQeRR0tnrWdircUGC3mPvtFy75+LFhyXYfKAEySSfgjG4aJYkoLbTIOIxSzrCFfC9uE9laJMlh0jiLv6ovEgJPO6Mq3SKj+2yFzXCK+AIc6LWdPxBwD4a/g/Fd0Ey9jwny/HE24h8MYTKo9MRnYzRtHjvg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739137385; c=relaxed/simple; bh=Tfsl+1a40BScE8ikvZaM3H+qVdmMOmXUCGzcdcW2ync=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CKgwHQ+ur7oUBcgM1f+k9UxZ9NEeC/Y5MC6d4PBezKvPwXIQIey0rKGCUyXeV2slsxZTTi9/3dH4Vtrlgk7RHGiu/cvQUDalObJvAvgDLzMkby56JE9PHY9U38ciPf+MCNt16f4QlScJD3xmoNyyKLb3jAizApeVzplPK7792Rc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=somainline.org; spf=pass smtp.mailfrom=somainline.org; arc=none smtp.client-ip=5.144.164.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=somainline.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=somainline.org Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 89E572018C; Sun, 9 Feb 2025 22:43:00 +0100 (CET) From: Marijn Suijten Date: Sun, 09 Feb 2025 22:42:53 +0100 Subject: [PATCH v2 2/3] drm/msm/dsi: Set PHY usescase (and mode) before registering DSI host Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250209-drm-msm-initial-dualpipe-dsc-fixes-v2-2-9a60184fdc36@somainline.org> References: <20250209-drm-msm-initial-dualpipe-dsc-fixes-v2-0-9a60184fdc36@somainline.org> In-Reply-To: <20250209-drm-msm-initial-dualpipe-dsc-fixes-v2-0-9a60184fdc36@somainline.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Vinod Koul , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jordan Crouse , ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Martin Botka , Jami Kettunen , Konrad Dybcio , Marijn Suijten X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3553; i=marijn.suijten@somainline.org; h=from:subject:message-id; bh=Tfsl+1a40BScE8ikvZaM3H+qVdmMOmXUCGzcdcW2ync=; b=owEBbQKS/ZANAwAIAfFi0jHH5IZ2AcsmYgBnqSFiT34CP+ZJaA+rzArxEFLoN1LWvZjH/Bies mr2e4ZztEmJAjMEAAEIAB0WIQROiwG5pb6la1/WZxbxYtIxx+SGdgUCZ6khYgAKCRDxYtIxx+SG dvTGEACxAnMNqxkekAmzf0r7lozEJOigflfa9+ZcLs+RUG7X/3DZ3zzzlLauHO0tzU/HWB+OWEm 3JJ1xU8ckjnH8J0J6shnG2dL3xS4VlHq5Ix55Z3ZkyJIF6pxnBuBqthHZGF3imuXex9fnHHVNp3 h8lTfYj42YJRUGDlEYDyWUHFSo5tD76Y8guTlcvyQ12vLXlPKudvCoVz8yqmK5JFlwdzywazPhf KlgFyWlyzBbHHG+XLel5Z0kqbTMI/b1PizeFvyPUuADCQ1zBwIur2M88v3scfDbA5TxUyQuUAnM 2+KlC2LVjgrG/h6VCK21Bg8ndojIowYAiDdsWMu/2HmAyH/X8L3/BBIudDLoo7Ya+xCeI7mBPvk oHzGMC60CVTp9Z4Xgd9Cq9xzO//SekabwP/RTMlkVk59eujBHGRDRs5i1p7IaawUVnF0QkON3EO 5eBNrhsvYFURfpiodTLrfg1gn9sNQkfhslulY/dr0nNtx8F82FIUBGu8qsJS40ZCWYeDfi+/Uof JWPwVLWsEtXBTys3nDGhMmG5jCb+mr1zhtHzbpOUQBS0qHAfxdVORnIZ5TYVzYrc/pnreo7J2mi SYMOmVIz8ZwP+dlyeAFY3WUHeRUFhmaYbvZvh2/k+ffO6lkSR8y4GTbEAMQBrR0NbwE+/k/kTQo 71QhOLH1+c0sUgA== X-Developer-Key: i=marijn.suijten@somainline.org; a=openpgp; fpr=4E8B01B9A5BEA56B5FD66716F162D231C7E48676 Ordering issues here cause an uninitialized (default STANDALONE) usecase to be programmed (which appears to be a MUX) in some cases when msm_dsi_host_register() is called, leading to the slave PLL in bonded-DSI mode to source from a clock parent (dsi1vco) that is off. This should seemingly not be a problem as the actual dispcc clocks from DSI1 that are muxed in the clock tree of DSI0 are way further down, this bit still seems to have an effect on them somehow and causes the right side of the panel controlled by DSI1 to not function. In an ideal world this code is refactored to no longer have such error-prone calls "across subsystems", and instead model the "PLL src" register field as a regular mux so that changing the clock parents programmatically or in DTS via `assigned-clock-parents` has the desired effect. But for the avid reader, the clocks that we *are* muxing into DSI0's tree are way further down, so if this bit turns out to be a simple mux between dsiXvco and out_div, that shouldn't have any effect as this whole tree is off anyway. Signed-off-by: Marijn Suijten --- drivers/gpu/drm/msm/dsi/dsi_manager.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index a210b7c9e5ca281a46fbdb226e25832719a684ea..b93205c034e4acc73d536deeddce6ebd694b4a80 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -74,17 +74,33 @@ static int dsi_mgr_setup_components(int id) int ret; if (!IS_BONDED_DSI()) { + /* Set the usecase before calling msm_dsi_host_register(), which would + * already program the PLL source mux based on a default usecase. + */ + msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE); + msm_dsi_host_set_phy_mode(msm_dsi->host, msm_dsi->phy); + ret = msm_dsi_host_register(msm_dsi->host); if (ret) return ret; - - msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE); - msm_dsi_host_set_phy_mode(msm_dsi->host, msm_dsi->phy); } else if (other_dsi) { struct msm_dsi *master_link_dsi = IS_MASTER_DSI_LINK(id) ? msm_dsi : other_dsi; struct msm_dsi *slave_link_dsi = IS_MASTER_DSI_LINK(id) ? other_dsi : msm_dsi; + + /* PLL0 is to drive both DSI link clocks in bonded DSI mode. + * + /* Set the usecase before calling msm_dsi_host_register(), which would + * already program the PLL source mux based on a default usecase. + */ + msm_dsi_phy_set_usecase(clk_master_dsi->phy, + MSM_DSI_PHY_MASTER); + msm_dsi_phy_set_usecase(clk_slave_dsi->phy, + MSM_DSI_PHY_SLAVE); + msm_dsi_host_set_phy_mode(msm_dsi->host, msm_dsi->phy); + msm_dsi_host_set_phy_mode(other_dsi->host, other_dsi->phy); + /* Register slave host first, so that slave DSI device * has a chance to probe, and do not block the master * DSI device's probe. @@ -98,14 +114,6 @@ static int dsi_mgr_setup_components(int id) ret = msm_dsi_host_register(master_link_dsi->host); if (ret) return ret; - - /* PLL0 is to drive both 2 DSI link clocks in bonded DSI mode. */ - msm_dsi_phy_set_usecase(clk_master_dsi->phy, - MSM_DSI_PHY_MASTER); - msm_dsi_phy_set_usecase(clk_slave_dsi->phy, - MSM_DSI_PHY_SLAVE); - msm_dsi_host_set_phy_mode(msm_dsi->host, msm_dsi->phy); - msm_dsi_host_set_phy_mode(other_dsi->host, other_dsi->phy); } return 0; From patchwork Sun Feb 9 21:42:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 863606 Received: from relay02.th.seeweb.it (relay02.th.seeweb.it [5.144.164.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE54B1E9B3C; Sun, 9 Feb 2025 21:43:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.144.164.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739137385; cv=none; b=gX0T8gPDxgFYjVhSMwvehAUHf7CHdgDwLvxEV8sHTUtJOOXob+N+ET6NZEnvs4ef45o8xhFGCr3lrHnsvTd7s7oeg6MUP3SURJhovPXCndVKXe3Wgo/XuTnQimsLnbWg1EpFlNvf0d5661I0b7q2jPx5OKC3wbrQaoemMKBcylo= ARC-Message-Signature: i=1; a=rsa-sha256; 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Sun, 9 Feb 2025 22:43:01 +0100 (CET) From: Marijn Suijten Date: Sun, 09 Feb 2025 22:42:54 +0100 Subject: [PATCH v2 3/3] drm/msm/dpu: Remove arbitrary limit of 1 interface in DSC topology Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250209-drm-msm-initial-dualpipe-dsc-fixes-v2-3-9a60184fdc36@somainline.org> References: <20250209-drm-msm-initial-dualpipe-dsc-fixes-v2-0-9a60184fdc36@somainline.org> In-Reply-To: <20250209-drm-msm-initial-dualpipe-dsc-fixes-v2-0-9a60184fdc36@somainline.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Vinod Koul , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jordan Crouse , ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Martin Botka , Jami Kettunen , Konrad Dybcio , Marijn Suijten X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=4E8B01B9A5BEA56B5FD66716F162D231C7E48676 When DSC is enabled the number of interfaces is forced to be 1, and documented that it is a "power-optimal" layout to use two DSC encoders together with two Layer Mixers. However, the same layout (two DSC hard-slice encoders with two LMs) is also used when the display is fed with data over two instead of one interface (common on 4k@120Hz smartphone panels with Dual-DSI). Solve this by simply removing the num_intf = 1 assignment as the count is already calculated by computing the number of physical encoders within the virtual encoder. Fixes: 7e9cc175b159 ("drm/msm/disp/dpu1: Add support for DSC in topology") Signed-off-by: Marijn Suijten --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index b585cd17462345f94bcc2ddd57902cc7c312ae63..b0870318471bd7cceda70fd15ea7bcc8658af604 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -686,20 +686,21 @@ static struct msm_display_topology dpu_encoder_get_topology( if (dsc) { /* - * Use 2 DSC encoders and 2 layer mixers per single interface + * Use 2 DSC encoders, 2 layer mixers and 1 or 2 interfaces * when Display Stream Compression (DSC) is enabled, * and when enough DSC blocks are available. * This is power-optimal and can drive up to (including) 4k * screens. */ - if (dpu_kms->catalog->dsc_count >= 2) { + WARN(topology.num_intf > 2, + "DSC topology cannot support more than 2 interfaces\n"); + if (intf_count >= 2 || dpu_kms->catalog->dsc_count >= 2) { topology.num_dsc = 2; topology.num_lm = 2; } else { topology.num_dsc = 1; topology.num_lm = 1; } - topology.num_intf = 1; } return topology;