From patchwork Mon Feb 10 07:01:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chukun Pan X-Patchwork-Id: 863906 Received: from mail-m49198.qiye.163.com (mail-m49198.qiye.163.com [45.254.49.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 252E01B4149; Mon, 10 Feb 2025 07:06:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739171211; cv=none; b=lHHjNkaHJU50Z7Wru1v4n3YtHTb7e38axWz86PtPygmbiTPUPTkmzby/vZcGzjUZ213xriuEgPTyG54dclUrPSombjhocL+k2iWLFHGPh/eop/P9kJrNn23u977OXXzIXVFYtVa0scqJ5Q7RbdiqkQSQdxYZvJqeHUEpgAGaT1I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739171211; c=relaxed/simple; bh=xJywoSB3ZphGXm9Arwqc+Z7YKhKh1ayvTAfnmDuMcvM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LxAH762OKNa1BHe7MhJvvRkUGUMyDSOvURbPe1LeqG5m4GTQBV3XN+BNS8PzesX0QT5Q/wl7zf/j2Kk/VNkfgTGyaPGSedXva7i1sPZl4vY8HWy67rovGm5LEixrhohEvMh/6E1ROWv9LA9ENhDGECGibFvLHFi6bZ6pXihOO54= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn; spf=pass smtp.mailfrom=jmu.edu.cn; arc=none smtp.client-ip=45.254.49.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=jmu.edu.cn Received: from amadeus-Vostro-3710.lan (unknown [119.122.213.246]) by smtp.qiye.163.com (Hmail) with ESMTP id a99674fd; Mon, 10 Feb 2025 15:01:32 +0800 (GMT+08:00) From: Chukun Pan To: Bjorn Andersson Cc: Konrad Dybcio , Krzysztof Kozlowski , Conor Dooley , Rob Herring , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Chukun Pan , Konrad Dybcio Subject: [PATCH v6 2/5] arm64: dts: qcom: ipq6018: add 1.5GHz CPU Frequency Date: Mon, 10 Feb 2025 15:01:19 +0800 Message-Id: <20250210070122.208842-3-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250210070122.208842-1-amadeus@jmu.edu.cn> References: <20250210070122.208842-1-amadeus@jmu.edu.cn> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkaQklNVkNIHUJISkJNSxlMTFYeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlKSkJVSklJVUlKSFVJT01ZV1kWGg8SFR0UWUFZT0tIVUpLSEpOTE5VSktLVU pCS0tZBg++ X-HM-Tid: 0a94eea9ca2d03a2kunma99674fd X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Phg6Nzo*DTITNEsUAjgWQkw4 MEwaCxBVSlVKTEhCSkxLQ0JISktKVTMWGhIXVRoWGh8eDgg7ERYOVR4fDlUYFUVZV1kSC1lBWUpK QlVKSUlVSUpIVUlPTVlXWQgBWUFCTks3Bg++ The early version of IPQ6000 (SoC id: IPQ6018, SBL version: BOOT.XF.0.3-00077-IPQ60xxLZB-2) and IPQ6005 SoCs can reach a max frequency of 1.5GHz, so add this CPU frequency. Signed-off-by: Chukun Pan Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 57ad6f0e6e34..7514919132b6 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -140,6 +140,13 @@ opp-1440000000 { clock-latency-ns = <200000>; }; + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <937500>; + opp-supported-hw = <0x2>; + clock-latency-ns = <200000>; + }; + opp-1608000000 { opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <987500>; From patchwork Mon Feb 10 07:01:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chukun Pan X-Patchwork-Id: 863907 Received: from mail-m49197.qiye.163.com (mail-m49197.qiye.163.com [45.254.49.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B505C1925BF; Mon, 10 Feb 2025 07:06:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739171208; cv=none; b=flWjKvN+JANcxIQcoSPtzQYVkR7onAn3zwbfk0+eWZ7/odQiGXBs5thvDjgdUwv+w3tf5LWcCTag1mqS/xNC4oV5epW5kWmNH/UXS5/VE+dPqmA63UDc50TiCI/6VJxkhXtNO86TGhcR47krktgU8x+jbMo794u6ToUs3eeWnfI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739171208; c=relaxed/simple; bh=wYVj+IxChyOk56G2sZ6I0GeRCsSGCtU00yNRkps0Tgw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=e/6pMqt262Fj8sOnHT81DKP2BVpb8HkHzq4+LPpXo8VTPnr0q4B9UuMpHsvuecUg+FlVcNPK/zYDX6xVRHZ7bCk0LAvy7VC0TGw6YVXJspHJJ43DxzpjFxqsLgaUR2i11Xz3iDs/5YYFn7x5M5NWQBJtVrCdFS0MztdtvPs+eO8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn; spf=pass smtp.mailfrom=jmu.edu.cn; arc=none smtp.client-ip=45.254.49.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=jmu.edu.cn Received: from amadeus-Vostro-3710.lan (unknown [119.122.213.246]) by smtp.qiye.163.com (Hmail) with ESMTP id a99674fe; Mon, 10 Feb 2025 15:01:33 +0800 (GMT+08:00) From: Chukun Pan To: Bjorn Andersson Cc: Konrad Dybcio , Krzysztof Kozlowski , Conor Dooley , Rob Herring , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Chukun Pan , Dmitry Baryshkov Subject: [PATCH v6 3/5] arm64: dts: qcom: ipq6018: move mp5496 regulator out of soc dtsi Date: Mon, 10 Feb 2025 15:01:20 +0800 Message-Id: <20250210070122.208842-4-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250210070122.208842-1-amadeus@jmu.edu.cn> References: <20250210070122.208842-1-amadeus@jmu.edu.cn> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlCHhoeVk4YSE5NSh9ISUoeSFYeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlKSkJVSklJVUlKSFVJT01ZV1kWGg8SFR0UWUFZT0tIVUpLSEpOTE5VSktLVU pCS0tZBg++ X-HM-Tid: 0a94eea9d0bc03a2kunma99674fe X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MDI6TBw4HjIOS0saAjgNQktD Kx4wFExVSlVKTEhCSkxLQ0JPQkJMVTMWGhIXVRoWGh8eDgg7ERYOVR4fDlUYFUVZV1kSC1lBWUpK QlVKSUlVSUpIVUlPTVlXWQgBWUFIT0NMNwY+ Some IPQ60xx SoCs don't come with the mp5496 pmic chip. The mp5496 pmic was never part of the IPQ60xx SoC, it's optional, so we moved it out of the soc dtsi. Signed-off-by: Chukun Pan Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 2 +- arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 35 ++++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 -------- 3 files changed, 36 insertions(+), 15 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index f5f4827c0e17..9c69d3027b43 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "ipq6018.dtsi" +#include "ipq6018-mp5496.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; diff --git a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi new file mode 100644 index 000000000000..fe2152df69f4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * ipq6018-mp5496.dtsi describes common properties (e.g. regulators) that + * apply to most devices that make use of the IPQ6018 SoC and MP5496 PMIC. + */ + +#include "ipq6018.dtsi" + +&cpu0 { + cpu-supply = <&ipq6018_s2>; +}; + +&cpu1 { + cpu-supply = <&ipq6018_s2>; +}; + +&cpu2 { + cpu-supply = <&ipq6018_s2>; +}; + +&cpu3 { + cpu-supply = <&ipq6018_s2>; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq6018_s2: s2 { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1062500>; + regulator-always-on; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 7514919132b6..a02aa641cb90 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -43,7 +43,6 @@ cpu0: cpu@0 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; #cooling-cells = <2>; }; @@ -56,7 +55,6 @@ cpu1: cpu@1 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; #cooling-cells = <2>; }; @@ -69,7 +67,6 @@ cpu2: cpu@2 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; #cooling-cells = <2>; }; @@ -82,7 +79,6 @@ cpu3: cpu@3 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; #cooling-cells = <2>; }; @@ -184,16 +180,6 @@ glink-edge { rpm_requests: rpm-requests { compatible = "qcom,rpm-ipq6018", "qcom,glink-smd-rpm"; qcom,glink-channels = "rpm_requests"; - - regulators { - compatible = "qcom,rpm-mp5496-regulators"; - - ipq6018_s2: s2 { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1062500>; - regulator-always-on; - }; - }; }; }; }; From patchwork Mon Feb 10 07:01:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chukun Pan X-Patchwork-Id: 863908 Received: from mail-m49197.qiye.163.com (mail-m49197.qiye.163.com [45.254.49.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B2C41ACEC2; Mon, 10 Feb 2025 07:01:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739170904; cv=none; b=E1Wx5SF291wa3DbqckFsHuxfk4lUSwcyYq4/FO1qfqlfrReAHK1yh3hod15Ef5wNfmhMa5d27MbS8w1kFT50+sSzbDQXhiZ2KBO0SX3kj03PYxPLD0IR9aI/HHCxpHNJvaUBLxE8pX9a2+xLcx2n8wUgF/MWv7OnKslcE10IxfE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739170904; c=relaxed/simple; bh=NlDPQ3SoBpBEm8Z+/r8oj4OA9TgTzyH5wymt+ye9W/k=; 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Suggested-by: Konrad Dybcio Suggested-by: Dmitry Baryshkov Signed-off-by: Chukun Pan --- arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi index fe2152df69f4..08b54b1e5249 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi @@ -7,26 +7,26 @@ #include "ipq6018.dtsi" &cpu0 { - cpu-supply = <&ipq6018_s2>; + cpu-supply = <&mp5496_s2>; }; &cpu1 { - cpu-supply = <&ipq6018_s2>; + cpu-supply = <&mp5496_s2>; }; &cpu2 { - cpu-supply = <&ipq6018_s2>; + cpu-supply = <&mp5496_s2>; }; &cpu3 { - cpu-supply = <&ipq6018_s2>; + cpu-supply = <&mp5496_s2>; }; &rpm_requests { regulators { compatible = "qcom,rpm-mp5496-regulators"; - ipq6018_s2: s2 { + mp5496_s2: s2 { regulator-min-microvolt = <725000>; regulator-max-microvolt = <1062500>; regulator-always-on;