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Bottomley" , Peter Wang , Eric Biggers , Minwoo Im , Manivannan Sadhasivam , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 3/8] scsi: ufs: core: Add a vop to map clock frequency to gear speed Date: Mon, 10 Feb 2025 18:02:06 +0800 Message-Id: <20250210100212.855127-4-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210100212.855127-1-quic_ziqichen@quicinc.com> References: <20250210100212.855127-1-quic_ziqichen@quicinc.com> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 4967QLHuataWq97NPQO_uzdjAxAsCPTg X-Proofpoint-ORIG-GUID: 4967QLHuataWq97NPQO_uzdjAxAsCPTg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-10_05,2025-02-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502100084 From: Can Guo Add a vop to map UFS host controller clock frequencies to the corresponding maximum supported UFS high speed gear speeds. During clock scaling, we can map the target clock frequency, demanded by devfreq, to the maximum supported gear speed, so that devfreq can scale the gear to the highest gear speed supported at the target clock frequency, instead of just scaling up/down the gear between the min and max gear speeds. Co-developed-by: Ziqi Chen Signed-off-by: Ziqi Chen Signed-off-by: Can Guo Reviewed-by: Bean Huo Reviewed-by: Bart Van Assche Tested-by: Neil Armstrong --- v2 ->v3: 1. Remove the parameter 'gear' and use it as function return result. 2. Change "vops" into "vop" in commit message. --- drivers/ufs/core/ufshcd-priv.h | 8 ++++++++ include/ufs/ufshcd.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h index 0549b65f71ed..4da3e65c6735 100644 --- a/drivers/ufs/core/ufshcd-priv.h +++ b/drivers/ufs/core/ufshcd-priv.h @@ -277,6 +277,14 @@ static inline int ufshcd_mcq_vops_config_esi(struct ufs_hba *hba) return -EOPNOTSUPP; } +static inline int ufshcd_vops_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) +{ + if (hba->vops && hba->vops->freq_to_gear_speed) + return hba->vops->freq_to_gear_speed(hba, freq); + + return -EOPNOTSUPP; +} + extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; /** diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index f51d425696e7..cdb853f5b871 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -336,6 +336,7 @@ struct ufs_pwr_mode_info { * @get_outstanding_cqs: called to get outstanding completion queues * @config_esi: called to config Event Specific Interrupt * @config_scsi_dev: called to configure SCSI device parameters + * @freq_to_gear_speed: called to map clock frequency to the max supported gear speed */ struct ufs_hba_variant_ops { const char *name; @@ -387,6 +388,7 @@ struct ufs_hba_variant_ops { unsigned long *ocqs); int (*config_esi)(struct ufs_hba *hba); void (*config_scsi_dev)(struct scsi_device *sdev); + int (*freq_to_gear_speed)(struct ufs_hba *hba, unsigned long freq); }; /* clock gating state */ From patchwork Mon Feb 10 10:02:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziqi Chen X-Patchwork-Id: 864032 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE5AE1CCB4B; Mon, 10 Feb 2025 10:02:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739181771; cv=none; b=cZcK4KHexs90GMUjpSKTGv+EeLfUQ7T5kDGGG+NTo1DNTLPcS1lLr2/BQVJXoHg6Y8BqcncibO7UYUpad5JQZkfhjYX4xqMFcKg+zuRf6sKc6zYkNxtBTnrzrCpHWQxBE14/6KXWq3g0zL45yf9nuWpXd6e4ub2HGbtuKosO0no= ARC-Message-Signature: i=1; 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Bottomley" , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 4/8] scsi: ufs: qcom: Implement the freq_to_gear_speed() vop Date: Mon, 10 Feb 2025 18:02:07 +0800 Message-Id: <20250210100212.855127-5-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210100212.855127-1-quic_ziqichen@quicinc.com> References: <20250210100212.855127-1-quic_ziqichen@quicinc.com> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: qU4BuDNPTVEgmtZWv3XBgh0MFAQJbN9h X-Proofpoint-GUID: qU4BuDNPTVEgmtZWv3XBgh0MFAQJbN9h X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-10_05,2025-02-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 mlxlogscore=999 phishscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 adultscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502100084 From: Can Guo Implement the freq_to_gear_speed() vop to map the unipro core clock frequency to the corresponding maximum supported gear speed. Signed-off-by: Can Guo Co-developed-by: Ziqi Chen Signed-off-by: Ziqi Chen Reviewed-by: Bean Huo Tested-by: Neil Armstrong --- v1 -> v2: Print out freq and gear info as debugging message. v2 -> v3: 1. Change "vops" to "vop" in commit message. 2. Removed variable 'ret' in function ufs_qcom_freq_to_gear_speed(). 3. Removed parameters '*gear' and use gear value as return value for funtion ufs_qcom_freq_to_gear_speed(). --- drivers/ufs/host/ufs-qcom.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index a1eb3cab45e4..47c3077705d9 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1804,6 +1804,36 @@ static int ufs_qcom_config_esi(struct ufs_hba *hba) return ret; } +static int ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) +{ + int gear = 0; + + switch (freq) { + case 403000000: + gear = UFS_HS_G5; + break; + case 300000000: + gear = UFS_HS_G4; + break; + case 201500000: + gear = UFS_HS_G3; + break; + case 150000000: + case 100000000: + gear = UFS_HS_G2; + break; + case 75000000: + case 37500000: + gear = UFS_HS_G1; + break; + default: + dev_err(hba->dev, "%s: Unsupported clock freq : %lu\n", __func__, freq); + return -EINVAL; + } + + return gear; +} + /* * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations * @@ -1834,6 +1864,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { .op_runtime_config = ufs_qcom_op_runtime_config, .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, .config_esi = ufs_qcom_config_esi, + .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed, }; 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Mon, 10 Feb 2025 10:02:39 +0000 Received: from APTAIPPMTA01.qualcomm.com (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 51AA2dNo011697; Mon, 10 Feb 2025 10:02:39 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 51AA2cL6011695 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Feb 2025 10:02:39 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 393357) id 0B91540BF7; Mon, 10 Feb 2025 18:02:38 +0800 (CST) From: Ziqi Chen To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com, quic_ziqichen@quicinc.com, quic_nguyenb@quicinc.com, quic_nitirawa@quicinc.com, quic_rampraka@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, Neil Armstrong , Alim Akhtar , "James E.J. Bottomley" , Peter Wang , Manivannan Sadhasivam , Andrew Halaney , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 6/8] scsi: ufs: core: Check if scaling up is required when disable clkscale Date: Mon, 10 Feb 2025 18:02:09 +0800 Message-Id: <20250210100212.855127-7-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210100212.855127-1-quic_ziqichen@quicinc.com> References: <20250210100212.855127-1-quic_ziqichen@quicinc.com> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: H_jyycwSs6mXwUlnsvaehZDp4gc84zHO X-Proofpoint-ORIG-GUID: H_jyycwSs6mXwUlnsvaehZDp4gc84zHO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-10_05,2025-02-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 mlxscore=0 adultscore=0 spamscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502100084 When disabling clkscale via the clkscale_enable sysfs entry, UFS driver shall perform scaling up once regardless. Check if scaling up is required or not first to avoid repetitive work. Co-developed-by: Can Guo Signed-off-by: Can Guo Signed-off-by: Ziqi Chen Reviewed-by: Bart Van Assche Tested-by: Neil Armstrong --- drivers/ufs/core/ufshcd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index ebab897080a6..bd93119a177d 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -1777,6 +1777,10 @@ static ssize_t ufshcd_clkscale_enable_store(struct device *dev, freq = clki->max_freq; ufshcd_suspend_clkscaling(hba); + + if (!ufshcd_is_devfreq_scaling_required(hba, freq, true)) + goto out_rel; + err = ufshcd_devfreq_scale(hba, freq, true); if (err) dev_err(hba->dev, "%s: failed to scale clocks up %d\n", From patchwork Mon Feb 10 10:02:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ziqi Chen X-Patchwork-Id: 864029 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 752401E32BD; Mon, 10 Feb 2025 10:03:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739181789; cv=none; b=LpoCJGUuM1qktFlfMCh6BdwUTLkAGRitLu/uIyuLQUQ45YLwBObVVq1pIOb763ZtOViANuqzr70gApPF/6z44mLk6/ADKdXXtNtIN/isfrW6y795O9+wstBcsgqMe8U1FokkP6AGYgq8bI+VivWECFDMwO99qzahWhUWOSEm/P8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739181789; c=relaxed/simple; bh=EI18NcIKCnuMhNBX5qr5t3aERRB0/uQDwrnH2W1PyFk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=oWCCtMaZqJxyCgO1FNiQOIWJt1DDMzVhi7gKgGUyRFvi8LjdNhGJlCTpIoyjZbF33M05hnto1ap0UI6hfOkm2t5RXl/22dQja3fYVIqK8zwFZeTrz+UnPjWIxRoVTInSKPhJ7Ef98mfJV/TZPpuWX0ORFHzUE5F+9Bi75W6Uvvo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Tz//8fAS; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Tz//8fAS" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51A9p8AC018199; Mon, 10 Feb 2025 10:02:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= FxbfDse5WOybmMXuL95q47SDxJXP4H0yw1vLl+9WEXE=; b=Tz//8fASHeFEFdRq KxkXEO2dvB/44wFhEmOAx8i5IS6aU20A9xVfdq4se8K2mhDf1SOdA9ngx7GyF87G QczR57C6D0M8FiE2Q30Zje+/fyhjCp0kTbYHh/vuU73HpYRgY0pgzez+2XQfd0st Arj8yl9wEFkFR1JUMN9r/fBlaqL4dRNfbGpZsppRhY55lAHY6CdOp5SAjOnT/gaS eFFMekfLeD/5DbZKh++w55SqUd62LiJxpnejhRSMycIAgvCK96xd9sHt7i2GC8/H 3nvLMQHHJmdk8AqKpBrrrcgRRhkHLDHFhSV2J0EZyJDhdLuRzSUrhImmojW6ohG/ aaQwBw== Received: from aptaippmta02.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com [103.229.16.4]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44p0dxkxxk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Feb 2025 10:02:48 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 51AA2Ha6011341; Mon, 10 Feb 2025 10:02:45 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 44p0bkhyk9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Feb 2025 10:02:45 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 51AA2jPr011430; Mon, 10 Feb 2025 10:02:45 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 51AA2ils011429 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Feb 2025 10:02:45 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 393357) id EC00A40BF7; Mon, 10 Feb 2025 18:02:43 +0800 (CST) From: Ziqi Chen To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com, quic_ziqichen@quicinc.com, quic_nguyenb@quicinc.com, quic_nitirawa@quicinc.com, quic_rampraka@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, Neil Armstrong , Alim Akhtar , "James E.J. Bottomley" , Peter Wang , Manivannan Sadhasivam , Andrew Halaney , Eric Biggers , Minwoo Im , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 7/8] scsi: ufs: core: Toggle Write Booster during clock scaling base on gear speed Date: Mon, 10 Feb 2025 18:02:10 +0800 Message-Id: <20250210100212.855127-8-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210100212.855127-1-quic_ziqichen@quicinc.com> References: <20250210100212.855127-1-quic_ziqichen@quicinc.com> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: sSQlad2BTlIyI63jAXbUEGmYMx_-44TD X-Proofpoint-ORIG-GUID: sSQlad2BTlIyI63jAXbUEGmYMx_-44TD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-10_05,2025-02-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxscore=0 phishscore=0 suspectscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502100084 From: Can Guo During clock scaling, Write Booster is toggled on or off based on whether the clock is scaled up or down. However, with OPP V2 powered multi-level gear scaling, the gear can be scaled amongst multiple gear speeds, e.g., it may scale down from G5 to G4, or from G4 to G2. To provide flexibilities, add a new field for clock scaling such that during clock scaling Write Booster can be enabled or disabled based on gear speeds but not based on scaling up or down. Signed-off-by: Can Guo Co-developed-by: Ziqi Chen Signed-off-by: Ziqi Chen Reviewed-by: Bean Huo Tested-by: Neil Armstrong --- v1 - > v2: Initialize the local variables "wb_en" as "false". v3 -> v4: 1. Add comment for default initialized wb_gear. 2. Remove the unnecessary variable “wb_en" in function ufshcd_clock_scaling_unprepare(). --- drivers/ufs/core/ufshcd.c | 12 ++++++++---- include/ufs/ufshcd.h | 3 +++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index bd93119a177d..1276f4a987bd 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -1393,13 +1393,13 @@ static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us) return ret; } -static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up) +static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err) { up_write(&hba->clk_scaling_lock); - /* Enable Write Booster if we have scaled up else disable it */ + /* Enable Write Booster if current gear requires it else disable it */ if (ufshcd_enable_wb_if_scaling_up(hba) && !err) - ufshcd_wb_toggle(hba, scale_up); + ufshcd_wb_toggle(hba, hba->pwr_info.gear_rx >= hba->clk_scaling.wb_gear); mutex_unlock(&hba->wb_mutex); @@ -1461,7 +1461,7 @@ static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq, } out_unprepare: - ufshcd_clock_scaling_unprepare(hba, ret, scale_up); + ufshcd_clock_scaling_unprepare(hba, ret); return ret; } @@ -1821,6 +1821,10 @@ static void ufshcd_init_clk_scaling(struct ufs_hba *hba) if (!hba->clk_scaling.min_gear) hba->clk_scaling.min_gear = UFS_HS_G1; + if (!hba->clk_scaling.wb_gear) + /* Use intermediate gear speed HS_G3 as the default wb_gear */ + hba->clk_scaling.wb_gear = UFS_HS_G3; + INIT_WORK(&hba->clk_scaling.suspend_work, ufshcd_clk_scaling_suspend_work); INIT_WORK(&hba->clk_scaling.resume_work, diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index cdb853f5b871..efca700d0520 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -447,6 +447,8 @@ struct ufs_clk_gating { * @resume_work: worker to resume devfreq * @target_freq: frequency requested by devfreq framework * @min_gear: lowest HS gear to scale down to + * @wb_gear: enable Write Booster when HS gear scales above or equal to it, else + * disable Write Booster * @is_enabled: tracks if scaling is currently enabled or not, controlled by * clkscale_enable sysfs node * @is_allowed: tracks if scaling is currently allowed or not, used to block @@ -467,6 +469,7 @@ struct ufs_clk_scaling { struct work_struct resume_work; unsigned long target_freq; u32 min_gear; + u32 wb_gear; bool is_enabled; bool is_allowed; bool is_initialized;