From patchwork Tue Feb 11 22:37:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QmFybmFiw6FzIEN6w6ltw6Fu?= X-Patchwork-Id: 864162 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C09AF268FC2; Tue, 11 Feb 2025 22:38:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739313497; cv=none; b=DEiPIdI8OX1jXv/WytOGKHywNDSHrLpAl0aiCPhz/mPeW98Cax6azoMyE0v3KSToX4k6uSl/XIQSzYCoxaq2kRUOiMlsGE6q35ZM0v89JebiQv6c0jJaJS26Olx8iOusR0DqOgkicaDHc1ZmBRdzWcJf2X+Crwx5r4D7VGUTfo8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739313497; c=relaxed/simple; bh=jmyK6OmAW4qYROU6mafw3Xc/B3JfTXW89rYfmgZBrUM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rNOn78U+Re0JIDmPhMTtFKDZ0HVX9wOme1cIJs9hVnYXCSfDXCdCMO0x9Z8S7LYVDP0PtALLISrw1o5VPz1CRrrKSMQwgEu2Ls7KVQ4n4M7L7Ui+zJ0LvyM5wy3/vBvBWgoNa6doNMtDXDV3iWUDxijrC2tIlEdpWVUn/WnidMM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=qeFFQ0zF; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="qeFFQ0zF" Received: from [192.168.244.162] (254C21CD.nat.pool.telekom.hu [37.76.33.205]) by mail.mainlining.org (Postfix) with ESMTPSA id ABE57E453A; Tue, 11 Feb 2025 22:38:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1739313487; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YpI4LDOINdeyIvkPaxY9t9lhB+DY2CS2HQIavrdvgdw=; b=qeFFQ0zFJ49j/KL/CLyJT7gBDrYgLuuHFW85mt7URcN2k04oG4WjHdqWIZlGBdgo7Yx1SW L4InU+VVShDxGCxJODiQuf5bnTsuaJe7732zOakbFeXG6t18FwWuxoClRNRdDc3z/zhBFd +aWPkgeAZE5qxYmimDt0s828dzUvkLF10a66O4zAJuAjDb4VQkqAAyf+1aiZcJrg+pM8xf VJeR9DdOmBva03YF3CjLgiIbakGKOxx7ugdG6WAttlDJK85fnw/ztX+KsgIR6TQyIdDfuY wW2E3AQHtiLHc8JaqAswD759vYvnuNDt2av9+Z7CdRREsqgYQtJzHH+g7FPDzw== From: =?utf-8?b?QmFybmFiw6FzIEN6w6ltw6Fu?= Date: Tue, 11 Feb 2025 23:37:45 +0100 Subject: [PATCH 01/10] dt-bindings: clock: gcc-msm8917: Split to separate schema Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250211-msm8937-v1-1-7d27ed67f708@mainlining.org> References: <20250211-msm8937-v1-0-7d27ed67f708@mainlining.org> In-Reply-To: <20250211-msm8937-v1-0-7d27ed67f708@mainlining.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephan Gerhold , =?utf-8?q?Otto_Pfl=C3=BCger?= , Linus Walleij , Lee Jones , Srinivas Kandagatla , Joerg Roedel , Will Deacon , Robin Murphy , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?b?QmFybmFiw6Fz?= =?utf-8?b?IEN6w6ltw6Fu?= , Daniil Titov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739313484; l=3709; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=HvgoiBX4M/pokAv1+f2Nk5xpaoeVGWOJhvn5e5Pbucg=; b=3R2/vaiVoJ6mof98/3ib2TxRX47spduj6OYzUAfcerShpoVoEtqx6NlCWPVT08I4qC5HzBdNp ZZGng50sXhCDTMQIOg0u6o5kKmH4kZNAH7sYe9F3m+rRdU8+CKgYr7x X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Daniil Titov The Qualcomm MSM8917 Global Clock controller after adding support for new SoCs has different clock inputs, thus existing qcom,gcc-msm8909.yaml was not describing it fully. Move the binding to it's own schema file and document the clocks based on DTS. Add driver contributors as it's maintainers. Signed-off-by: Daniil Titov Signed-off-by: Barnabás Czémán --- .../bindings/clock/qcom,gcc-msm8909.yaml | 10 ++-- .../bindings/clock/qcom,gcc-msm8917.yaml | 59 ++++++++++++++++++++++ 2 files changed, 62 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml index ce1f5a60bd8c9dfe60a791881868337d3e1723df..5a4ff4f78d4e1d9ecdc06ec171f9b126194e3bc4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml @@ -4,25 +4,21 @@ $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Global Clock & Reset Controller on MSM8909, MSM8917 and QM215 +title: Qualcomm Global Clock & Reset Controller on MSM8909 maintainers: - Stephan Gerhold description: | Qualcomm global clock control module provides the clocks, resets and power - domains on MSM8909, MSM8917 or QM215. + domains on MSM8909. - See also:: - include/dt-bindings/clock/qcom,gcc-msm8909.h - include/dt-bindings/clock/qcom,gcc-msm8917.h + See also:: include/dt-bindings/clock/qcom,gcc-msm8909.h properties: compatible: enum: - qcom,gcc-msm8909 - - qcom,gcc-msm8917 - - qcom,gcc-qm215 clocks: items: diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8917.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8917.yaml new file mode 100644 index 0000000000000000000000000000000000000000..6e567b2a5153af9bb32958154633d6da5fd1cd50 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8917.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8917.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on MSM8917 and QM215 + +maintainers: + - Otto Pflüger + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on MSM8917 or QM215. + + See also:: include/dt-bindings/clock/qcom,gcc-msm8917.h + +properties: + compatible: + enum: + - qcom,gcc-msm8917 + - qcom,gcc-qm215 + + clocks: + items: + - description: XO source + - description: Sleep clock source + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: dsi0pll + - const: dsi0pllbyte + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-msm8917"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&xo_board>, <&sleep_clk>, <&dsi0_phy 1>, <&dsi0_phy 0>; + clock-names = "xo", "sleep_clk", "dsi0pll", "dsi0pllbyte"; + }; +... From patchwork Tue Feb 11 22:37:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QmFybmFiw6FzIEN6w6ltw6Fu?= X-Patchwork-Id: 864161 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62F6326A08B; Tue, 11 Feb 2025 22:38:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739313499; cv=none; b=XvmABXRMbnbk1CbSAuV979E64BQ7++KPTFjpsoi7qNMuxXOjcjb2SnpbB1F01XKGiaqVVYyPwywmtrTwr0TlZpScKwpar1zLD5NBfj/KgJNwBfv5W5nr0XrscUVgWCZ6WiPhFB722JSQt15jBM6SHKpk6cMLstBxCENBBoS8aIo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739313499; c=relaxed/simple; bh=kTovJs3a0UNCe/c9EpjLatpkIpZCGVIT/AOKQ3UWCOE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cnxYud/auEWOsGNge3yhCRvpSCWWEPogv+D8n8pAyScRySGHZqqkwVxgE7OZwSuFABaYRvG/6b0sXAc54jVPRjnb+hCAo2/FNOJ/9aU2WYOKxSMMNpA51K5KrUsZk+6hnndrKSrJ98Ks24tbVjLWcAXkBQsrqZ1RO/s4jHUucmk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=lkDcU1R1; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="lkDcU1R1" Received: from [192.168.244.162] (254C21CD.nat.pool.telekom.hu [37.76.33.205]) by mail.mainlining.org (Postfix) with ESMTPSA id 82AE1E453B; Tue, 11 Feb 2025 22:38:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1739313489; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=E8/ajVjMHyCO8T9Hq+plvxZcT5GFd9UYD9UL7qcPwfY=; b=lkDcU1R1RPH4LwvEF6jTh8oYqu7Qyz6OGPXB++1vsuPu5EYmWq4Yfx8u4B3PnNYpwOy0HW yia94aZPYIexLjMdEumPwiwf7mn5/EHvKI/DnS5v3If0JByPC4rbPKBZX85Uu8xksKSOEa eZTxePgiL3XHHe2McCjYvGpFbdDO4ujjsyA0fHZ/YiYLydA7Pk/Bqpw/EwKZl3wYN7O2kh xAqqF3eMi7OUROinXNzaclhgOi3ekZDDLvz7cpe4UXoxFcjtkITGm8zVkPU/4OUA52SwCV A5B+p7+pTcOm22ZJ+Xxsb2JDCXV+8/fbmgmCoFAP0yKYNaLaaDrUy2lojUGYBQ== From: =?utf-8?b?QmFybmFiw6FzIEN6w6ltw6Fu?= Date: Tue, 11 Feb 2025 23:37:46 +0100 Subject: [PATCH 02/10] dt-bindings: clock: Add MSM8937 Global Clock controller compatible Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250211-msm8937-v1-2-7d27ed67f708@mainlining.org> References: <20250211-msm8937-v1-0-7d27ed67f708@mainlining.org> In-Reply-To: <20250211-msm8937-v1-0-7d27ed67f708@mainlining.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephan Gerhold , =?utf-8?q?Otto_Pfl=C3=BCger?= , Linus Walleij , Lee Jones , Srinivas Kandagatla , Joerg Roedel , Will Deacon , Robin Murphy , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?b?QmFybmFiw6Fz?= =?utf-8?b?IEN6w6ltw6Fu?= , Daniil Titov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739313484; l=3960; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=tMkGJGxDIeGByyVrfX+6woLjEpGaWkEndc230QD+arY=; b=zMBOHa8FKmVRlT19Kzal0uTME3fxFcs0Xg3Bq2yUqSMhiKgHfDxxV+glaclJ8qdY3h4GFDSei tyOlHv2S2TSDagd6GEL8gaPRr4Y7mRoKCxvM6QjL5USij3QwnsnyGM4 X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Daniil Titov Document the qcom,gcc-msm8937 compatible and add new input clocks. Signed-off-by: Daniil Titov Signed-off-by: Barnabás Czémán --- .../bindings/clock/qcom,gcc-msm8917.yaml | 23 ++++++++++++++++++---- include/dt-bindings/clock/qcom,gcc-msm8917.h | 17 ++++++++++++++++ 2 files changed, 36 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8917.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8917.yaml index 6e567b2a5153af9bb32958154633d6da5fd1cd50..689c5760d9cd1fc96d97e5705cd1fcd48324433a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8917.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8917.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8917.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Global Clock & Reset Controller on MSM8917 and QM215 +title: Qualcomm Global Clock & Reset Controller on MSM8917, MSM8937 and QM215 maintainers: - Otto Pflüger description: | Qualcomm global clock control module provides the clocks, resets and power - domains on MSM8917 or QM215. + domains on MSM8917, MSM8937 or QM215. See also:: include/dt-bindings/clock/qcom,gcc-msm8917.h @@ -20,6 +20,7 @@ properties: enum: - qcom,gcc-msm8917 - qcom,gcc-qm215 + - qcom,gcc-msm8937 clocks: items: @@ -27,6 +28,8 @@ properties: - description: Sleep clock source - description: DSI phy instance 0 dsi clock - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock clock-names: items: @@ -34,6 +37,8 @@ properties: - const: sleep_clk - const: dsi0pll - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte required: - compatible @@ -53,7 +58,17 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clocks = <&xo_board>, <&sleep_clk>, <&dsi0_phy 1>, <&dsi0_phy 0>; - clock-names = "xo", "sleep_clk", "dsi0pll", "dsi0pllbyte"; + clocks = <&xo_board>, + <&sleep_clk>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>; + clock-names = "xo", + "sleep", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte"; }; ... diff --git a/include/dt-bindings/clock/qcom,gcc-msm8917.h b/include/dt-bindings/clock/qcom,gcc-msm8917.h index 4b421e7414b50bef2e2400f868ae5b7212a427bb..ec1f0b261dd5ccfe4896a00ffa9cf86de98b9cb3 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8917.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8917.h @@ -170,6 +170,22 @@ #define VFE1_CLK_SRC 163 #define VSYNC_CLK_SRC 164 #define GPLL0_SLEEP_CLK_SRC 165 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 166 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 167 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 168 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 169 +#define BYTE1_CLK_SRC 170 +#define ESC1_CLK_SRC 171 +#define PCLK1_CLK_SRC 172 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 173 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 174 +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 175 +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 176 +#define GCC_MDSS_BYTE1_CLK 177 +#define GCC_MDSS_ESC1_CLK 178 +#define GCC_MDSS_PCLK1_CLK 179 +#define GCC_OXILI_AON_CLK 180 +#define GCC_OXILI_TIMER_CLK 181 /* GCC block resets */ #define GCC_CAMSS_MICRO_BCR 0 @@ -187,5 +203,6 @@ #define VENUS_GDSC 5 #define VFE0_GDSC 6 #define VFE1_GDSC 7 +#define OXILI_CX_GDSC 8 #endif From patchwork Tue Feb 11 22:37:47 2025 Content-Type: text/plain; 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a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1739313491; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+V5vUgXkJSNNfUlBjoGkeWN9tX8d45HdvDrrEGICyT8=; b=MgquUGl50ey3mTcbqUpTqOeSzw+J9m4gu0g47Ix3tt/hCC2oag08QxH7MNiScNy98qEnmx CgpYpheqok7wKS7Gyp8we+b8seIEvLpohKP9LDnBUBk/YsK2dFACuCHbnYLG1QWkutqCpj 64KzLxYCqJuoJ32RjvaZsDB6NctDGqLMccgcnvAc/wFozLG2CsXkKcbFaetUtflu9C8tJm yTTCnJrvntRcsTRV2p9IHY/TICL+Pxt7uJi2WoEydVEb6Cxn5tUgwFlQ9QCU0gHZ0+/76s ChTUR9cw7IHznUGXqllXgsuVKz8RR42hZ3xKJ48zPNp1b6f1iaKMj5jQynYI7w== From: =?utf-8?b?QmFybmFiw6FzIEN6w6ltw6Fu?= Date: Tue, 11 Feb 2025 23:37:47 +0100 Subject: [PATCH 03/10] clk: qcom: gcc: Add support for Global Clock controller found on MSM8937 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250211-msm8937-v1-3-7d27ed67f708@mainlining.org> References: <20250211-msm8937-v1-0-7d27ed67f708@mainlining.org> In-Reply-To: <20250211-msm8937-v1-0-7d27ed67f708@mainlining.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephan Gerhold , =?utf-8?q?Otto_Pfl=C3=BCger?= , Linus Walleij , Lee Jones , Srinivas Kandagatla , Joerg Roedel , Will Deacon , Robin Murphy , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?b?QmFybmFiw6Fz?= =?utf-8?b?IEN6w6ltw6Fu?= , Daniil Titov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739313484; l=30434; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=HmV0DhQNC60RKOB6+hVCTEwtgYq381AdPv/PyjAZgMI=; b=TNw/r8q/xKHfDVB120vYJuioLP62gat7ufrzX5Nj+kvEpzfudcIXe6eo7+j1fx1Weolxv0kEu 0utZaYwHbj4Bo/SZHrDwGvrecT9y6uZAVU9+k6rvtvmJJDag2Fk5der X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Daniil Titov Modify existing MSM8917 driver to support MSM8937 SoC. Override frequencies which are different in this chip. Register all the clocks to the framework for the clients to be able to request for them. Add new variant of GDSC for new chip. Signed-off-by: Daniil Titov Signed-off-by: Barnabás Czémán --- drivers/clk/qcom/Kconfig | 6 +- drivers/clk/qcom/gcc-msm8917.c | 617 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 616 insertions(+), 7 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 69bbf62ba3cd7b8d1cb2bb784416ac0e5fdbf9e3..3a04b11d34c41d16fc0941f6615237e626226ed1 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -316,12 +316,12 @@ config MSM_GCC_8916 SD/eMMC, display, graphics, camera etc. config MSM_GCC_8917 - tristate "MSM8917/QM215 Global Clock Controller" + tristate "MSM89(17/37)/QM215 Global Clock Controller" depends on ARM64 || COMPILE_TEST select QCOM_GDSC help - Support for the global clock controller on msm8917 and qm215 - devices. + Support for the global clock controller on msm8917, msm8937 + and qm215 devices. Say Y if you want to use devices such as UART, SPI i2c, USB, SD/eMMC, display, graphics, camera etc. diff --git a/drivers/clk/qcom/gcc-msm8917.c b/drivers/clk/qcom/gcc-msm8917.c index 3e2a2ae2ee6e9e647fb68c493ae7b0e49af79968..54b9df0a561084f43942fc50386ccb74cbd40417 100644 --- a/drivers/clk/qcom/gcc-msm8917.c +++ b/drivers/clk/qcom/gcc-msm8917.c @@ -37,6 +37,8 @@ enum { DT_SLEEP_CLK, DT_DSI0PLL, DT_DSI0PLL_BYTE, + DT_DSI1PLL, + DT_DSI1PLL_BYTE, }; enum { @@ -48,6 +50,8 @@ enum { P_GPLL6, P_DSI0PLL, P_DSI0PLL_BYTE, + P_DSI1PLL, + P_DSI1PLL_BYTE, }; static struct clk_alpha_pll gpll0_sleep_clk_src = { @@ -102,7 +106,11 @@ static const struct pll_vco gpll3_p_vco[] = { { 700000000, 1400000000, 0 }, }; -static const struct alpha_pll_config gpll3_early_config = { +static const struct pll_vco gpll3_p_vco_msm8937[] = { + { 525000000, 1066000000, 0 }, +}; + +static struct alpha_pll_config gpll3_early_config = { .l = 63, .config_ctl_val = 0x4001055b, .early_output_mask = 0, @@ -273,6 +281,19 @@ static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = { { } }; +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { + .cmd_rcgr = 0x0200c, + .hid_width = 5, + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0_data, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), + .ops = &clk_rcg2_ops, + }, +}; + static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .cmd_rcgr = 0x03000, .hid_width = 5, @@ -351,6 +372,19 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { } }; +static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { + .cmd_rcgr = 0x18000, + .hid_width = 5, + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup4_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0_data, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), + .ops = &clk_rcg2_ops, + }, +}; + static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = { F(960000, P_XO, 10, 1, 2), F(4800000, P_XO, 4, 0, 0), @@ -362,6 +396,20 @@ static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = { { } }; +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { + .cmd_rcgr = 0x02024, + .mnd_width = 8, + .hid_width = 5, + .freq_tbl = ftbl_blsp_spi_apps_clk_src, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0_data, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), + .ops = &clk_rcg2_ops, + }, +}; + static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .cmd_rcgr = 0x03014, .hid_width = 5, @@ -446,6 +494,20 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { } }; +static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { + .cmd_rcgr = 0x18024, + .mnd_width = 8, + .hid_width = 5, + .freq_tbl = ftbl_blsp_spi_apps_clk_src, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup4_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0_data, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), + .ops = &clk_rcg2_ops, + }, +}; + static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = { F(3686400, P_GPLL0, 1, 72, 15625), F(7372800, P_GPLL0, 1, 144, 15625), @@ -525,11 +587,19 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = { static const struct parent_map gcc_byte0_map[] = { { P_XO, 0 }, { P_DSI0PLL_BYTE, 1 }, + { P_DSI1PLL_BYTE, 3 }, +}; + +static const struct parent_map gcc_byte1_map[] = { + { P_XO, 0 }, + { P_DSI0PLL_BYTE, 3 }, + { P_DSI1PLL_BYTE, 1 }, }; static const struct clk_parent_data gcc_byte_data[] = { { .index = DT_XO }, { .index = DT_DSI0PLL_BYTE }, + { .index = DT_DSI1PLL_BYTE }, }; static struct clk_rcg2 byte0_clk_src = { @@ -545,6 +615,19 @@ static struct clk_rcg2 byte0_clk_src = { } }; +static struct clk_rcg2 byte1_clk_src = { + .cmd_rcgr = 0x4d0b0, + .hid_width = 5, + .parent_map = gcc_byte1_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "byte1_clk_src", + .parent_data = gcc_byte_data, + .num_parents = ARRAY_SIZE(gcc_byte_data), + .ops = &clk_byte2_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + static const struct freq_tbl ftbl_camss_gp_clk_src[] = { F(100000000, P_GPLL0, 8, 0, 0), F(160000000, P_GPLL0, 5, 0, 0), @@ -642,6 +725,17 @@ static const struct freq_tbl ftbl_cpp_clk_src[] = { { } }; +static const struct freq_tbl ftbl_cpp_clk_src_msm8937[] = { + F(133330000, P_GPLL0, 6, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(200000000, P_GPLL0, 5, 0, 0), + F(266666667, P_GPLL0, 3, 0, 0), + F(308570000, P_GPLL6, 3.5, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), + F(360000000, P_GPLL6, 3, 0, 0), + { } +}; + static struct clk_rcg2 cpp_clk_src = { .cmd_rcgr = 0x58018, .hid_width = 5, @@ -655,6 +749,13 @@ static struct clk_rcg2 cpp_clk_src = { } }; +static struct clk_init_data vcodec0_clk_src_init_msm8937 = { + .name = "vcodec0_clk_src", + .parent_data = gcc_cpp_data, + .num_parents = ARRAY_SIZE(gcc_cpp_data), + .ops = &clk_rcg2_ops, +}; + static const struct freq_tbl ftbl_crypto_clk_src[] = { F(50000000, P_GPLL0, 16, 0, 0), F(80000000, P_GPLL0, 10, 0, 0), @@ -730,6 +831,13 @@ static const struct freq_tbl ftbl_csi_phytimer_clk_src[] = { { } }; +static const struct freq_tbl ftbl_csi_phytimer_clk_src_msm8937[] = { + F(100000000, P_GPLL0, 8, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + { } +}; + static struct clk_rcg2 csi0phytimer_clk_src = { .cmd_rcgr = 0x4e000, .hid_width = 5, @@ -774,6 +882,19 @@ static struct clk_rcg2 esc0_clk_src = { } }; +static struct clk_rcg2 esc1_clk_src = { + .cmd_rcgr = 0x4d0a8, + .hid_width = 5, + .freq_tbl = ftbl_esc0_1_clk_src, + .parent_map = gcc_xo_gpll0_out_aux_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "esc1_clk_src", + .parent_data = gcc_xo_gpll0_data, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), + .ops = &clk_rcg2_ops, + }, +}; + static const struct parent_map gcc_gfx3d_map[] = { { P_XO, 0 }, { P_GPLL0, 1 }, @@ -817,6 +938,25 @@ static const struct freq_tbl ftbl_gfx3d_clk_src[] = { { } }; +static const struct freq_tbl ftbl_gfx3d_clk_src_msm8937[] = { + F(19200000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0, 16, 0, 0), + F(80000000, P_GPLL0, 10, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(216000000, P_GPLL6, 5, 0, 0), + F(228570000, P_GPLL0, 3.5, 0, 0), + F(240000000, P_GPLL6, 4.5, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), + F(300000000, P_GPLL3, 1, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), + F(375000000, P_GPLL3, 1, 0, 0), + F(400000000, P_GPLL0, 2, 0, 0), + F(450000000, P_GPLL3, 1, 0, 0), + { } +}; + static struct clk_rcg2 gfx3d_clk_src = { .cmd_rcgr = 0x59000, .hid_width = 5, @@ -973,21 +1113,29 @@ static struct clk_rcg2 mdp_clk_src = { } }; -static const struct parent_map gcc_pclk_map[] = { +static const struct parent_map gcc_pclk0_map[] = { { P_XO, 0 }, { P_DSI0PLL, 1 }, + { P_DSI1PLL, 3 }, +}; + +static const struct parent_map gcc_pclk1_map[] = { + { P_XO, 0 }, + { P_DSI0PLL, 3 }, + { P_DSI1PLL, 1 }, }; static const struct clk_parent_data gcc_pclk_data[] = { { .index = DT_XO }, { .index = DT_DSI0PLL }, + { .index = DT_DSI1PLL }, }; static struct clk_rcg2 pclk0_clk_src = { .cmd_rcgr = 0x4d000, .hid_width = 5, .mnd_width = 8, - .parent_map = gcc_pclk_map, + .parent_map = gcc_pclk0_map, .clkr.hw.init = &(struct clk_init_data) { .name = "pclk0_clk_src", .parent_data = gcc_pclk_data, @@ -997,6 +1145,20 @@ static struct clk_rcg2 pclk0_clk_src = { } }; +static struct clk_rcg2 pclk1_clk_src = { + .cmd_rcgr = 0x4d0b8, + .hid_width = 5, + .mnd_width = 8, + .parent_map = gcc_pclk1_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pclk1_clk_src", + .parent_data = gcc_pclk_data, + .num_parents = ARRAY_SIZE(gcc_pclk_data), + .ops = &clk_pixel_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + static const struct freq_tbl ftbl_pdm2_clk_src[] = { F(64000000, P_GPLL0, 12.5, 0, 0), { } @@ -1108,6 +1270,14 @@ static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = { { } }; +static const struct freq_tbl ftbl_usb_hs_system_clk_src_msm8937[] = { + F(57142857, P_GPLL0, 14, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(133333333, P_GPLL0, 6, 0, 0), + F(177777778, P_GPLL0, 4.5, 0, 0), + { } +}; + static struct clk_rcg2 usb_hs_system_clk_src = { .cmd_rcgr = 0x41010, .hid_width = 5, @@ -1132,6 +1302,15 @@ static const struct freq_tbl ftbl_vcodec0_clk_src[] = { { } }; +static const struct freq_tbl ftbl_vcodec0_clk_src_msm8937[] = { + F(166150000, P_GPLL6, 6.5, 0, 0), + F(240000000, P_GPLL6, 4.5, 0, 0), + F(308571428, P_GPLL6, 3.5, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), + F(360000000, P_GPLL6, 3, 0, 0), + { } +}; + static struct clk_rcg2 vcodec0_clk_src = { .cmd_rcgr = 0x4c000, .hid_width = 5, @@ -1160,6 +1339,23 @@ static const struct freq_tbl ftbl_vfe_clk_src[] = { { } }; +static const struct freq_tbl ftbl_vfe_clk_src_msm8937[] = { + F(50000000, P_GPLL0, 16, 0, 0), + F(80000000, P_GPLL0, 10, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(133333333, P_GPLL0, 6, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(177777778, P_GPLL0, 4.5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(266666667, P_GPLL0, 3, 0, 0), + F(308571428, P_GPLL6, 3.5, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), + F(360000000, P_GPLL6, 3, 0, 0), + F(400000000, P_GPLL0, 2, 0, 0), + F(432000000, P_GPLL6, 2.5, 0, 0), + { } +}; + static struct clk_rcg2 vfe0_clk_src = { .cmd_rcgr = 0x58000, .hid_width = 5, @@ -1269,6 +1465,24 @@ static struct clk_branch gcc_blsp2_ahb_clk = { } }; +static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { + .halt_reg = 0x02008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x02008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_i2c_apps_clk", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup1_i2c_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { .halt_reg = 0x03010, .halt_check = BRANCH_HALT, @@ -1377,6 +1591,42 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { } }; +static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { + .halt_reg = 0x18020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x18020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup4_i2c_apps_clk", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup4_i2c_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { + .halt_reg = 0x02004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x02004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_spi_apps_clk", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup1_spi_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { .halt_reg = 0x0300c, .halt_check = BRANCH_HALT, @@ -1485,6 +1735,24 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { } }; +static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { + .halt_reg = 0x1801c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1801c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup4_spi_apps_clk", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup4_spi_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_branch gcc_blsp1_uart1_apps_clk = { .halt_reg = 0x0203c, .halt_check = BRANCH_HALT, @@ -2521,6 +2789,24 @@ static struct clk_branch gcc_mdss_byte0_clk = { } }; +static struct clk_branch gcc_mdss_byte1_clk = { + .halt_reg = 0x4d0a0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4d0a0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mdss_byte1_clk", + .parent_hws = (const struct clk_hw*[]){ + &byte1_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_branch gcc_mdss_esc0_clk = { .halt_reg = 0x4d098, .halt_check = BRANCH_HALT, @@ -2539,6 +2825,24 @@ static struct clk_branch gcc_mdss_esc0_clk = { } }; +static struct clk_branch gcc_mdss_esc1_clk = { + .halt_reg = 0x4d09c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4d09c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mdss_esc1_clk", + .parent_hws = (const struct clk_hw*[]){ + &esc1_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_branch gcc_mdss_mdp_clk = { .halt_reg = 0x4d088, .halt_check = BRANCH_HALT, @@ -2575,6 +2879,24 @@ static struct clk_branch gcc_mdss_pclk0_clk = { } }; +static struct clk_branch gcc_mdss_pclk1_clk = { + .halt_reg = 0x4d0a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4d0a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mdss_pclk1_clk", + .parent_hws = (const struct clk_hw*[]){ + &pclk1_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_branch gcc_mdss_vsync_clk = { .halt_reg = 0x4d090, .halt_check = BRANCH_HALT, @@ -2632,6 +2954,24 @@ static struct clk_branch gcc_oxili_ahb_clk = { } }; +static struct clk_branch gcc_oxili_aon_clk = { + .halt_reg = 0x5904c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5904c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_oxili_aon_clk", + .parent_hws = (const struct clk_hw*[]){ + &gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_branch gcc_oxili_gfx3d_clk = { .halt_reg = 0x59020, .halt_check = BRANCH_HALT, @@ -2650,6 +2990,19 @@ static struct clk_branch gcc_oxili_gfx3d_clk = { } }; +static struct clk_branch gcc_oxili_timer_clk = { + .halt_reg = 0x59040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x59040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_oxili_timer_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pdm2_clk = { .halt_reg = 0x4400c, .halt_check = BRANCH_HALT, @@ -3027,6 +3380,28 @@ static struct gdsc oxili_gx_gdsc = { .flags = CLAMP_IO, }; +static struct gdsc oxili_gx_gdsc_msm8937 = { + .gdscr = 0x5901c, + .clamp_io_ctrl = 0x5b00c, + .cxcs = (unsigned int []){ 0x59000 }, + .cxc_count = 1, + .pd = { + .name = "oxili_gx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO, +}; + +static struct gdsc oxili_cx_gdsc = { + .gdscr = 0x59044, + .cxcs = (unsigned int []){ 0x59020 }, + .cxc_count = 1, + .pd = { + .name = "oxili_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct gdsc cpp_gdsc = { .gdscr = 0x58078, .cxcs = (unsigned int []){ 0x5803c, 0x58064 }, @@ -3207,6 +3582,188 @@ static struct clk_regmap *gcc_msm8917_clocks[] = { [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr, }; +static struct clk_regmap *gcc_msm8937_clocks[] = { + [GPLL0] = &gpll0.clkr, + [GPLL0_EARLY] = &gpll0_early.clkr, + [GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr, + [GPLL3] = &gpll3.clkr, + [GPLL3_EARLY] = &gpll3_early.clkr, + [GPLL4] = &gpll4.clkr, + [GPLL4_EARLY] = &gpll4_early.clkr, + [GPLL6] = &gpll6, + [GPLL6_EARLY] = &gpll6_early.clkr, + [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, + [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, + [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, + [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, + [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, + [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, + [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, + [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, + [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, + [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, + [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, + [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, + [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, + [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, + [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, + [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, + [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, + [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, + [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, + [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, + [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, + [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, + [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, + [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, + [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, + [CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr, + [CCI_CLK_SRC] = &cci_clk_src.clkr, + [CPP_CLK_SRC] = &cpp_clk_src.clkr, + [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr, + [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, + [CSI0_CLK_SRC] = &csi0_clk_src.clkr, + [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, + [CSI1_CLK_SRC] = &csi1_clk_src.clkr, + [CSI2_CLK_SRC] = &csi2_clk_src.clkr, + [ESC0_CLK_SRC] = &esc0_clk_src.clkr, + [ESC1_CLK_SRC] = &esc1_clk_src.clkr, + [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, + [GP1_CLK_SRC] = &gp1_clk_src.clkr, + [GP2_CLK_SRC] = &gp2_clk_src.clkr, + [GP3_CLK_SRC] = &gp3_clk_src.clkr, + [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, + [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, + [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, + [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, + [MDP_CLK_SRC] = &mdp_clk_src.clkr, + [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, + [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, + [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, + [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, + [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr, + [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, + [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, + [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, + [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, + [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, + [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, + [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, + [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, + [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr, + [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, + [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, + [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, + [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, + [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, + [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, + [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, + [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, + [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, + [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, + [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, + [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr, + [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr, + [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr, + [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr, + [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr, + [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, + [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr, + [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr, + [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr, + [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr, + [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr, + [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, + [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr, + [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr, + [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr, + [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr, + [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr, + [GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr, + [GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr, + [GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr, + [GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr, + [GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr, + [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr, + [GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr, + [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr, + [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr, + [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr, + [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr, + [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr, + [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr, + [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, + [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, + [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, + [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr, + [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, + [GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr, + [GCC_CAMSS_VFE0_AXI_CLK] = &gcc_camss_vfe0_axi_clk.clkr, + [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr, + [GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr, + [GCC_CAMSS_VFE1_AXI_CLK] = &gcc_camss_vfe1_axi_clk.clkr, + [GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr, + [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr, + [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, + [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, + [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, + [GCC_DCC_CLK] = &gcc_dcc_clk.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr, + [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr, + [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr, + [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr, + [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr, + [GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr, + [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr, + [GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr, + [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr, + [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr, + [GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr, + [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr, + [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, + [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, + [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr, + [GCC_OXILI_AON_CLK] = &gcc_oxili_aon_clk.clkr, + [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr, + [GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr, + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, + [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr, + [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, + [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, + [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr, + [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, + [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr, + [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr, + [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr, + [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr, + [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr, + [GCC_VFE1_TBU_CLK] = &gcc_vfe1_tbu_clk.clkr, + [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr, +}; + static const struct qcom_reset_map gcc_msm8917_resets[] = { [GCC_CAMSS_MICRO_BCR] = { 0x56008 }, [GCC_MSS_BCR] = { 0x71000 }, @@ -3234,6 +3791,18 @@ static struct gdsc *gcc_msm8917_gdscs[] = { [VFE1_GDSC] = &vfe1_gdsc, }; +static struct gdsc *gcc_msm8937_gdscs[] = { + [CPP_GDSC] = &cpp_gdsc, + [JPEG_GDSC] = &jpeg_gdsc, + [MDSS_GDSC] = &mdss_gdsc, + [OXILI_GX_GDSC] = &oxili_gx_gdsc_msm8937, + [OXILI_CX_GDSC] = &oxili_cx_gdsc, + [VENUS_CORE0_GDSC] = &venus_core0_gdsc, + [VENUS_GDSC] = &venus_gdsc, + [VFE0_GDSC] = &vfe0_gdsc, + [VFE1_GDSC] = &vfe1_gdsc, +}; + static const struct qcom_cc_desc gcc_msm8917_desc = { .config = &gcc_msm8917_regmap_config, .clks = gcc_msm8917_clocks, @@ -3254,6 +3823,41 @@ static const struct qcom_cc_desc gcc_qm215_desc = { .num_gdscs = ARRAY_SIZE(gcc_msm8917_gdscs), }; +static const struct qcom_cc_desc gcc_msm8937_desc = { + .config = &gcc_msm8917_regmap_config, + .clks = gcc_msm8937_clocks, + .num_clks = ARRAY_SIZE(gcc_msm8937_clocks), + .resets = gcc_msm8917_resets, + .num_resets = ARRAY_SIZE(gcc_msm8917_resets), + .gdscs = gcc_msm8937_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_msm8937_gdscs), +}; + +static void msm8937_clock_override(void) +{ + /* GPLL3 750MHz configuration */ + gpll3_early_config.l = 47; + gpll3_early.vco_table = gpll3_p_vco_msm8937; + gpll3_early.num_vco = ARRAY_SIZE(gpll3_p_vco_msm8937); + + /* + * Set below clocks for use specific msm8937 parent map. + */ + vcodec0_clk_src.parent_map = gcc_cpp_map; + vcodec0_clk_src.clkr.hw.init = &vcodec0_clk_src_init_msm8937; + + /* + * Set below clocks for use specific msm8937 freq table. + */ + vfe0_clk_src.freq_tbl = ftbl_vfe_clk_src_msm8937; + vfe1_clk_src.freq_tbl = ftbl_vfe_clk_src_msm8937; + cpp_clk_src.freq_tbl = ftbl_cpp_clk_src_msm8937; + vcodec0_clk_src.freq_tbl = ftbl_vcodec0_clk_src_msm8937; + csi0phytimer_clk_src.freq_tbl = ftbl_csi_phytimer_clk_src_msm8937; + csi1phytimer_clk_src.freq_tbl = ftbl_csi_phytimer_clk_src_msm8937; + usb_hs_system_clk_src.freq_tbl = ftbl_usb_hs_system_clk_src_msm8937; +} + static int gcc_msm8917_probe(struct platform_device *pdev) { struct regmap *regmap; @@ -3261,8 +3865,12 @@ static int gcc_msm8917_probe(struct platform_device *pdev) gcc_desc = of_device_get_match_data(&pdev->dev); - if (gcc_desc == &gcc_qm215_desc) + if (gcc_desc == &gcc_qm215_desc) { gfx3d_clk_src.parent_map = gcc_gfx3d_map_qm215; + } else if (gcc_desc == &gcc_msm8937_desc) { + msm8937_clock_override(); + gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_msm8937; + } regmap = qcom_cc_map(pdev, gcc_desc); if (IS_ERR(regmap)) @@ -3276,6 +3884,7 @@ static int gcc_msm8917_probe(struct platform_device *pdev) static const struct of_device_id gcc_msm8917_match_table[] = { { .compatible = "qcom,gcc-msm8917", .data = &gcc_msm8917_desc }, { .compatible = "qcom,gcc-qm215", .data = &gcc_qm215_desc }, + { .compatible = "qcom,gcc-msm8937", .data = &gcc_msm8937_desc }, {}, }; MODULE_DEVICE_TABLE(of, gcc_msm8917_match_table); From patchwork Tue Feb 11 22:37:50 2025 Content-Type: text/plain; charset="utf-8" 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Signed-off-by: Barnabás Czémán --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 39c209249c9c0bdf1eb5693306daf3de6e19dff5..bc10e038852c9278d2f4d8875f7498ca4c4bdc17 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -28,6 +28,7 @@ properties: - qcom,msm8226-qfprom - qcom,msm8916-qfprom - qcom,msm8917-qfprom + - qcom,msm8937-qfprom - qcom,msm8974-qfprom - qcom,msm8976-qfprom - qcom,msm8996-qfprom From patchwork Tue Feb 11 22:37:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QmFybmFiw6FzIEN6w6ltw6Fu?= X-Patchwork-Id: 864158 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C83F26F45B; Tue, 11 Feb 2025 22:38:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739313505; cv=none; b=koCUY3AV1MD4uKdjUe5isGUVzHJkNouzAhNmaYkIhWdihEPwugUrSekiVDz8u/OLC/J54G2NzJUx5cvfcf24NDiu/o4e3LNoQVNt+7srcQXSaymp0p1KDYQoNTWtaKTYisSgTvM8fIbAm8UAwU/hrhWmSmT1sqVEh3wWAWNcW64= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739313505; c=relaxed/simple; bh=XrDG6cJ7Znm3MYNEA0g9g+f4KIS+HpIdNachXJLtRoE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AVByGrcPfT2MEJHzIc+P7tf2JEjA1fd2IPtQNL2HG5QJtQC5qWAfc/rUkiOQ9H41tfcg5DwBG1p1Z0dGZZiP/ukClJviI7EkpIl4WXiKuuNTaG7u75O8mdgHyIRthSPz24NBy5mBc9Uhx4NCU7io1ROf70/zLDIkD67CqlkQxic= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=cqN32ge8; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="cqN32ge8" Received: from [192.168.244.162] (254C21CD.nat.pool.telekom.hu [37.76.33.205]) by mail.mainlining.org (Postfix) with ESMTPSA id 6B571E4533; Tue, 11 Feb 2025 22:38:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1739313501; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=643BFBiyMT2GIqqHLVDLrJjWeBjJ/C+QADvp9Eruf1c=; b=cqN32ge8f6MMJ6RG88K+arp2eoXsjXKnjqTD3dv892UeQmzfiH9/MaYXvdKHO6U1AEDY5e M/Un86GwCB4VBn5tWzXPwZTkJ7fd4HPiWFPB7FjCPLixszfh0kwGt4nLg9re8lgX1fTCcs 1FusO34sunsGYwFJ1I9hcBrh3vxvQXP4kO8YkAW50VmqEQyF5PYyWZ8BuUt8GCyeTy6Znj ihkNd4OWSlK5dt2LmFtplGJBudWkacgKeoTC7/z49GJfcXU8ITWD7kYa/FBRDVdxt/SL31 5yS8/iU1gEaRiavGTRX7fJBQWkG1kja7GXLmpphqQXMztFdtkdXHZpfJu5MZsQ== From: =?utf-8?b?QmFybmFiw6FzIEN6w6ltw6Fu?= Date: Tue, 11 Feb 2025 23:37:54 +0100 Subject: [PATCH 10/10] arm64: dts: qcom: Add Xiaomi Redmi 3S Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250211-msm8937-v1-10-7d27ed67f708@mainlining.org> References: <20250211-msm8937-v1-0-7d27ed67f708@mainlining.org> In-Reply-To: <20250211-msm8937-v1-0-7d27ed67f708@mainlining.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephan Gerhold , =?utf-8?q?Otto_Pfl=C3=BCger?= , Linus Walleij , Lee Jones , Srinivas Kandagatla , Joerg Roedel , Will Deacon , Robin Murphy , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?b?QmFybmFiw6Fz?= =?utf-8?b?IEN6w6ltw6Fu?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739313484; l=10280; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=XrDG6cJ7Znm3MYNEA0g9g+f4KIS+HpIdNachXJLtRoE=; b=tUDswN3BrdPDkJrkeQCnazOPJAsjs+MBpj0HZzGOA/To+eh4nZxCeRXmxetZfLNzjdOpbLFbS c2KW9YyZneKBDHgkIMH232KDpSd5MIQet7T2TL5xFslNmxreG3lKIMT X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Add initial support for Xiaomi Redmi 3S (land). Signed-off-by: Barnabás Czémán --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts | 402 +++++++++++++++++++++++ 2 files changed, 403 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 140b0b2abfb555b8ef61bd9ed0217d8997800809..18f0c0f7ebadf86a36b02461c02bdba7bfebe397 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -64,6 +64,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8917-xiaomi-riva.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8929-wingtech-wt82918hd.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8937-xiaomi-land.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-huawei-kiwi.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-longcheer-l9100.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-samsung-a7.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts b/arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts new file mode 100644 index 0000000000000000000000000000000000000000..3bc324851d54df01f08aa61548ce1794261c7313 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts @@ -0,0 +1,402 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Barnabas Czeman + */ +/dts-v1/; + +#include +#include +#include + +#include "msm8937.dtsi" +#include "pm8937.dtsi" +#include "pmi8950.dtsi" + +/delete-node/ &qseecom_mem; + +/ { + model = "Xiaomi Redmi 3S (land)"; + compatible = "xiaomi,land", "qcom,msm8937"; + chassis-type = "handset"; + + qcom,msm-id = ; + qcom,board-id = <0x1000b 1>, <0x2000b 1>; + + aliases { + serial0 = &blsp1_uart2; + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + }; + + speaker_amp: audio-amplifier { + compatible = "awinic,aw8738"; + mode-gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>; + awinic,mode = <5>; + sound-name-prefix = "Speaker Amp"; + pinctrl-0 = <&speaker_amp_default>; + pinctrl-names = "default"; + }; + + headphones_switch: audio-switch { + compatible = "simple-audio-amplifier"; + enable-gpios = <&tlmm 129 GPIO_ACTIVE_HIGH>; + sound-name-prefix = "Headphones Switch"; + pinctrl-0 = <&headphones_switch_default>; + pinctrl-names = "default"; + }; + + battery: battery { + compatible = "simple-battery"; + + charge-full-design-microamp-hours = <4100000>; + constant-charge-current-max-microamp = <1000000>; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4400000>; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "framebuffer0"; + + framebuffer0: framebuffer@8dd01000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x8dd01000 0x0 (720 * 1280 * 3)>; + width = <720>; + height = <1280>; + stride = <(720 * 3)>; + format = "r8g8b8"; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + power-domains = <&gcc MDSS_GDSC>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + key-volup { + label = "Volume Up"; + linux,code = ; + gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + }; + + irled { + compatible = "gpio-ir-tx"; + gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + }; + + reserved-memory { + reserved@84a00000 { + reg = <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + framebuffer: memory@8dd01000 { + reg = <0x0 0x8dd01000 0x0 (720 * 1280 * 3)>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + + led-controller@45 { + compatible = "awinic,aw2013"; + reg = <0x45>; + #address-cells = <1>; + #size-cells = <0>; + + vcc-supply = <&pm8937_l10>; + vio-supply = <&pm8937_l5>; + + led@0 { + reg = <0>; + function = LED_FUNCTION_INDICATOR; + led-max-microamp = <5000>; + color = ; + }; + + led@1 { + reg = <1>; + function = LED_FUNCTION_INDICATOR; + led-max-microamp = <5000>; + color = ; + }; + }; +}; + +&blsp1_i2c3 { + status = "okay"; + + touchscreen@3e { + compatible = "edt,edt-ft5306"; + reg = <0x3e>; + + interrupts-extended = <&tlmm 65 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + vcc-supply = <&pm8937_l10>; + iovcc-supply = <&pm8937_l5>; + + pinctrl-0 = <&tsp_int_rst_default>; + pinctrl-names = "default"; + + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + }; +}; + +&pm8937_resin { + linux,code = ; + status = "okay"; +}; + +&pm8937_spmi_regulators { + pm8937_s5: s5 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&pmi8950_wled { + qcom,num-strings = <2>; + qcom,external-pfet; + qcom,current-limit-microamp = <20000>; + qcom,ovp-millivolt = <29600>; + + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8937-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + + vdd_l1_l19-supply = <&pm8937_s3>; + vdd_l2_l23-supply = <&pm8937_s3>; + vdd_l3-supply = <&pm8937_s3>; + vdd_l4_l5_l6_l7_l16-supply = <&pm8937_s4>; + vdd_l8_l11_l12_l17_l22-supply = <&vph_pwr>; + vdd_l9_l10_l13_l14_l15_l18-supply = <&vph_pwr>; + + pm8937_s1: s1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1225000>; + }; + + pm8937_s3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pm8937_s4: s4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8937_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8937_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8937_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8937_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8937_l8: l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + pm8937_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8937_l10: l10 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8937_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + pm8937_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8937_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8937_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8937_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8937_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8937_l17: l17 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2900000>; + }; + + pm8937_l19: l19 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1350000>; + }; + + pm8937_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8937_l23: l23 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; +}; + +&sdc2_cmd_default { + drive-strength = <12>; +}; + +&sdc2_data_default { + drive-strength = <12>; +}; + +&sdhc_1 { + vmmc-supply = <&pm8937_l8>; + vqmmc-supply = <&pm8937_l5>; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 67 GPIO_ACTIVE_LOW>; + vmmc-supply = <&pm8937_l11>; + vqmmc-supply = <&pm8937_l12>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32768>; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <20 4>; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio91"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + headphones_switch_default: headphones-switch-default-state { + pins = "gpio129"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio67"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + speaker_amp_default: speaker-amp-default-state { + pins = "gpio124"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_rst_default: tsp-int-rst-default-state { + pins = "gpio64", "gpio65"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&wcnss { + vddpx-supply = <&pm8937_l5>; + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; + vddxo-supply = <&pm8937_l7>; + vddrfa-supply = <&pm8937_l19>; + vddpa-supply = <&pm8937_l9>; + vdddig-supply = <&pm8937_l5>; +}; + +&wcnss_mem { + status = "okay"; +}; + +&xo_board { + clock-frequency = <19200000>; +};