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Mon, 10 Feb 2025 14:13:45 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 01/15] dt-bindings: mfd: syscon: add microchip,sama7d65-ddr3phy Date: Mon, 10 Feb 2025 14:13:01 -0700 Message-ID: <7e2c590467171cb3a942692aef5a679f127e567e.1739221064.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 DDR3phy compatible to DT bindings documentation Signed-off-by: Ryan Wanner --- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index b414de4fa779b..51d896c88dafa 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -90,6 +90,7 @@ select: - microchip,lan966x-cpu-syscon - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr + - microchip,sama7d65-ddr3phy - microchip,sama7g5-ddr3phy - mscc,ocelot-cpu-syscon - mstar,msc313-pmsleep @@ -188,6 +189,7 @@ properties: - microchip,lan966x-cpu-syscon - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr + - microchip,sama7d65-ddr3phy - microchip,sama7g5-ddr3phy - mscc,ocelot-cpu-syscon - mstar,msc313-pmsleep From patchwork Mon Feb 10 21:13:03 2025 Content-Type: text/plain; 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Mon, 10 Feb 2025 14:13:45 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 03/15] dt-bindings: sram: Add microchip,sama7d65-sram Date: Mon, 10 Feb 2025 14:13:03 -0700 Message-ID: <384759dc826f9e37b43a69a1f2f6b79f56b99d38.1739221064.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add microchip,sama7d65-sram compatibility to DT binding documentation. Signed-off-by: Ryan Wanner Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/sram/sram.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index 7c1337e159f23..3071c5075ee48 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -31,6 +31,7 @@ properties: - amlogic,meson-gxbb-sram - arm,juno-sram-ns - atmel,sama5d2-securam + - microchip,sama7d65-securam - nvidia,tegra186-sysram - nvidia,tegra194-sysram - nvidia,tegra234-sysram From patchwork Mon Feb 10 21:13:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 864327 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5416524E4A3; Mon, 10 Feb 2025 21:14:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222056; cv=none; b=PzP0Fg2QEYOq2nGIylx9kxPhEcRjZcSpdFoSkfQ+kF6/BTlBolN0VtOZpuS8QoxFVv8aSH1GgX5o+e/aKtXq4yUR8GYfj9CsSBFDRub2rdyWbzbj5+4JOzuFRmuTR1gmxtfDPwl/4OdtxoN44/92J9hIw5Lsq+w1ptDxo9nVRRY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222056; c=relaxed/simple; bh=w2RzJqYLQDLs0eAHKRPSDmffq9ISN4Icv+3CsJAeg28=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=F+bybh0LhdsVWdcxh2SKJ/OTJbwl9bTguXeo8l+euu01G15u6m+rh468oZ1CrVTQeAfcVHMi+3xi1OhIwGFh169P/uLh6C3O6CKzgQmkL0W0Icb8ax5b88OlEuvqXbvlffJBSZlGscITf1M00znLA7p8mqfAn4Hdcs4uVZi8wbY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=LHg5L9Sy; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="LHg5L9Sy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1739222054; x=1770758054; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w2RzJqYLQDLs0eAHKRPSDmffq9ISN4Icv+3CsJAeg28=; b=LHg5L9SyFhUSgUy5uLaa76Y293UtQ61iMpGhdIkSiQFdXT57ghEA0U+1 nI0CzdgQPha4oKAdCmneUhlmaZbuwr+0tKLwR6/HKusaThCSCPLDMAYQS REhQVSarGU038XzCRJU5pg6azkOVc8Bn9BhCu9SVaYV6CQQT8ZWKGRgkK ObeDbMw+O/jwzxh5PqatoDYvcrv+cBbmGLuHlQKGr4KEM/va6aFkjY4SX mspZOapjOBqu9uF1Uf2ju5z1TQzKHA/kntii5exd+cI8L/zR9JmNuH/8e uiDIxiYgvon5TIhj1pqWzVEYfw8vzj0sY2WDLuejSU48twg7qLi2j6eXU A==; X-CSE-ConnectionGUID: AYqW9AG9RbOJ2Xf8Pt97Yw== X-CSE-MsgGUID: AglZBN5NShyfNxjZ8zWUqw== X-IronPort-AV: E=Sophos;i="6.13,275,1732604400"; d="scan'208";a="205027973" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Feb 2025 14:14:04 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Feb 2025 14:13:46 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Feb 2025 14:13:46 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 05/15] dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc Date: Mon, 10 Feb 2025 14:13:05 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 RSTC compatible to DT bindings documentation. The sama7d65-rstc is compatible with the sama7g5-rstc. Signed-off-by: Ryan Wanner --- .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml index 98465d26949ee..a1c21c3880f9d 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -23,6 +23,11 @@ properties: - atmel,sama5d3-rstc - microchip,sam9x60-rstc - microchip,sama7g5-rstc + + - items: + - const: microchip,sama7d65-rstc + - const: microchip,sama7g5-rstc + - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc From patchwork Mon Feb 10 21:13:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 864326 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2B892505C5; Mon, 10 Feb 2025 21:14:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222057; cv=none; b=GaT1GPRl78rc9cXcz9ygEYvgSUx1xRUvxop3NK80P4nveii/vqHZmJc7aJI6XEkRBOGpyzy2LO47TaOt39I9pQSOAvk+jd8O9NQIlLdLbmvm+YBD34vJzKDZHBmheUueKMLWkYgV8brp/aHfyLMDvEpKY7TdSnuLmsZvftqhxms= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222057; c=relaxed/simple; bh=vVcwZO42JPNUOdcIsOkBSUgYQfQ7lZG5absw3HX57CE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gu/AVTPCP03ZnCU2tsGBQbcVK6HRuAtgmoezY0vJ7JkA+2EuFB5OBtNFtRQvMrHqgc7Ll0V3rYlbZZNSFq18XbypO+UZA8FFtMj1KCdC35r3ouMrRbZorw+AYsJKkoFkvvpu7SyooYFGKZ4f9/YddTTNf2tl/4+S/zt5v0cA9rQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=i5+O+11F; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="i5+O+11F" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1739222056; x=1770758056; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vVcwZO42JPNUOdcIsOkBSUgYQfQ7lZG5absw3HX57CE=; b=i5+O+11FdDiGDgz8/JLHizzQ0Uqdx0R/t0KXgCAXFwzfwz1bkGd/fPiL ocxjffT+pb7nNb5GI8TtTiijTshrr9zbEbiuZtSn8l40SiDeCADaIMbMq 12qxZKxF1ogjvNuIpw0uz5vIj2CZb6cURCev8I76ME7GY+FqhsuxM1FNX hkDEtxc9kzXcxDZJapoo7wRidKc29xJIJ2UodqBLhuxn8mLuOidXK3n19 H2VNPgQmp4f/mS3K+wfBJFQp3KxHJe2xFYs6qQrbNjpyssEKT2OnxQZEx lbk0/qOLwvN8O88KpFD4nukB1iZB1J+pHbL9PSkSHYap9Ye+eouTLNoNV Q==; X-CSE-ConnectionGUID: AYqW9AG9RbOJ2Xf8Pt97Yw== X-CSE-MsgGUID: wAxkISw7RgW1cXiYsTRZ6A== X-IronPort-AV: E=Sophos;i="6.13,275,1732604400"; d="scan'208";a="205027978" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Feb 2025 14:14:05 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Feb 2025 14:13:46 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Feb 2025 14:13:46 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 07/15] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt Date: Mon, 10 Feb 2025 14:13:07 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SAMA7D65 RTT compatible to DT bindings documentation. Signed-off-by: Ryan Wanner --- .../devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml index a7f6c1d1a08ab..48a2e013a6b24 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml @@ -23,6 +23,9 @@ properties: - microchip,sam9x60-rtt - microchip,sam9x7-rtt - const: atmel,at91sam9260-rtt + - items: + - const: microchip,sama7d65-rtt + - const: atmel,at91sam9260-rtt - items: - const: microchip,sama7g5-rtt - const: microchip,sam9x60-rtt From patchwork Mon Feb 10 21:13:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 864325 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35E1624C667; Mon, 10 Feb 2025 21:14:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222059; cv=none; b=He7ZrJ+IJywMWxuW8aui1F8tbuKZKwBc1Hyzwaj3Wg/k+Q988ozl+KdOh1qhuEUIOjeIzZ9coMwIh6Q1IBsphydO18GaQIhS0iyNjNgxI5e7FKsjVt2rqrOGzHAXZXLDlKGyiQYZfavKMePyGAx1jK6pgeAlb0OcinqzC435PoY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222059; c=relaxed/simple; bh=EC1+VWxeTyKipOmsfV+ugr3Ogr25ipgQiLkDdijoRG8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hk/WNpPQYgIAzUnz6hBe6gHM7ZKRVl7MuvhOhOfPjz/lRPnYFyqgrensxz2BK8MGipIE9Jcx1nNEc9WTEoT6iJa/uTsrPWWyoSW5xOOYIi6nd9NpenT8T3QIBryjo5FGyKWE3wmaF3HLBFW1+Hu+v8uUJ0JtIIlHN49nbYhYgzw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=pNo0CyUI; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="pNo0CyUI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1739222057; x=1770758057; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EC1+VWxeTyKipOmsfV+ugr3Ogr25ipgQiLkDdijoRG8=; b=pNo0CyUIGpry6AtIuS+DDwY9qR/LfWnxHaLGLx/ebx9YavdVDuJbODc6 QJcDKuR8oruPQB59XtPF1nbX1aGbGKwhYoONsZUNiuv3Vxdjt1vP7ZV9A mIR+vZ8DTACtsYt6TuQD+ScI9tGzupTr1lIU1d7v4ZqLuJPyySaZGIPhH PdU/ZAnlpWEK4gHthFxTOCUQorkTx/xczhhx7TsC0zInJNj66hwSqx4VU AI1VWko+yzW1mD8ACt1CChGPD82RUGAlf1eurJ2y33d35diowwvQg67RP /xIgXtDLT4jNM706O4F7nBw0go58Fk0DB8qnEmqi7bBo1xL5cvI1r4jAG w==; X-CSE-ConnectionGUID: AYqW9AG9RbOJ2Xf8Pt97Yw== X-CSE-MsgGUID: 1dErltO1Rla3Z/Bsv54o7g== X-IronPort-AV: E=Sophos;i="6.13,275,1732604400"; d="scan'208";a="205027983" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Feb 2025 14:14:06 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Feb 2025 14:13:46 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Feb 2025 14:13:46 -0700 From: To: , , , , , , , , CC: , , , , , , Li Bin , Ryan Wanner , "Durai Manickam KR" , Andrei Simion Subject: [PATCH v2 09/15] ARM: at91: pm: fix at91_suspend_finish for ZQ calibration Date: Mon, 10 Feb 2025 14:13:09 -0700 Message-ID: <4e685b1f1828b006cb60aa6b66239f2c0966501a.1739221064.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Li Bin For sama7g5 and sama7d65 backup mode, we encountered a "ZQ calibrate error" during recalibrating the impedance in BootStrap. We found that the impedance value saved in at91_suspend_finish() before the DDR entered self-refresh mode did not match the resistor values. The ZDATA field in the DDR3PHY_ZQ0CR0 register uses a modified gray code to select the different impedance setting. But these gray code are incorrect, a workaournd from design team fixed the bug in the calibration logic. The ZDATA contains four independent impedance elements, but the algorithm combined the four elements into one. The elements were fixed using properly shifted offsets. Signed-off-by: Li Bin [nicolas.ferre@microchip.com: fix indentation and combine 2 patches] Signed-off-by: Nicolas Ferre Tested-by: Ryan Wanner Tested-by: Durai Manickam KR Tested-by: Andrei Simion --- arch/arm/mach-at91/pm.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 05a1547642b60..6c3e6aa22606f 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -545,11 +545,12 @@ extern u32 at91_pm_suspend_in_sram_sz; static int at91_suspend_finish(unsigned long val) { - unsigned char modified_gray_code[] = { - 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d, - 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b, - 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, - 0x10, 0x11, + /* SYNOPSYS workaround to fix a bug in the calibration logic */ + unsigned char modified_fix_code[] = { + 0x00, 0x01, 0x01, 0x06, 0x07, 0x0c, 0x06, 0x07, 0x0b, 0x18, + 0x0a, 0x0b, 0x0c, 0x0d, 0x0d, 0x0a, 0x13, 0x13, 0x12, 0x13, + 0x14, 0x15, 0x15, 0x12, 0x18, 0x19, 0x19, 0x1e, 0x1f, 0x14, + 0x1e, 0x1f, }; unsigned int tmp, index; int i; @@ -560,25 +561,25 @@ static int at91_suspend_finish(unsigned long val) * restore the ZQ0SR0 with the value saved here. But the * calibration is buggy and restoring some values from ZQ0SR0 * is forbidden and risky thus we need to provide processed - * values for these (modified gray code values). + * values for these. */ tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0); /* Store pull-down output impedance select. */ index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] = modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDO_OFF; /* Store pull-up output impedance select. */ index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PUO_OFF; /* Store pull-down on-die termination impedance select. */ index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDODT_OFF; /* Store pull-up on-die termination impedance select. */ index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SRO_PUODT_OFF; /* * The 1st 8 words of memory might get corrupted in the process From patchwork Mon Feb 10 21:13:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 864324 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A2D72512E7; Mon, 10 Feb 2025 21:14:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222060; cv=none; b=qwHRAux0ckjHePmm0T4ihg6YmUWAoGjjaAb08IsB7ehlrLY18DKp8sdlvFVQZAN5zI9Tyf1Lo63nBvZe93RWCQ2za5p4SMzLBsNJp6McOoSslxdYbbI4uEZA4JX0K7fJPcXU2hFMPtppvy4k1bUtHpymG+w0xBGp9GnNxJDk6xk= ARC-Message-Signature: i=1; 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Mon, 10 Feb 2025 14:13:47 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Feb 2025 14:13:47 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 11/15] ARM: at91: PM: Add Backup mode for SAMA7D65 Date: Mon, 10 Feb 2025 14:13:11 -0700 Message-ID: <76a89f1ae5e9c4d337c2a28e4b1d0e5cef63e5fe.1739221064.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add config check that enables Backup mode for SAMA7D65 SoC. Add SHDWC_SR read to clear the status bits once finished exiting low power modes. This is only for SAMA7D65 SoCs. Signed-off-by: Ryan Wanner --- arch/arm/mach-at91/pm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 1eec68e92f8d8..55cab31ce1ecb 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -707,6 +707,9 @@ static int at91_pm_enter(suspend_state_t state) static void at91_pm_end(void) { at91_pm_config_ws(soc_pm.data.mode, false); + + if (IS_ENABLED(CONFIG_SOC_SAMA7D65)) + readl(soc_pm.data.shdwc + 0x08); } @@ -1065,7 +1068,8 @@ static int __init at91_pm_backup_init(void) int ret = -ENODEV, located = 0; if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) && - !IS_ENABLED(CONFIG_SOC_SAMA7G5)) + !IS_ENABLED(CONFIG_SOC_SAMA7G5) && + !IS_ENABLED(CONFIG_SOC_SAMA7D65)) return -EPERM; if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) From patchwork Mon Feb 10 21:13:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 864323 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55A912512D1; Mon, 10 Feb 2025 21:14:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222062; cv=none; b=lGyWUzCvWd+fhxSDDlj8sPwYy9RN0lNtNB4H4S9iqaABrvsrLn4YhcggMYYneq7lSz8gXjHMat1Y+NexTeSdYPxd1BriW5zNMfgkT110gszHdevpY0yJckq2ymulnGfnqSKQrLn8zXPQEK3ysnaqqz5Abx2/Vdwgr+pVjFt5pSg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222062; c=relaxed/simple; bh=Q6EhuaD18bf95yOzyUc9NiJbUcTYlA0vWWENLIJPl9s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AVEpw/z9+Y8lVECxhsnh3Ll/CHY1KsUjtrCMDowB7VaHWHAy7H16jTnZYiShGe4LHAkIH+BcsXj1w0psB2+wnhnxXwXh8VXbgJWXKV9XdbhA6NeT2hOJTJzrc1z28uwqCrWAZAyotMIsRnEpFOUXSTQ/7Qe59MG1KqiqabtMrig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=p53bhYCY; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="p53bhYCY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1739222060; x=1770758060; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Q6EhuaD18bf95yOzyUc9NiJbUcTYlA0vWWENLIJPl9s=; b=p53bhYCY4isZxmeqhVY3rbD6Vw21Fm3Uy7QB3S4JOot9At/3hbVKb+Px Q4zmTRoJun6IkyXTWz8RwfwnrOCZNc0tQqsTJ0rKehU+adqhjT+qBd4MR j44HJwqbYUQXTUIf8UtI3+6fqKqzpm5aoy3ZpjluhBEq1K3SxP01W+cP4 DMdT/a+8FZPG5YmVNCRKRVv5R0w77C6TwP3WPdnGHLywEMZdojUp84qun lBubRNJibZ/t6EFNnCwRhOFPcfsuOuT6fUOsfujminM0T9myqKiPNr3zv 8az1gRG/DYa4M6ue66VGO5nfcwft0UP6dWrWG6Swok864N8faxNxaG0iV Q==; X-CSE-ConnectionGUID: AYqW9AG9RbOJ2Xf8Pt97Yw== X-CSE-MsgGUID: TtqIL6VfTqq+6rCYBPi7Ew== X-IronPort-AV: E=Sophos;i="6.13,275,1732604400"; d="scan'208";a="205027991" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Feb 2025 14:14:07 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Feb 2025 14:13:47 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Feb 2025 14:13:47 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 13/15] power: reset: at91-sama5d2_shdwc: Add sama7d65 PMC Date: Mon, 10 Feb 2025 14:13:13 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add sama7d65-pmc compatible string to the list of valid PMC IDs. Signed-off-by: Ryan Wanner --- drivers/power/reset/at91-sama5d2_shdwc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c index edb0df86aff45..0cb7fe9f25a07 100644 --- a/drivers/power/reset/at91-sama5d2_shdwc.c +++ b/drivers/power/reset/at91-sama5d2_shdwc.c @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = { { .compatible = "atmel,sama5d2-pmc" }, { .compatible = "microchip,sam9x60-pmc" }, { .compatible = "microchip,sama7g5-pmc" }, + { .compatible = "microchip,sama7d65-pmc" }, { /* Sentinel. */ } }; From patchwork Mon Feb 10 21:13:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 864322 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE0A5256C6B; Mon, 10 Feb 2025 21:14:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222063; cv=none; b=eIXtepFhgDukadQ+xM6ohNcJA8ymlDZqPXNvNSldIDVBMLtcRg0pMnqeZkPQPeTgDHaK6UYht6IaXbJXayTPZA8k7AU09FeXW1OWGEFakp31AQFtg5OjEspuef79gxZg5RgbURXJ9Ko0DTw/qOo2qvw7pZAQXyhRwRd30xe19+0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222063; c=relaxed/simple; bh=unETEqL21PPGjcJ+5ThZ5Xx9TlKma2kepF5jLOEMdPY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OJfWwL6xPeo/mHrkSnEdZqD5WbYnfWx5OPXdN+Z0rpgfzDeNkLKHROn/eAAHvyHNsZBTjbTgEoNe7SPgUzZZQ/4hcmxZaBFPeiYIT8OdjcGcGlz31lszBO7lS51xOyMAO/B3I3IYU/N/aiiU/JPNBRt+3zf7kFEHYBQKc0A/TMI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=dDwEnlh/; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="dDwEnlh/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1739222061; x=1770758061; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=unETEqL21PPGjcJ+5ThZ5Xx9TlKma2kepF5jLOEMdPY=; b=dDwEnlh//fm9WkQOm9Th9vpn88QnBCfcrvol9jw9fsbMrbCqnd0tjMwJ Jm6WT03DbahE4haHRNbLeezHg1wrEDBc8PJugDKOTKiiROS5nX+5U6sZu fiy07Eza1ZIthNRpHIFU+yJ59xKuEn0+LQOoG58AeIU+0qVdE0cXrtnd3 n300gu5mVDkzttFblyJ7UXdpLo8tx43CQRSiVNbQ8VjcdvFP4y951fN+9 IghVvNLknX++Ay42d0Nr5rp5SMOsC1X8zXABt6IJlzdQkxK4Km+WaX/H6 OdJFPSFsCCT9p0i2hUaQaeLsxMxwynmfjWpIkdKcVTrBg/cQH5UKqUtZB w==; X-CSE-ConnectionGUID: AYqW9AG9RbOJ2Xf8Pt97Yw== X-CSE-MsgGUID: 0agEuR3bS46pa3Vj3mw/1g== X-IronPort-AV: E=Sophos;i="6.13,275,1732604400"; d="scan'208";a="205027996" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Feb 2025 14:14:07 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Feb 2025 14:13:47 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Feb 2025 14:13:47 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v2 15/15] ARM: dts: microchip: add shutdown controller and rtt timer Date: Mon, 10 Feb 2025 14:13:15 -0700 Message-ID: <709f5268da63c123cc4eee9e47875324df81c454.1739221064.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add shutdown controller and rtt timer to support shutdown and wake up. Signed-off-by: Ryan Wanner --- .../boot/dts/microchip/at91-sama7d65_curiosity.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index 0f86360fb733a..d1d0b06fbfc43 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -77,6 +77,11 @@ pinctrl_uart6_default: uart6-default { }; }; +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "disabled"; +}; + &sdmmc1 { bus-width = <4>; pinctrl-names = "default"; @@ -84,6 +89,15 @@ &sdmmc1 { status = "okay"; }; +&shdwc { + debounce-delay-us = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + &slow_xtal { clock-frequency = <32768>; };