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Wed, 12 Feb 2025 07:15:53 GMT Received: from cse-cd01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 11 Feb 2025 23:15:47 -0800 From: Yongxing Mou Date: Wed, 12 Feb 2025 15:12:25 +0800 Subject: [PATCH 2/4] dt-bindings: display/msm: Add stream 1 pixel clock for QCS8300 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250212-mst_qcs8300-v1-2-38a8aa08394b@quicinc.com> References: <20250212-mst_qcs8300-v1-0-38a8aa08394b@quicinc.com> In-Reply-To: <20250212-mst_qcs8300-v1-0-38a8aa08394b@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , "Bjorn Andersson" , Konrad Dybcio CC: , , , , , Yongxing Mou X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Signed-off-by: Yongxing Mou --- .../devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml index eb7f36387f748793ebf662baded4a13a61b3ce39..610742ceebf8ee5e140a409bfeb92d9f43085214 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml @@ -53,7 +53,6 @@ patternProperties: compatible: items: - const: qcom,qcs8300-dp - - const: qcom,sm8650-dp required: - compatible @@ -164,7 +163,7 @@ examples: }; displayport-controller@af54000 { - compatible = "qcom,qcs8300-dp", "qcom,sm8650-dp"; + compatible = "qcom,qcs8300-dp"; pinctrl-0 = <&dp_hot_plug_det>; pinctrl-names = "default"; @@ -181,15 +180,18 @@ examples: <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>, <&mdss_edp_phy 1>; phys = <&mdss_edp_phy>; phy-names = "dp"; operating-points-v2 = <&dp_opp_table>; From patchwork Wed Feb 12 07:12:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongxing Mou X-Patchwork-Id: 864565 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9144A204C18; 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Wed, 12 Feb 2025 07:16:07 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51C7G5aS014438 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 12 Feb 2025 07:16:05 GMT Received: from cse-cd01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 11 Feb 2025 23:15:59 -0800 From: Yongxing Mou Date: Wed, 12 Feb 2025 15:12:27 +0800 Subject: [PATCH 4/4] arm64: dts: qcom: qcs8300: Add support for stream 1 clk for DP MST Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250212-mst_qcs8300-v1-4-38a8aa08394b@quicinc.com> References: <20250212-mst_qcs8300-v1-0-38a8aa08394b@quicinc.com> In-Reply-To: <20250212-mst_qcs8300-v1-0-38a8aa08394b@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , "Bjorn Andersson" , Konrad Dybcio CC: , , , , , Yongxing Mou X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Compatile with qcs8300 dp controller driver and populate the stream clock for qcs8300 DP0 controller in MST mode. Signed-off-by: Yongxing Mou --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index e10db7275accf769500abbebf57a6cbbbc4bf167..5166686981617707ba19245723e9215a53300392 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -2865,12 +2865,13 @@ mdss_dp0_phy: phy@aec2a00 { }; mdss_dp0: displayport-controller@af54000 { - compatible = "qcom,qcs8300-dp", "qcom,sm8650-dp"; + compatible = "qcom,qcs8300-dp"; reg = <0x0 0x0af54000 0x0 0x200>, <0x0 0x0af54200 0x0 0x200>, <0x0 0x0af55000 0x0 0xc00>, - <0x0 0x0af56000 0x0 0x400>; + <0x0 0x0af56000 0x0 0x400>, + <0x0 0x0af57000 0x0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; @@ -2884,10 +2885,13 @@ mdss_dp0: displayport-controller@af54000 { "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents = <&mdss_dp0_phy 0>, + <&mdss_dp0_phy 1>, <&mdss_dp0_phy 1>; phys = <&mdss_dp0_phy>; phy-names = "dp";