From patchwork Thu Feb 13 21:04:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anjelique Melendez X-Patchwork-Id: 865007 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 050B5210F58 for ; Thu, 13 Feb 2025 21:04:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739480650; cv=none; b=RWVww12jQTP1WW4JMU8ULhbWVXr4q+IdFW089jlodO0kJbOEsu3qo+2Tf14jg0m7keXxJPbSNcLDTyGZTzXFlbvI5jxyvM6WBGwa2xLYmPS8P8JGiyPOmN9SF6UZSyQtC6i3jFnX6AdpkBe+FMaNwHGg19Ihfm0zeoGBcD3e2q4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739480650; c=relaxed/simple; bh=Hm34EcCZY7Nya6IWrGgD3q/+JNM1BPaGd40TDCxo+LM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AB21fOKg50GPx78B9yEDWT5I21f2oT6tfL9EcleX+coMOSq7eQDElSK+uc+/ROeq9VmXaS7XMvhAr7B3qG7HjRR6rk2uAJDOl/+vFVJaXZYrO91CQFB8ACdcgjeWTEnFUp4yeT7tM5AkDlroQFLklGS08asnDwiAPG2YeYhamDs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=G4lIXjpW; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="G4lIXjpW" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51D9gmIW027460 for ; Thu, 13 Feb 2025 21:04:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=/E2f4sNa5dJ 1J/+u/sCAiw4E4qFHfywaLempWlQrqbI=; b=G4lIXjpWbUU5RKfBQ/y4NncLt/G E0J85o1BuM3mk2EWd5+Sk9EXLpYI/SoEudUG7XpMsK6H+AsHJ7LnBG9BSdHG+fHi FMmfXqpjd+1rgNPg4MqFAOo0Cp7hQHiHBS5OaoyjM8r8VrT8YGckhykJeqCdxWTj pKc8NuCFhcKAmnzkyoJSJp/GiuKT+i0G/B/0kbHBYiAWLn+EZwZPgANzOPfvkb7+ R+GisppLdtNJ/oiUX7Zna/ruzj7Gjjs4XB+lnhn9CcgQK+pm9KC5ncSy6m0ObgYY l6nCQRDBM91Ib3ugWoadoHXruulywezBt2g3HHl7o58AajwX//ChzDDmffg== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44sebn9qvx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 13 Feb 2025 21:04:07 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-21f022fc6a3so27857325ad.1 for ; Thu, 13 Feb 2025 13:04:07 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739480646; x=1740085446; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/E2f4sNa5dJ1J/+u/sCAiw4E4qFHfywaLempWlQrqbI=; b=hh5INk4BkTwkSADzCyGbAeDJqPRBhOKDxcs69YRGG0ppNVIW2f8GWI0GhlkXfPLF4x mv4DTcEA/iKJ7jJFYq6KGUNgBWfmB3oM00jurlcL7XHdq6eKXjymSYAlr1SGlHeaJ30k /eTWZfO76PHbYzc/ctJmHeWscGoum3vbqU4w5lDm0LGFwhoWir9DYYVv/icAX4Svqav8 NFe5q7nJg29uoASdIcGTk+HZRbedMlKtOgopdRLiABQGP9SNmTmUtZSuhaZkBgDQ+04Q sA+6FITJ3Yadybo5cJzwkv4GZgXlcqAQw8VLAOzUOBLY0wvTG6FvYevAmczRpYo+n3lh CQSQ== X-Forwarded-Encrypted: i=1; AJvYcCUAhbbSEXUmv8S9UQdCTMDXuSvjA2zRY/hUgDOnj/TBoTOVsUM1g9vkGd0FrUcfCfhRt0mJYoiDJA==@vger.kernel.org X-Gm-Message-State: AOJu0YyYj7eC9aJ9uNeI4I/f8pDUmgl9Yw3pVhOtWn/39QBOEXoxoOAQ xw1nf7zU/42x9ncC213wLvr4wV8xsZn+rfDNtZl4Fn5XYW0RQvv49z3AOTOfjPH6D+69vcL3ph2 w8tLSrCoFcCqM6umNXxWVQWSQF2+7YrLnwqVvKmI0OcKvSJ34tdZu/+wUmw== X-Gm-Gg: ASbGncsIOtccUWt5s5hSyAd9+nsVmVuWQsp0pdKPgQonsd879xgIua+Ekofm2skjf6X 6l7RTitQbcNnMoVebTB+dmizpnuztPhhS1dfEobVlNEQ62HogrOHtTcAWgR3alpFj0ZFduvkvCc mzpHWMfvFApe5HepL0jQ9RgT4WAGxHx4ol3bIumoDR5y6U0pTdJ4LF+WrA0IqswoNHW6S2Ww37o tCfepxuOLZU84qDJCXrPWXlIm7nyofOzPEsmV24tweTwjaSNhrLn6vICaNVcy7WmGQHHYUYDTmq J7dygqplclpiaGZt5Q5eW8+dNrZXclR7a9UxYfnmR21meVDWs2IOUkjbs8KjwhqmupUZ X-Received: by 2002:a17:902:f689:b0:21f:98fc:8414 with SMTP id d9443c01a7336-220d35e2297mr70289415ad.26.1739480646261; Thu, 13 Feb 2025 13:04:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IFgZkxefzAh1dnDM8xO5GuAGXCpKBllT6VbOz2bGnH6gN5UaFfTD4wPjuQFCzfXfUFkHcgqag== X-Received: by 2002:a17:902:f689:b0:21f:98fc:8414 with SMTP id d9443c01a7336-220d35e2297mr70288985ad.26.1739480645828; Thu, 13 Feb 2025 13:04:05 -0800 (PST) Received: from hu-amelende-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-220dacfc769sm14339375ad.201.2025.02.13.13.04.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2025 13:04:05 -0800 (PST) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] thermal: qcom-spmi-temp-alarm: enable stage 2 shutdown when required Date: Thu, 13 Feb 2025 13:04:00 -0800 Message-Id: <20250213210403.3396392-2-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250213210403.3396392-1-anjelique.melendez@oss.qualcomm.com> References: <20250213210403.3396392-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: kQjtbATrKKdO-sENlCebOehtOEmoAKef X-Proofpoint-ORIG-GUID: kQjtbATrKKdO-sENlCebOehtOEmoAKef X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-13_08,2025-02-13_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 mlxlogscore=999 phishscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 adultscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502130147 From: David Collins Certain TEMP_ALARM GEN2 PMIC peripherals need over-temperature stage 2 automatic PMIC partial shutdown to be enabled in order to avoid repeated faults in the event of reaching over-temperature stage 3. Modify the stage 2 shutdown control logic to ensure that stage 2 shutdown is enabled on all affected PMICs. Read the digital major and minor revision registers to identify these PMICs. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 32 +++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c index c2d59cbfaea9..b2077ff9fe73 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -16,6 +17,7 @@ #include "../thermal_hwmon.h" +#define QPNP_TM_REG_DIG_MINOR 0x00 #define QPNP_TM_REG_DIG_MAJOR 0x01 #define QPNP_TM_REG_TYPE 0x04 #define QPNP_TM_REG_SUBTYPE 0x05 @@ -71,6 +73,7 @@ struct qpnp_tm_chip { struct device *dev; struct thermal_zone_device *tz_dev; unsigned int subtype; + unsigned int dig_revision; long temp; unsigned int thresh; unsigned int stage; @@ -78,6 +81,7 @@ struct qpnp_tm_chip { /* protects .thresh, .stage and chip registers */ struct mutex lock; bool initialized; + bool require_s2_shutdown; struct iio_channel *adc; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; @@ -255,7 +259,7 @@ static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, skip: reg |= chip->thresh; - if (disable_s2_shutdown) + if (disable_s2_shutdown && !chip->require_s2_shutdown) reg |= SHUTDOWN_CTRL1_OVERRIDE_S2; return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg); @@ -350,7 +354,7 @@ static int qpnp_tm_probe(struct platform_device *pdev) { struct qpnp_tm_chip *chip; struct device_node *node; - u8 type, subtype, dig_major; + u8 type, subtype, dig_major, dig_minor; u32 res; int ret, irq; @@ -403,6 +407,30 @@ static int qpnp_tm_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, ret, "could not read dig_major\n"); + ret = qpnp_tm_read(chip, QPNP_TM_REG_DIG_MINOR, &dig_minor); + if (ret < 0) { + dev_err(&pdev->dev, "could not read dig_minor\n"); + return ret; + } + + chip->dig_revision = (dig_major << 8) | dig_minor; + + if (chip->subtype == QPNP_TM_SUBTYPE_GEN2) { + /* + * Check if stage 2 automatic partial shutdown must remain + * enabled to avoid potential repeated faults upon reaching + * over-temperature stage 3. + */ + switch (chip->dig_revision) { + case 0x0001: + case 0x0002: + case 0x0100: + case 0x0101: + chip->require_s2_shutdown = true; + break; + } + } + if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1 && subtype != QPNP_TM_SUBTYPE_GEN2)) { dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n", From patchwork Thu Feb 13 21:04:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anjelique Melendez X-Patchwork-Id: 865704 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6792F266B76 for ; Thu, 13 Feb 2025 21:04:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739480652; cv=none; b=M/fkVsUjMR7uGFxabDTqIgzG62Jincmpzf4DcvGipN0u30Dgm69gtiCiXJrcFUK1Xud/DJMtqIl+4EV2LfY9zS6WHX6dFie1w9slV5CkYoTRevO7ieX3Aa+I71HXxxiUbz2KryNtqyFowB+aR2vbuD8lKMFWn//SKrGHSyHntfU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739480652; c=relaxed/simple; bh=GM+4bhNAl1441YOTR5MbZ5/yN2e4mNV75gEtdPN/F1c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=A0EmyBH9V9WHsrfW7e+1/Dx4Tt1i9ZoUW+XOxTy+8VOTWlGwvE+ELeKo4SwV3ZOqV4YZbTIhKH3jr1KQQw7yd/GIEGjW1iDUiZ6ebuR4M3wZlRiJUyYZAc7wb0kvJZfYey7FEEvIxoYhcJFuNPHk9JIJZMnFl7VoNonE4CEIzB4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=nlAEbEhb; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="nlAEbEhb" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51DHN98c008091 for ; Thu, 13 Feb 2025 21:04:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=rSa4lNLlL57 Ev4X2zTTAhjSNjhxW2Koo6K25PXXREP8=; b=nlAEbEhb/OYR3tI/SQrL/srpiqF Yfujqbi6rnEyVMrfJIv0YL/v9qcl0y3ObrvJrR3g+HiM3t6Gkwq1TD93rNvF6lIY FfaeOpf7AYn8XVNTvAoWtON+wAeBLru6tUXY9wFsK5alire2GqU9DbwaAEE9xKzU SNe6IazVtnDrS46ESSgXOB93gpSRrWBNF9nU2D9XL3MXSh3oulZTkWm8ZA6ncxGg rWGNXwoD3pHESnp9WedrTd0a9jzDF8aAQX442E3ISKLwaIX4DqmKVJSLyE7nHcyE reu8/YiWH03ZtEjnnSpUiviDn7d7IJIChfWduwXumd1W7n1neSJ19eOblrg== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44rr1qw8s5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 13 Feb 2025 21:04:09 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-220e62c4fc2so8989655ad.3 for ; Thu, 13 Feb 2025 13:04:09 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739480648; x=1740085448; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rSa4lNLlL57Ev4X2zTTAhjSNjhxW2Koo6K25PXXREP8=; b=pKjFPMvYlJrD0WPvL4fdHGJ/PGlxzu9namovHLKeAfzK72lCstpcv7+bVK8FcoZ61K GhJ/gPvnOpxe2ci2Py2DLnp+p0x2DRaegGRrAMih5n45yvCQ9Ro3RapQ1yeSk69a5OJG 7baM5m8gY42UzQhKZ8hVMzuSVmKdZ080vwEHkj9uJTc9/DiPRavdmwR7nN9c1hBZuVZV DK35/YkTGO4vuxK+d2Ta0Q6o/dTCkszx1cL/yS1zKjxGQ9OaG3A2BFmEHuJa341xKy5I +S6CDpaWTSnBX4mYWc7IOrk5ARtXf2P5wRVsXcfAMCQY/tb1a+eF+KGROPQhJad0Lgfl 7bYw== X-Forwarded-Encrypted: i=1; AJvYcCXY6f6Hco1kIs6x4k0CTNmCFWp22f5EXmcyGstxCFTbFCyBklMYA8JAlOxy/38H9eECL2OL23tQTQ==@vger.kernel.org X-Gm-Message-State: AOJu0YwxtaJ/J7XAZhfXHuTmjonazM9Gt3I6WG1RgNN03QRrW2FIUYpS OGIrxTi3WGsqsTuspCNHVfqfCajCeJtCVOIHf7HfJ1PXFxG+NH5Ug5Vr0AtBcPcINAfq7e62D14 lf1BN18ihXK4gsLv9hLRZUIATMtqV9A0TrTNhdT5CUzGaaf5bJSoWeZRLxg== X-Gm-Gg: ASbGncuZ1p1s3QIETnbsVotpth1FcCpSGrR4e4Dylh9VrxJ7hVRvOpHNOUiFMEt7Ddq Ix7/2iPfG/cycOQOcpYFvrMpxgDj3Z0N+oW/tlErlIawlxawGaXLj4iHv/yWC1c9TNXk20uUmMW NhruOhwlVrLDzh7QGq0TbS8l1uQ8pbgV/eAJMgxSGMXiFOU19O0OOJBuV6RjzMVmgfkG6X1w+q9 tg1Htr1aRHXlZe4YuvRNz4UaG82qWoxJcYosqt90pm7s34gtmUNi+yPbBzZ4WXMOE1gGxv2xhkL kMSDsRMQVeXtpV8+HOMtLcZFZFpQHI00YdD9TbQ5wgVUDzqARq0Iz3wpzOtTC1+9UEO3 X-Received: by 2002:a17:902:e74e:b0:216:760c:3879 with SMTP id d9443c01a7336-220bbc7b79dmr146033185ad.46.1739480647605; Thu, 13 Feb 2025 13:04:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IFgKGFpXY49cB7/WgrJ0o/4+EO/NF/DO/9XpQ+ewKlCA1oyIhD8ja67LLFDR1fOkvkZtaSRIw== X-Received: by 2002:a17:902:e74e:b0:216:760c:3879 with SMTP id d9443c01a7336-220bbc7b79dmr146032745ad.46.1739480647163; Thu, 13 Feb 2025 13:04:07 -0800 (PST) Received: from hu-amelende-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-220dacfc769sm14339375ad.201.2025.02.13.13.04.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2025 13:04:06 -0800 (PST) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] thermal: qcom-spmi-temp-alarm: Add temp alarm data struct based on HW subtype Date: Thu, 13 Feb 2025 13:04:01 -0800 Message-Id: <20250213210403.3396392-3-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250213210403.3396392-1-anjelique.melendez@oss.qualcomm.com> References: <20250213210403.3396392-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: jthVsERnP1TujFuSgPvJluisqkknCqLd X-Proofpoint-ORIG-GUID: jthVsERnP1TujFuSgPvJluisqkknCqLd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-13_08,2025-02-13_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 mlxscore=0 impostorscore=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 suspectscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502130148 Currently multiple if/else statements are used in functions to decipher between SPMI temp alarm Gen 1, Gen 2 and Gen 2 Rev 1 functionality. Instead refactor the driver so that SPMI temp alarm chips will have reference to a spmi_temp_alarm_data struct which defines data and function callbacks based on the HW subtype. Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 143 +++++++++++++------- 1 file changed, 95 insertions(+), 48 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c index b2077ff9fe73..af71d4238340 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -31,7 +31,6 @@ #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0) #define STATUS_GEN2_STATE_MASK GENMASK(6, 4) -#define STATUS_GEN2_STATE_SHIFT 4 #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6) #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0) @@ -68,10 +67,20 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_COUNT] = { /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */ #define DEFAULT_TEMP 37000 +struct qpnp_tm_chip; + +struct spmi_temp_alarm_data { + const struct thermal_zone_device_ops *ops; + const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; + int (*get_temp_stage)(struct qpnp_tm_chip *chip); + int (*configure_trip_temps)(struct qpnp_tm_chip *chip); +}; + struct qpnp_tm_chip { struct regmap *map; struct device *dev; struct thermal_zone_device *tz_dev; + const struct spmi_temp_alarm_data *data; unsigned int subtype; unsigned int dig_revision; long temp; @@ -82,14 +91,11 @@ struct qpnp_tm_chip { struct mutex lock; bool initialized; bool require_s2_shutdown; + long temp_thresh_map[STAGE_COUNT]; struct iio_channel *adc; - const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; }; -/* This array maps from GEN2 alarm state to GEN1 alarm stage */ -static const unsigned int alarm_state_map[8] = {0, 1, 1, 2, 2, 3, 3, 3}; - static int qpnp_tm_read(struct qpnp_tm_chip *chip, u16 addr, u8 *data) { unsigned int val; @@ -118,34 +124,51 @@ static int qpnp_tm_write(struct qpnp_tm_chip *chip, u16 addr, u8 data) */ static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int stage) { - if (!chip->temp_map || chip->thresh >= THRESH_COUNT || stage == 0 || - stage > STAGE_COUNT) + if (stage == 0 || stage > STAGE_COUNT) return 0; - return (*chip->temp_map)[chip->thresh][stage - 1]; + return chip->temp_thresh_map[stage - 1]; } /** * qpnp_tm_get_temp_stage() - return over-temperature stage * @chip: Pointer to the qpnp_tm chip * - * Return: stage (GEN1) or state (GEN2) on success, or errno on failure. + * Return: stage on success, or errno on failure. */ static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip *chip) { + u8 reg = 0; int ret; + + ret = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, ®); + if (ret < 0) + return ret; + + return FIELD_GET(STATUS_GEN1_STAGE_MASK, reg); +} + +/* This array maps from GEN2 alarm state to GEN1 alarm stage */ +static const unsigned int alarm_state_map[8] = {0, 1, 1, 2, 2, 3, 3, 3}; + +/** + * qpnp_tm_get_gen2_temp_stage() - return over-temperature stage + * @chip: Pointer to the qpnp_tm chip + * + * Return: stage on success, or errno on failure. + */ +static int qpnp_tm_gen2_get_temp_stage(struct qpnp_tm_chip *chip) +{ u8 reg = 0; + int ret; ret = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, ®); if (ret < 0) return ret; - if (chip->subtype == QPNP_TM_SUBTYPE_GEN1) - ret = reg & STATUS_GEN1_STAGE_MASK; - else - ret = (reg & STATUS_GEN2_STATE_MASK) >> STATUS_GEN2_STATE_SHIFT; + ret = FIELD_GET(STATUS_GEN2_STATE_MASK, reg); - return ret; + return alarm_state_map[ret]; } /* @@ -154,23 +177,16 @@ static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip *chip) */ static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip) { - unsigned int stage, stage_new, stage_old; + unsigned int stage_new, stage_old; int ret; WARN_ON(!mutex_is_locked(&chip->lock)); - ret = qpnp_tm_get_temp_stage(chip); + ret = chip->data->get_temp_stage(chip); if (ret < 0) return ret; - stage = ret; - - if (chip->subtype == QPNP_TM_SUBTYPE_GEN1) { - stage_new = stage; - stage_old = chip->stage; - } else { - stage_new = alarm_state_map[stage]; - stage_old = alarm_state_map[chip->stage]; - } + stage_new = ret; + stage_old = chip->stage; if (stage_new > stage_old) { /* increasing stage, use lower bound */ @@ -182,7 +198,7 @@ static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip) - TEMP_STAGE_HYSTERESIS; } - chip->stage = stage; + chip->stage = stage_new; return 0; } @@ -222,8 +238,8 @@ static int qpnp_tm_get_temp(struct thermal_zone_device *tz, int *temp) static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, int temp) { - long stage2_threshold_min = (*chip->temp_map)[THRESH_MIN][1]; - long stage2_threshold_max = (*chip->temp_map)[THRESH_MAX][1]; + long stage2_threshold_min = (*chip->data->temp_map)[THRESH_MIN][1]; + long stage2_threshold_max = (*chip->data->temp_map)[THRESH_MAX][1]; bool disable_s2_shutdown = false; u8 reg; @@ -258,6 +274,8 @@ static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, } skip: + memcpy(chip->temp_thresh_map, chip->data->temp_map[chip->thresh], + sizeof(chip->temp_thresh_map)); reg |= chip->thresh; if (disable_s2_shutdown && !chip->require_s2_shutdown) reg |= SHUTDOWN_CTRL1_OVERRIDE_S2; @@ -295,6 +313,42 @@ static irqreturn_t qpnp_tm_isr(int irq, void *data) return IRQ_HANDLED; } +static int qpnp_tm_configure_trip_temp(struct qpnp_tm_chip *chip) +{ + int crit_temp, ret; + + mutex_unlock(&chip->lock); + + ret = thermal_zone_get_crit_temp(chip->tz_dev, &crit_temp); + if (ret) + crit_temp = THERMAL_TEMP_INVALID; + + mutex_lock(&chip->lock); + + return qpnp_tm_update_critical_trip_temp(chip, crit_temp); +} + +static const struct spmi_temp_alarm_data spmi_temp_alarm_data = { + .ops = &qpnp_tm_sensor_ops, + .temp_map = &temp_map_gen1, + .configure_trip_temps = qpnp_tm_configure_trip_temp, + .get_temp_stage = qpnp_tm_get_temp_stage, +}; + +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_data = { + .ops = &qpnp_tm_sensor_ops, + .temp_map = &temp_map_gen1, + .configure_trip_temps = qpnp_tm_configure_trip_temp, + .get_temp_stage = qpnp_tm_gen2_get_temp_stage, +}; + +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev1_data = { + .ops = &qpnp_tm_sensor_ops, + .temp_map = &temp_map_gen2_v1, + .configure_trip_temps = qpnp_tm_configure_trip_temp, + .get_temp_stage = qpnp_tm_gen2_get_temp_stage, +}; + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. Setup threshold control and @@ -305,7 +359,6 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) unsigned int stage; int ret; u8 reg = 0; - int crit_temp; mutex_lock(&chip->lock); @@ -316,26 +369,15 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) chip->thresh = reg & SHUTDOWN_CTRL1_THRESHOLD_MASK; chip->temp = DEFAULT_TEMP; - ret = qpnp_tm_get_temp_stage(chip); - if (ret < 0) + stage = chip->data->get_temp_stage(chip); + if (stage < 0) goto out; - chip->stage = ret; - - stage = chip->subtype == QPNP_TM_SUBTYPE_GEN1 - ? chip->stage : alarm_state_map[chip->stage]; + chip->stage = stage; if (stage) chip->temp = qpnp_tm_decode_temp(chip, stage); - mutex_unlock(&chip->lock); - - ret = thermal_zone_get_crit_temp(chip->tz_dev, &crit_temp); - if (ret) - crit_temp = THERMAL_TEMP_INVALID; - - mutex_lock(&chip->lock); - - ret = qpnp_tm_update_critical_trip_temp(chip, crit_temp); + ret = chip->data->configure_trip_temps(chip); if (ret < 0) goto out; @@ -439,10 +481,15 @@ static int qpnp_tm_probe(struct platform_device *pdev) } chip->subtype = subtype; - if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major >= 1) - chip->temp_map = &temp_map_gen2_v1; + + if (subtype == QPNP_TM_SUBTYPE_GEN1) + chip->data = &spmi_temp_alarm_data; + else if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major >= 1) + chip->data = &spmi_temp_alarm_gen2_rev1_data; + else if (subtype == QPNP_TM_SUBTYPE_GEN2) + chip->data = &spmi_temp_alarm_gen2_data; else - chip->temp_map = &temp_map_gen1; + return -ENODEV; /* * Register the sensor before initializing the hardware to be able to @@ -450,7 +497,7 @@ static int qpnp_tm_probe(struct platform_device *pdev) * before the hardware initialization is completed. */ chip->tz_dev = devm_thermal_of_zone_register( - &pdev->dev, 0, chip, &qpnp_tm_sensor_ops); + &pdev->dev, 0, chip, chip->data->ops); if (IS_ERR(chip->tz_dev)) return dev_err_probe(&pdev->dev, PTR_ERR(chip->tz_dev), "failed to register sensor\n"); From patchwork Thu Feb 13 21:04:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anjelique Melendez X-Patchwork-Id: 865006 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36EAF26980C for ; Thu, 13 Feb 2025 21:04:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739480652; cv=none; b=aX50oSCEc3YmhmtcZl6n6GSKGibxCUCiN8sa+0n3Qk4H7Mf2JmNSJiEwvvoVBeCCFPgCBHS97GtNnC4Zp46zf5FDiYnWC7p/uPR4ULdh/TulgsC7Y0cu6kSXOED6uEOcnps242b97W7A5DH7Mbx/0CUxecGgMeKXWDsd07vPRyM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739480652; c=relaxed/simple; bh=RI03jic5DoODF2Ud42i4jxiHLYF7EG5DlqIewOfwoWw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Y/VM+D8MC4bWPhwbZXiiq8BlbzuT2IjDGu8qKxtP4m/ZHToENdj+dgwEqKlZMQHVkbYuYF+jhyufqXB0kJ/uy1tOiyYn86sWYix8L0ywksZtg5Bf/50Gqz9fP/J3yFAENrNrtFKfOa8bZha4TiC4zdgyLXOKCiTQ59/WC8Dc+Nk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=lW7IN9Kb; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="lW7IN9Kb" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51DJqUbv028708 for ; Thu, 13 Feb 2025 21:04:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=tV/aMqmQdVU PKtTU3soSpl6m/OCQWaKUT3FDY13LKkk=; b=lW7IN9KbMvAaTR/bZmjL1Ps+E8I GcFl+5ZTGs+bt8XGbqgpqkOin11Ool5Y1peixFaj/vPrwPMm4wtu3rfHybBkDtrV +Y9Av67o6YFftgrUdQNisTBmyCz97OEQSDzcT7CrIQtqS3OEDrVlwrcYX39sF8H7 SLGj0Xm0QSNuYiJ6ys8zvKb3UKUzPJ3r0FiTW91l6RWGDqb45y3B0kwDy1p2NElK heZcm/IploBa13LiZeTgsBJMWqgbCx/gSVX+8zj2ryeMDwGn+FMbp8y9Mj7GYjlo t3MqMk6QzoGaXKG332orBvr6VGsx7hrWghb92wpTrN8RRiZ0+7GAaK2WIgA== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44sebn9qw8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 13 Feb 2025 21:04:10 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-21f68852b7bso47179315ad.1 for ; Thu, 13 Feb 2025 13:04:10 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739480649; x=1740085449; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tV/aMqmQdVUPKtTU3soSpl6m/OCQWaKUT3FDY13LKkk=; b=CCXwKbgWNq009ty28pxstgvDouOx7xeVVjczdOi3+yTygeOFcSXnzAHVNFU055VB32 ED4NOSGo8jmVB59eax+lvVPHYLWdnyLXXFxATnAjBILzlec6ZJ6IWb1olq2YFVjZP6ZZ QX0y13+G+QeO2iUAe8zooebDNGjI95IIT9LvI3iZEGW2BSVXJ4sDtOFray/zSmvKqxeJ +54fcTgC5dQgNZekeHlyUomoK7R3XFqpZfjozRPrCHSYXoDuD4N1n+J+zj0BLfFPORrh BUb0TwyactBotnhbJyHncrhMua3CkIXA1oigrlV8nfhlTNWduHq0OBraE6WUis64LVY0 FFnA== X-Forwarded-Encrypted: i=1; AJvYcCU1YGpygo9g7SSmkP7h93wST7CNsxaNxEtN0U1ibjM76bLKnmB7QPGSZceJMyHMR8KlU00tVugRkQ==@vger.kernel.org X-Gm-Message-State: AOJu0YxHW8WhK3HyZlhHeyJtUA0+hZ2tm6Q/e5NEE0dLrvsFwt+rB+IH bPx9FWV4Mcmh63afmIONLfDqOCIPIobEgk+DrOROYGdTSc4P2yNQjSSp2nP69bIeKAP4HeyjwzG 8HjllQ1/wRZnO4b55+e7kxmd/OOYJne9M1Z3zkGAYDuGFCdlo1CDY31QdcXbYWGRryA== X-Gm-Gg: ASbGncum4SkmD3HydB1VOXF3cG8SgUXQTuavmhoImI7irM6kzxDrHF/LNEc1PBeIPQM Wd6PP1mm8uFaZCBbGsu/5ugobka0NWRmFOhhuj3FRsgW+MUJfOgcBLJvuRGjvDmEaul5prpJ4y0 Jwn8IwuOqUf9Mx38FBSy1p5NffFHDc2heUf/BD9g4DrJYA7w8e7LBNqcuXym5jvGuwzm5nHSyhS RDMOMwXGumePbFevbWmzOrSNZOedbhPcenmoicncOsSZtmbF4O0u3TvVrD8RE0Fx9P5Z/uGjLgg jUccOwtS4syRedxPbgdgMQyIXXkdEqMtAyYZTTykj2/80aZNwMSap584CbAFEGY0sM5l X-Received: by 2002:a17:902:ecc4:b0:216:2474:3c9f with SMTP id d9443c01a7336-220bbdf188dmr130666985ad.52.1739480648776; Thu, 13 Feb 2025 13:04:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IH9zLko3u11MbZvHhmrlovw6VTGrXYSekGUZQPeHBW0JNIWw3OrQm1fOmrQL2az7eFMnokhsQ== X-Received: by 2002:a17:902:ecc4:b0:216:2474:3c9f with SMTP id d9443c01a7336-220bbdf188dmr130666475ad.52.1739480648273; Thu, 13 Feb 2025 13:04:08 -0800 (PST) Received: from hu-amelende-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-220dacfc769sm14339375ad.201.2025.02.13.13.04.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2025 13:04:07 -0800 (PST) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] thermal: qcom-spmi-temp-alarm: add support for GEN2 rev 2 PMIC peripherals Date: Thu, 13 Feb 2025 13:04:02 -0800 Message-Id: <20250213210403.3396392-4-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250213210403.3396392-1-anjelique.melendez@oss.qualcomm.com> References: <20250213210403.3396392-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: XvbYwfzSPiidDPGE4wf4je3wgQlc_KVl X-Proofpoint-ORIG-GUID: XvbYwfzSPiidDPGE4wf4je3wgQlc_KVl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-13_08,2025-02-13_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 lowpriorityscore=0 clxscore=1011 mlxlogscore=999 phishscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 adultscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502130147 Add support for TEMP_ALARM GEN2 PMIC peripherals with digital major revision 2. This revision utilizes individual temp DAC registers to set the threshold temperature for over-temperature stages 1, 2, and 3 instead of a single register to specify a set of thresholds. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 136 ++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c index af71d4238340..a10f368f2039 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -25,6 +25,11 @@ #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 #define QPNP_TM_REG_ALARM_CTRL 0x46 +/* TEMP_DAC_STGx registers are only present for TEMP_GEN2 v2.0 */ +#define QPNP_TM_REG_TEMP_DAC_STG1 0x47 +#define QPNP_TM_REG_TEMP_DAC_STG2 0x48 +#define QPNP_TM_REG_TEMP_DAC_STG3 0x49 + #define QPNP_TM_TYPE 0x09 #define QPNP_TM_SUBTYPE_GEN1 0x08 #define QPNP_TM_SUBTYPE_GEN2 0x09 @@ -64,6 +69,25 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_COUNT] = { #define TEMP_STAGE_HYSTERESIS 2000 +/* + * For TEMP_GEN2 v2.0, TEMP_DAC_STG1/2/3 registers are used to set the threshold + * for each stage independently. + * TEMP_DAC_STG* = 0 --> 80 C + * Each 8 step increase in TEMP_DAC_STG* value corresponds to 5 C (5000 mC). + */ +#define TEMP_DAC_MIN 80000 +#define TEMP_DAC_SCALE_NUM 8 +#define TEMP_DAC_SCALE_DEN 5000 + +#define TEMP_DAC_TEMP_TO_REG(temp) \ + (((temp) - TEMP_DAC_MIN) * TEMP_DAC_SCALE_NUM / TEMP_DAC_SCALE_DEN) +#define TEMP_DAC_REG_TO_TEMP(reg) \ + (TEMP_DAC_MIN + (reg) * TEMP_DAC_SCALE_DEN / TEMP_DAC_SCALE_NUM) + +static const long temp_dac_max[STAGE_COUNT] = { + 119375, 159375, 159375 +}; + /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */ #define DEFAULT_TEMP 37000 @@ -72,6 +96,7 @@ struct qpnp_tm_chip; struct spmi_temp_alarm_data { const struct thermal_zone_device_ops *ops; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; + int (*setup)(struct qpnp_tm_chip *chip); int (*get_temp_stage)(struct qpnp_tm_chip *chip); int (*configure_trip_temps)(struct qpnp_tm_chip *chip); }; @@ -87,6 +112,7 @@ struct qpnp_tm_chip { unsigned int thresh; unsigned int stage; unsigned int base; + unsigned int ntrips; /* protects .thresh, .stage and chip registers */ struct mutex lock; bool initialized; @@ -304,6 +330,52 @@ static const struct thermal_zone_device_ops qpnp_tm_sensor_ops = { .set_trip_temp = qpnp_tm_set_trip_temp, }; +static int qpnp_tm_gen2_rev2_set_temp_thresh(struct qpnp_tm_chip *chip, int trip, int temp) +{ + int ret, temp_cfg; + u8 reg; + + if (trip < 0 || trip >= STAGE_COUNT) { + dev_err(chip->dev, "invalid TEMP_DAC trip = %d\n", trip); + return -EINVAL; + } else if (temp < TEMP_DAC_MIN || temp > temp_dac_max[trip]) { + dev_err(chip->dev, "invalid TEMP_DAC temp = %d\n", temp); + return -EINVAL; + } + + reg = TEMP_DAC_TEMP_TO_REG(temp); + temp_cfg = TEMP_DAC_REG_TO_TEMP(reg); + + ret = qpnp_tm_write(chip, QPNP_TM_REG_TEMP_DAC_STG1 + trip, reg); + if (ret < 0) { + dev_err(chip->dev, "TEMP_DAC_STG write failed, ret=%d\n", ret); + return ret; + } + + chip->temp_thresh_map[trip] = temp_cfg; + + return 0; +} + +static int qpnp_tm_gen2_rev2_set_trip_temp(struct thermal_zone_device *tz, + const struct thermal_trip *trip, int temp) +{ + unsigned int trip_index = THERMAL_TRIP_PRIV_TO_INT(trip->priv); + struct qpnp_tm_chip *chip = thermal_zone_device_priv(tz); + int ret; + + mutex_lock(&chip->lock); + ret = qpnp_tm_gen2_rev2_set_temp_thresh(chip, trip_index, temp); + mutex_unlock(&chip->lock); + + return ret; +} + +static const struct thermal_zone_device_ops qpnp_tm_gen2_rev2_sensor_ops = { + .get_temp = qpnp_tm_get_temp, + .set_trip_temp = qpnp_tm_gen2_rev2_set_trip_temp, +}; + static irqreturn_t qpnp_tm_isr(int irq, void *data) { struct qpnp_tm_chip *chip = data; @@ -328,6 +400,58 @@ static int qpnp_tm_configure_trip_temp(struct qpnp_tm_chip *chip) return qpnp_tm_update_critical_trip_temp(chip, crit_temp); } +/* Configure TEMP_DAC registers based on DT thermal_zone trips */ +static int qpnp_tm_gen2_rev2_configure_trip_temps_cb(struct thermal_trip *trip, void *data) +{ + struct qpnp_tm_chip *chip = data; + int ret; + + trip->priv = THERMAL_INT_TO_TRIP_PRIV(chip->ntrips); + ret = qpnp_tm_gen2_rev2_set_temp_thresh(chip, chip->ntrips, trip->temperature); + chip->ntrips++; + + return ret; +} + +static int qpnp_tm_gen2_rev2_configure_trip_temps(struct qpnp_tm_chip *chip) +{ + int ret, i; + + ret = thermal_zone_for_each_trip(chip->tz_dev, + qpnp_tm_gen2_rev2_configure_trip_temps_cb, chip); + if (ret < 0) + return ret; + + /* Verify that trips are strictly increasing. */ + for (i = 1; i < STAGE_COUNT; i++) { + if (chip->temp_thresh_map[i] <= chip->temp_thresh_map[i - 1]) { + dev_err(chip->dev, "Threshold %d=%ld <= threshold %d=%ld\n", + i, chip->temp_thresh_map[i], i - 1, + chip->temp_thresh_map[i - 1]); + return -EINVAL; + } + } + + return 0; +} + +/* Read the hardware default TEMP_DAC stage threshold temperatures */ +static int qpnp_tm_gen2_rev2_init(struct qpnp_tm_chip *chip) +{ + int ret, i; + u8 reg = 0; + + for (i = 0; i < STAGE_COUNT; i++) { + ret = qpnp_tm_read(chip, QPNP_TM_REG_TEMP_DAC_STG1 + i, ®); + if (ret < 0) + return ret; + + chip->temp_thresh_map[i] = TEMP_DAC_REG_TO_TEMP(reg); + } + + return 0; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data = { .ops = &qpnp_tm_sensor_ops, .temp_map = &temp_map_gen1, @@ -349,6 +473,13 @@ static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev1_data = { .get_temp_stage = qpnp_tm_gen2_get_temp_stage, }; +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev2_data = { + .ops = &qpnp_tm_gen2_rev2_sensor_ops, + .setup = qpnp_tm_gen2_rev2_init, + .configure_trip_temps = qpnp_tm_gen2_rev2_configure_trip_temps, + .get_temp_stage = qpnp_tm_gen2_get_temp_stage, +}; + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. Setup threshold control and @@ -484,6 +615,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) if (subtype == QPNP_TM_SUBTYPE_GEN1) chip->data = &spmi_temp_alarm_data; + else if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major >= 2) + chip->data = &spmi_temp_alarm_gen2_rev2_data; else if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major >= 1) chip->data = &spmi_temp_alarm_gen2_rev1_data; else if (subtype == QPNP_TM_SUBTYPE_GEN2) @@ -491,6 +624,9 @@ static int qpnp_tm_probe(struct platform_device *pdev) else return -ENODEV; + if (chip->data->setup) + chip->data->setup(chip); + /* * Register the sensor before initializing the hardware to be able to * read the trip points. get_temp() returns the default temperature From patchwork Thu Feb 13 21:04:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anjelique Melendez X-Patchwork-Id: 865703 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 886A1266B65 for ; Thu, 13 Feb 2025 21:04:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739480653; cv=none; b=fadexnzXUpu+huzE6a0Fk8l9mZpC+N2fm2D7CC9h7iL9zXR8uTYn0JlHybfUxqP6avr6dHpvYVR79hns2+JnNa6n5CtEwVT3ME2JJJMJgh9aTaTtXDh9kRwUb80fejEd+H9Kp+vj6uJrwtvStqIzWv/jhPmYIdzPw8bqbmKNiGM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739480653; c=relaxed/simple; bh=DecLmToxwMQkR8jL+PSo4Tt2J4g+s8DpyxCx4NCWX3Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Q455DefnI4uwLbyzeUUPouim3nMAJ03U5JJXSjCnfMPdv3hXn3eN5jCqBwJX2IfeTQpVfiU8P08uCTXL0kEZEo9e4I1GRYAK4iZDblW9AWmgpdssOzYck8bbKrR9nyclv1E88TsZiuNcCm+KJXZ7D7Ndg9vRbqMFYPCFsIUZ3NM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=YEr3JE7G; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="YEr3JE7G" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51DHocxA007881 for ; Thu, 13 Feb 2025 21:04:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=ix8czGogiPA veGuEM67krjF1GRJMfjhSqgWNw496tqY=; b=YEr3JE7G9y/Y7Zz5CTVFPkpHNeK Qtc4KiE/qjV5PKhd4OQI4CyQGyE7uwirlox2h+qXlqo6VBePpL6/9EFtgr5dmm2H 6KhqwGi2oKVysP1b/CoSdoEd9zSqjmecSS9YBvaROpEHKZj6EyPVTeLXvI+A6CTe kah6wuFFTMlMHid7v/pa9K4z3OZbZvi9UPVInpy1D7oBt28GATgJYgf2DvgOSfpC AgHKgu1RTHgISYtLI2egx3IZlCsY86V29Yc1KmBOZIjIMwhqq32VqhByFoTLvl4B w51k2PTJJZaR0DCYSi3SPMn8EixTygtsD2FV4r26fT0fOfcY2otmWjXzsbQ== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44rr1qw8sa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 13 Feb 2025 21:04:10 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-21f7671a821so26600345ad.1 for ; Thu, 13 Feb 2025 13:04:10 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739480650; x=1740085450; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ix8czGogiPAveGuEM67krjF1GRJMfjhSqgWNw496tqY=; b=sUh0sSL99uPLINUEv7BYaWresKyLIdCGTTm8M1nmJeNtXPqwTZ7NV7yE7f9EJGVQm7 AZ0RQ8B4TIs3qGcsj/dRPrhBeQhfJVZBvCU/2ulaXpDtGOf61O6eP53bEZQ9l2LO99+p HASYuzDDUvxJKelln9QT5wELzZPnP+5O7vErtytGnQtQNTTn2JwSLZE+DV3ZtEmAC4h9 mAHmRU0JNk2V8iJl4sNddKDi162dweXez0aKbuD+WsJ8C5GChEeRX32w6t5vplfX4eGO hfEx0E6hWGJe/NoBkqH5k34dMn7sdO3RU0lbSAiPndzWI9VweoRkj6mgF547S2QkzxBI xX2Q== X-Forwarded-Encrypted: i=1; AJvYcCUjCRB4han9cp9HMqUwRwwjar5pmKVhOho8m2A0S+6cOXZmBoOqsRebzzOr5Lk8ouHCE1zDdfraeA==@vger.kernel.org X-Gm-Message-State: AOJu0YwdFNYgIesRndYLoPA9ON1HKTC2SdjZb7kWTB3k3+7qoyJVwHk3 joERII5sehw9jh4p3mCTEpT3maI/HMyOAY86bKyNMkerR1wY6dQh+exifod/3rgA2FkBVRbQO48 mhud89WMs6EQ2vU1KnBq8OCueVfXAchjfCVI8URmuqqYK3opRdGj2rrWioA== X-Gm-Gg: ASbGncu9aU8ifLVoD5+KM8hm9M1VX7E5tqJvG7SajhwAPE3fYyGZ23XyHqGdrcQDjid HB3LLHeCZu9RLBcl6lpssfGY3b92OvEkeOgvxoYGoXdG9lnIOPtaKu8+D9XYFqyg9M+jz2UgDJn NGQead4k0rHWV2jvcWrcv2xe1+SZtDP/mJkCh3yy1EqU/jWRUp3ojrPH1S65rFHjAndFlKGAvju dOz3vDA2u37M2vjgs8i4JiXgz6eFW6bwcoYCZC26vRa0BWiEBBMavpTiYQtCQo56fjCGM5RSHmb eLz7ZI+Nr2lrPapkqzVPndkMJIDiAVyrLkMAyXksKeU4yC97k4jn6u4PMHPDT1nFnZji X-Received: by 2002:a17:903:290:b0:216:7ee9:220b with SMTP id d9443c01a7336-220d1eee443mr87217735ad.22.1739480649776; Thu, 13 Feb 2025 13:04:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IGxiHWh5/198xxh/vHKG28dp2GWtimkNHpX9GPLIowPDihT48qdQifh6lQ3aKFPzNiGhGDi6g== X-Received: by 2002:a17:903:290:b0:216:7ee9:220b with SMTP id d9443c01a7336-220d1eee443mr87217315ad.22.1739480649332; Thu, 13 Feb 2025 13:04:09 -0800 (PST) Received: from hu-amelende-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-220dacfc769sm14339375ad.201.2025.02.13.13.04.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2025 13:04:09 -0800 (PST) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] thermal: qcom-spmi-temp-alarm: add support for LITE PMIC peripherals Date: Thu, 13 Feb 2025 13:04:03 -0800 Message-Id: <20250213210403.3396392-5-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250213210403.3396392-1-anjelique.melendez@oss.qualcomm.com> References: <20250213210403.3396392-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: 0K6PF2JXnUJvQWgfNVXV8jb7nuaJHm_x X-Proofpoint-ORIG-GUID: 0K6PF2JXnUJvQWgfNVXV8jb7nuaJHm_x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-13_08,2025-02-13_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 mlxscore=0 impostorscore=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 suspectscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502130148 Add support for TEMP_ALARM LITE PMIC peripherals. This subtype utilizes a pair of registers to configure a warning interrupt threshold temperature and an automatic hardware shutdown threshold temperature. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 204 +++++++++++++++++++- 1 file changed, 203 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c index a10f368f2039..081db1a85b8a 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -22,6 +22,7 @@ #define QPNP_TM_REG_TYPE 0x04 #define QPNP_TM_REG_SUBTYPE 0x05 #define QPNP_TM_REG_STATUS 0x08 +#define QPNP_TM_REG_IRQ_STATUS 0x10 #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 #define QPNP_TM_REG_ALARM_CTRL 0x46 @@ -29,14 +30,20 @@ #define QPNP_TM_REG_TEMP_DAC_STG1 0x47 #define QPNP_TM_REG_TEMP_DAC_STG2 0x48 #define QPNP_TM_REG_TEMP_DAC_STG3 0x49 +#define QPNP_TM_REG_LITE_TEMP_CFG1 0x50 +#define QPNP_TM_REG_LITE_TEMP_CFG2 0x51 #define QPNP_TM_TYPE 0x09 #define QPNP_TM_SUBTYPE_GEN1 0x08 #define QPNP_TM_SUBTYPE_GEN2 0x09 +#define QPNP_TM_SUBTYPE_LITE 0xC0 #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0) #define STATUS_GEN2_STATE_MASK GENMASK(6, 4) +/* IRQ status only needed for TEMP_ALARM_LITE */ +#define IRQ_STATUS_MASK BIT(0) + #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6) #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0) @@ -44,6 +51,8 @@ #define ALARM_CTRL_FORCE_ENABLE BIT(7) +#define LITE_TEMP_CFG_THRESHOLD_MASK GENMASK(3, 2) + #define THRESH_COUNT 4 #define STAGE_COUNT 3 @@ -88,6 +97,19 @@ static const long temp_dac_max[STAGE_COUNT] = { 119375, 159375, 159375 }; +/* + * TEMP_ALARM_LITE has two stages: warning and shutdown with independently + * configured threshold temperatures. + */ + +static const long temp_lite_warning_map[THRESH_COUNT] = { + 115000, 125000, 135000, 145000 +}; + +static const long temp_lite_shutdown_map[THRESH_COUNT] = { + 135000, 145000, 160000, 175000 +}; + /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */ #define DEFAULT_TEMP 37000 @@ -197,6 +219,24 @@ static int qpnp_tm_gen2_get_temp_stage(struct qpnp_tm_chip *chip) return alarm_state_map[ret]; } +/** + * qpnp_tm_lite_get_temp_stage() - return over-temperature stage + * @chip: Pointer to the qpnp_tm chip + * + * Return: alarm interrupt state on success, or errno on failure. + */ +static int qpnp_tm_lite_get_temp_stage(struct qpnp_tm_chip *chip) +{ + u8 reg = 0; + int ret; + + ret = qpnp_tm_read(chip, QPNP_TM_REG_IRQ_STATUS, ®); + if (ret < 0) + return ret; + + return reg & IRQ_STATUS_MASK; +} + /* * This function updates the internal temp value based on the * current thermal stage and threshold as well as the previous stage @@ -376,6 +416,96 @@ static const struct thermal_zone_device_ops qpnp_tm_gen2_rev2_sensor_ops = { .set_trip_temp = qpnp_tm_gen2_rev2_set_trip_temp, }; +static int qpnp_tm_lite_set_temp_thresh(struct qpnp_tm_chip *chip, int trip, int temp) +{ + int ret, temp_cfg, i; + const long *temp_map; + u16 addr; + u8 reg, thresh; + + if (trip < 0 || trip >= STAGE_COUNT) { + dev_err(chip->dev, "invalid TEMP_LITE trip = %d\n", trip); + return -EINVAL; + } + + switch (trip) { + case 0: + temp_map = temp_lite_warning_map; + addr = QPNP_TM_REG_LITE_TEMP_CFG1; + break; + case 1: + /* + * The second trip point is purely in software to facilitate + * a controlled shutdown after the warning threshold is crossed + * but before the automatic hardware shutdown threshold is + * crossed. + */ + return 0; + case 2: + temp_map = temp_lite_shutdown_map; + addr = QPNP_TM_REG_LITE_TEMP_CFG2; + break; + default: + return 0; + } + + if (temp < temp_map[THRESH_MIN] || temp > temp_map[THRESH_MAX]) { + dev_err(chip->dev, "invalid TEMP_LITE temp = %d\n", temp); + return -EINVAL; + } + + thresh = 0; + temp_cfg = temp_map[thresh]; + for (i = THRESH_MAX; i >= THRESH_MIN; i--) { + if (temp >= temp_map[i]) { + thresh = i; + temp_cfg = temp_map[i]; + break; + } + } + + if (temp_cfg == chip->temp_thresh_map[trip]) + return 0; + + ret = qpnp_tm_read(chip, addr, ®); + if (ret < 0) { + dev_err(chip->dev, "LITE_TEMP_CFG read failed, ret=%d\n", ret); + return ret; + } + + reg &= ~LITE_TEMP_CFG_THRESHOLD_MASK; + reg |= FIELD_PREP(LITE_TEMP_CFG_THRESHOLD_MASK, thresh); + + ret = qpnp_tm_write(chip, addr, reg); + if (ret < 0) { + dev_err(chip->dev, "LITE_TEMP_CFG write failed, ret=%d\n", ret); + return ret; + } + + chip->temp_thresh_map[trip] = temp_cfg; + + return 0; +} + +static int qpnp_tm_lite_set_trip_temp(struct thermal_zone_device *tz, + const struct thermal_trip *trip, int temp) +{ + unsigned int trip_index = THERMAL_TRIP_PRIV_TO_INT(trip->priv); + struct qpnp_tm_chip *chip = thermal_zone_device_priv(tz); + int ret; + + mutex_lock(&chip->lock); + ret = qpnp_tm_lite_set_temp_thresh(chip, trip_index, temp); + mutex_unlock(&chip->lock); + + return ret; +} + +static const struct thermal_zone_device_ops qpnp_tm_lite_sensor_ops = { + .get_temp = qpnp_tm_get_temp, + .set_trip_temp = qpnp_tm_lite_set_trip_temp, +}; + static irqreturn_t qpnp_tm_isr(int irq, void *data) { struct qpnp_tm_chip *chip = data; @@ -452,6 +582,68 @@ static int qpnp_tm_gen2_rev2_init(struct qpnp_tm_chip *chip) return 0; } +/* Configure TEMP_LITE registers based on DT thermal_zone trips */ +static int qpnp_tm_lite_configure_trip_temps_cb(struct thermal_trip *trip, void *data) +{ + struct qpnp_tm_chip *chip = data; + int ret; + + trip->priv = THERMAL_INT_TO_TRIP_PRIV(chip->ntrips); + ret = qpnp_tm_lite_set_temp_thresh(chip, chip->ntrips, trip->temperature); + chip->ntrips++; + + return ret; +} + +static int qpnp_tm_lite_configure_trip_temps(struct qpnp_tm_chip *chip) +{ + int ret; + + ret = thermal_zone_for_each_trip(chip->tz_dev, qpnp_tm_lite_configure_trip_temps_cb, chip); + if (ret < 0) + return ret; + + /* Verify that trips are strictly increasing. */ + if (chip->temp_thresh_map[2] <= chip->temp_thresh_map[0]) { + dev_err(chip->dev, "Threshold 2=%ld <= threshold 0=%ld\n", + chip->temp_thresh_map[2], chip->temp_thresh_map[0]); + return -EINVAL; + } + + return 0; +} + +/* Read the hardware default TEMP_LITE stage threshold temperatures */ +static int qpnp_tm_lite_init(struct qpnp_tm_chip *chip) +{ + int ret, thresh; + u8 reg = 0; + + /* + * Store the warning trip temp in temp_thresh_map[0] and the shutdown trip + * temp in temp_thresh_map[2]. The second trip point is purely in software + * to facilitate a controlled shutdown after the warning threshold is + * crossed but before the automatic hardware shutdown threshold is + * crossed. Thus, there is no register to read for the second trip + * point. + */ + ret = qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG1, ®); + if (ret < 0) + return ret; + + thresh = FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg); + chip->temp_thresh_map[0] = temp_lite_warning_map[thresh]; + + ret = qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG2, ®); + if (ret < 0) + return ret; + + thresh = FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg); + chip->temp_thresh_map[2] = temp_lite_shutdown_map[thresh]; + + return 0; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data = { .ops = &qpnp_tm_sensor_ops, .temp_map = &temp_map_gen1, @@ -480,6 +672,13 @@ static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev2_data = { .get_temp_stage = qpnp_tm_gen2_get_temp_stage, }; +static const struct spmi_temp_alarm_data spmi_temp_alarm_lite_data = { + .ops = &qpnp_tm_lite_sensor_ops, + .setup = qpnp_tm_lite_init, + .configure_trip_temps = qpnp_tm_lite_configure_trip_temps, + .get_temp_stage = qpnp_tm_lite_get_temp_stage, +}; + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. Setup threshold control and @@ -605,7 +804,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) } if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1 - && subtype != QPNP_TM_SUBTYPE_GEN2)) { + && subtype != QPNP_TM_SUBTYPE_GEN2 + && subtype != QPNP_TM_SUBTYPE_LITE)) { dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n", type, subtype); return -ENODEV; @@ -621,6 +821,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) chip->data = &spmi_temp_alarm_gen2_rev1_data; else if (subtype == QPNP_TM_SUBTYPE_GEN2) chip->data = &spmi_temp_alarm_gen2_data; + else if (subtype == QPNP_TM_SUBTYPE_LITE) + chip->data = &spmi_temp_alarm_lite_data; else return -ENODEV;