From patchwork Fri Feb 14 00:37:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 865187 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AB1B517E; Fri, 14 Feb 2025 00:40:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739493605; cv=none; b=n2k1rvViSblGA+aqnaCI4WfVukPRumIxqNG+bTNc0I+z+aSStgfg3w1ZJJD2Xsg7gFZkrSRGLsHXZEwT+hYuMl+jQitzUo8AXlaOYASgdhLS6a2+BDUvGQmA4RqlOq1C3qbMpaUk37ghauxm50iJLDZK1DOMnUd04l8gp3zQdMs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739493605; c=relaxed/simple; bh=121spaMlpCdmk+wzfSLjmbf5MLhgPjLXeYoXRdBa9Cw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=phqWxjLHbQRgJBTPqXcAM0F1Y4iWRVFQQiVouzeF2tT639S1e70LLRB6/v2TNlzT10eROAekVODRTX2yC4p/5BEJ5x3FK4fHjdBORlJ+Q4mzBMNVS+13di7XVKKxk6MXUSBZnMl1Ha1dkN5Xzwt/97suWX1ARvoq79TbkjV2byI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8EFF81A9A; Thu, 13 Feb 2025 16:40:23 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 69B303F5A1; Thu, 13 Feb 2025 16:40:01 -0800 (PST) From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/8] pinctrl: sunxi: increase number of GPIO bank regulators Date: Fri, 14 Feb 2025 00:37:28 +0000 Message-ID: <20250214003734.14944-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250214003734.14944-1-andre.przywara@arm.com> References: <20250214003734.14944-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 By design, the Allwinner pinctrl IP always supported up to 11 GPIO banks, though no SoC ever used more than 9 banks so far. The Allwinner A523 has pins in all 11 banks, which exceeds the number of per-bank regulators that we currently support, as this was set to 9. Increase the size of the array to hold up to 11 regulator structs, to support pins in bank J and K as well. Signed-off-by: Andre Przywara --- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 8e2eca45b57f8..fbbf070a87542 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -155,7 +155,7 @@ struct sunxi_pinctrl { struct gpio_chip *chip; const struct sunxi_pinctrl_desc *desc; struct device *dev; - struct sunxi_pinctrl_regulator regulators[9]; + struct sunxi_pinctrl_regulator regulators[11]; struct irq_domain *domain; struct sunxi_pinctrl_function *functions; unsigned nfunctions; From patchwork Fri Feb 14 00:37:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 865186 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 710D177F11; Fri, 14 Feb 2025 00:40:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739493609; cv=none; b=p7SvMMDg5I0sAmYcyGzHuNjN0RTwpnvjtzo9XpiXX25XYkOAOS1ZplcDihwWBs1lrGIppqWtaFHININp1grC0ZgSt6s1tk5KkiDXT0u7Kqrf+tHRk/bjfE7V1jAwbWjYymZc/ZDsosiUeNJecFzxkdDR9gRlAyQIVohU8AAia2g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739493609; c=relaxed/simple; bh=G8oxcqO+dc9UTnFKaCm94HcHeWF2Pu0JSvz8JhDF3Og=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MSwi+g9TIta5mhhvG88k3z/bITm/oGG7k1QWfVB2c5tyR+jABibqUWoQBdYFCwyeKyAL6HIq+xM3Rdkm6m0Ah14hJ+dL+cJidSwK2J6nCwULmepGTqGr5sI0iCbISQ+ZBekIwNHzQn8mJBOwQAC6C6AVGTuIPiDzm6aB/eHSROo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5901A1682; Thu, 13 Feb 2025 16:40:27 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 340443F5A1; Thu, 13 Feb 2025 16:40:05 -0800 (PST) From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/8] pinctrl: sunxi: support moved power configuration registers Date: Fri, 14 Feb 2025 00:37:30 +0000 Message-ID: <20250214003734.14944-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250214003734.14944-1-andre.przywara@arm.com> References: <20250214003734.14944-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Allwinner pincontroller IP features some registers to control the withstand voltage of each pin group. So far those registers were always located at the same offset, but the A523 SoC has moved them (probably to accommodate all eleven pin banks). Add a flag to note this feature, and use that to program the registers either at offset 0x340 or 0x380. So far no pincontroller driver uses this flag, but we need it for the upcoming A523 support. Signed-off-by: Andre Przywara --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 15 +++++++++++---- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 7 +++++-- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 83a031ceb29f2..a1057122272bd 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -736,9 +736,9 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, val = uV > 1800000 && uV <= 2500000 ? BIT(bank) : 0; raw_spin_lock_irqsave(&pctl->lock, flags); - reg = readl(pctl->membase + PIO_POW_MOD_CTL_REG); + reg = readl(pctl->membase + pctl->pow_mod_sel_offset); reg &= ~BIT(bank); - writel(reg | val, pctl->membase + PIO_POW_MOD_CTL_REG); + writel(reg | val, pctl->membase + pctl->pow_mod_sel_offset); raw_spin_unlock_irqrestore(&pctl->lock, flags); fallthrough; @@ -746,9 +746,12 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, val = uV <= 1800000 ? 1 : 0; raw_spin_lock_irqsave(&pctl->lock, flags); - reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG); + reg = readl(pctl->membase + pctl->pow_mod_sel_offset + + PIO_POW_MOD_SEL_OFS); reg &= ~(1 << bank); - writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); + writel(reg | val << bank, + pctl->membase + pctl->pow_mod_sel_offset + + PIO_POW_MOD_SEL_OFS); raw_spin_unlock_irqrestore(&pctl->lock, flags); return 0; default: @@ -1520,6 +1523,10 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev, pctl->pull_regs_offset = PULL_REGS_OFFSET; pctl->dlevel_field_width = DLEVEL_FIELD_WIDTH; } + if (flags & SUNXI_PINCTRL_ELEVEN_BANKS) + pctl->pow_mod_sel_offset = PIO_11B_POW_MOD_SEL_REG; + else + pctl->pow_mod_sel_offset = PIO_POW_MOD_SEL_REG; pctl->irq_array = devm_kcalloc(&pdev->dev, IRQ_PER_BANK * pctl->desc->irq_banks, diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 6cf721876d89d..a93385e456a57 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -87,9 +87,11 @@ #define SUNXI_PINCTRL_VARIANT_MASK GENMASK(7, 0) #define SUNXI_PINCTRL_NEW_REG_LAYOUT BIT(8) #define SUNXI_PINCTRL_PORTF_SWITCH BIT(9) +#define SUNXI_PINCTRL_ELEVEN_BANKS BIT(10) -#define PIO_POW_MOD_SEL_REG 0x340 -#define PIO_POW_MOD_CTL_REG 0x344 +#define PIO_POW_MOD_SEL_REG 0x340 +#define PIO_11B_POW_MOD_SEL_REG 0x380 +#define PIO_POW_MOD_SEL_OFS 0x004 #define PIO_BANK_K_OFFSET 0x500 @@ -173,6 +175,7 @@ struct sunxi_pinctrl { u32 bank_mem_size; u32 pull_regs_offset; u32 dlevel_field_width; + u32 pow_mod_sel_offset; }; #define SUNXI_PIN(_pin, ...) \ From patchwork Fri Feb 14 00:37:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 865185 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1551077F11; Fri, 14 Feb 2025 00:40:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739493612; cv=none; b=hj0ecaNP50OU0bWNbdtmaRxw5tD+eGu4UY6q0dtK4ksvi5HcGRMLlxkP46ArQUU9bUV1gQbiWm8cxKVw0aF45Hfo2kaH3rCntvVMKft0xEF3ExpYMBYA4OemuRo+3RH3Vdu2XiJaIzVtthw71fVJU3EfqjNBsZQ3UVeZGKA6CT4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739493612; c=relaxed/simple; bh=hTi3hbtPz/Jj6nO9h6+FpMPFddPSZHwWpY7KCYazFA0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lLjPqpnchI0A0GiMG/lzoXR7ghel9Gi30qHWLbkT37MW4fVxoeSBwDp43TaeF6jPqELY/GvLTe41AKh9Za8+kSH7HZY8Ry3a5GwcsHhNHE5FIA4idVGUcQXo02jvoPQJBU3XFRJyLVYmfU6xjz/PcebwKGWpMbwOorn5FH8rC9M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 41CA8113E; Thu, 13 Feb 2025 16:40:31 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1CF9D3F5A1; Thu, 13 Feb 2025 16:40:09 -0800 (PST) From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/8] dt-bindings: pinctrl: add compatible for Allwinner A523/T527 Date: Fri, 14 Feb 2025 00:37:32 +0000 Message-ID: <20250214003734.14944-7-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250214003734.14944-1-andre.przywara@arm.com> References: <20250214003734.14944-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The A523 contains a pin controller similar to previous SoCs, although using 10 GPIO banks (PortB-PortK), all of them being IRQ capable. With this SoC we introduce a new style of binding, where the pinmux values for each pin group are stored in the new "allwinner,pinmux" property in the DT node, instead of requiring every driver to store a mapping between the function names and the required pinmux. Add a new binding file, since all the different variants of the old binding are making the file a bit unwieldy to handle already, and the new property would make the situation worse. Signed-off-by: Andre Przywara --- .../allwinner,sun55i-a523-pinctrl.yaml | 177 ++++++++++++++++++ 1 file changed, 177 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml new file mode 100644 index 0000000000000..1de6ccaefc1ce --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml @@ -0,0 +1,177 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/allwinner,sun55i-a523-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A523 Pin Controller + +maintainers: + - Andre Przywara + +properties: + "#gpio-cells": + const: 3 + description: + GPIO consumers must use three arguments, first the number of the + bank, then the pin number inside that bank, and finally the GPIO + flags. + + "#interrupt-cells": + const: 3 + description: + Interrupts consumers must use three arguments, first the number + of the bank, then the pin number inside that bank, and finally + the interrupts flags. + + compatible: + enum: + - allwinner,sun55i-a523-pinctrl + - allwinner,sun55i-a523-r-pinctrl + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 10 + description: + One interrupt per external interrupt bank supported on the + controller, sorted by bank number ascending order. + + clocks: + items: + - description: Bus Clock + - description: High Frequency Oscillator + - description: Low Frequency Oscillator + + clock-names: + items: + - const: apb + - const: hosc + - const: losc + + gpio-controller: true + interrupt-controller: true + gpio-line-names: true + + input-debounce: + description: + Debouncing periods in microseconds, one period per interrupt + bank found in the controller + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 10 + +patternProperties: + # It's pretty scary, but the basic idea is that: + # - One node name can start with either s- or r- for PRCM nodes, + # - Then, the name itself can be any repetition of - (to + # accommodate with nodes like uart4-rts-cts-pins), where each + # string can be either starting with 'p' but in a string longer + # than 3, or something that doesn't start with 'p', + # - Then, the bank name is optional and will be between pa and pm. + # Some pins groups that have several options will have the pin + # numbers then, + # - Finally, the name will end with either -pin or pins. + + "^([rs]-)?(([a-z0-9]{3,}|[a-oq-z][a-z0-9]*?)?-)+?(p[a-m][0-9]*?-)??pins?$": + type: object + + properties: + pins: true + function: true + bias-disable: true + bias-pull-up: true + bias-pull-down: true + + drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [10, 20, 30, 40] + + allwinner,pinmux: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Pinmux selector value, for each pin. Almost every time this value + is the same for all pins, so any array shorter than the number of + pins will repeat the last value, to allow just specifying a single + cell, for all cells. + + required: + - pins + - allwinner,pinmux + - function + + additionalProperties: false + + "^vcc-p[a-m]-supply$": + description: + Power supplies for pin banks. + +required: + - "#gpio-cells" + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - "#interrupt-cells" + - interrupts + - interrupt-controller + +allOf: + - $ref: pinctrl.yaml# + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-pinctrl + + then: + properties: + interrupts: + minItems: 10 + maxItems: 10 + + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-r-pinctrl + + then: + properties: + interrupts: + minItems: 2 + maxItems: 2 + +additionalProperties: false + +examples: + - | + #include + + r_pio: pinctrl@7022000 { + compatible = "allwinner,sun55i-a523-r-pinctrl"; + reg = <0x7022000 0x800>; + interrupts = <0 159 4>, <0 161 4>; + clocks = <&r_ccu CLK_R_APB0>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + r_i2c_pins: r-i2c-pins { + pins = "PL0", "PL1"; + allwinner,pinmux = <2>; + function = "r_i2c0"; + bias-pull-up; + }; + + r_spi_pins: r-spi-pins { + pins = "PL11" ,"PL12", "PL13"; + allwinner,pinmux = <6>; + function = "r_spi"; + }; + }; From patchwork Fri Feb 14 00:37:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 865184 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DEF291487FA; Fri, 14 Feb 2025 00:40:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739493616; cv=none; b=JqTGngirpOnyVDuQTXAz7SEFjEvG4J7hxeFwTond1zTzB6jimf0DC0IGKNeIdobJsOSQZaoRn03fr0Lil6MluBObWFsXg0jNFAtbDHWyZUa5rWAdTPmGfYOnJBoJJXWHHJ+ZJmZ6cB6cTFFaNwYl0yrjWdmqidPXHY2w4noMl20= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739493616; c=relaxed/simple; bh=9DJX4GeezJm5XmMAY97rH2s9kYvmm6DkOakDepGm7+s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=i1xJefPUoa9SeSo+joji7NHEaM21MjBmDTb73eFQWt3MYXUbjU5DPEFAQJJVS4QQsFg7/bPnbiQTGR6A2NVanjmTwitOwiDasV2HzuvKLClOeyoLWt3QRojb6FjTbMmNH7G0umVcRztZ8ytyqLeoa9L2jpccYZ0XPiwBbXVugw4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0C5F6113E; Thu, 13 Feb 2025 16:40:35 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DBE353F5A1; Thu, 13 Feb 2025 16:40:12 -0800 (PST) From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 8/8] pinctrl: sunxi: Add support for the secondary A523 GPIO ports Date: Fri, 14 Feb 2025 00:37:34 +0000 Message-ID: <20250214003734.14944-9-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250214003734.14944-1-andre.przywara@arm.com> References: <20250214003734.14944-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 As most other Allwinner SoCs before, the A523 chip contains a second GPIO controller, managing banks PL and PM. Use the newly introduced DT based pinctrl driver to describe just the generic pinctrl properties, so advertise the number of pins per bank and the interrupt capabilities. The actual function/mux assignment is taken from the devicetree. Signed-off-by: Andre Przywara --- drivers/pinctrl/sunxi/Kconfig | 5 ++ drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c | 54 +++++++++++++++++++ 3 files changed, 60 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 0cbe466683650..dc62eba96348e 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -136,4 +136,9 @@ config PINCTRL_SUN55I_A523 default ARM64 && ARCH_SUNXI select PINCTRL_SUNXI +config PINCTRL_SUN55I_A523_R + bool "Support for the Allwinner A523 R-PIO" + default ARM64 && ARCH_SUNXI + select PINCTRL_SUNXI + endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 4e55508ff7f76..951b3f1e4b4f1 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -28,5 +28,6 @@ obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o obj-$(CONFIG_PINCTRL_SUN50I_H616_R) += pinctrl-sun50i-h616-r.o obj-$(CONFIG_PINCTRL_SUN55I_A523) += pinctrl-sun55i-a523.o +obj-$(CONFIG_PINCTRL_SUN55I_A523_R) += pinctrl-sun55i-a523-r.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c new file mode 100644 index 0000000000000..69cd2b4ebd7d7 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Allwinner A523 SoC r-pinctrl driver. + * + * Copyright (C) 2024 Arm Ltd. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const u8 a523_r_nr_bank_pins[SUNXI_PINCTRL_MAX_BANKS] = +/* PL PM */ + { 14, 6 }; + +static const unsigned int a523_r_irq_bank_map[] = { 0, 1 }; + +static const u8 a523_r_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] = +/* PL PM */ + { 14, 14 }; + +static struct sunxi_pinctrl_desc a523_r_pinctrl_data = { + .irq_banks = ARRAY_SIZE(a523_r_irq_bank_map), + .irq_bank_map = a523_r_irq_bank_map, + .irq_read_needs_mux = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, + .pin_base = PL_BASE, +}; + +static int a523_r_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_dt_table_init(pdev, a523_r_nr_bank_pins, + a523_r_irq_bank_muxes, + &a523_r_pinctrl_data, + SUNXI_PINCTRL_NEW_REG_LAYOUT); +} + +static const struct of_device_id a523_r_pinctrl_match[] = { + { .compatible = "allwinner,sun55i-a523-r-pinctrl", }, + {} +}; + +static struct platform_driver a523_r_pinctrl_driver = { + .probe = a523_r_pinctrl_probe, + .driver = { + .name = "sun55i-a523-r-pinctrl", + .of_match_table = a523_r_pinctrl_match, + }, +}; +builtin_platform_driver(a523_r_pinctrl_driver);