From patchwork Wed Feb 19 18:41:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 866469 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72BAB1F3FC8; Wed, 19 Feb 2025 19:28:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739993308; cv=none; b=WN6a6iFrkzuE7yZSyumUnm1soq5ZMin8q8r6g+drE9KDjalzg8/RcPHoyYUqy7UoS9Kh3wMCxI/vrXuXyvD+e4V8Lg3ltQy6glxxFBoWQ8jyBMhgJeFXnXUOyYndH0KuzbDXkruEWtoFThed2W9oZ4XgB15xrhZHNHn1ImRHoKA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739993308; c=relaxed/simple; bh=ZxgjjTOf0eO9C1n3ehn9Thqcxmzs3zf5Ywl8XjOse/8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oKwCT4XKtZ5i4KKaa930rduBASLf2C13fP/gQ849omzjygF6OA0Y7X8CGeastJKnI8MACS/fwlj3QSXAR1aRbOaanLFGuNGAnn13ppDY+l+bULFoCerpOCczrFZgsF79bUUJW+Ny4im9gkS6hc+4gNYbroCnFuGLLaXMniMT4Bw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=SRuqLXOF; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="SRuqLXOF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739993306; x=1771529306; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZxgjjTOf0eO9C1n3ehn9Thqcxmzs3zf5Ywl8XjOse/8=; b=SRuqLXOF6J3LKEmLdY1jWNzl9pCckXe7FF4qCh3S4nKLweLQYfWB2e/A F67PEeAEbU90KLzANEctxP/YHTOtrynR2MhCpB0zf/uvN9qXGPCi+7duQ aSdz2OX6zcBQBXbO5oQtt8MXsVaGGPmvMkYuh8EcnnXF588kyITIZ7QsZ Y2M33phCuWJ7lfgNiTCufoUWoeVuS0QB6JX19ispOmi3eZcGLlKfTIb36 vEvm6FT1Ziag/o3oYanqH9Z52Fo7u10D77rJ7SN+I2ekcHjb499KBsLBY 0R5mGZN2tqiqXOwERhDBGc1k2OYj0ZpWsHrdlRpLPLlrUaQZG8Lc43Nx0 g==; X-CSE-ConnectionGUID: AHKtx7FyRH2htuouk/77Zw== X-CSE-MsgGUID: 78MBF8+bTBK2E3smqdcOog== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="52182745" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="52182745" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2025 11:28:25 -0800 X-CSE-ConnectionGUID: RkoY1f1PRZCz0fmsoR8Ojw== X-CSE-MsgGUID: 8VxTYZAmRWqjzcXqWfscoQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,299,1732608000"; d="scan'208";a="115344001" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa010.fm.intel.com with ESMTP; 19 Feb 2025 10:44:48 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Dapeng Mi , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 01/15] x86/apic: Fix 32-bit APIC initialization for extended Intel Families Date: Wed, 19 Feb 2025 18:41:19 +0000 Message-ID: <20250219184133.816753-2-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250219184133.816753-1-sohil.mehta@intel.com> References: <20250219184133.816753-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 APIC detection is currently limited to a few specific Families and will not match the upcoming Families >=18. Extend the check to include all Families 6 or greater. Also convert it to a VFM check to make it simpler. Signed-off-by: Sohil Mehta Acked-by: Dave Hansen --- v3: No change v2: Update commit message to make it more precise --- arch/x86/kernel/apic/apic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index e893dc6f11c1..4d99bd65faf5 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2014,8 +2014,8 @@ static bool __init detect_init_APIC(void) case X86_VENDOR_HYGON: break; case X86_VENDOR_INTEL: - if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || - (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) + if ((boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)) || + boot_cpu_data.x86_vfm >= INTEL_PENTIUM_PRO) break; goto no_apic; default: From patchwork Wed Feb 19 18:41:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 866468 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7277522B5B6; Wed, 19 Feb 2025 19:28:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739993317; cv=none; b=e2bVhgYCzgE2Ejj1rvEAosGdfvPE3Qsq8ouhLTYuAt5lG4UdnZOPHNIqcC5AfV2bK6kb+W1bD9RQOjb8lem+nCpBVXseMwuiWVrAeI0pJ9S64bFy1TxdurilGUn9v4QlCioUuxnMTH3CTZsaIi5upvY+hGVVl7X0PTE/3Q2YamM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739993317; c=relaxed/simple; bh=XcZCN0XcDsRlRdxcZACk+AqTvXZkPzdsqu3ONzEfFfw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GzQ/Yj7ltC5PLpV1SJuU7skZ71enL0zEbem6XsS/4h2/X/SFeDRZY8Pn/N2ME9vLQpct8ACWEgJwE2fAxLsg4fULm43yw+TUcs/1xO59uQIwhaQV66XfVdkySTqwGMf+tPsyOkrEfMQNjZecAT7ET6DSY2AQ5mRWG+34OVmklAo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bDhRixsp; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bDhRixsp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739993315; x=1771529315; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XcZCN0XcDsRlRdxcZACk+AqTvXZkPzdsqu3ONzEfFfw=; b=bDhRixsp2uzQUjVRG/weU/2ACsHc6t1Itixxb8KxckWaKgTRCfGyTl+i dZw+jYdm2dsla7qpxkctRe3tUZqEpsuilvcQ5rnUPvvta4m20IWcGRbuN Gb+EeutfXyXFzNAC5PmViQL22b+Ao2Tqm4XHxEdZsnMIYIv3jSWDT6ldh wPfxv1xciMIFdphqBHvTIRnVEQvoRxk9AdtEvmpzI15sj92lNIciGP2bQ a70MB5dOjc8Hr4pl+1E9jAD86Oye19E8s0uveaqswcnH3yhURfYjW3Qb6 Z2OUoOFlPukLNoc+NOhsnVnqLftRfw0H+0KBsBYxP5KqA8No/5eJlaijZ A==; X-CSE-ConnectionGUID: WUNT1v7RRsCTv2a35lhKvg== X-CSE-MsgGUID: oEtZh6u+TGSV0vXPX96gEA== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="52182791" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="52182791" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2025 11:28:33 -0800 X-CSE-ConnectionGUID: xvQ7NeXFRNi8UApQAnE6dg== X-CSE-MsgGUID: Eao1edzORxqeawS+xufnyQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,299,1732608000"; d="scan'208";a="115344008" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa010.fm.intel.com with ESMTP; 19 Feb 2025 10:45:43 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Dapeng Mi , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 03/15] x86/microcode: Update the Intel processor flag scan check Date: Wed, 19 Feb 2025 18:41:21 +0000 Message-ID: <20250219184133.816753-4-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250219184133.816753-1-sohil.mehta@intel.com> References: <20250219184133.816753-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Family model check to read the processor flag MSR is misleading and potentially incorrect. It doesn't consider Family while comparing the model number. The original check did have a Family number but it got lost/moved during refactoring. intel_collect_cpu_info() is called through multiple paths such as early initialization, CPU hotplug as well as IFS image load. Some of these flows would be error prone due to the ambiguous check. Correct the processor flag scan check to use a Family number and update it to a VFM based one to make it more readable. Signed-off-by: Sohil Mehta Acked-by: Dave Hansen --- v3: Picked up Dave's Ack. v2: Use a VFM check instead of hardcoded numbers. --- arch/x86/include/asm/intel-family.h | 1 + arch/x86/kernel/cpu/microcode/intel.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 6d7b04ffc5fd..cccc932d761e 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -46,6 +46,7 @@ #define INTEL_ANY IFM(X86_FAMILY_ANY, X86_MODEL_ANY) #define INTEL_PENTIUM_PRO IFM(6, 0x01) +#define INTEL_PENTIUM_III_DESCHUTES IFM(6, 0x05) #define INTEL_CORE_YONAH IFM(6, 0x0E) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index f3d534807d91..819199bc0119 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -74,7 +74,7 @@ void intel_collect_cpu_info(struct cpu_signature *sig) sig->pf = 0; sig->rev = intel_get_microcode_revision(); - if (x86_model(sig->sig) >= 5 || x86_family(sig->sig) > 6) { + if (IFM(x86_family(sig->sig), x86_model(sig->sig)) >= INTEL_PENTIUM_III_DESCHUTES) { unsigned int val[2]; /* get processor flags from MSR 0x17 */ From patchwork Wed Feb 19 18:41:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 866467 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FD5A22AE5E; Wed, 19 Feb 2025 19:29:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739993355; cv=none; b=CvYbQZkZOfixG+4NSyl+OUQWz+qK4YGWAUwCRgJKyGMm5Vyl5Ra+BTmCGWesZH6xWPv0RatdtiJZihG/myLbQshAocW3gAjT3KMmtklrZlL7lKErvFv0QPcM0aVjAtVfM5Qbv6BxMupAevJPLE58dCChJPOn16BiXMx4jcFnLLE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739993355; c=relaxed/simple; bh=2SmzUbbDEc07NOQm9JqvNZnwNZ90VP9jDICztH0L0P4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cX26gvPbDLzIsYW5aTiZYLNHiveV6KHIBfi94ieNUy54Ut6KN6e6NmNbHlaBQmwR1NjXFTGaN3NuINjAA0GRnDmspntDMMHrKVrGhF9YScS5aKAnkSeaVmb+nI8MOYp2ysZrQOFR0MycAWoNqWge4XFxU/pPwIHhprOJHoQHdKs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FjoWcgqO; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FjoWcgqO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739993354; x=1771529354; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2SmzUbbDEc07NOQm9JqvNZnwNZ90VP9jDICztH0L0P4=; b=FjoWcgqOEMy9HCKGxiw/5nCeNm3fnLC3ghvPBFR8QCtVB9D+nJ1ZnMdC KSUGYy1YdsIjBOdbWzYuKJeQh2kfzBSbozfdakELsEz6MWFgH43AJsELx f5DLxYIOTmGAsgKd3e1thwiIC1FrCqZNaGjBlVfge9fnLSHVn7Xv9pXGH guA4iaBRXEYOSZjUuBdfIYdWCTnoTIXtCqQOq6nk45yT+7VJh8H3Ttrjy H2j1a4oV5GPYZAuKOxznQpBoAEauFEtGfyZ1NHSzRiuDuIrnjoX2MFcE/ SezqURh5/vQRTvknTgXTpiRnltmivooAuyylEL0YSpWxYAP8KXCr9iQDv w==; X-CSE-ConnectionGUID: hdxFHQo+QDeVTUTwRzmZcw== X-CSE-MsgGUID: y5m34wtSQpikZEacq9uQcw== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="52182873" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="52182873" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2025 11:29:13 -0800 X-CSE-ConnectionGUID: HCqRkrYdQJKW/N4Mb1UZbQ== X-CSE-MsgGUID: bykoVxlrTVOo+qXyh4q+Dg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,299,1732608000"; d="scan'208";a="115344022" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa010.fm.intel.com with ESMTP; 19 Feb 2025 10:46:59 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Dapeng Mi , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 05/15] x86/cpu/intel: Replace early Family 6 checks with VFM ones Date: Wed, 19 Feb 2025 18:41:23 +0000 Message-ID: <20250219184133.816753-6-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250219184133.816753-1-sohil.mehta@intel.com> References: <20250219184133.816753-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce names for some old pentium models and replace the x86_model checks with VFM ones. Signed-off-by: Sohil Mehta Acked-by: Dave Hansen --- v3: Picked up Dave's Ack. v2: No change --- arch/x86/include/asm/intel-family.h | 4 ++++ arch/x86/kernel/cpu/intel.c | 11 +++++------ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index cccc932d761e..c1a081585fcb 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -45,8 +45,12 @@ /* Wildcard match so X86_MATCH_VFM(ANY) works */ #define INTEL_ANY IFM(X86_FAMILY_ANY, X86_MODEL_ANY) +/* Family 6 */ #define INTEL_PENTIUM_PRO IFM(6, 0x01) +#define INTEL_PENTIUM_II_KLAMATH IFM(6, 0x03) #define INTEL_PENTIUM_III_DESCHUTES IFM(6, 0x05) +#define INTEL_PENTIUM_III_TUALATIN IFM(6, 0x0B) +#define INTEL_PENTIUM_M_DOTHAN IFM(6, 0x0D) #define INTEL_CORE_YONAH IFM(6, 0x0E) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index e5f34a90963e..8e67d1ef4c73 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -195,7 +195,7 @@ void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) return; - if (c->x86 < 6 || (c->x86 == 6 && c->x86_model < 0xd)) + if (c->x86_vfm < INTEL_PENTIUM_M_DOTHAN) return; /* @@ -350,9 +350,7 @@ static void bsp_init_intel(struct cpuinfo_x86 *c) int ppro_with_ram_bug(void) { /* Uses data from early_cpu_detect now */ - if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && - boot_cpu_data.x86 == 6 && - boot_cpu_data.x86_model == 1 && + if (boot_cpu_data.x86_vfm == INTEL_PENTIUM_PRO && boot_cpu_data.x86_stepping < 8) { pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); return 1; @@ -413,7 +411,8 @@ static void intel_workarounds(struct cpuinfo_x86 *c) * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until * model 3 mask 3 */ - if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) + if ((c->x86_vfm == INTEL_PENTIUM_II_KLAMATH && c->x86_stepping < 3) || + c->x86_vfm < INTEL_PENTIUM_II_KLAMATH) clear_cpu_cap(c, X86_FEATURE_SEP); /* @@ -615,7 +614,7 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) * to determine which, so we use a boottime override * for the 512kb model, and assume 256 otherwise. */ - if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) + if (c->x86_vfm == INTEL_PENTIUM_III_TUALATIN && size == 0) size = 256; /* From patchwork Wed Feb 19 18:41:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 866466 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4839722D7BA; Wed, 19 Feb 2025 19:29:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739993359; cv=none; b=ACaC+dPm/JxHrdhaNl5l6Mp4JBZh4R+mTvC/Te8MO0etFkKk2F5uQKJh84ONZaukvEqX6J2rm+v2yYREYOs+i1Au5V18WLWDRNWvbW54idNX95UatJyeql+GkqTbSUqzML4Vc7mB1tLRKLy17UHpSjnKcV+PlErlaTyJc3Exi+s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739993359; c=relaxed/simple; bh=lQKLUlUSGZP50W6KTqoKN+hX0s24dtJkBUC4fQJlixE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AwImYry4ExaKsh4agKG0DkEhL0BhC+NAJMlRPVFrSoOVgxOcYJ7Brho2J8NBeq9BdjqTlSEi0V3XICA5fStTQQQwXWtYdKM/ZblHqC6KDzhM55iBqWRfHuKoPCoICHqLUamuIAcOMihC9BKJ7vQAQNKngynFiy2JXReYZqcMfhU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Q1Ma5BZE; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Q1Ma5BZE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739993357; x=1771529357; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lQKLUlUSGZP50W6KTqoKN+hX0s24dtJkBUC4fQJlixE=; b=Q1Ma5BZE42LfVkKgqOOBAJ1BeBpGh1LIDVBJUrSYptwTgbwlst1qRBJP fRSJaY/dXe1X3T6tN+yxcaUmlmjjCyxuU2UnZvI1Ln0ysAdFHpRCqtM/x D1M6AWqk/ysqqWUwe/Ygx9d69oxzzJYpZB8Z6Ht0g6GkFUTaJEyBvs18P 1i2tHbxqdPxg6KiVYpWcEQzBagRb2AEHOjLEEzapQXJIb+12HYu4G/RQD FZov5YUeCtWL4PQbQItIMQEDGOQIpA8qX8hsYpeTbfM+SHs35+4ZQLgCC QQf/Ez9/S5hfVRmnezG9x2DowRizhxaxOL9c4Rwwa8pe4LZxWaXIcNNkj A==; X-CSE-ConnectionGUID: yVxGRnBZQXa+N6L9Z5z8gg== X-CSE-MsgGUID: v8cwJYRsSqWjxJ8ejgJ7mQ== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="52182906" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="52182906" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2025 11:29:17 -0800 X-CSE-ConnectionGUID: MXjDvxrtQKSOXL9vpvw0nQ== X-CSE-MsgGUID: s6eTw20zQU6lDpbLxpfUDw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,299,1732608000"; d="scan'208";a="115344030" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa010.fm.intel.com with ESMTP; 19 Feb 2025 10:47:53 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Dapeng Mi , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 07/15] x86/cpu/intel: Replace Family 5 model checks with VFM ones Date: Wed, 19 Feb 2025 18:41:25 +0000 Message-ID: <20250219184133.816753-8-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250219184133.816753-1-sohil.mehta@intel.com> References: <20250219184133.816753-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce names for some Family 5 models and convert some of the checks to be VFM based. Also, to keep the file sorted by family, move Family 5 to the top of the header file. Signed-off-by: Sohil Mehta Acked-by: Dave Hansen --- v3: Picked up Dave's Ack. v2: Reorder the Family 5 models to be at the top of the file. --- arch/x86/include/asm/intel-family.h | 9 ++++++--- arch/x86/kernel/cpu/intel.c | 11 +++++------ 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index f509061b8c7e..9e6a13f03f0e 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -45,6 +45,12 @@ /* Wildcard match so X86_MATCH_VFM(ANY) works */ #define INTEL_ANY IFM(X86_FAMILY_ANY, X86_MODEL_ANY) +/* Family 5 */ +#define INTEL_FAM5_START IFM(5, 0x00) /* Notational marker, also P5 A-step */ +#define INTEL_PENTIUM_75 IFM(5, 0x02) /* P54C */ +#define INTEL_PENTIUM_MMX IFM(5, 0x04) /* P55C */ +#define INTEL_QUARK_X1000 IFM(5, 0x09) /* Quark X1000 SoC */ + /* Family 6 */ #define INTEL_PENTIUM_PRO IFM(6, 0x01) #define INTEL_PENTIUM_II_KLAMATH IFM(6, 0x03) @@ -181,9 +187,6 @@ #define INTEL_XEON_PHI_KNL IFM(6, 0x57) /* Knights Landing */ #define INTEL_XEON_PHI_KNM IFM(6, 0x85) /* Knights Mill */ -/* Family 5 */ -#define INTEL_QUARK_X1000 IFM(5, 0x09) /* Quark X1000 SoC */ - /* Family 15 - NetBurst */ #define INTEL_P4_WILLAMETTE IFM(15, 0x01) /* Also Xeon Foster */ #define INTEL_P4_PRESCOTT IFM(15, 0x03) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 30f3812ba62c..48aad9bcf300 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -367,9 +367,8 @@ static void intel_smp_check(struct cpuinfo_x86 *c) /* * Mask B, Pentium, but not Pentium MMX */ - if (c->x86 == 5 && - c->x86_stepping >= 1 && c->x86_stepping <= 4 && - c->x86_model <= 3) { + if (c->x86_vfm >= INTEL_FAM5_START && c->x86_vfm < INTEL_PENTIUM_MMX && + c->x86_stepping >= 1 && c->x86_stepping <= 4) { /* * Remember we have B step Pentia with bugs */ @@ -396,7 +395,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c) * The Quark is also family 5, but does not have the same bug. */ clear_cpu_bug(c, X86_BUG_F00F); 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a="52182966" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="52182966" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2025 11:29:30 -0800 X-CSE-ConnectionGUID: 9sXsdfyqQMeJqq6ImAulxQ== X-CSE-MsgGUID: lcyiGrYiTPmTIU3ZJYh27w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,299,1732608000"; d="scan'208";a="115344042" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa010.fm.intel.com with ESMTP; 19 Feb 2025 10:48:34 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Dapeng Mi , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 09/15] x86/smpboot: Remove confusing quirk usage in INIT delay Date: Wed, 19 Feb 2025 18:41:27 +0000 Message-ID: <20250219184133.816753-10-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250219184133.816753-1-sohil.mehta@intel.com> References: <20250219184133.816753-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Very old multiprocessor systems required a 10 msec delay between asserting and de-asserting INIT but modern processors do not require this delay. Over time the usage of the "quirk" wording while setting the INIT delay has become misleading. The code comments suggest that modern processors need to be quirked, which clears the default init_udelay of 10 msec, while legacy processors don't need the quirk and continue to use the default init_udelay. With a lot more modern processors, the wording should be inverted if at all needed. Instead, simplify the comments and the code by getting rid of "quirk" usage altogether and clarifying the following: Old legacy processors -> Set the "legacy" 10 msec delay Modern processors -> Do not set any delay No functional change. Signed-off-by: Sohil Mehta --- v3: Improve commit message v2: New patch --- arch/x86/kernel/smpboot.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index c10850ae6f09..eb91ed0f2a06 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -654,10 +654,9 @@ static void impress_friends(void) * But that slows boot and resume on modern processors, which include * many cores and don't require that delay. * - * Cmdline "init_cpu_udelay=" is available to over-ride this delay. - * Modern processor families are quirked to remove the delay entirely. + * Cmdline "cpu_init_udelay=" is available to override this delay. */ -#define UDELAY_10MS_DEFAULT 10000 +#define UDELAY_10MS_LEGACY 10000 static unsigned int init_udelay = UINT_MAX; @@ -669,7 +668,7 @@ static int __init cpu_init_udelay(char *str) } early_param("cpu_init_udelay", cpu_init_udelay); -static void __init smp_quirk_init_udelay(void) +static void __init smp_set_init_udelay(void) { /* if cmdline changed it from default, leave it alone */ if (init_udelay != UINT_MAX) @@ -683,7 +682,7 @@ static void __init smp_quirk_init_udelay(void) return; } /* else, use legacy delay */ - init_udelay = UDELAY_10MS_DEFAULT; + init_udelay = UDELAY_10MS_LEGACY; } /* @@ -1094,7 +1093,7 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus) uv_system_init(); - smp_quirk_init_udelay(); + smp_set_init_udelay(); speculative_store_bypass_ht_init(); From patchwork Wed Feb 19 18:41:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 866464 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3222422AE55; Wed, 19 Feb 2025 19:29:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739993390; cv=none; b=IBTZYz/lx2c52bf5Izza4RANGDf9mf14odpdGdrcq3R69s4OAmC4EmPIro+hghhCA+8nhiOuIjNK5tJGQK8wTKcgmjQEN9TXTFt0l/wH+1uwjzJ+gbBWHEzow4Wk9jgGhFkJNzCvzG6OuPrIbCnNNzfJ7oz6GQ0a0ncb5d5cCfk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739993390; c=relaxed/simple; bh=kfnGOt0+eNdaQoCOZBz02E74O7l/rkUOG6IfNzeHRzY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qv6LUqmgQpIxfOHLL6yFDSIMQ2A3iG1qpXgwMgQKTZ3fQnmxnxByNStLb158B41d2yZVfQ9aZW0f+VX9HgKB0JLtCaKpZlf28+eE668l5Q0FHa3OzS7X87gAka3vadPBeWJkFFiRTPN9YJajcRpWSZws2foR55nBReuuazUMA7I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=UfGCuuaM; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="UfGCuuaM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739993389; x=1771529389; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kfnGOt0+eNdaQoCOZBz02E74O7l/rkUOG6IfNzeHRzY=; b=UfGCuuaMit6VEGk1+qNl36nW9mt/nnZhd+FKeNNNuf/FWl+TAx/Fvh0k s3QnI8c4l59XIbCKftfivBW6ds3SQbXqfcovKNR0mpoWp2wiFL6wd1z+D 8EspGZtHc30F/cP2I8hk/mwyFH4T2Gu9Td3ECT0RECC1tBU9YTwmdMv/F lRsRT1TvTO9MqXFDisl/BgxdVHSXOiWm/xfW9/2+MB/7j1B6n7ENG/V2J MdIj0poejk+IvVhoumetvPCAatLj6f9vx8nErseEAoEkBRx72aqTwrCo6 2zntPlIisodCe9msxufEoGEEQRpHM5smrCKyLNxxyBkwiU95a5fLYv0Bl A==; X-CSE-ConnectionGUID: Z9CpoZbqTjuZ4uWlDNQNeQ== X-CSE-MsgGUID: AyX66Op+Rk2IpR8cnQtxRg== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="52183033" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="52183033" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2025 11:29:47 -0800 X-CSE-ConnectionGUID: arUhFe+LQByrjdFsDbdoAg== X-CSE-MsgGUID: 4EQ0QxjcRaqQhB5tzwEZcg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,299,1732608000"; d="scan'208";a="115344060" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa010.fm.intel.com with ESMTP; 19 Feb 2025 10:49:34 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Dapeng Mi , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 11/15] x86/cpu/intel: Fix fast string initialization for extended Families Date: Wed, 19 Feb 2025 18:41:29 +0000 Message-ID: <20250219184133.816753-12-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250219184133.816753-1-sohil.mehta@intel.com> References: <20250219184133.816753-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X86_FEATURE_REP_GOOD is a linux defined feature flag to track whether fast string operations should be used for copy_page(). It is also used as a second alternative for clear_page() if enhanced fast string operations (ERMS) are not available. X86_FEATURE_ERMS is an Intel-specific hardware-defined feature flag that tracks hardware support for Enhanced Fast strings. It is used to track whether Fast strings should be used for similar memory copy and memory clearing operations. On top of these, there is a FAST_STRING enable bit in the IA32_MISC_ENABLE MSR. It is typically controlled by the BIOS to provide a hint to the hardware and the OS on whether fast string operations are preferred. commit 161ec53c702c ("x86, mem, intel: Initialize Enhanced REP MOVSB/STOSB") introduced a mechanism to honor the BIOS preference for fast string operations and clear the above feature flags if needed. Unfortunately, the current initialization code for Intel to set and clear these bits is confusing at best and likely incorrect. X86_FEATURE_REP_GOOD is cleared in early_init_intel() if MISC_ENABLE.FAST_STRING is 0. But it gets set later on unconditionally for all Family 6 processors in init_intel(). This not only overrides the BIOS preference but also contradicts the earlier check. Fix this by combining the related checks and always relying on the BIOS provided preference for fast string operations. This simplification makes sure the upcoming Intel Family 18 and 19 models are covered as well. Signed-off-by: Sohil Mehta --- v3: Combine the REP_GOOD checks to one place. Improve code comments. v2: Separate out the REP_GOOD (copy page) specific change into a separate commit. --- arch/x86/kernel/cpu/intel.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 48aad9bcf300..fc68561d9f92 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -298,12 +298,19 @@ static void early_init_intel(struct cpuinfo_x86 *c) clear_cpu_cap(c, X86_FEATURE_PAT); /* - * If fast string is not enabled in IA32_MISC_ENABLE for any reason, - * clear the fast string and enhanced fast string CPU capabilities. + * Modern CPUs are generally expected to have a sane fast string + * implementation. However, BIOSes typically have a knob to tweak + * the architectural MISC_ENABLE.FAST_STRING enable bit. + * + * Adhere to the preference and program the linux-defined fast + * string flag and enhanced fast string capabilities accordingly. */ - if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { + if (c->x86_vfm >= INTEL_PENTIUM_M_DOTHAN) { rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); - if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { + if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) { + /* X86_FEATURE_ERMS is set based on CPUID */ + set_cpu_cap(c, X86_FEATURE_REP_GOOD); + } else { pr_info("Disabled fast string operations\n"); setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); setup_clear_cpu_cap(X86_FEATURE_ERMS); @@ -554,8 +561,6 @@ static void init_intel(struct cpuinfo_x86 *c) #ifdef CONFIG_X86_64 if (c->x86 == 15) c->x86_cache_alignment = c->x86_clflush_size * 2; - if (c->x86 == 6) - set_cpu_cap(c, X86_FEATURE_REP_GOOD); #else /* * Names for the Pentium II/Celeron processors From patchwork Wed Feb 19 18:41:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 866463 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4102423314C; Wed, 19 Feb 2025 19:29:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739993393; cv=none; b=XZO954yts68sbKHbZ+aMK2sJ0njIqse9ecrS4D+2ri0yQVbT1gWtcuUUAd/FIuOqlqyzmiXjX3GLMVXjyrYYVZ0FtVKNEFIvoEzp+bQAoP8I7RGBBD3oj6SCQikOkKXfOgENhvCyfR8kQ0u1drQacYPh9cOQkB2vAUIzLrexzcM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739993393; c=relaxed/simple; bh=GmXwBXf7o6X1iHu+tHqsXntz3Xo5SDeaPBJSRIAxMDU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IaURz0kkbhXromYMxsMIKvl+B8LgXoZ+Tn3e+ii6grGFlCLlOYDOKht1BE5MevP9tRvpvAbri6jRJcydwfpnVsY+tZI9HUduLYu9KrHNuAA8LhYsGAHIEMzbrU13nGO4c3vHj4dyhNY2Gsm4t24HUeeI+CanczDz5oNjaa9Lzs4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YarBi1iG; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YarBi1iG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739993392; x=1771529392; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GmXwBXf7o6X1iHu+tHqsXntz3Xo5SDeaPBJSRIAxMDU=; b=YarBi1iGnEuQ05r/kIcFaygk1k29EAcYIW4IauUyMRt9YVZQWMDveCsB GatyJxe80dfEMDfcmPZVVp/jLu1UWFf+ybXE7ce2+QlgIJR4ElPIC/MM7 t/O2hDHIh+BPWHTUdn0QZXqDqF/rpAJRECRagMqCzubVi+3My4HNEEgji ebTo0cNh3GVBPRYzmm5q7/oggvu3WrQpjuJRBh2L6U+fPeN2ws/xW9R0n O7/oepEFBDwlNzIn1uk/YmXuT6tqgm+I1xFkbv7dtoNH6no6s8aexaaeY IyyimtbgwRg+OZuLxDPJl41vJIZrzHUdH6fJnVYZoczF1XadxkeOG/sZF w==; X-CSE-ConnectionGUID: +IDdg6V8Sd2a/ARZrC4fmQ== X-CSE-MsgGUID: V5CmblIYQNq1wO8x0DXahw== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="52183067" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="52183067" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2025 11:29:51 -0800 X-CSE-ConnectionGUID: 5TYVdDi5SWCIpXUNqA0fHw== X-CSE-MsgGUID: JKgeboEKRKisXI+7sHYqvA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,299,1732608000"; d="scan'208";a="115344070" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa010.fm.intel.com with ESMTP; 19 Feb 2025 10:50:19 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Dapeng Mi , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 13/15] x86/cpu/intel: Bound the non-architectural constant_tsc model checks Date: Wed, 19 Feb 2025 18:41:31 +0000 Message-ID: <20250219184133.816753-14-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250219184133.816753-1-sohil.mehta@intel.com> References: <20250219184133.816753-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X86_FEATURE_CONSTANT_TSC is a Linux-defined, synthesized feature flag. It is used across several vendors. Intel CPUs will set the feature when the architectural CPUID.80000007.EDX[1] bit is set. There are also some Intel CPUs that have the X86_FEATURE_CONSTANT_TSC behavior but don't enumerate it with the architectural bit. Those currently have a model range check. Today, virtually all of the CPUs that have the CPUID bit *also* match the "model >= 0x0e" check. This is confusing. Instead of an open-ended check, pick some models (INTEL_IVYBRIDGE and P4_WILLAMETTE) as the end of goofy CPUs that should enumerate the bit but don't. These models are relatively arbitrary but conservative pick for this. This makes it obvious that later CPUs (like Family 18+) no longer need to synthesize X86_FEATURE_CONSTANT_TSC. Signed-off-by: Sohil Mehta --- v3: Make the non-architectural model checks more explicit. Improve commit message. v2: No change. --- arch/x86/kernel/cpu/intel.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index fc68561d9f92..4fbc5465ca67 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -210,10 +210,6 @@ static void early_init_intel(struct cpuinfo_x86 *c) { u64 misc_enable; - if ((c->x86 == 0xf && c->x86_model >= 0x03) || - (c->x86 == 0x6 && c->x86_model >= 0x0e)) - set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); - if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) c->microcode = intel_get_microcode_revision(); @@ -266,10 +262,16 @@ static void early_init_intel(struct cpuinfo_x86 *c) * * It is also reliable across cores and sockets. (but not across * cabinets - we turn it off in that case explicitly.) + * + * Use a model-specific check for some older CPUs that have invariant + * TSC but may not report it architecturally via 8000_0007. */ if (c->x86_power & (1 << 8)) { set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); + } else if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_WILLAMETTE) || + (c->x86_vfm >= INTEL_CORE_YONAH && c->x86_vfm <= INTEL_IVYBRIDGE)) { + set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); } /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ From patchwork Wed Feb 19 18:41:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 866462 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4574423957F; Wed, 19 Feb 2025 19:30:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739993402; cv=none; b=aBlnOK0kVeGgmxcf11riE2VM/e+q3s4O57MHv37iU7AyCHgDwkl1ZoEbBP9XxLLoq4NraAZrmpCKjlzg8Ma62OgR+SLznYtNNditU8Ab/0NS/pHaOFCAtQLLW5/vkB+aEIPVpHlhjVHlEj6EAgKkcaW+ZqLLU2Utybr+iRVPa/w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739993402; c=relaxed/simple; bh=QLIMnNXCwjgKCC5aNgIRCQTRlUzz0+nUlS5cRZ36n7M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eIk0gJ5tdJ8nVVonoLNXyudfTDXfuIrV4SE7RW+yndlB+ZLyai6jc8MMhz66t3yAkR+/ZX4kYQrWNgxV8eM5GlA7arQotlLJrAm9bzN9/agf6+UZXkVdQlL+G92HBygyRstGMCcGck+m3SZxJyDGIbZuD+jTI885uXB+5quUu2A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HUMWxafv; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HUMWxafv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739993400; x=1771529400; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QLIMnNXCwjgKCC5aNgIRCQTRlUzz0+nUlS5cRZ36n7M=; b=HUMWxafvQUZ08vO46pAafrfGQeDYR/2mttDR881RDD001mDxetNnqwRQ ALGn4rt9JeNU/iEfzXzTd8lRmMUKKO75wnXaXMg61LYP4j5sG776pMoc9 kz36Oa/M2foT8ZvJ/HlnxHYUFvZhvriZw89vyjv4JPpeKT5vRGqZd975N kZJTeDQeewUr/MqKdV6PdkPq4rCiP6spe9/zmNGQHdreNS+45bUHa6ZHw EIdilgKfH/ULEiner3qtF7aOAOdYsddMUC9bvm88+ixfkX9hkMr5B7RHo i3AGh4XFzTFqBwbVG1j509fSjVFKvqWl57VtkOjclnXcfJzf2Bav7RiBR g==; X-CSE-ConnectionGUID: L5CK+tJwRWqrfRFhvJX/pg== X-CSE-MsgGUID: Xk95ySiIScy67JUblkBj8Q== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="52183103" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="52183103" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2025 11:29:58 -0800 X-CSE-ConnectionGUID: pCzsR04cRdaYRECqVCeYJw== X-CSE-MsgGUID: nDUq0+YwTgG3+goNBDOSbQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,299,1732608000"; d="scan'208";a="115344084" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa010.fm.intel.com with ESMTP; 19 Feb 2025 10:50:35 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Dapeng Mi , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 15/15] perf/x86/p4: Replace Pentium 4 model checks with VFM ones Date: Wed, 19 Feb 2025 18:41:33 +0000 Message-ID: <20250219184133.816753-16-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250219184133.816753-1-sohil.mehta@intel.com> References: <20250219184133.816753-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce names for some old pentium 4 models and replace x86_model checks with VFM ones. Signed-off-by: Sohil Mehta --- v3: No change. v2: No change. --- arch/x86/events/intel/p4.c | 7 ++++--- arch/x86/include/asm/intel-family.h | 1 + 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/p4.c b/arch/x86/events/intel/p4.c index 844bc4fc4724..fb726c6fc6e7 100644 --- a/arch/x86/events/intel/p4.c +++ b/arch/x86/events/intel/p4.c @@ -10,6 +10,7 @@ #include #include +#include #include #include @@ -732,9 +733,9 @@ static bool p4_event_match_cpu_model(unsigned int event_idx) { /* INSTR_COMPLETED event only exist for model 3, 4, 6 (Prescott) */ if (event_idx == P4_EVENT_INSTR_COMPLETED) { - if (boot_cpu_data.x86_model != 3 && - boot_cpu_data.x86_model != 4 && - boot_cpu_data.x86_model != 6) + if (boot_cpu_data.x86_vfm != INTEL_P4_PRESCOTT && + boot_cpu_data.x86_vfm != INTEL_P4_PRESCOTT_2M && + boot_cpu_data.x86_vfm != INTEL_P4_CEDARMILL) return false; } diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 6621d796bb3d..89cb545d521b 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -193,6 +193,7 @@ /* Family 15 - NetBurst */ #define INTEL_P4_WILLAMETTE IFM(15, 0x01) /* Also Xeon Foster */ #define INTEL_P4_PRESCOTT IFM(15, 0x03) +#define INTEL_P4_PRESCOTT_2M IFM(15, 0x04) #define INTEL_P4_CEDARMILL IFM(15, 0x06) /* Also Xeon Dempsey */ /* Family 19 */