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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73264729945sm10067375b3a.179.2025.02.20.01.29.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 20 Feb 2025 01:29:30 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Magnus Damm , Thomas Huth , Shin'ichiro Kawasaki , Rayhan Faizel , qemu-arm@nongnu.org, Evgeny Iakovlev , Paolo Bonzini , Peter Maydell , Luc Michel , Yoshinori Sato , Richard Henderson Subject: [PATCH v2 1/9] hw/char/pl011: Warn when using disabled receiver Date: Thu, 20 Feb 2025 10:28:54 +0100 Message-ID: <20250220092903.3726-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250220092903.3726-1-philmd@linaro.org> References: <20250220092903.3726-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=philmd@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We shouldn't receive characters when the full UART or its receiver is disabled. However we don't want to break the possibly incomplete "my first bare metal assembly program"s, so we choose to simply display a warning when this occurs. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel --- hw/char/pl011.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 06ce851044d..12a2d4bc7bd 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -85,6 +85,7 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) #define CR_OUT1 (1 << 12) #define CR_RTS (1 << 11) #define CR_DTR (1 << 10) +#define CR_RXE (1 << 9) #define CR_TXE (1 << 8) #define CR_LBE (1 << 7) #define CR_UARTEN (1 << 0) @@ -487,6 +488,14 @@ static int pl011_can_receive(void *opaque) PL011State *s = (PL011State *)opaque; int r; + if (!(s->cr & CR_UARTEN)) { + qemu_log_mask(LOG_GUEST_ERROR, + "PL011 receiving data on disabled UART\n"); + } + if (!(s->cr & CR_RXE)) { + qemu_log_mask(LOG_GUEST_ERROR, + "PL011 receiving data on disabled RX UART\n"); + } r = s->read_count < pl011_get_fifo_depth(s); trace_pl011_can_receive(s->lcr, s->read_count, r); return r; From patchwork Thu Feb 20 09:28:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 866726 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1f85:b0:38f:210b:807b with SMTP id hj5csp106986wrb; Thu, 20 Feb 2025 01:30:36 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVnCgGdVNdlv51iVx/camK4KOh/7kCKWEsVzQAGbMA4g0fH+1mvLw0DmAlI/LH9IqQnoLW2Mg==@linaro.org X-Google-Smtp-Source: AGHT+IGYC9lbDO7hzsLdj6cl4mdxzqTSvvXeIU+I0NdIb/Mi8ihVoOn7TMlYGFjcZQteWqpcUbHC X-Received: by 2002:a05:6214:2524:b0:6e6:5bc0:1521 with SMTP id 6a1803df08f44-6e6974f8119mr75948586d6.17.1740043836508; Thu, 20 Feb 2025 01:30:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1740043836; cv=none; d=google.com; s=arc-20240605; b=LXZ2ikQk2lmn6PH9kYVj2zN3VtJMPzlQcQgK+5Z7O/yMqGpQrI4qz5dLqaE8Jcinv2 7Kf73DZKKLH7bhZJI9G62aNVFfd6D2KkYwof7BbFY14RbCLq53vwNRT15ZM1RBsaM/36 slTkqtN5lWlboqgiCvYgvOZ7NdtWcUKZxKqQ3zPm/mFZ0Ouk/2StcFfCmJKuFXSLEvPA eR4ULWLkn5j8hHZR7fResnh1UfnW+gbRCnbSPiMFP3LJ1BewReFGJ1DQgOXx8mwe+Thx faaGtFwbRTjHfz0k5LfHK1FNgG39XQSJrg54KCimPGkwC3DAr3RIJvq0+Z0ec+Pvxb9L igDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=U+pfJWALs0vQU6dXlJLT5cjO4jcFzB6bulUI2QERKYM=; fh=SmfC3sO/Je+MRtxTrJqoqGWQJjYliq56u/HVO0sNWv8=; b=hZAQyk41L4sjtzxlzwGAOe9IxI1OaX2aE6gJj0ExeInUQ3mOA2M5sRLRZI4Ftb4N+r Wt3WaNN65Ma/q+gr4PErHTOt7oLzI0eGK7ZW3aCWXqfR68UDE8eG+M4EDxRA1V3+Kk6A n8ha5qYR5VJfTdsx6meg7jiajVrmi+1jGF6UI3FqhSVf0YwfPyqnPJkm6lgrCpIesIrF EQNkJMlAPQwzWEqNVlCQRUZwVn1P7FK3O4mqoYXkv8DFGd0tQKcY4eI5KLgQrmIA59gl 1dTs+YQzF9HMBiKQHZS1lk81qyKGyf03j8HUUD2ynya6gVbZDKk/VjbH9QlsojzDW+/d MHDQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DFgbUxZ0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73264729945sm10067857b3a.179.2025.02.20.01.29.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 20 Feb 2025 01:29:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Magnus Damm , Thomas Huth , Shin'ichiro Kawasaki , Rayhan Faizel , qemu-arm@nongnu.org, Evgeny Iakovlev , Paolo Bonzini , Peter Maydell , Luc Michel , Yoshinori Sato Subject: [PATCH v2 2/9] hw/char/pl011: Simplify a bit pl011_can_receive() Date: Thu, 20 Feb 2025 10:28:55 +0100 Message-ID: <20250220092903.3726-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250220092903.3726-1-philmd@linaro.org> References: <20250220092903.3726-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduce 'fifo_depth' and 'fifo_available' local variables to better express the 'r' variable use. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel --- hw/char/pl011.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 12a2d4bc7bd..5bb83c54216 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -486,7 +486,9 @@ static void pl011_write(void *opaque, hwaddr offset, static int pl011_can_receive(void *opaque) { PL011State *s = (PL011State *)opaque; - int r; + unsigned fifo_depth = pl011_get_fifo_depth(s); + unsigned fifo_available = fifo_depth - s->read_count; + int r = fifo_available ? 1 : 0; if (!(s->cr & CR_UARTEN)) { qemu_log_mask(LOG_GUEST_ERROR, @@ -496,7 +498,6 @@ static int pl011_can_receive(void *opaque) qemu_log_mask(LOG_GUEST_ERROR, "PL011 receiving data on disabled RX UART\n"); } - r = s->read_count < pl011_get_fifo_depth(s); trace_pl011_can_receive(s->lcr, s->read_count, r); return r; } From patchwork Thu Feb 20 09:28:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 866725 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1f85:b0:38f:210b:807b with SMTP id hj5csp106960wrb; Thu, 20 Feb 2025 01:30:32 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWGn/E391LztWoJHfSH4hdpnAF2+rZCxXnOsibgeNvcFOf6KYjgYl7u53j+FAauScpqa/+GWA==@linaro.org X-Google-Smtp-Source: AGHT+IFRqE9ATnMX/1P+edbr+qN4h1RfLLB80dDy6ScPqn1U1NDp1X7GnXEXHYXW2PuFvL5/J3vH X-Received: by 2002:a05:620a:2b9a:b0:7c0:be39:1a34 with SMTP id af79cd13be357-7c0c4349f8amr221968685a.43.1740043831839; Thu, 20 Feb 2025 01:30:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1740043831; cv=none; d=google.com; s=arc-20240605; b=Q+WHkHyAn7+GNxo+opoMBu8Gg/4F2ayNGol0cPoMDOkE0giO5CdLocFDkHxomOfJ+E naqdgyAUCtCJ6sJsjixzvmHLHSV7WhD7MDh9XacMQSJVTc+zy4WKYnO8L8e4vSXlHkEP ej9LYLnKOc7djyNbEWw4Ilb2cIaXmEEgQuxLrsqaxdBbjyo4viV6AWgSFsQ2qyL54bxZ LLdusE0KM2yp7Vst0pKsogSsBFkpHIjX3f/DQq0QhdRSowr5KBfmVir1JIkTwoEg+O2w YFcKNcQwfBBHLVP4UvvdFpl+aty797kcAW8RwaL81p8vcMIr131p69VnHAc+DtVEmWnA XNtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=X18oBKzoazjCfVrAQBfQueu5gB0Bm4XcS+Nhh43VH0E=; fh=SmfC3sO/Je+MRtxTrJqoqGWQJjYliq56u/HVO0sNWv8=; b=HVhL7djeXshhyxbTjXGGsEAM4j+WcIo7mC1EMtYkZO5hokvDETUwqsczZ7I0XySF1m 6uPtiAsW5UyT35SFsOLhO8V6T7eeqHwCQSVzOrOXQZItqcOmqaAJ1EPXbvQKLEXAvxWI WERO4Hg3sUSyHMtMfhvMm52C5DLqwilvT2dPxqgsp1fFMy15M9pP+BeC+gti/IlhZIWo F/S/YT7tNDxRaXt9wBcKu2Ii9JQhYT59B6yUEfSLZzhDBiFhIAzueYktvUsIFg5mKJ0k WbuosisTtHlofs3pf+KQC95mSBGfBXcCrUHYSS7+pZgQhUve8NVakdQUyIl7NiBKTtxi wzlg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sGyhHRgz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-732581df0bbsm11052819b3a.156.2025.02.20.01.29.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 20 Feb 2025 01:30:02 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Magnus Damm , Thomas Huth , Shin'ichiro Kawasaki , Rayhan Faizel , qemu-arm@nongnu.org, Evgeny Iakovlev , Paolo Bonzini , Peter Maydell , Luc Michel , Yoshinori Sato Subject: [PATCH v2 3/9] hw/char/pl011: Improve RX flow tracing events Date: Thu, 20 Feb 2025 10:28:56 +0100 Message-ID: <20250220092903.3726-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250220092903.3726-1-philmd@linaro.org> References: <20250220092903.3726-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=philmd@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Log FIFO use (availability and depth). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Luc Michel --- hw/char/pl011.c | 10 ++++++---- hw/char/trace-events | 7 ++++--- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 5bb83c54216..f7485e7c541 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -185,7 +185,7 @@ static void pl011_fifo_rx_put(void *opaque, uint32_t value) s->read_fifo[slot] = value; s->read_count++; s->flags &= ~PL011_FLAG_RXFE; - trace_pl011_fifo_rx_put(value, s->read_count); + trace_pl011_fifo_rx_put(value, s->read_count, pipe_depth); if (s->read_count == pipe_depth) { trace_pl011_fifo_rx_full(); s->flags |= PL011_FLAG_RXFF; @@ -248,12 +248,13 @@ static void pl011_write_txdata(PL011State *s, uint8_t data) static uint32_t pl011_read_rxdata(PL011State *s) { uint32_t c; + unsigned fifo_depth = pl011_get_fifo_depth(s); s->flags &= ~PL011_FLAG_RXFF; c = s->read_fifo[s->read_pos]; if (s->read_count > 0) { s->read_count--; - s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1); + s->read_pos = (s->read_pos + 1) & (fifo_depth - 1); } if (s->read_count == 0) { s->flags |= PL011_FLAG_RXFE; @@ -261,7 +262,7 @@ static uint32_t pl011_read_rxdata(PL011State *s) if (s->read_count == s->read_trigger - 1) { s->int_level &= ~INT_RX; } - trace_pl011_read_fifo(s->read_count); + trace_pl011_read_fifo(s->read_count, fifo_depth); s->rsr = c >> 8; pl011_update(s); qemu_chr_fe_accept_input(&s->chr); @@ -498,12 +499,13 @@ static int pl011_can_receive(void *opaque) qemu_log_mask(LOG_GUEST_ERROR, "PL011 receiving data on disabled RX UART\n"); } - trace_pl011_can_receive(s->lcr, s->read_count, r); + trace_pl011_can_receive(s->lcr, s->read_count, fifo_depth, fifo_available); return r; } static void pl011_receive(void *opaque, const uint8_t *buf, int size) { + trace_pl011_receive(size); /* * In loopback mode, the RX input signal is internally disconnected * from the entire receiving logics; thus, all inputs are ignored, diff --git a/hw/char/trace-events b/hw/char/trace-events index b2e3d25ae34..05a33036c12 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -60,12 +60,13 @@ imx_serial_put_data(const char *chrname, uint32_t value) "%s: 0x%" PRIx32 # pl011.c pl011_irq_state(int level) "irq state %d" pl011_read(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s" -pl011_read_fifo(int read_count) "FIFO read, read_count now %d" +pl011_read_fifo(unsigned rx_fifo_used, size_t rx_fifo_depth) "RX FIFO read, used %u/%zu" pl011_write(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s" -pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count %d returning %d" -pl011_fifo_rx_put(uint32_t c, int read_count) "new char 0x%02x read_count now %d" +pl011_can_receive(uint32_t lcr, unsigned rx_fifo_used, size_t rx_fifo_depth, unsigned rx_fifo_available) "LCR 0x%02x, RX FIFO used %u/%zu, can_receive %u chars" +pl011_fifo_rx_put(uint32_t c, unsigned read_count, size_t rx_fifo_depth) "RX FIFO push char [0x%02x] %d/%zu depth used" pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set" pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd, uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd: %" PRIu32 ")" +pl011_receive(int size) "recv %d chars" # cmsdk-apb-uart.c cmsdk_apb_uart_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB UART read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" From patchwork Thu Feb 20 09:28:57 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fbf98b4c45sm15328183a91.2.2025.02.20.01.30.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 20 Feb 2025 01:30:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Magnus Damm , Thomas Huth , Shin'ichiro Kawasaki , Rayhan Faizel , qemu-arm@nongnu.org, Evgeny Iakovlev , Paolo Bonzini , Peter Maydell , Luc Michel , Yoshinori Sato Subject: [PATCH v2 4/9] hw/char/pl011: Really use RX FIFO depth Date: Thu, 20 Feb 2025 10:28:57 +0100 Message-ID: <20250220092903.3726-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250220092903.3726-1-philmd@linaro.org> References: <20250220092903.3726-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=philmd@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org While we model a 16-elements RX FIFO since the PL011 model was introduced in commit cdbdb648b7c ("ARM Versatile Platform Baseboard emulation"), we only read 1 char at a time! Have the IOCanReadHandler handler return how many elements are available, and use that in the IOReadHandler handler. Example of FIFO better used by enabling the pl011 tracing events and running the tests/functional/test_aarch64_virt.py tests: pl011_can_receive LCR 0x70, RX FIFO used 0/16, can_receive 16 chars pl011_receive recv 5 chars pl011_fifo_rx_put RX FIFO push char [0x72] 1/16 depth used pl011_irq_state irq state 1 pl011_fifo_rx_put RX FIFO push char [0x6f] 2/16 depth used pl011_fifo_rx_put RX FIFO push char [0x6f] 3/16 depth used pl011_fifo_rx_put RX FIFO push char [0x74] 4/16 depth used pl011_fifo_rx_put RX FIFO push char [0x0d] 5/16 depth used pl011_can_receive LCR 0x70, RX FIFO used 5/16, can_receive 11 chars pl011_can_receive LCR 0x70, RX FIFO used 5/16, can_receive 11 chars pl011_write addr 0x038 value 0x00000050 reg IMSC pl011_irq_state irq state 1 pl011_can_receive LCR 0x70, RX FIFO used 5/16, can_receive 11 chars pl011_read addr 0x03c value 0x00000030 reg RIS pl011_write addr 0x044 value 0x00000000 reg ICR pl011_irq_state irq state 1 pl011_read addr 0x018 value 0x00000080 reg FR pl011_read_fifo RX FIFO read, used 4/16 pl011_irq_state irq state 1 pl011_read addr 0x000 value 0x00000072 reg DR pl011_can_receive LCR 0x70, RX FIFO used 4/16, can_receive 12 chars pl011_read addr 0x018 value 0x00000080 reg FR pl011_read_fifo RX FIFO read, used 3/16 pl011_irq_state irq state 1 pl011_read addr 0x000 value 0x0000006f reg DR pl011_can_receive LCR 0x70, RX FIFO used 3/16, can_receive 13 chars pl011_read addr 0x018 value 0x00000080 reg FR pl011_read_fifo RX FIFO read, used 2/16 pl011_irq_state irq state 1 pl011_read addr 0x000 value 0x0000006f reg DR pl011_can_receive LCR 0x70, RX FIFO used 2/16, can_receive 14 chars pl011_read addr 0x018 value 0x00000080 reg FR pl011_read_fifo RX FIFO read, used 1/16 pl011_irq_state irq state 1 pl011_read addr 0x000 value 0x00000074 reg DR pl011_can_receive LCR 0x70, RX FIFO used 1/16, can_receive 15 chars pl011_read addr 0x018 value 0x00000080 reg FR pl011_read_fifo RX FIFO read, used 0/16 pl011_irq_state irq state 0 pl011_read addr 0x000 value 0x0000000d reg DR pl011_can_receive LCR 0x70, RX FIFO used 0/16, can_receive 16 chars pl011_read addr 0x018 value 0x00000090 reg FR pl011_read addr 0x03c value 0x00000020 reg RIS pl011_write addr 0x038 value 0x00000050 reg IMSC pl011_irq_state irq state 0 pl011_can_receive LCR 0x70, RX FIFO used 0/16, can_receive 16 chars pl011_can_receive LCR 0x70, RX FIFO used 0/16, can_receive 16 chars pl011_read addr 0x018 value 0x00000090 reg FR pl011_write addr 0x000 value 0x00000072 reg DR Inspired-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel --- hw/char/pl011.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index f7485e7c541..23a9db8c57c 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -489,7 +489,6 @@ static int pl011_can_receive(void *opaque) PL011State *s = (PL011State *)opaque; unsigned fifo_depth = pl011_get_fifo_depth(s); unsigned fifo_available = fifo_depth - s->read_count; - int r = fifo_available ? 1 : 0; if (!(s->cr & CR_UARTEN)) { qemu_log_mask(LOG_GUEST_ERROR, @@ -500,7 +499,8 @@ static int pl011_can_receive(void *opaque) "PL011 receiving data on disabled RX UART\n"); } trace_pl011_can_receive(s->lcr, s->read_count, fifo_depth, fifo_available); - return r; + + return fifo_available; } static void pl011_receive(void *opaque, const uint8_t *buf, int size) @@ -515,7 +515,9 @@ static void pl011_receive(void *opaque, const uint8_t *buf, int size) return; } - pl011_fifo_rx_put(opaque, *buf); + for (int i = 0; i < size; i++) { + pl011_fifo_rx_put(opaque, buf[i]); + } } static void pl011_event(void *opaque, QEMUChrEvent event) From patchwork Thu Feb 20 09:28:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 866733 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1f85:b0:38f:210b:807b with SMTP id hj5csp107594wrb; Thu, 20 Feb 2025 01:32:12 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWQdzIXRBomP73RRi1ZM/Lr04c3pzHw9t40KkKUSwsWJixsCWXJl/I9OVm6iT4cU5DS6+WZxA==@linaro.org X-Google-Smtp-Source: AGHT+IEh6Jffae4KOA4BHFuR2rAUzK7bj8PG8f5whlaya2V2iYPC9OLzP1kIaCXbaE/XTXsAm8ap X-Received: by 2002:a05:620a:1a9f:b0:7c0:ae97:7fa0 with SMTP id af79cd13be357-7c0c434cc87mr173940085a.45.1740043932069; Thu, 20 Feb 2025 01:32:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1740043932; cv=none; d=google.com; s=arc-20240605; b=SiTagDmr1CV9F8kRbvNf4e7cCHE5PuPDYUzfkuZP/XgsNVglhDt6X7+YkkFtSxivhp S8SDySojjR/uBe4khy6CEsmMNWNH2mPfl8Vi9grNKZC+AnBMyxVFFq/FE3X1Nf9EOUV2 6q4O6xL8XGhD6q62HmN8DgQ1BrkaRCa0XHmwBurKg/XGYjXRlqk9Yfkv8ioKVko9oxYj R53aPMfhkAyHVUxFuZD5T+EUO9MeIof1BwkOCebEOnwN5x2EdoRo94gna8ezif7KM4R2 7GycYbHbsoGL9/TLXeQMdeUeQN4VLfIPFPP0mmD0/IQoXjRYLIC0t8wPz1QniS+beiuM l7RQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GNUu0QLM1jJD6vp7svI4zxOCu3a+5YIL+dQ3Ih3Jc18=; fh=SmfC3sO/Je+MRtxTrJqoqGWQJjYliq56u/HVO0sNWv8=; b=jN3sSPdP4cSFydSQlAlmwHSLHUqFaa0duyOv12/71cB5X3Wm/tEgDzIZ0a+EGXTlPo Jxuh0dcNDaNTEEWu2JxWwLR4VEY20NIQlE12D2CPaF2J9520MWvWZ/u4Z3bAiwL+GwwB NQcjf9j/ZTS1grSC3aFYqyuq4AE513kfn19YYlMnYBuokfzBCoIirpSm10p+d/6k4l4I X26Vg5wj2o9sWvRYNtftpriRIwis0GFJJKXlCfzOVdv2xQakma7KYfd2a/lxRbAeP80b 2/uyegeR60ikiWqmPQ8OTO6uK16DN29k/xT5aAEb6g3RXY9Ys9uCqfZMes9FB+ipUQen KTgg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ccJG7RB/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7324273c8a4sm13283568b3a.85.2025.02.20.01.30.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 20 Feb 2025 01:30:33 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Magnus Damm , Thomas Huth , Shin'ichiro Kawasaki , Rayhan Faizel , qemu-arm@nongnu.org, Evgeny Iakovlev , Paolo Bonzini , Peter Maydell , Luc Michel , Yoshinori Sato Subject: [PATCH v2 5/9] hw/char/bcm2835_aux: Really use RX FIFO depth Date: Thu, 20 Feb 2025 10:28:58 +0100 Message-ID: <20250220092903.3726-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250220092903.3726-1-philmd@linaro.org> References: <20250220092903.3726-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=philmd@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org While we model a 8-elements RX FIFO since the BCM2835 AUX model was introduced in commit 97398d900ca ("bcm2835_aux: add emulation of BCM2835 AUX block") we only read 1 char at a time! Have the IOCanReadHandler handler return how many elements are available, and use that in the IOReadHandler handler. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel --- hw/char/bcm2835_aux.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c index 73ad5934067..c6e7eccf7dd 100644 --- a/hw/char/bcm2835_aux.c +++ b/hw/char/bcm2835_aux.c @@ -221,7 +221,7 @@ static int bcm2835_aux_can_receive(void *opaque) { BCM2835AuxState *s = opaque; - return s->read_count < BCM2835_AUX_RX_FIFO_LEN; + return BCM2835_AUX_RX_FIFO_LEN - s->read_count; } static void bcm2835_aux_put_fifo(void *opaque, uint8_t value) @@ -243,7 +243,9 @@ static void bcm2835_aux_put_fifo(void *opaque, uint8_t value) static void bcm2835_aux_receive(void *opaque, const uint8_t *buf, int size) { - bcm2835_aux_put_fifo(opaque, *buf); + for (int i = 0; i < size; i++) { + bcm2835_aux_put_fifo(opaque, buf[i]); + } } static const MemoryRegionOps bcm2835_aux_ops = { From patchwork Thu Feb 20 09:28:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 866729 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1f85:b0:38f:210b:807b with SMTP id hj5csp107277wrb; Thu, 20 Feb 2025 01:31:27 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU5aAo5OvXAgAIPUQaPzr2pJypBswD9610pUFR/Rmbb+WqwMPLm13X2KFlAOMwofFZUQilaKA==@linaro.org X-Google-Smtp-Source: AGHT+IEprZTA2aBDa3d5j4UaZRePUI38WnnuXgwRUGeWFlVCfdkJBJG/bNP1Kppeu3oE1kKPK3BA X-Received: by 2002:a05:620a:45a8:b0:7b6:7850:21d4 with SMTP id af79cd13be357-7c0b5331dfdmr1023112085a.52.1740043886860; Thu, 20 Feb 2025 01:31:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1740043886; cv=none; d=google.com; s=arc-20240605; b=SE2BADdYTEZPo0h8WUeF5RzBcneI/6AzMfFfauRHuMGbzziK6hyOkH+JPNoTAwLYxa 2Scc/4allwGVAUfy3122PFi6NOpUxdRfymwnWu0qjDTUpKt/bhb3jaM49+2qCcChbL7g tCgv6yN6ZU0SRfBzX6kWXpfBY5PP0swBtxhSYO/VKpKEOEzSw+83+wF2J0Pjq7Em4BDS 3AkxxYoRLpo23r6fhrK7qZ9zbwxBsd8AvNFn3fyc1K8vOJdQsdGr4ikJc2bcPLO0B/k7 e807boseMiYHnP3b1KBDN39G/yWsyYFhyc6wROvkTH9HVgCZdyvnQC21k8kC3mygpC1d 980g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=H2/xpK9DtdqY8a6ieh8rBtI4fW+GPrI9nBJmXLMfGvA=; fh=SmfC3sO/Je+MRtxTrJqoqGWQJjYliq56u/HVO0sNWv8=; b=WdSqMPtI+RY/2bMnfjF85bwL33YvEEGG3MU+KQBujjZWbi8i23hRrqsG9JUhG83S6H mKQ7A8IoKMD7kdcv2SirGb3zxHtMUjVQpG1UnWUXp6B2+wSRXIHXtddnRVPdrc1mtMJv rtD/2+BgUmcdsJwvvt9HKMAIIcKj7DubKtjfO2CbHjO6hEwId9Wr+C0tK9WRMZ+YsnYg pgMvjxOn1GqUONKblPdJuRCxuU7bE8krxpICMYHZPSCERyfHKUlPmnCNA/Qx1PlPTYBn xQJWUd8pVLyW32k8tgSD3AwJZK6uM2qUIBMVainMjEfFE3xwHkjm2mleo2kog0aaGPEk 9sDw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dsCNQMJU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-732700c1c31sm8603468b3a.1.2025.02.20.01.30.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 20 Feb 2025 01:30:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Magnus Damm , Thomas Huth , Shin'ichiro Kawasaki , Rayhan Faizel , qemu-arm@nongnu.org, Evgeny Iakovlev , Paolo Bonzini , Peter Maydell , Luc Michel , Yoshinori Sato Subject: [PATCH v2 6/9] hw/char/imx_serial: Really use RX FIFO depth Date: Thu, 20 Feb 2025 10:28:59 +0100 Message-ID: <20250220092903.3726-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250220092903.3726-1-philmd@linaro.org> References: <20250220092903.3726-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=philmd@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org While we model a 32-elements RX FIFO since the IMX serial model was introduced in commit 988f2442971 ("hw/char/imx_serial: Implement receive FIFO and ageing timer") we only read 1 char at a time! Have the IOCanReadHandler handler return how many elements are available, and use that in the IOReadHandler handler. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel --- hw/char/imx_serial.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index 38b4865157e..6f14f8403a9 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -386,7 +386,8 @@ static void imx_serial_write(void *opaque, hwaddr offset, static int imx_can_receive(void *opaque) { IMXSerialState *s = (IMXSerialState *)opaque; - return s->ucr2 & UCR2_RXEN && fifo32_num_used(&s->rx_fifo) < FIFO_SIZE; + + return s->ucr2 & UCR2_RXEN ? fifo32_num_free(&s->rx_fifo) : 0; } static void imx_put_data(void *opaque, uint32_t value) @@ -417,7 +418,10 @@ static void imx_receive(void *opaque, const uint8_t *buf, int size) IMXSerialState *s = (IMXSerialState *)opaque; s->usr2 |= USR2_WAKE; - imx_put_data(opaque, *buf); + + for (int i = 0; i < size; i++) { + imx_put_data(opaque, buf[i]); + } } static void imx_event(void *opaque, QEMUChrEvent event) From patchwork Thu Feb 20 09:29:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 866730 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1f85:b0:38f:210b:807b with SMTP id hj5csp107280wrb; Thu, 20 Feb 2025 01:31:27 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXrZ5hkPXO9IXEuEUXLyc12U0USeYqPbWe8G1sxGCNF6+hm5uSqWxd/QYgaWvXfVF0/nU10Ew==@linaro.org X-Google-Smtp-Source: AGHT+IF3rqZ7x6M/z/brm2jOMYaoQajgJAx4LZV3wZsEbnoJ0Qgwp/vO3G4h6cnI6icgg369VRpO X-Received: by 2002:a05:620a:29c9:b0:7c0:a1ee:e8d2 with SMTP id af79cd13be357-7c0b530814bmr966055485a.41.1740043887598; Thu, 20 Feb 2025 01:31:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1740043887; cv=none; d=google.com; s=arc-20240605; b=a7xMo34U9Qi29YmAfivUuXMngHldD5gLd1+P/+emyc5q6VWX3JNjM8EW5WW6O8ImSu ZdXgbXfl0H3PcS0MhovPxVz3l8CV8L3SfJ5xnGYYmm4jT8Xj48/qLsqiWKZK0ruuBRbk kXSVzIa0nKMQytwgR0T9tTPbdFXdsAF9c2Ul6INP92rKe1ykRXKut7/zETSaYVAjyUA7 GjQzsLJ2F3Q1jsiaEH1l3J/LygojIDTR3I7u2tdwOKKSfIhI51RJaLRvZI/vJlg0a20K zPWM+QZuBNzYBURYBTNeFRQA9auDtHwqTnRfagmolnuYtqqVNT78gBdNjm+ECkXXo2Fw 27Lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2DkPTvskXfEKDS8ksEDRN9mL+hSgQIvFZ8gbNR3D4CQ=; fh=SmfC3sO/Je+MRtxTrJqoqGWQJjYliq56u/HVO0sNWv8=; b=S9JnhyabykgeylqwP0UZOho65fpe+9BLjDtc3vKPQE9kUbtX7Q3vYu+Fec+/05Cm9o Uy5zqwYDB4jZ/CtP/iHwHqL5CSnGzJE4il3hh6NgfGYQPFnSpNW+LygGqU/R0zGDpwui qjIMyfl6hQfYvxPVJQ9cmoCHXFXiHY+qQUeIYxLsc3q6PqxGcOKujH2LqOs4mpcNk7tW k2W5m4CFKP6l1d9KnFsKqazPkikkSDg7U3w2b9ecR/Y+yFnKc2qt2xzcEdHC3G1kgA1u KDKbKpXPWoCRdjFhLVfC9wlV66M4BZ9SqsJ96h7FoUMzboqcCs2H7byJz7nhVsnvVwq2 9gBA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o9jRQniZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-220d5349077sm118268655ad.1.2025.02.20.01.30.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 20 Feb 2025 01:31:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Magnus Damm , Thomas Huth , Shin'ichiro Kawasaki , Rayhan Faizel , qemu-arm@nongnu.org, Evgeny Iakovlev , Paolo Bonzini , Peter Maydell , Luc Michel , Yoshinori Sato Subject: [PATCH v2 7/9] hw/char/mcf_uart: Use FIFO_DEPTH definition instead of magic values Date: Thu, 20 Feb 2025 10:29:00 +0100 Message-ID: <20250220092903.3726-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250220092903.3726-1-philmd@linaro.org> References: <20250220092903.3726-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Defines FIFO_DEPTH and use it, fixing coding style. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Reviewed-by: Thomas Huth --- hw/char/mcf_uart.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/hw/char/mcf_uart.c b/hw/char/mcf_uart.c index 980a12fcb7d..95f269ee9b7 100644 --- a/hw/char/mcf_uart.c +++ b/hw/char/mcf_uart.c @@ -17,6 +17,8 @@ #include "chardev/char-fe.h" #include "qom/object.h" +#define FIFO_DEPTH 4 + struct mcf_uart_state { SysBusDevice parent_obj; @@ -27,7 +29,7 @@ struct mcf_uart_state { uint8_t imr; uint8_t bg1; uint8_t bg2; - uint8_t fifo[4]; + uint8_t fifo[FIFO_DEPTH]; uint8_t tb; int current_mr; int fifo_len; @@ -247,14 +249,16 @@ static void mcf_uart_reset(DeviceState *dev) static void mcf_uart_push_byte(mcf_uart_state *s, uint8_t data) { /* Break events overwrite the last byte if the fifo is full. */ - if (s->fifo_len == 4) + if (s->fifo_len == FIFO_DEPTH) { s->fifo_len--; + } s->fifo[s->fifo_len] = data; s->fifo_len++; s->sr |= MCF_UART_RxRDY; - if (s->fifo_len == 4) + if (s->fifo_len == FIFO_DEPTH) { s->sr |= MCF_UART_FFULL; + } mcf_uart_update(s); } From patchwork Thu Feb 20 09:29:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 866731 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1f85:b0:38f:210b:807b with SMTP id hj5csp107372wrb; Thu, 20 Feb 2025 01:31:39 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX4SGHBSzUUacNK8N9Prhu1hHTDzl/MH94KesZgvyv5j8/E/kiRSK2ycSL0eGiCKfSTbofM8g==@linaro.org X-Google-Smtp-Source: AGHT+IEBqRj+oqveMC30uxL/hHAZbULF2s7pCOqVCtU6QtCYbtWry8u9DeoZqb22OkZ2aXiK7rfW X-Received: by 2002:a05:620a:a007:b0:7c0:9dc9:7553 with SMTP id af79cd13be357-7c09dc980d0mr1252590885a.0.1740043899542; Thu, 20 Feb 2025 01:31:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1740043899; cv=none; d=google.com; s=arc-20240605; b=hdYpDSf6uLfu06Dq/wBeM5wEUPZe584KdRbCOy3dAcpRxQ14esVg1rQbzvyLijR1RS DrbQckm5ZO52hPgkJiaCKbfGoZyzVBcYWSOympl/dZizpvKVliNH4SOSpdrk/xSUU4vu tR29KrYu8UTC6PCX6NE3zCZ+7wmeJ4COF0Guy+dBHlccGFzNjx2kwUaIrwloCDUzOCKF r2IUogcY8Pb+8BRGIoqstpV7CiP7ImVnajrL37Oo3JvTv9ABmvLFK+LnrHXsFWnqLBBi 5pKKHcC48Oa4a5Ct+gU4aPvaipvZ5BvACQAuDbQ+WkjtwePMFtAVy0bFO3EDZPFKwv/l LwEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HC4oun0jFc0+NwBeUFjNGte1nRrGw6nA41LdkLLgvBM=; fh=SmfC3sO/Je+MRtxTrJqoqGWQJjYliq56u/HVO0sNWv8=; b=XNxDYjknUsA+i8OkXzkHp7/vz1VgArGo6mhR5u/GtfpkJhDLKbht5HyMl505NDnRgf 1xv/uMEa2CYmNJJb4vhraTYAyNmPYhjXdiYhaCH9j0iB8+Tb60GDn7jsnisGOUfjhPUQ wetdSSnjNEB+dRR/WJVY167atx9jixMIg92OmrI9OcO9hPIQpn6qsXBcgUFuvTKkkzA2 1X3npX7+yWVYquRilM0QX6URLs/qdt1zPGUhRjxI6Qa3JC6YsEAP0/y+qMRzYRN6z0Hy e7JkVawcWCvkTAeFPmeOuZPGrxbacn+5NjWvPtutQ1lAwsQvng7fYV+mZ/S7IWYnOJeg x8VA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="t7/b7faV"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-adb57c5ea71sm12264684a12.8.2025.02.20.01.31.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 20 Feb 2025 01:31:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Magnus Damm , Thomas Huth , Shin'ichiro Kawasaki , Rayhan Faizel , qemu-arm@nongnu.org, Evgeny Iakovlev , Paolo Bonzini , Peter Maydell , Luc Michel , Yoshinori Sato Subject: [PATCH v2 8/9] hw/char/mcf_uart: Really use RX FIFO depth Date: Thu, 20 Feb 2025 10:29:01 +0100 Message-ID: <20250220092903.3726-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250220092903.3726-1-philmd@linaro.org> References: <20250220092903.3726-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=philmd@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org While we model a 4-elements RX FIFO since the MCF UART model was introduced in commit 20dcee94833 ("MCF5208 emulation"), we only read 1 char at a time! Have the IOCanReadHandler handler return how many elements are available, and use that in the IOReadHandler handler. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Tested-by: Thomas Huth Reviewed-by: Thomas Huth --- hw/char/mcf_uart.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/char/mcf_uart.c b/hw/char/mcf_uart.c index 95f269ee9b7..529c26be93a 100644 --- a/hw/char/mcf_uart.c +++ b/hw/char/mcf_uart.c @@ -281,14 +281,16 @@ static int mcf_uart_can_receive(void *opaque) { mcf_uart_state *s = (mcf_uart_state *)opaque; - return s->rx_enabled && (s->sr & MCF_UART_FFULL) == 0; + return s->rx_enabled ? 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fcbaaf3f38sm1628375a91.1.2025.02.20.01.31.29 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 20 Feb 2025 01:31:35 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Magnus Damm , Thomas Huth , Shin'ichiro Kawasaki , Rayhan Faizel , qemu-arm@nongnu.org, Evgeny Iakovlev , Paolo Bonzini , Peter Maydell , Luc Michel , Yoshinori Sato Subject: [PATCH v2 9/9] hw/char/sh_serial: Return correct number of empty RX FIFO elements Date: Thu, 20 Feb 2025 10:29:02 +0100 Message-ID: <20250220092903.3726-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250220092903.3726-1-philmd@linaro.org> References: <20250220092903.3726-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=philmd@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In the IOCanReadHandler sh_serial_can_receive(), if the Serial Control Register 'Receive Enable' bit is set (bit 4), then we return a size of (1 << 4) which happens to be equal to 16, so effectively SH_RX_FIFO_LENGTH. The IOReadHandler, sh_serial_receive1() takes care to receive multiple chars, but if the FIFO is partly filled, we only process the number of free slots in the FIFO, discarding the other chars! Fix by returning how many elements the FIFO can queue in the IOCanReadHandler, so we don't have to process more than that in the IOReadHandler, thus not discarding anything. Remove the now unnecessary check on 's->rx_cnt < SH_RX_FIFO_LENGTH' in IOReadHandler, reducing the block indentation. Fixes: 63242a007a1 ("SH4: Serial controller improvement") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel --- hw/char/sh_serial.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 247aeb071ac..41c8175a638 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -320,7 +320,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs, static int sh_serial_can_receive(SHSerialState *s) { - return s->scr & (1 << 4); + return s->scr & (1 << 4) ? SH_RX_FIFO_LENGTH - s->rx_head : 0; } static void sh_serial_receive_break(SHSerialState *s) @@ -353,22 +353,20 @@ static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) if (s->feat & SH_SERIAL_FEAT_SCIF) { int i; for (i = 0; i < size; i++) { - if (s->rx_cnt < SH_RX_FIFO_LENGTH) { - s->rx_fifo[s->rx_head++] = buf[i]; - if (s->rx_head == SH_RX_FIFO_LENGTH) { - s->rx_head = 0; - } - s->rx_cnt++; - if (s->rx_cnt >= s->rtrg) { - s->flags |= SH_SERIAL_FLAG_RDF; - if (s->scr & (1 << 6) && s->rxi) { - timer_del(&s->fifo_timeout_timer); - qemu_set_irq(s->rxi, 1); - } - } else { - timer_mod(&s->fifo_timeout_timer, - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu); + s->rx_fifo[s->rx_head++] = buf[i]; + if (s->rx_head == SH_RX_FIFO_LENGTH) { + s->rx_head = 0; + } + s->rx_cnt++; + if (s->rx_cnt >= s->rtrg) { + s->flags |= SH_SERIAL_FLAG_RDF; + if (s->scr & (1 << 6) && s->rxi) { + timer_del(&s->fifo_timeout_timer); + qemu_set_irq(s->rxi, 1); } + } else { + timer_mod(&s->fifo_timeout_timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu); } } } else {