From patchwork Mon Mar 3 04:47:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 870273 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05DEC1C3BEE; Mon, 3 Mar 2025 04:47:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740977272; cv=none; b=f5UtbbVu0xg4idmyn/DpsuxRxWsMQtepAHYGkFzuGpaThCkn4mmcb1vKCONS5V1LoB7fhpb2b4EqS8O0zxJKFAkuFPOsV4G/FcEhwXQoAYWf2po72+fyEI8+12NVjV1ny0rPlzPgAuQjobkX6xhsyNV093NduSU3U5eMGXnNSKI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740977272; c=relaxed/simple; bh=zgp/lBPbKz+16VAdbdVWjEJ14+jqNgFywH05sjjNqpE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JvaHibjcxTkHlIi5C02+m+O7dFA4Pi/34BeGGX4+oHwAy6Pb6gY5Evuvwtfjcb6vfyXHfDeI4Aup6TehgRmx2MYoZCJwBXLh3zHIG15JUl5Gc+rMON2jJSc9Y8mx9wRC13MXsLchsZoWIyeYKk5J4Z5SQxd28hsAFYd27gvJMGo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PGC3ulXx; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PGC3ulXx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740977271; x=1772513271; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zgp/lBPbKz+16VAdbdVWjEJ14+jqNgFywH05sjjNqpE=; b=PGC3ulXx+QE+kzc2JAKQhoS86JetHPdYqxmwc0MTme2oJkApk3lRbui0 xsGU0VTaxDMk0T6PaZPVt2HvDT6JDuUP9/eEB/yZ0AqkIivBWOKeG4Gi1 cx5/VRFJCnRNTrJ7Cfok9Q9ffKANEUEbS2NVYcVn0INwdHR6m2XDuA6kC LCSy4oKX7oqWL0CcOD5ipgxKKQB3Mh0WxFWRgoEtN+uP/mZnYBmaGL4U1 3l8RvRhMYcFCpJRQkLKfm7YGbTAfMftvn/ab6Fyp95vqVHIFwteVezwIU rVxTrqt6ltq+qyELxKoupOWVdwyu8+FG6/oz45pmXpVDTeTa5CkdybBLz w==; X-CSE-ConnectionGUID: U4uMmf1PSXKEcdrH+1vJ6w== X-CSE-MsgGUID: YBK1ApdcTHyI4AXhn4Slyw== X-IronPort-AV: E=McAfee;i="6700,10204,11361"; a="59382058" X-IronPort-AV: E=Sophos;i="6.13,328,1732608000"; d="scan'208";a="59382058" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2025 20:47:50 -0800 X-CSE-ConnectionGUID: xpXjG9ASQ2iB6hxmjmi+Ag== X-CSE-MsgGUID: FuluKIpuQyqSc4nJqvGreQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="123123932" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by orviesa005.jf.intel.com with ESMTP; 02 Mar 2025 20:47:48 -0800 From: Raag Jadav To: lee@kernel.org, giometti@enneenne.com, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, raymond.tan@intel.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Raag Jadav Subject: [PATCH v2 1/5] mfd: intel_ehl_pse_gpio: Introduce Intel Elkhart Lake PSE GPIO and TIO Date: Mon, 3 Mar 2025 10:17:41 +0530 Message-Id: <20250303044745.268964-2-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250303044745.268964-1-raag.jadav@intel.com> References: <20250303044745.268964-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Intel Elkhart Lake Programmable Service Engine (PSE) includes two PCI devices that expose two different capabilities of GPIO and Timed I/O as a single PCI function through shared MMIO. Signed-off-by: Raag Jadav Reviewed-by: Andy Shevchenko --- MAINTAINERS | 5 ++ drivers/mfd/Kconfig | 12 ++++ drivers/mfd/Makefile | 1 + drivers/mfd/intel_ehl_pse_gpio.c | 100 +++++++++++++++++++++++++++++++ 4 files changed, 118 insertions(+) create mode 100644 drivers/mfd/intel_ehl_pse_gpio.c diff --git a/MAINTAINERS b/MAINTAINERS index d4280facbe51..9077ab11478c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11643,6 +11643,11 @@ F: drivers/gpio/gpio-sodaville.c F: drivers/gpio/gpio-tangier.c F: drivers/gpio/gpio-tangier.h +INTEL GPIO MFD DRIVER +M: Raag Jadav +S: Supported +F: drivers/mfd/intel_ehl_pse_gpio.c + INTEL GVT-g DRIVERS (Intel GPU Virtualization) M: Zhenyu Wang M: Zhi Wang diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 6b0682af6e32..36eac5245179 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -597,6 +597,18 @@ config MFD_HI655X_PMIC help Select this option to enable Hisilicon hi655x series pmic driver. +config MFD_INTEL_EHL_PSE_GPIO + tristate "Intel Elkhart Lake PSE GPIO MFD" + depends on PCI && (X86 || COMPILE_TEST) + select MFD_CORE + help + This MFD provides support for GPIO and TIO that exist on Intel + Elkhart Lake PSE as a single PCI device. It splits the two I/O + devices to their respective I/O drivers. + + To compile this driver as a module, choose M here: the module will + be called intel_ehl_pse_gpio. + config MFD_INTEL_QUARK_I2C_GPIO tristate "Intel Quark MFD I2C GPIO" depends on PCI diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 9220eaf7cf12..8f7d257856db 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -196,6 +196,7 @@ obj-$(CONFIG_MFD_TIMBERDALE) += timberdale.o obj-$(CONFIG_PMIC_ADP5520) += adp5520.o obj-$(CONFIG_MFD_ADP5585) += adp5585.o obj-$(CONFIG_MFD_KEMPLD) += kempld-core.o +obj-$(CONFIG_MFD_INTEL_EHL_PSE_GPIO) += intel_ehl_pse_gpio.o obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o obj-$(CONFIG_LPC_SCH) += lpc_sch.o obj-$(CONFIG_LPC_ICH) += lpc_ich.o diff --git a/drivers/mfd/intel_ehl_pse_gpio.c b/drivers/mfd/intel_ehl_pse_gpio.c new file mode 100644 index 000000000000..6a6ad1390a7b --- /dev/null +++ b/drivers/mfd/intel_ehl_pse_gpio.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel MFD driver for Elkhart Lake - Programmable Service Engine + * (PSE) GPIO & TIO + * + * Copyright (c) 2025 Intel Corporation + * + * Intel Elkhart Lake PSE includes two PCI devices that expose two + * different capabilities of GPIO and Timed I/O as a single PCI + * function through shared MMIO. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PSE_GPIO_OFFSET 0x0000 +#define PSE_GPIO_SIZE 0x0134 + +#define PSE_TIO_OFFSET 0x1000 +#define PSE_TIO_SIZE 0x06B0 + +static struct resource ehl_pse_gpio_resources[] = { + DEFINE_RES_MEM(PSE_GPIO_OFFSET, PSE_GPIO_SIZE), + DEFINE_RES_IRQ(0), +}; + +static struct resource ehl_pse_tio_resources[] = { + DEFINE_RES_MEM(PSE_TIO_OFFSET, PSE_TIO_SIZE), + DEFINE_RES_IRQ(1), +}; + +static struct mfd_cell ehl_pse_gpio_devs[] = { + { + .name = "gpio-elkhartlake", + .num_resources = ARRAY_SIZE(ehl_pse_gpio_resources), + .resources = ehl_pse_gpio_resources, + .ignore_resource_conflicts = true, + }, + { + .name = "pps-gen-tio", + .num_resources = ARRAY_SIZE(ehl_pse_tio_resources), + .resources = ehl_pse_tio_resources, + .ignore_resource_conflicts = true, + }, +}; + +static int ehl_pse_gpio_probe(struct pci_dev *pci, const struct pci_device_id *id) +{ + int ret; + + ret = pcim_enable_device(pci); + if (ret) + return ret; + + pci_set_master(pci); + + ret = pci_alloc_irq_vectors(pci, 2, 2, PCI_IRQ_ALL_TYPES); + if (ret < 0) + return ret; + + ret = mfd_add_devices(&pci->dev, PLATFORM_DEVID_AUTO, ehl_pse_gpio_devs, + ARRAY_SIZE(ehl_pse_gpio_devs), pci_resource_n(pci, 0), + pci_irq_vector(pci, 0), NULL); + if (ret) + pci_free_irq_vectors(pci); + + return ret; +} + +static void ehl_pse_gpio_remove(struct pci_dev *pdev) +{ + mfd_remove_devices(&pdev->dev); + pci_free_irq_vectors(pdev); +} + +static const struct pci_device_id ehl_pse_gpio_ids[] = { + { PCI_VDEVICE(INTEL, 0x4b88) }, + { PCI_VDEVICE(INTEL, 0x4b89) }, + {} +}; +MODULE_DEVICE_TABLE(pci, ehl_pse_gpio_ids); + +static struct pci_driver ehl_pse_gpio_driver = { + .probe = ehl_pse_gpio_probe, + .remove = ehl_pse_gpio_remove, + .id_table = ehl_pse_gpio_ids, + .name = "ehl_pse_gpio", +}; +module_pci_driver(ehl_pse_gpio_driver); + +MODULE_AUTHOR("Raymond Tan "); +MODULE_AUTHOR("Raag Jadav "); +MODULE_DESCRIPTION("Intel MFD for Elkhart Lake PSE GPIO & TIO"); +MODULE_LICENSE("GPL"); From patchwork Mon Mar 3 04:47:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 869941 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FDCD1DF965; Mon, 3 Mar 2025 04:47:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740977275; cv=none; b=j4ChosW9PLgEA+7TpMEuRY9QyUDW8cg1pGBc8Gp/7kr6O6FjNv+ht24fLNvDnMfqH/O1oYmrv+acAzUKM93BS2rApcG+OTCCHunnkUNEUUoF2oH4dxlRD/6Cx/vEMrM2HxKyM3OEf3i/1EEpB7S4Cjp8mDCFyYLs0Ig92A7E64U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740977275; c=relaxed/simple; bh=GQjFOSjwtcq2rQBKngc2Gphmz7RBHeegkQmYgOQYA/o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FYfo2fsbntl2IrI6hi5B7+xeyazJUystuDVKL0yneN2PoE1vj7CqpqPRtgLeeEl2i9hkwMS5AACQZkmGvoAIUl7lpk834OkDxsvpuUA8rSKm0+oYjHMgxKbLYMqoeou8xycq6dW0wIi4i80Qcnc23q2DxuXms+YkBav7KlWpXnM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NyGHb0cq; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NyGHb0cq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740977273; x=1772513273; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GQjFOSjwtcq2rQBKngc2Gphmz7RBHeegkQmYgOQYA/o=; b=NyGHb0cqOR51XO6atknnaWj3gI0bPQCbtxnVNm5NT4NIKTro19Hq7BPe gqVGvd6Ce3uymueVzg2avOq5vlX93BM7Vu8HShZB0XU1g9Ke+sJ5Z2m29 zVwXZZRFTthsEkXyLWx6iQgRen0EoQtNUfQ9LbJUZT5VfdAZc5HsNxJxp 2vPWT/2TZ4lkhp7RwehWDyFQ2uN1C3lbvnxXU0yU8S6gElzxmRybvXisG alk7G4fGmi6CGBSw2tzw0g6jq6Wp//0fCsn2tRm43y/wLvLHxk36LpGYg 2bdcf5fuOL2jt3z3qE01Bl6q83+qwzFrs2PBoj8+roeRmcBVVfx8pFzKa g==; X-CSE-ConnectionGUID: wLwI4XH1QvCZ6sqaVZVM4g== X-CSE-MsgGUID: 4gNHWHTjRDq1FZgB3NVB8w== X-IronPort-AV: E=McAfee;i="6700,10204,11361"; a="59382063" X-IronPort-AV: E=Sophos;i="6.13,328,1732608000"; d="scan'208";a="59382063" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2025 20:47:53 -0800 X-CSE-ConnectionGUID: LV0DQmYNS2Ojkd5xSbeRfg== X-CSE-MsgGUID: lF+6nGHiRvKdDB8CtzN1Tg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="123123942" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by orviesa005.jf.intel.com with ESMTP; 02 Mar 2025 20:47:51 -0800 From: Raag Jadav To: lee@kernel.org, giometti@enneenne.com, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, raymond.tan@intel.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Raag Jadav Subject: [PATCH v2 2/5] gpio: elkhartlake: depend on MFD_INTEL_EHL_PSE_GPIO Date: Mon, 3 Mar 2025 10:17:42 +0530 Message-Id: <20250303044745.268964-3-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250303044745.268964-1-raag.jadav@intel.com> References: <20250303044745.268964-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Now that we have Intel MFD driver for PSE GPIO, depend on it. Signed-off-by: Raag Jadav --- drivers/gpio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 98b4d1633b25..b2efd2533630 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1372,7 +1372,7 @@ config HTC_EGPIO config GPIO_ELKHARTLAKE tristate "Intel Elkhart Lake PSE GPIO support" - depends on X86 || COMPILE_TEST + depends on (X86 && MFD_INTEL_EHL_PSE_GPIO) || COMPILE_TEST select GPIO_TANGIER help Select this option to enable GPIO support for Intel Elkhart Lake From patchwork Mon Mar 3 04:47:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 870272 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48CB91E3DEB; Mon, 3 Mar 2025 04:47:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740977277; cv=none; b=Q9IXwRdCCk67nxOrNKLJFnn12+dUSvuhO9XzZTNoxoCuWD/PNhFV2bWuuNTHyn7VG3iFU9sh44oQtJXHk4xcW9SIHPTPvvykiEPTAl4FLdoabw+dx1SM0RAtAPQihrJUzAXMJvOZiNXQFYWc/MJjv7AjeSZX9cjwckqKzWXtc8c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740977277; c=relaxed/simple; bh=ly2+UQPrNEC+dhK+lw2hYNlNtYQJW3WWubbEtSJyOss=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JRAI86lStzIArwem3tcOV5MPiug7oXOkNkCMCUjHeTNQF3VjYwDGt0hbTSRkKJTr+gjr8TLxEEgsx36en9h8PCwlyGhcL7Mp2BZKf7fN7AL/6Ro+Aqavwfm+irtX18PFJEaPRFiRLr6XB7IOj67XKd2tM/jqxlDnBed/F7z5dlw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RZDugyf3; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RZDugyf3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740977276; x=1772513276; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ly2+UQPrNEC+dhK+lw2hYNlNtYQJW3WWubbEtSJyOss=; b=RZDugyf30aSTLmc562d3JfrZ1Pi6UoXnfpTuKWbV3zgPJoSC2t3aOih2 rGP6iHNX6tqJiJM+XGSfWtA+uNjJtgfmhTl78HH8EYbqzoVf/HV1MVST1 l7EMkKhNomh+YQAYnI5zk8wiQsSUD26H6hwKxRnbUsMzkByvj+kPv3F47 S+wD48Ua/7tmAYXrYs9MC8sWdnkbPMHjvzwK0bvrMzPRO+rgCI77CGN48 mAmf5KZU2XCPMqK6XfMVV9RA3CkrykUYElYFVb1lpHep7k0TSaCB/mebG VeOAiKX8E6tpACF+NhrtrYrfe9SJK0tI0p3/h83DJ+CrM6fRI+UMLQvxU A==; X-CSE-ConnectionGUID: JKk+AvgpQfmtMP6GGbDeRA== X-CSE-MsgGUID: XRdcpV2QTO+Eng9MAQPPqw== X-IronPort-AV: E=McAfee;i="6700,10204,11361"; a="59382074" X-IronPort-AV: E=Sophos;i="6.13,328,1732608000"; d="scan'208";a="59382074" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2025 20:47:56 -0800 X-CSE-ConnectionGUID: P80XCKM+TiSSq6RM87gFHg== X-CSE-MsgGUID: Y3je1SV1RSmL/0ns1gIf8Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="123123957" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by orviesa005.jf.intel.com with ESMTP; 02 Mar 2025 20:47:53 -0800 From: Raag Jadav To: lee@kernel.org, giometti@enneenne.com, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, raymond.tan@intel.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Raag Jadav Subject: [PATCH v2 3/5] pps: generators: tio: split pps_gen_tio.h Date: Mon, 3 Mar 2025 10:17:43 +0530 Message-Id: <20250303044745.268964-4-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250303044745.268964-1-raag.jadav@intel.com> References: <20250303044745.268964-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Split macros and structure definition to header file for better maintainability. Signed-off-by: Raag Jadav Acked-by: Rodolfo Giometti Reviewed-by: Andy Shevchenko --- drivers/pps/generators/pps_gen_tio.c | 30 +---------------- drivers/pps/generators/pps_gen_tio.h | 49 ++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 29 deletions(-) create mode 100644 drivers/pps/generators/pps_gen_tio.h diff --git a/drivers/pps/generators/pps_gen_tio.c b/drivers/pps/generators/pps_gen_tio.c index 6c46b46c66cd..7f2aab1219af 100644 --- a/drivers/pps/generators/pps_gen_tio.c +++ b/drivers/pps/generators/pps_gen_tio.c @@ -5,8 +5,6 @@ * Copyright (C) 2024 Intel Corporation */ -#include -#include #include #include #include @@ -21,33 +19,7 @@ #include -#define TIOCTL 0x00 -#define TIOCOMPV 0x10 -#define TIOEC 0x30 - -/* Control Register */ -#define TIOCTL_EN BIT(0) -#define TIOCTL_DIR BIT(1) -#define TIOCTL_EP GENMASK(3, 2) -#define TIOCTL_EP_RISING_EDGE FIELD_PREP(TIOCTL_EP, 0) -#define TIOCTL_EP_FALLING_EDGE FIELD_PREP(TIOCTL_EP, 1) -#define TIOCTL_EP_TOGGLE_EDGE FIELD_PREP(TIOCTL_EP, 2) - -/* Safety time to set hrtimer early */ -#define SAFE_TIME_NS (10 * NSEC_PER_MSEC) - -#define MAGIC_CONST (NSEC_PER_SEC - SAFE_TIME_NS) -#define ART_HW_DELAY_CYCLES 2 - -struct pps_tio { - struct pps_gen_source_info gen_info; - struct pps_gen_device *pps_gen; - struct hrtimer timer; - void __iomem *base; - u32 prev_count; - spinlock_t lock; - struct device *dev; -}; +#include "pps_gen_tio.h" static inline u32 pps_tio_read(u32 offset, struct pps_tio *tio) { diff --git a/drivers/pps/generators/pps_gen_tio.h b/drivers/pps/generators/pps_gen_tio.h new file mode 100644 index 000000000000..5033d5efdf92 --- /dev/null +++ b/drivers/pps/generators/pps_gen_tio.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel PPS signal Generator Driver + * + * Copyright (C) 2025 Intel Corporation + */ + +#ifndef _PPS_GEN_TIO_H_ +#define _PPS_GEN_TIO_H_ + +#include +#include +#include +#include +#include +#include +#include + +struct device; + +#define TIOCTL 0x00 +#define TIOCOMPV 0x10 +#define TIOEC 0x30 + +/* Control Register */ +#define TIOCTL_EN BIT(0) +#define TIOCTL_DIR BIT(1) +#define TIOCTL_EP GENMASK(3, 2) +#define TIOCTL_EP_RISING_EDGE FIELD_PREP(TIOCTL_EP, 0) +#define TIOCTL_EP_FALLING_EDGE FIELD_PREP(TIOCTL_EP, 1) +#define TIOCTL_EP_TOGGLE_EDGE FIELD_PREP(TIOCTL_EP, 2) + +/* Safety time to set hrtimer early */ +#define SAFE_TIME_NS (10 * NSEC_PER_MSEC) + +#define MAGIC_CONST (NSEC_PER_SEC - SAFE_TIME_NS) +#define ART_HW_DELAY_CYCLES 2 + +struct pps_tio { + struct pps_gen_source_info gen_info; + struct pps_gen_device *pps_gen; + struct hrtimer timer; + void __iomem *base; + u32 prev_count; + spinlock_t lock; + struct device *dev; +}; + +#endif /* _PPS_GEN_TIO_H_ */ From patchwork Mon Mar 3 04:47:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 869940 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 040751E5706; Mon, 3 Mar 2025 04:47:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740977280; cv=none; b=LqxHNwJE2d7f6Umi2ALP0uBsd/X1GzOpi4MOjkuVUnG2j7/kVZt9aXzmm/NaGMspLB2zFKC98/YjN/BZmfxYOuqtVRUB0wkK7KwYAjOspgkzUwckkCQP6BKKNICzWScpt7iSiUxpk7MsZUWGSzb1cHHV3zUN6C5LGbZcLfQZ5O0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740977280; c=relaxed/simple; bh=hFUryWsDI/x1+UyJwD1J1wtnUu6+KwV5oMs/3+d9nec=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uPTtWMdBK7QDRPRJomCVIF4+HjTWlrixgsGDg4gLbzXpy5tQWgyP41iC/TBTNU+9AJAg9VlnrgYGILTZyMHb192Zsj17VkpzXE4Ztwe1FdkDjqMutk5drF3mYUKetHLU+xMmk9zXDYG3iXOCZ6Op9bXDEW2I2uNR9wTxozLznzU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=BQcPQTy7; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="BQcPQTy7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740977279; x=1772513279; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hFUryWsDI/x1+UyJwD1J1wtnUu6+KwV5oMs/3+d9nec=; b=BQcPQTy7wnO9tgNVd0ZLMQlvHabn5T8DJLuLcvfW4JLwUMQ4Co5FI2Fd iFwDK+NtaXTrHoxGbRQj/BRGl91ok4ZzukqezYAUYP+1ao7E0XiL4O74h l6PaRbzH8ggIHWveA6UsN7XL17eGhdCbuMrovGuE0LLXejt9/1pZXwAQN wvQYg/jSlcJR6P4lMvDWD+2x5EIk+8WJK8azFHmhcDkJiim9dwurU/W5E Li1LmcbtV/OyLc6+tjJRZHF7gC+tarIeh7sjadyQnqUvfk8nlDjk3IjOf 60IT+nslbznya2ObN1x6Hdk+nJQBPFR6cBk3kSJpyCu26LqvbCRwFfAf2 Q==; X-CSE-ConnectionGUID: /QrkII0wQTqJekX2LmRjAw== X-CSE-MsgGUID: 94/fSLAwTLubO0Yfbpga7Q== X-IronPort-AV: E=McAfee;i="6700,10204,11361"; a="59382085" X-IronPort-AV: E=Sophos;i="6.13,328,1732608000"; d="scan'208";a="59382085" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2025 20:47:58 -0800 X-CSE-ConnectionGUID: qD23Thi5Ram65Z9cuXRtWw== X-CSE-MsgGUID: UlEJPod2TwyXiIBMmFrWBg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="123123964" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by orviesa005.jf.intel.com with ESMTP; 02 Mar 2025 20:47:56 -0800 From: Raag Jadav To: lee@kernel.org, giometti@enneenne.com, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, raymond.tan@intel.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Raag Jadav Subject: [PATCH v2 4/5] pps: generators: tio: move to match_data() model Date: Mon, 3 Mar 2025 10:17:44 +0530 Message-Id: <20250303044745.268964-5-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250303044745.268964-1-raag.jadav@intel.com> References: <20250303044745.268964-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use device_get_match_data() which allows configuring platform specific data like number of pins and MMIO registers for TIO. Signed-off-by: Raag Jadav Acked-by: Rodolfo Giometti Reviewed-by: Andy Shevchenko --- drivers/pps/generators/pps_gen_tio.c | 33 ++++++++++++++++++++-------- drivers/pps/generators/pps_gen_tio.h | 19 +++++++++++++--- 2 files changed, 40 insertions(+), 12 deletions(-) diff --git a/drivers/pps/generators/pps_gen_tio.c b/drivers/pps/generators/pps_gen_tio.c index 7f2aab1219af..6e3a4b198259 100644 --- a/drivers/pps/generators/pps_gen_tio.c +++ b/drivers/pps/generators/pps_gen_tio.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -28,7 +29,7 @@ static inline u32 pps_tio_read(u32 offset, struct pps_tio *tio) static inline void pps_ctl_write(u32 value, struct pps_tio *tio) { - writel(value, tio->base + TIOCTL); + writel(value, tio->base + tio->regs.ctl); } /* @@ -37,7 +38,7 @@ static inline void pps_ctl_write(u32 value, struct pps_tio *tio) */ static inline void pps_compv_write(u64 value, struct pps_tio *tio) { - hi_lo_writeq(value, tio->base + TIOCOMPV); + hi_lo_writeq(value, tio->base + tio->regs.compv); } static inline ktime_t first_event(struct pps_tio *tio) @@ -49,7 +50,7 @@ static u32 pps_tio_disable(struct pps_tio *tio) { u32 ctrl; - ctrl = pps_tio_read(TIOCTL, tio); + ctrl = pps_tio_read(tio->regs.ctl, tio); pps_compv_write(0, tio); ctrl &= ~TIOCTL_EN; @@ -63,7 +64,7 @@ static void pps_tio_enable(struct pps_tio *tio) { u32 ctrl; - ctrl = pps_tio_read(TIOCTL, tio); + ctrl = pps_tio_read(tio->regs.ctl, tio); ctrl |= TIOCTL_EN; pps_ctl_write(ctrl, tio); tio->pps_gen->enabled = true; @@ -112,7 +113,7 @@ static enum hrtimer_restart hrtimer_callback(struct hrtimer *timer) * Check if any event is missed. * If an event is missed, TIO will be disabled. */ - event_count = pps_tio_read(TIOEC, tio); + event_count = pps_tio_read(tio->regs.ec, tio); if (tio->prev_count && tio->prev_count == event_count) goto err; tio->prev_count = event_count; @@ -172,6 +173,7 @@ static int pps_tio_get_time(struct pps_gen_device *pps_gen, static int pps_gen_tio_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + const struct pps_tio_data *data; struct pps_tio *tio; if (!(cpu_feature_enabled(X86_FEATURE_TSC_KNOWN_FREQ) && @@ -184,6 +186,11 @@ static int pps_gen_tio_probe(struct platform_device *pdev) if (!tio) return -ENOMEM; + data = device_get_match_data(dev); + if (!data) + return -ENODEV; + + tio->regs = data->regs; tio->gen_info.use_system_clock = true; tio->gen_info.enable = pps_tio_gen_enable; tio->gen_info.get_time = pps_tio_get_time; @@ -216,11 +223,19 @@ static void pps_gen_tio_remove(struct platform_device *pdev) pps_gen_unregister_source(tio->pps_gen); } +static const struct pps_tio_data pmc_data = { + .regs = { + .ctl = TIOCTL_PMC, + .compv = TIOCOMPV_PMC, + .ec = TIOEC_PMC, + }, +}; + static const struct acpi_device_id intel_pmc_tio_acpi_match[] = { - { "INTC1021" }, - { "INTC1022" }, - { "INTC1023" }, - { "INTC1024" }, + { "INTC1021", (kernel_ulong_t)&pmc_data }, + { "INTC1022", (kernel_ulong_t)&pmc_data }, + { "INTC1023", (kernel_ulong_t)&pmc_data }, + { "INTC1024", (kernel_ulong_t)&pmc_data }, {} }; MODULE_DEVICE_TABLE(acpi, intel_pmc_tio_acpi_match); diff --git a/drivers/pps/generators/pps_gen_tio.h b/drivers/pps/generators/pps_gen_tio.h index 5033d5efdf92..4329b6dbd598 100644 --- a/drivers/pps/generators/pps_gen_tio.h +++ b/drivers/pps/generators/pps_gen_tio.h @@ -18,9 +18,10 @@ struct device; -#define TIOCTL 0x00 -#define TIOCOMPV 0x10 -#define TIOEC 0x30 +/* PMC Registers */ +#define TIOCTL_PMC 0x00 +#define TIOCOMPV_PMC 0x10 +#define TIOEC_PMC 0x30 /* Control Register */ #define TIOCTL_EN BIT(0) @@ -36,9 +37,21 @@ struct device; #define MAGIC_CONST (NSEC_PER_SEC - SAFE_TIME_NS) #define ART_HW_DELAY_CYCLES 2 +struct pps_tio_regs { + u32 ctl; + u32 compv; + u32 ec; +}; + +struct pps_tio_data { + struct pps_tio_regs regs; + u32 num_pins; +}; + struct pps_tio { struct pps_gen_source_info gen_info; struct pps_gen_device *pps_gen; + struct pps_tio_regs regs; struct hrtimer timer; void __iomem *base; u32 prev_count; From patchwork Mon Mar 3 04:47:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 870271 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C92541E5714; Mon, 3 Mar 2025 04:48:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740977283; cv=none; b=qZDouUakLpjL+UM71i4JD+GQtS5qooY50emPzID5TRFrFeUlfoJ5Dke1ledn2cGijDXiNqh+ORrI/QsPgruEua1qJXV/PS5eLITVUqp+LwjOlWUxQDBFM/DVF2MVVgwywBMup3aLMf1pzO8rUwUUrMmcv5U6euL9f9+ywzzmJMY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740977283; c=relaxed/simple; bh=yRACNcqql97q+efeIS5QfsCUY4jQh++OfyCum2WBK0A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Xjp/EU3cMviRNsC2l0iKUigjWvYhsJ/l8cozFmGxU1r6HNZh2eRmB7qH7S8xWcBjgyN1kRKTFFufCphhumgSL099YLzzfopCHXpZ4YQ0E+OHv6Nd44gFb7mb8CUxzHNlgKuQvHfEAPbSo1eU+UFiRChBbaXbyGOkpTuRYMgZlH4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EbOTC9QV; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EbOTC9QV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740977281; x=1772513281; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yRACNcqql97q+efeIS5QfsCUY4jQh++OfyCum2WBK0A=; b=EbOTC9QVfp3FyfmeOf3PqOd8OghrWD6jM2/+m2L3kL7qPcNKsu8L8xXH ZvCYKG99vluz2ueQjeu/iflZ0TFmtLdgQpMbx3h/YIKE8HEoSV4lXK38B CKxrp904GlKqyrAXaNk1FDrw+z4mv0SZWTkXaMp4XbaA3dLVErzKWywOx PVCgJmGNhbZ9MLTl/mng9Tc5JHd+mluULhbY/T/L5CvSGQwmI+hIeApi+ VXefMGDGRuHry9sK58Q9CVW7W9sGgHntMhlI9Loq5oQgjaS0MMBFi77hO 5DOW4TJGhLhrKn138n5tS15LeS3rWYj/xAxX1PZbdx0jatMKMf/a1x/xe g==; X-CSE-ConnectionGUID: WJCQsNdoR12bpFPFP7Yg9w== X-CSE-MsgGUID: 2BCNiu2QT1m4D5BQSBsYPg== X-IronPort-AV: E=McAfee;i="6700,10204,11361"; a="59382092" X-IronPort-AV: E=Sophos;i="6.13,328,1732608000"; d="scan'208";a="59382092" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2025 20:48:01 -0800 X-CSE-ConnectionGUID: zHKP/mAXRAO72IJRguYZDg== X-CSE-MsgGUID: C+lMtO/6S8CkGHObHw5qwQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="123123972" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by orviesa005.jf.intel.com with ESMTP; 02 Mar 2025 20:47:59 -0800 From: Raag Jadav To: lee@kernel.org, giometti@enneenne.com, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, raymond.tan@intel.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Raag Jadav Subject: [PATCH v2 5/5] pps: generators: tio: Introduce Intel Elkhart Lake PSE TIO Date: Mon, 3 Mar 2025 10:17:45 +0530 Message-Id: <20250303044745.268964-6-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250303044745.268964-1-raag.jadav@intel.com> References: <20250303044745.268964-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add initial support for Intel Elkhart Lake PSE TIO controller. Signed-off-by: Raag Jadav Acked-by: Rodolfo Giometti Reviewed-by: Andy Shevchenko --- drivers/pps/generators/Kconfig | 2 +- drivers/pps/generators/pps_gen_tio.c | 17 ++++++++++++++++- drivers/pps/generators/pps_gen_tio.h | 5 +++++ 3 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/pps/generators/Kconfig b/drivers/pps/generators/Kconfig index b3f340ed3163..83aada693ad2 100644 --- a/drivers/pps/generators/Kconfig +++ b/drivers/pps/generators/Kconfig @@ -33,7 +33,7 @@ config PPS_GENERATOR_PARPORT config PPS_GENERATOR_TIO tristate "TIO PPS signal generator" - depends on X86 && CPU_SUP_INTEL + depends on X86 && CPU_SUP_INTEL && MFD_INTEL_EHL_PSE_GPIO help If you say yes here you get support for a PPS TIO signal generator which generates a pulse at a prescribed time based on the system clock. diff --git a/drivers/pps/generators/pps_gen_tio.c b/drivers/pps/generators/pps_gen_tio.c index 6e3a4b198259..a2a23cdc2568 100644 --- a/drivers/pps/generators/pps_gen_tio.c +++ b/drivers/pps/generators/pps_gen_tio.c @@ -231,6 +231,14 @@ static const struct pps_tio_data pmc_data = { }, }; +static const struct pps_tio_data ehl_pse_data = { + .regs = { + .ctl = TIOCTL_PSE, + .compv = TIOCOMPV_PSE, + .ec = TIOEC_PSE, + }, +}; + static const struct acpi_device_id intel_pmc_tio_acpi_match[] = { { "INTC1021", (kernel_ulong_t)&pmc_data }, { "INTC1022", (kernel_ulong_t)&pmc_data }, @@ -240,9 +248,16 @@ static const struct acpi_device_id intel_pmc_tio_acpi_match[] = { }; MODULE_DEVICE_TABLE(acpi, intel_pmc_tio_acpi_match); +static const struct platform_device_id pps_gen_tio_ids[] = { + { "pps-gen-tio", (kernel_ulong_t)&ehl_pse_data }, + { } +}; +MODULE_DEVICE_TABLE(platform, pps_gen_tio_ids); + static struct platform_driver pps_gen_tio_driver = { .probe = pps_gen_tio_probe, .remove = pps_gen_tio_remove, + .id_table = pps_gen_tio_ids, .driver = { .name = "intel-pps-gen-tio", .acpi_match_table = intel_pmc_tio_acpi_match, @@ -255,5 +270,5 @@ MODULE_AUTHOR("Lakshmi Sowjanya D "); MODULE_AUTHOR("Pandith N "); MODULE_AUTHOR("Thejesh Reddy T R "); MODULE_AUTHOR("Subramanian Mohan "); -MODULE_DESCRIPTION("Intel PMC Time-Aware IO Generator Driver"); +MODULE_DESCRIPTION("Intel Time-Aware IO Generator Driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/pps/generators/pps_gen_tio.h b/drivers/pps/generators/pps_gen_tio.h index 4329b6dbd598..509bd2633dfb 100644 --- a/drivers/pps/generators/pps_gen_tio.h +++ b/drivers/pps/generators/pps_gen_tio.h @@ -18,6 +18,11 @@ struct device; +/* EHL PSE Registers */ +#define TIOCTL_PSE 0x00 +#define TIOCOMPV_PSE 0x04 +#define TIOEC_PSE 0x24 + /* PMC Registers */ #define TIOCTL_PMC 0x00 #define TIOCOMPV_PMC 0x10