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Wed, 05 Mar 2025 11:05:27 -0800 (PST) From: Neil Armstrong Date: Wed, 05 Mar 2025 20:05:19 +0100 Subject: [PATCH v2 1/7] dt-bindings: media: qcom,sm8550-iris: document SM8650 IRIS accelerator Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250305-topic-sm8x50-iris-v10-v2-1-bd65a3fc099e@linaro.org> References: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> In-Reply-To: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1966; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=rZobr5wcTlhEiVAtYQB5i/HT1qKxwHEGG9fjtMu74sg=; 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Reviewed-by: Rob Herring (Arm) Signed-off-by: Neil Armstrong --- .../bindings/media/qcom,sm8550-iris.yaml | 33 ++++++++++++++++++---- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml index e424ea84c211f473a799481fd5463a16580187ed..536cf458dcb08141e5a1ec8c3df964196e599a57 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml @@ -14,12 +14,11 @@ description: The iris video processing unit is a video encode and decode accelerator present on Qualcomm platforms. -allOf: - - $ref: qcom,venus-common.yaml# - properties: compatible: - const: qcom,sm8550-iris + enum: + - qcom,sm8550-iris + - qcom,sm8650-iris power-domains: maxItems: 4 @@ -49,11 +48,15 @@ properties: - const: video-mem resets: - maxItems: 1 + minItems: 1 + maxItems: 3 reset-names: + minItems: 1 items: - const: bus + - const: xo + - const: core iommus: maxItems: 2 @@ -75,6 +78,26 @@ required: - iommus - dma-coherent +allOf: + - $ref: qcom,venus-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm8650-iris + then: + properties: + resets: + minItems: 3 + reset-names: + minItems: 3 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 + unevaluatedProperties: false examples: From patchwork Wed Mar 5 19:05:21 2025 Content-Type: text/plain; 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Wed, 05 Mar 2025 11:05:29 -0800 (PST) From: Neil Armstrong Date: Wed, 05 Mar 2025 20:05:21 +0100 Subject: [PATCH v2 3/7] media: platform: qcom/iris: add power_off_controller to vpu_ops Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250305-topic-sm8x50-iris-v10-v2-3-bd65a3fc099e@linaro.org> References: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> In-Reply-To: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4579; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=0NeaNRcSK7UDoUfhdeNVtRUD9cUv0qEzjzihXO0mJMs=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnyKB0ioFERG5p8hkTpF4LR4U4q4zIzMg4nHr0lS+m qlav25eJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ8igdAAKCRB33NvayMhJ0Xf2D/ 4stwZ91WXybax6cmCvoEr1csv9LMhjo+wdMjJ430DaUkhkufJGnUiLqKEu2iQ8NV7Pn+4V1Lu8KoXo KrOi3Zq95vpojWYRv655+uhyc9OnSHj3tSzJv/w+TWDsbq/gPKXBJFFkrB69pzEho/9IODcyb2pDFs r5tQs0h+rjS/nqSw1tcgSw84S/GCdgg7rNXxFUI/Oiw31JzhVE7oQCRGryP2DK9uVsyJq/Q68ZLDcD WeC5iGrVeCJFzOliwSZL4YXLxslaS9J8Uc1KtMZMq4wbNsRrp3ESjKjrF9WL8HN8KU6fGfELjLVsrR RNoiMIkF2wWTjHCU9ULx16mg113l+yh5mZfZbiF8RlcsKrs76dMU6ibSpUuPk42ybTjyBVMKwMzy/x CKnd58DOw+x8DDGg/zoQ8Vv+232VYO7B/0da6J7ybxyRH+zhv7Sj8fuSEN2qAknJrUsuqJ6UnTvfDv qtVyg5nXx3jDL1GGFVayW2r1An4iN1r9cYxNPjcTDyFSDreMg7GajLwns/ntYcq3Idht2Q+O7IZlk1 vRiMqwsnDKGAcwItUOPoJHH4aJB58qINjAFx0p/2jpB0QT53+bk3NfTB2iq7/briSV0Pmv5lj3qpxb dcjheQlzRA94NYHokLrnQ8jPZS31zELUJyenra6bBDUPkWYQ6RRWPRbnc+Bg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE In order to support the SM8650 iris33 hardware, we need to provide a specific constoller power off sequences via the vpu_ops callbacks. Add the callback, and use the current helper for currently supported platforms. Signed-off-by: Neil Armstrong --- drivers/media/platform/qcom/iris/iris_vpu2.c | 1 + drivers/media/platform/qcom/iris/iris_vpu3.c | 2 ++ drivers/media/platform/qcom/iris/iris_vpu_common.c | 14 ++++++++++---- drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 ++ 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/platform/qcom/iris/iris_vpu2.c index 8f502aed43ce2fa6a272a2ce14ff1ca54d3e63a2..7cf1bfc352d34b897451061b5c14fbe90276433d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -34,5 +34,6 @@ static u64 iris_vpu2_calc_freq(struct iris_inst *inst, size_t data_size) const struct vpu_ops iris_vpu2_ops = { .power_off_hw = iris_vpu_power_off_hw, + .power_off_controller = iris_vpu_power_off_controller, .calc_freq = iris_vpu2_calc_freq, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu3.c b/drivers/media/platform/qcom/iris/iris_vpu3.c index b484638e6105a69319232f667ee7ae95e3853698..95f362633c95b101ecfda6480c4c0b73416bd00c 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3.c @@ -117,6 +117,8 @@ static u64 iris_vpu3_calculate_frequency(struct iris_inst *inst, size_t data_siz } const struct vpu_ops iris_vpu3_ops = { + .reset_controller = iris_vpu_reset_controller, .power_off_hw = iris_vpu3_power_off_hardware, + .power_off_controller = iris_vpu_power_off_controller, .calc_freq = iris_vpu3_calculate_frequency, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index d6ce92f3c7544e44dccca26bf6a4c95a720f9229..3b3e1ca1e42183561ee78c89f50946fd0cc3c3ab 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -251,7 +251,7 @@ static void iris_vpu_power_off_controller_disable(struct iris_core *core) iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); } -static int iris_vpu_power_off_controller(struct iris_core *core) +int iris_vpu_power_off_controller(struct iris_core *core) { u32 val = 0; int ret; @@ -284,23 +284,29 @@ void iris_vpu_power_off(struct iris_core *core) { dev_pm_opp_set_rate(core->dev, 0); core->iris_platform_data->vpu_ops->power_off_hw(core); - iris_vpu_power_off_controller(core); + core->iris_platform_data->vpu_ops->power_off_controller(core); iris_unset_icc_bw(core); if (!iris_vpu_watchdog(core, core->intr_status)) disable_irq_nosync(core->irq); } -static int iris_vpu_power_on_controller(struct iris_core *core) +static int iris_vpu_reset_controller(struct iris_core *core) { u32 rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size; + + return reset_control_bulk_reset(rst_tbl_size, core->resets); +} + +static int iris_vpu_power_on_controller(struct iris_core *core) +{ int ret; ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); if (ret) return ret; - ret = reset_control_bulk_reset(rst_tbl_size, core->resets); + ret = iris_vpu_reset_controller(core); if (ret) goto err_disable_power; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h index 63fa1fa5a4989e48aebdb6c7619c140000c0b44c..f8965661c602f990d5a7057565f79df4112d097e 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -13,6 +13,7 @@ extern const struct vpu_ops iris_vpu3_ops; struct vpu_ops { void (*power_off_hw)(struct iris_core *core); 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Wed, 05 Mar 2025 11:05:31 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-391241bd151sm2045218f8f.21.2025.03.05.11.05.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Mar 2025 11:05:31 -0800 (PST) From: Neil Armstrong Date: Wed, 05 Mar 2025 20:05:23 +0100 Subject: [PATCH v2 5/7] media: platform: qcom/iris: rename iris_vpu3 to iris_vpu3x Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250305-topic-sm8x50-iris-v10-v2-5-bd65a3fc099e@linaro.org> References: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> In-Reply-To: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The vpu33 HW is very close to vpu3, and shares most of the operations, so rename file to vpu3x since we'll handle all vpu3 variants in it. Signed-off-by: Neil Armstrong --- drivers/media/platform/qcom/iris/Makefile | 2 +- drivers/media/platform/qcom/iris/{iris_vpu3.c => iris_vpu3x.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile index 35390534534e93f4617c1036a05ca0921567ba1d..473aaf655448180ade917e642289677fc1277f99 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -20,7 +20,7 @@ qcom-iris-objs += \ iris_vb2.o \ iris_vdec.o \ iris_vpu2.o \ - iris_vpu3.o \ + iris_vpu3x.o \ iris_vpu_buffer.o \ iris_vpu_common.o \ diff --git a/drivers/media/platform/qcom/iris/iris_vpu3.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c similarity index 100% rename from drivers/media/platform/qcom/iris/iris_vpu3.c rename to drivers/media/platform/qcom/iris/iris_vpu3x.c From patchwork Wed Mar 5 19:05:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 870608 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2A822571AC for ; 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Wed, 05 Mar 2025 11:05:32 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-391241bd151sm2045218f8f.21.2025.03.05.11.05.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Mar 2025 11:05:32 -0800 (PST) From: Neil Armstrong Date: Wed, 05 Mar 2025 20:05:25 +0100 Subject: [PATCH v2 7/7] media: platform: qcom/iris: add sm8650 support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250305-topic-sm8x50-iris-v10-v2-7-bd65a3fc099e@linaro.org> References: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> In-Reply-To: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add support for the SM8650 platform by re-using the SM8550 definitions and using the vpu33 ops. The SM8650/vpu33 requires more reset lines, but the H.284 decoder capabilities are identical. Signed-off-by: Neil Armstrong --- .../platform/qcom/iris/iris_platform_common.h | 1 + .../platform/qcom/iris/iris_platform_sm8550.c | 64 ++++++++++++++++++++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 ++ 3 files changed, 69 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index fdd40fd80178c4c66b37e392d07a0a62f492f108..6bc3a7975b04d612f6c89206eae95dac678695fc 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -35,6 +35,7 @@ enum pipe_type { extern struct iris_platform_data sm8250_data; extern struct iris_platform_data sm8550_data; +extern struct iris_platform_data sm8650_data; enum platform_clk_type { IRIS_AXI_CLK, diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c b/drivers/media/platform/qcom/iris/iris_platform_sm8550.c index 35d278996c430f2856d0fe59586930061a271c3e..d0f8fa960d53367023e41bc5807ba3f8beae2efc 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.c @@ -144,6 +144,10 @@ static const struct icc_info sm8550_icc_table[] = { static const char * const sm8550_clk_reset_table[] = { "bus" }; +static const char * const sm8650_clk_reset_table[] = { "bus", "core" }; + +static const char * const sm8650_controller_reset_table[] = { "xo" }; + static const struct bw_info sm8550_bw_table_dec[] = { { ((4096 * 2160) / 256) * 60, 1608000 }, { ((4096 * 2160) / 256) * 30, 826000 }, @@ -264,3 +268,63 @@ struct iris_platform_data sm8550_data = { .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), }; + +/* + * Shares most of SM8550 data except: + * - vpu_ops to iris_vpu33_ops + * - clk_rst_tbl to sm8650_clk_reset_table + * - controller_rst_tbl to sm8650_controller_reset_table + * - fwname to "qcom/vpu/vpu33_p4.mbn" + */ +struct iris_platform_data sm8650_data = { + .get_instance = iris_hfi_gen2_get_instance, + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, + .vpu_ops = &iris_vpu33_ops, + .set_preset_registers = iris_set_sm8550_preset_registers, + .icc_tbl = sm8550_icc_table, + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl = sm8650_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(sm8650_clk_reset_table), + .controller_rst_tbl = sm8650_controller_reset_table, + .controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table), + .bw_tbl_dec = sm8550_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl = sm8550_pmdomain_table, + .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl = sm8550_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl = sm8550_clk_table, + .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .fwname = "qcom/vpu/vpu33_p4.mbn", + .pas_id = IRIS_PAS_ID, + .inst_caps = &platform_inst_cap_sm8550, + .inst_fw_caps = inst_fw_cap_sm8550, + .inst_fw_caps_size = ARRAY_SIZE(inst_fw_cap_sm8550), + .tz_cp_config_data = &tz_cp_config_sm8550, + .core_arch = VIDEO_ARCH_LX, + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, + .ubwc_config = &ubwc_config_sm8550, + .num_vpp_pipe = 4, + .max_session_count = 16, + .max_core_mbpf = ((8192 * 4352) / 256) * 2, + .input_config_params = + sm8550_vdec_input_config_params, + .input_config_params_size = + ARRAY_SIZE(sm8550_vdec_input_config_params), + .output_config_params = + sm8550_vdec_output_config_params, + .output_config_params_size = + ARRAY_SIZE(sm8550_vdec_output_config_params), + .dec_input_prop = sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), + .dec_output_prop = sm8550_vdec_subscribe_output_properties, + .dec_output_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_output_properties), + + .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), +}; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 4f8bce6e2002bffee4c93dcaaf6e52bf4e40992e..7cd8650fbe9c09598670530103e3d5edf32953e7 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -345,6 +345,10 @@ static const struct of_device_id iris_dt_match[] = { .data = &sm8250_data, }, #endif + { + .compatible = "qcom,sm8650-iris", + .data = &sm8650_data, + }, { }, }; MODULE_DEVICE_TABLE(of, iris_dt_match);