From patchwork Wed Mar 5 18:58:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 870737 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C906E255250; Wed, 5 Mar 2025 18:59:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741201169; cv=none; b=WK2AwAgDmxOipgpXC7qAkbKK+bWO7im+qclC1dQe/0DFvI7M4VhsG5yNwNy0kADaTdwYfUweLdoEHeZYXENCASwlQcY7+n/4MTFF8MIGKyAV20UazNhR+sI7M6ZkwfcIuR2fsVh5n82pkTnpfOJvSS8NMVAgQ+fg6f/4kgLk4Zg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741201169; c=relaxed/simple; bh=acUZEVmdOu80f/7L3NgXf/R3B0sCOGH3PeEgX6a2U2w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mGr5UJ0t1otYhlwpv4SiryTlfFyNp5zn94brxwZdoV+6ttk6vKwmfituq7uOUGSYgoxTjdfDB2lD+dE+uvKlZ9mTJg5aF0sOw02O+0NzG5X9qlUe/jdjQszrLz3Y/lattXeouYpkq08KvMCw/vLaOl7jctdTCTqRzsGSqwkaY/s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Abo9Xoco; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Abo9Xoco" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1741201166; bh=acUZEVmdOu80f/7L3NgXf/R3B0sCOGH3PeEgX6a2U2w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Abo9Xoco5BZ6WU42i2n8OHs+MacWHLzr5cWpH/Vj8lV7FobM5DrotgY3UG/QBPmhL pinANvay6rnmht2LOK3N+1p+D1/XHDbTUIJX8x/UVNWB6xZ2epK7GLkhBDn/4pKE1v yxTOWcCwjsUWKvnGJkRv6q2HiUtIY2gnVEfkkP7zhP4iFBVPKYoLhflODNnghG2CbZ nRqBW5z2eQvI3owf1W/sW9C9rQwM1QA1yrdZipgiC4t9cwUcUPLbSePr15liY7s59+ bUnz/L6hIntMre5JBbD2oF5HOE1Dm5iyoq6nZdZ0SsSTCsTQLZD7DSzraHEfpFzg+E D0tXnQe8ECUrw== Received: from [192.168.0.47] (unknown [IPv6:2804:14c:1a9:53ee::1004]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9AE5617E05E7; Wed, 5 Mar 2025 19:59:20 +0100 (CET) From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= Date: Wed, 05 Mar 2025 15:58:16 -0300 Subject: [PATCH v4 01/19] dt-bindings: mfd: mediatek: mt6397: Add accdet subnode Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250305-mt6359-accdet-dts-v4-1-e5ffa5ee9991@collabora.com> References: <20250305-mt6359-accdet-dts-v4-0-e5ffa5ee9991@collabora.com> In-Reply-To: <20250305-mt6359-accdet-dts-v4-0-e5ffa5ee9991@collabora.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Jaroslav Kysela , Takashi Iwai , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Mailer: b4 0.14.2 Describe the accessory detection (accdet) module as a possible subnode of the MT6359 PMIC. Signed-off-by: Nícolas F. R. A. Prado --- .../devicetree/bindings/mfd/mediatek,mt6397.yaml | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml index 6a89b479d10fad3c8b61cab5a3af1453baca4d1a..51012b8bbfaef3df7bdb619a4f8d828d6f9cc15a 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml @@ -24,6 +24,7 @@ description: | - LED - Keys - Power controller + - Accessory Detection It is interfaced to host controller using SPI interface by a proprietary hardware called PMIC wrapper or pwrap. MT6397/MT6323 PMIC is a child device of pwrap. @@ -224,6 +225,30 @@ properties: description: Pin controller + accdet: + type: object + additionalProperties: false + description: + The Accessory Detection module found on the PMIC allows detecting audio + jack insertion and removal, as well as identifying the type of events + connected to the jack. + + properties: + compatible: + const: mediatek,mt6359-accdet + + mediatek,hp-eint-high: + type: boolean + description: + By default, MT6359's HP_EINT pin is assumed to be pulled high and + connected to a normally open 3.5mm jack. Plug insertion is detected + when the pin is brought low in that case. Add this property if the + behavior should be inverted, for example if a normally closed 3.5mm + jack is used, or if the line is pulled low on open. + + required: + - compatible + required: - compatible - regulators @@ -598,3 +623,29 @@ examples: compatible = "mediatek,mt6397-rtc"; }; }; + - | + #include + #include + + pmic { + compatible = "mediatek,mt6359"; + interrupt-controller; + #interrupt-cells = <2>; + + accdet { + compatible = "mediatek,mt6359-accdet"; + mediatek,hp-eint-high; + }; + + regulators { + compatible = "mediatek,mt6359-regulator"; + + buck_vs1 { + regulator-name = "vs1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2200000>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + }; + }; From patchwork Wed Mar 5 18:58:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 870736 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4C54253329; Wed, 5 Mar 2025 18:59:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741201182; cv=none; b=sF7P6JdRUiyEmbrqYaQ+G/oEfiUj5rXd0Zq/Hm5IuSHbLUgXUVD3mKBO9uJpATG7y5x12pEQYgt5Y+pKtE5GOVlR2Cr1GfSB8Xk8XG7UWWw/vQMQbd7Rn0/nN34aAJar3aVQXWrHvxcIRfVIk2lcbRWIh/k5h1aIR37VVVoEjNs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741201182; c=relaxed/simple; bh=7unty8UXqbw+pOftMZfZMEYJgXbtayExa3QUkhZmST8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EBFf6LvZKp9y7e5DCzo2nqTFQkbNDCVBIJEr2fu/cmGtLMAvb79YDK7kwpWvShvQ3S+9mc/OZ5pcmOs+M8vz9PK6VHyp19ivXIpty+wSbr52vwbELdZNfpPwdsKxg4RNUnlIaMSpbF50FYVLi2DewQLLnweXJeNRl6yzq6kI27Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Gnu5ek0j; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Gnu5ek0j" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1741201178; bh=7unty8UXqbw+pOftMZfZMEYJgXbtayExa3QUkhZmST8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Gnu5ek0jDhwqQz4n+vs9wTNjmYg3IM26mbEuFo3m8l3nRPaKX3AeZAusjqQG7tDkJ /9a7OEOXimGE8mCBRt3fxArsWloBx2pw7JG+q/+XGgKI0z65Ef0XHaIgx6BNwcTJiw Zo2xlj0MQJyA+DiMhwD1LvFKIRB8kf8i+OrLardIGzieceOgdLlAvcN8mMuuGRwXgw TERFcB7rOjy02xiw29kjFORyyl+Y4GQjjYKvhmDSqp7omzk+U/Vo1ohDzL12BGCo9q Ow15ERJ9oSpeoXQmnt5RcjcsTRP7LfEiI47JwVnAZ7YplsvZmOnQtW0rIa2Fin2ej2 ZLhKHkV74hg4g== Received: from [192.168.0.47] (unknown [IPv6:2804:14c:1a9:53ee::1004]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4C0E617E05E7; Wed, 5 Mar 2025 19:59:32 +0100 (CET) From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= Date: Wed, 05 Mar 2025 15:58:18 -0300 Subject: [PATCH v4 03/19] ASoC: mediatek: mt6359-accdet: Add compatible property Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250305-mt6359-accdet-dts-v4-3-e5ffa5ee9991@collabora.com> References: <20250305-mt6359-accdet-dts-v4-0-e5ffa5ee9991@collabora.com> In-Reply-To: <20250305-mt6359-accdet-dts-v4-0-e5ffa5ee9991@collabora.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Jaroslav Kysela , Takashi Iwai , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Andrew Perepech X-Mailer: b4 0.14.2 Add a compatible property and add it to the module device table for the mt6359-accdet platform driver to allow automatic module loading and probing when the compatible is present in DT. Co-developed-by: Andrew Perepech Signed-off-by: Andrew Perepech Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nícolas F. R. A. Prado --- sound/soc/codecs/mt6359-accdet.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/sound/soc/codecs/mt6359-accdet.c b/sound/soc/codecs/mt6359-accdet.c index ed34cc15b80e856356c07fd53af22207124e0d19..9bbd4497e8d481ee125693be2fc576b439574b39 100644 --- a/sound/soc/codecs/mt6359-accdet.c +++ b/sound/soc/codecs/mt6359-accdet.c @@ -1047,9 +1047,16 @@ static int mt6359_accdet_probe(struct platform_device *pdev) return ret; } +const struct of_device_id accdet_of_match[] = { + { .compatible = "mediatek,mt6359-accdet", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, accdet_of_match); + static struct platform_driver mt6359_accdet_driver = { .driver = { .name = "pmic-codec-accdet", + .of_match_table = accdet_of_match, }, .probe = mt6359_accdet_probe, }; From patchwork Wed Mar 5 18:58:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 870735 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB6D62580C8; Wed, 5 Mar 2025 18:59:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741201192; cv=none; b=RXfukYa3F5w0yzWxd5MTaPOILxHNsYKKc7Utnt6ji+MCUwbBA3uRmf73liBODS3KdBMpJzPi06DjI1iXkjyoF5ZpFr/DuLa/Vd0oi4p/a+qmJKsgV2/tv9k4I90vizYoPGpZFgtwokA1llVTNFlNmnqanaCrvRVk125fmmQHlx0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741201192; c=relaxed/simple; bh=oENbZq9wxTXMu0zGgWXBpMvdBFjW1P8NsiaK44heerA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aTafld018ZytCKSNuAyb81vytZgo7f2/EXmZCt1OtJMrW0vBq95EtrLOm09KMc/7LWjc+MlL1sev8VlRRO81pXNInmD3lOIKwqg4Q7aWiOMyZfQD1Ivyyxh3o4QepVpmf10fX9a5g1JrLjcyZdMcYXgmCQFhXzMWuMl5Qt74s/w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=AdLBpMEW; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="AdLBpMEW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1741201189; bh=oENbZq9wxTXMu0zGgWXBpMvdBFjW1P8NsiaK44heerA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=AdLBpMEWWs1CWBuswRd67tsyOyvWg5NHhTBhApz8Hkdp3knGYg/ATT+lvO7r2TXwK r/efCet+eFfeG0k2slA6aAjm+ZLWv+qywI65WTVwVuhB+Z73rFZf4XyMEGxTHeOuGh iLB88PWR8zCyneg9c3HjbIpI2nfQ/u+dPaVMp8RJVrOkrcKP4nnMYjzDAl0OWdE0+W iVpm6qTLvieVuHmJJwF5nOJjWb7pH/kc+1eNKkV5z2vknpUZJL2oB9lwIqUaTC5N99 yVQREWBj4gN9qi9tnLYouYTYqPUdH8ozbsWz9WRm+DSaToCO7+8I9pTLzgR7Gt2j0W hsRCsNNXi5ldg== Received: from [192.168.0.47] (unknown [IPv6:2804:14c:1a9:53ee::1004]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 2E3A217E017D; Wed, 5 Mar 2025 19:59:43 +0100 (CET) From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= Date: Wed, 05 Mar 2025 15:58:20 -0300 Subject: [PATCH v4 05/19] ASoC: mediatek: mt6359-accdet: Implement HP_EINT polarity configuration Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250305-mt6359-accdet-dts-v4-5-e5ffa5ee9991@collabora.com> References: <20250305-mt6359-accdet-dts-v4-0-e5ffa5ee9991@collabora.com> In-Reply-To: <20250305-mt6359-accdet-dts-v4-0-e5ffa5ee9991@collabora.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Jaroslav Kysela , Takashi Iwai , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Andrew Perepech X-Mailer: b4 0.14.2 From: Andrew Perepech The driver currently reads the HP_EINT polarity from the Devicetree but never actually configures the hardware accordingly. Implement the polarity configuration in hardware. Signed-off-by: Andrew Perepech Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nícolas F. R. A. Prado --- sound/soc/codecs/mt6359-accdet.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/sound/soc/codecs/mt6359-accdet.c b/sound/soc/codecs/mt6359-accdet.c index ca3be59d2d0ecaadccd9ba399649ba93f20490c4..1d4481109f6e4f473610e0797c9d3c636bdf12cf 100644 --- a/sound/soc/codecs/mt6359-accdet.c +++ b/sound/soc/codecs/mt6359-accdet.c @@ -730,6 +730,17 @@ static void config_digital_init_by_mode(struct mt6359_accdet *priv) BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT)); } } + + if (priv->data->hp_eint_high) { + /* EINT polarity inverse */ + regmap_update_bits(priv->regmap, ACCDET_EINT_IN_INVERSE_ADDR, + ACCDET_EINT_IN_INVERSE_MASK_SFT, + BIT(ACCDET_EINT_IN_INVERSE_SFT)); + } else { + /* EINT polarity normal */ + regmap_update_bits(priv->regmap, ACCDET_EINT_IN_INVERSE_ADDR, + ACCDET_EINT_IN_INVERSE_MASK_SFT, 0); + } } static void config_eint_init_by_mode(struct mt6359_accdet *priv) From patchwork Wed Mar 5 18:58:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 870734 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C55824CEE3; Wed, 5 Mar 2025 19:00:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741201203; cv=none; b=IB8nVvrT/d/sbdJi+RBWg4jtwx8xIEcF8kSEQq2bPUXQTwFAEQR5P0szXORt0M0HjeqhrSduHPTXI2J61CSXGi5gru0dnSIWxnVKzaJhGiVQX5fZm2c21JY/epXJXdv1OVm1VYAgVa/F0z7o+zSuvlz7fbef9HAL2eJOzw/96Y0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741201203; c=relaxed/simple; bh=ew/lKKPHiRKrKA2kFSoKnjYv5WzKBHZsXi8V5xGuf2g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oe9RwgRqlFoSzCCNQUJaqJTy2A0v1xOIggHFI0pfMUtweGllIEdxOUonCCIwNvHPd/bKboX2Od1y8df8XUkN2DM3IKl8pejjZEAv1bE3DLbkWEcCGRSb9rXPMTsFJGVLrujsQfmQm+Mbo5igVuV8xIkAxRljxVylzHfM+JYr7uA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=kq6yxcbH; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="kq6yxcbH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1741201200; bh=ew/lKKPHiRKrKA2kFSoKnjYv5WzKBHZsXi8V5xGuf2g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kq6yxcbHxf5FMrDZ2VxBAMOctt94KtnY4rsGqlZmwu23S0gyG9yVy3C7iT2k/W0aD 2tMUVtJyKqua8F3g2T7l3jggQrjCoXuVNBPISFOjGjbNexrSuxSQoBs87kZ+UYz37d F+N8V5oUaFIrwdWskV+LUK0RUGYRaOaAiovQv9Qo8UdZ9TripU1dh5zLSX91H1+3ei o8FJOGVPAPUcl3i1spc/yezhz0mnSML/WohRJe70xV5FTb5PCkoTvPV9ugaTVq2Zez swd3wamisYOfoxWPodkrGAXt9L+nxgP+cUj60yOfGDjPQC/zj5OhfwPRclAmsSsoZ1 uCfOCusap729A== Received: from [192.168.0.47] (unknown [IPv6:2804:14c:1a9:53ee::1004]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 6E41517E017D; Wed, 5 Mar 2025 19:59:55 +0100 (CET) From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= Date: Wed, 05 Mar 2025 15:58:22 -0300 Subject: [PATCH v4 07/19] ASoC: mediatek: mt6359-accdet: Drop dead code for EINT trigger setting Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250305-mt6359-accdet-dts-v4-7-e5ffa5ee9991@collabora.com> References: <20250305-mt6359-accdet-dts-v4-0-e5ffa5ee9991@collabora.com> In-Reply-To: <20250305-mt6359-accdet-dts-v4-0-e5ffa5ee9991@collabora.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Jaroslav Kysela , Takashi Iwai , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Mailer: b4 0.14.2 None of the EINT trigger options are implemented and the DT property is not described in the binding. Remove the unused code. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nícolas F. R. A. Prado --- sound/soc/codecs/mt6359-accdet.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/sound/soc/codecs/mt6359-accdet.c b/sound/soc/codecs/mt6359-accdet.c index ce8a5e64e0b9ca508124043ca1f93aaa3cc5f9a0..a21c6544174517e3eebc8cf25d1ea3029ba014f6 100644 --- a/sound/soc/codecs/mt6359-accdet.c +++ b/sound/soc/codecs/mt6359-accdet.c @@ -35,8 +35,6 @@ #define ACCDET_PMIC_EINT1 BIT(3) #define ACCDET_PMIC_BI_EINT BIT(4) -#define ACCDET_PMIC_GPIO_TRIG_EINT BIT(5) -#define ACCDET_PMIC_INVERTER_TRIG_EINT BIT(6) #define ACCDET_PMIC_RSV_EINT BIT(7) #define ACCDET_THREE_KEY BIT(8) @@ -593,15 +591,6 @@ static int mt6359_accdet_parse_dt(struct mt6359_accdet *priv) else if (tmp == 2) priv->caps |= ACCDET_PMIC_BI_EINT; - ret = of_property_read_u32(node, "mediatek,eint-trig-mode", - &tmp); - if (ret) - tmp = 0; - if (tmp == 0) - priv->caps |= ACCDET_PMIC_GPIO_TRIG_EINT; - else if (tmp == 1) - priv->caps |= ACCDET_PMIC_INVERTER_TRIG_EINT; - ret = of_property_read_u32(node, "mediatek,eint-use-ext-res", &priv->data->eint_use_ext_res); if (ret) { From patchwork Wed Mar 5 18:58:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 870733 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4BE325A2AE; Wed, 5 Mar 2025 19:00:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741201214; cv=none; b=lrc0mIQmuKUBkcux1eMIAC3gkXV9MzHB381FOWahcWV9vxPYYu5zq4xcUWEH/hP8E+WsfNXgUf48DWe87PjHsxfNAdf94eoia4kLUN0C1bkN5CC8h8mehBe7lcuv/mUiXi09Q7LKKmA/A6tFvU4mqJURws0KtjFC35l0UIbZgWA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741201214; c=relaxed/simple; bh=25TENqi8q+kBqzrzX/J7Q2+OaNY4swWOeoiOQighkU8=; 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h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=mAhx/i5rvlXXoTH4k9hox7FMCKAQo0dnsBU5AwbFnRPsYlJkD81eXnUFpEMjaJrki 6BLyhmgw0xYYJcQUIqDsOc9EmKW7Z6PIq5NmOftisqQOoju83COFY3iVNWDelejr0B p4EN8KwYH2tVE5e6Lo/EBvtwR+JNrXAfUKEIXMMqa7/HLGLdz4WE753l8d1MnNDdAu UOslnmAm2sxcvqIUxwoN2wiqePDZ75cTScFXfmVmOE9Uq+YfPsU3jgXzYnxQRhLLWH qdsfD1caxsukbwhwc4QLgkWXWUYXRMiUeNu//+8Q4Xd//D6j07uaGwnBRQU7gT2zR3 0FqMvtBUrYsYQ== Received: from [192.168.0.47] (unknown [IPv6:2804:14c:1a9:53ee::1004]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 617F317E0343; Wed, 5 Mar 2025 20:00:06 +0100 (CET) From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= Date: Wed, 05 Mar 2025 15:58:24 -0300 Subject: [PATCH v4 09/19] ASoC: mediatek: mt6359-accdet: Drop dead code for plugout-debounce Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250305-mt6359-accdet-dts-v4-9-e5ffa5ee9991@collabora.com> References: <20250305-mt6359-accdet-dts-v4-0-e5ffa5ee9991@collabora.com> In-Reply-To: <20250305-mt6359-accdet-dts-v4-0-e5ffa5ee9991@collabora.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Jaroslav Kysela , Takashi Iwai , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Mailer: b4 0.14.2 The mediatek,plugout-debounce property is undocumented in the binding and unhandled by the driver. Remove it. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nícolas F. R. A. Prado --- sound/soc/codecs/mt6359-accdet.c | 5 ----- sound/soc/codecs/mt6359-accdet.h | 1 - 2 files changed, 6 deletions(-) diff --git a/sound/soc/codecs/mt6359-accdet.c b/sound/soc/codecs/mt6359-accdet.c index 6b0178976d91e37c32540991693ebfd8e29c11f5..d78d7516342a5c2273b1c2962c0346646aa6390f 100644 --- a/sound/soc/codecs/mt6359-accdet.c +++ b/sound/soc/codecs/mt6359-accdet.c @@ -513,11 +513,6 @@ static int mt6359_accdet_parse_dt(struct mt6359_accdet *priv) if (ret) priv->data->mic_vol = 8; - ret = of_property_read_u32(node, "mediatek,plugout-debounce", - &priv->data->plugout_deb); - if (ret) - priv->data->plugout_deb = 1; - ret = of_property_read_u32(node, "mediatek,mic-mode", &priv->data->mic_mode); if (ret) diff --git a/sound/soc/codecs/mt6359-accdet.h b/sound/soc/codecs/mt6359-accdet.h index 09e1072b61a4c929bf6b764b4fab3c4b26f7cf4a..54a33a0f0e084f80df33386b3df9bba9525fa880 100644 --- a/sound/soc/codecs/mt6359-accdet.h +++ b/sound/soc/codecs/mt6359-accdet.h @@ -72,7 +72,6 @@ struct pwm_deb_settings { struct dts_data { unsigned int mic_vol; unsigned int mic_mode; - unsigned int plugout_deb; bool hp_eint_high; struct pwm_deb_settings *pwm_deb; unsigned int moisture_detect_enable; From patchwork Wed Mar 5 18:58:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 870732 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD8C1252908; Wed, 5 Mar 2025 19:00:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741201235; cv=none; b=uSCPq16+CuXEvRGF5HNdmOqw2CdpAB8vtwMPxUpj6QrC+VzhqaUXJ4r2Tn5VG79wbgw6hhZ7piQfb7ScCOx7rhxgxCKKzYHiwUtpxQoVOSrQJSOE8HGa7ufwGq1NEyFOIX4ahhm1rnooxqlPIDkWnFBQeKtUuQwLjx3zGl1IR+8= ARC-Message-Signature: i=1; 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There are no current users of these DT properties, so no backward compatibility needs to be maintained. The properties can be properly introduced in the binding in the future if different boards really need to override them. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nícolas F. R. A. Prado --- sound/soc/codecs/mt6359-accdet.c | 70 ++++++++++++++++++++++------------------ sound/soc/codecs/mt6359-accdet.h | 20 ------------ 2 files changed, 38 insertions(+), 52 deletions(-) diff --git a/sound/soc/codecs/mt6359-accdet.c b/sound/soc/codecs/mt6359-accdet.c index e04cfb9a607aa5d38d46329eb1387545fda37ccc..6728f1018c992fc9d4e4133dbaf091d256567683 100644 --- a/sound/soc/codecs/mt6359-accdet.c +++ b/sound/soc/codecs/mt6359-accdet.c @@ -43,6 +43,25 @@ #define ACCDET_DIGITAL_FASTDISCHARGE BIT(13) #define ACCDET_AD_FASTDISCHRAGE BIT(14) +/* Debounce time = (DEBOUNCE/32768) sec */ +#define ACCDET_DEBOUNCE0_625MS 0x800 +#define ACCDET_DEBOUNCE1_625MS 0x800 +#define ACCDET_DEBOUNCE3_976US 0x20 +#define ACCDET_DEBOUNCE_AUXADC_2MS 0x44 +/* PWM frequency = 32768/(PWM_WIDTH + 1) Hz */ +#define ACCDET_PWM_WIDTH_25_580HZ 0x500 +/* Duty cycle = (PWM_THRESH + 1) / (PWM_WIDTH + 1) */ +#define ACCDET_PWM_THRESH_100PERCENT ACCDET_PWM_WIDTH_25_580HZ +#define ACCDET_RISE_DELAY 0x1f0 +#define ACCDET_FALL_DELAY 1 +#define ACCDET_EINT_DEBOUNCE0_1MS 5 +#define ACCDET_EINT_DEBOUNCE1_900US 3 +#define ACCDET_EINT_DEBOUNCE2_900US 3 +#define ACCDET_EINT_DEBOUNCE3_1MS 5 +#define ACCDET_EINT_INVERTER_DEBOUNCE_256MS 0xe +#define ACCDET_EINT_CMPMEN_PWM_WIDTH_400MS 4 +#define ACCDET_EINT_CMPMEN_PWM_THRESH_2MS 1 + static struct platform_driver mt6359_accdet_driver; static const struct snd_soc_component_driver mt6359_accdet_soc_driver; @@ -130,7 +149,7 @@ static unsigned int mt6359_accdet_jd_setting(struct mt6359_accdet *priv) } else if (priv->jd_sts == M_PLUG_OUT) { /* set debounce to 1ms */ accdet_set_debounce(priv, eint_state000, - priv->data->pwm_deb->eint_debounce0); + ACCDET_EINT_DEBOUNCE0_1MS); } else { dev_dbg(priv->dev, "should not be here %s()\n", __func__); } @@ -241,11 +260,11 @@ static void mt6359_accdet_recover_jd_setting(struct mt6359_accdet *priv) /* recover accdet debounce0,3 */ accdet_set_debounce(priv, accdet_state000, - priv->data->pwm_deb->debounce0); + ACCDET_DEBOUNCE0_625MS); accdet_set_debounce(priv, accdet_state001, - priv->data->pwm_deb->debounce1); + ACCDET_DEBOUNCE1_625MS); accdet_set_debounce(priv, accdet_state011, - priv->data->pwm_deb->debounce3); + ACCDET_DEBOUNCE3_976US); priv->jack_type = 0; priv->accdet_status = 0x3; @@ -390,7 +409,7 @@ static void mt6359_accdet_jd_work(struct work_struct *work) priv->jack_plugged = false; accdet_set_debounce(priv, accdet_state011, - priv->data->pwm_deb->debounce3); + ACCDET_DEBOUNCE3_976US); regmap_update_bits(priv->regmap, ACCDET_SW_EN_ADDR, ACCDET_SW_EN_MASK_SFT, 0); mt6359_accdet_recover_jd_setting(priv); @@ -497,7 +516,6 @@ static int mt6359_accdet_parse_dt(struct mt6359_accdet *priv) int ret; struct device *dev = priv->dev; struct device_node *node = NULL; - int pwm_deb[15] = {0}; unsigned int tmp = 0; node = of_get_child_by_name(dev->parent->of_node, "accdet"); @@ -514,12 +532,6 @@ static int mt6359_accdet_parse_dt(struct mt6359_accdet *priv) if (ret) priv->data->mic_mode = 2; - ret = of_property_read_u32_array(node, "mediatek,pwm-deb-setting", - pwm_deb, ARRAY_SIZE(pwm_deb)); - /* debounce8(auxadc debounce) is default, needn't get from dts */ - if (!ret) - memcpy(priv->data->pwm_deb, pwm_deb, sizeof(pwm_deb)); - priv->data->hp_eint_high = of_property_read_bool(node, "mediatek,hp-eint-high"); ret = of_property_read_u32(node, "mediatek,eint-detect-mode", @@ -554,8 +566,8 @@ static void config_digital_init_by_mode(struct mt6359_accdet *priv) { /* enable eint cmpmem pwm */ regmap_write(priv->regmap, ACCDET_EINT_CMPMEN_PWM_THRESH_ADDR, - (priv->data->pwm_deb->eint_pwm_width << 4 | - priv->data->pwm_deb->eint_pwm_thresh)); + (ACCDET_EINT_CMPMEN_PWM_WIDTH_400MS << 4 | + ACCDET_EINT_CMPMEN_PWM_THRESH_2MS)); /* DA signal stable */ if (priv->caps & ACCDET_PMIC_EINT0) { regmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR, @@ -675,22 +687,22 @@ static void mt6359_accdet_init(struct mt6359_accdet *priv) mdelay(1); /* init the debounce time (debounce/32768)sec */ accdet_set_debounce(priv, accdet_state000, - priv->data->pwm_deb->debounce0); + ACCDET_DEBOUNCE0_625MS); accdet_set_debounce(priv, accdet_state001, - priv->data->pwm_deb->debounce1); + ACCDET_DEBOUNCE1_625MS); accdet_set_debounce(priv, accdet_state011, - priv->data->pwm_deb->debounce3); + ACCDET_DEBOUNCE3_976US); accdet_set_debounce(priv, accdet_auxadc, - priv->data->pwm_deb->debounce4); + ACCDET_DEBOUNCE_AUXADC_2MS); accdet_set_debounce(priv, eint_state000, - priv->data->pwm_deb->eint_debounce0); + ACCDET_EINT_DEBOUNCE0_1MS); accdet_set_debounce(priv, eint_state001, - priv->data->pwm_deb->eint_debounce1); + ACCDET_EINT_DEBOUNCE1_900US); accdet_set_debounce(priv, eint_state011, - priv->data->pwm_deb->eint_debounce3); + ACCDET_EINT_DEBOUNCE3_1MS); accdet_set_debounce(priv, eint_inverter_state000, - priv->data->pwm_deb->eint_inverter_debounce); + ACCDET_EINT_INVERTER_DEBOUNCE_256MS); regmap_update_bits(priv->regmap, RG_ACCDET_RST_ADDR, RG_ACCDET_RST_MASK_SFT, BIT(RG_ACCDET_RST_SFT)); @@ -705,12 +717,12 @@ static void mt6359_accdet_init(struct mt6359_accdet *priv) /* init pwm frequency, duty & rise/falling delay */ regmap_write(priv->regmap, ACCDET_PWM_WIDTH_ADDR, - REGISTER_VAL(priv->data->pwm_deb->pwm_width)); + REGISTER_VAL(ACCDET_PWM_WIDTH_25_580HZ)); regmap_write(priv->regmap, ACCDET_PWM_THRESH_ADDR, - REGISTER_VAL(priv->data->pwm_deb->pwm_thresh)); + REGISTER_VAL(ACCDET_PWM_THRESH_100PERCENT)); regmap_write(priv->regmap, ACCDET_RISE_DELAY_ADDR, - (priv->data->pwm_deb->fall_delay << 15 | - priv->data->pwm_deb->rise_delay)); + (ACCDET_FALL_DELAY << 15 | + ACCDET_RISE_DELAY)); regmap_read(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, ®); if (priv->data->mic_vol <= 7) { @@ -806,12 +818,6 @@ static int mt6359_accdet_probe(struct platform_device *pdev) if (!priv->data) return -ENOMEM; - priv->data->pwm_deb = devm_kzalloc(&pdev->dev, - sizeof(struct pwm_deb_settings), - GFP_KERNEL); - if (!priv->data->pwm_deb) - return -ENOMEM; - priv->regmap = mt6397->regmap; if (IS_ERR(priv->regmap)) { ret = PTR_ERR(priv->regmap); diff --git a/sound/soc/codecs/mt6359-accdet.h b/sound/soc/codecs/mt6359-accdet.h index 99de5037a2294b62cb8535fc45dbf4c6fafb5c7f..287201eebe0330fa170093fd6192bf5694c30469 100644 --- a/sound/soc/codecs/mt6359-accdet.h +++ b/sound/soc/codecs/mt6359-accdet.h @@ -50,30 +50,10 @@ enum { eint_inverter_state000, }; -struct pwm_deb_settings { - unsigned int pwm_width; - unsigned int pwm_thresh; - unsigned int fall_delay; - unsigned int rise_delay; - unsigned int debounce0; - unsigned int debounce1; - unsigned int debounce3; - unsigned int debounce4; - unsigned int eint_pwm_width; - unsigned int eint_pwm_thresh; - unsigned int eint_debounce0; - unsigned int eint_debounce1; - unsigned int eint_debounce2; - unsigned int eint_debounce3; - unsigned int eint_inverter_debounce; - -}; - struct dts_data { unsigned int mic_vol; unsigned int mic_mode; bool hp_eint_high; - struct pwm_deb_settings *pwm_deb; unsigned int eint_detect_mode; unsigned int eint_comp_vth; }; From patchwork Wed Mar 5 18:58:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 870731 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5C5725A654; Wed, 5 Mar 2025 19:00:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741201238; cv=none; b=rhxA+hmSluys3rqIQf+XaPr+GNj/3Qik+FrJEUly8gW4jUxouwCYn+uf+xCdpivOGVmPU1tjVpjbLNUVHYsXdI8OmrVA+GFIZ0Kbguu7tsddzp+EmhxuxJUFz6rjsUE6RsY9+W7aIXS5H0MZFSIXqiTLaDa6Ru2sFdmPE3wnE2c= ARC-Message-Signature: i=1; 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Since there are no users of the property, it doesn't directly describe the hardware, and the default value (4) is known to work across multiple boards, remove the handling for this property and always assume mode 4 is used. The property can be properly introduced in the binding in the future if different boards actually need different configurations. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nícolas F. R. A. Prado --- sound/soc/codecs/mt6359-accdet.c | 208 +++++++++++++-------------------------- sound/soc/codecs/mt6359-accdet.h | 1 - 2 files changed, 70 insertions(+), 139 deletions(-) diff --git a/sound/soc/codecs/mt6359-accdet.c b/sound/soc/codecs/mt6359-accdet.c index 6728f1018c992fc9d4e4133dbaf091d256567683..83e65b6d5845dea00a8a77d68df4b7df1f62a87c 100644 --- a/sound/soc/codecs/mt6359-accdet.c +++ b/sound/soc/codecs/mt6359-accdet.c @@ -81,31 +81,22 @@ static void recover_eint_setting(struct mt6359_accdet *priv); static unsigned int adjust_eint_analog_setting(struct mt6359_accdet *priv) { - if (priv->data->eint_detect_mode == 0x3 || - priv->data->eint_detect_mode == 0x4) { - /* ESD switches off */ - regmap_update_bits(priv->regmap, - RG_ACCDETSPARE_ADDR, 1 << 8, 0); - } - if (priv->data->eint_detect_mode == 0x4) { - if (priv->caps & ACCDET_PMIC_EINT0) { - /* enable RG_EINT0CONFIGACCDET */ - regmap_update_bits(priv->regmap, - RG_EINT0CONFIGACCDET_ADDR, - RG_EINT0CONFIGACCDET_MASK_SFT, - BIT(RG_EINT0CONFIGACCDET_SFT)); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - /* enable RG_EINT1CONFIGACCDET */ - regmap_update_bits(priv->regmap, - RG_EINT1CONFIGACCDET_ADDR, - RG_EINT1CONFIGACCDET_MASK_SFT, - BIT(RG_EINT1CONFIGACCDET_SFT)); - } - /*select 500k, use internal resistor */ - regmap_update_bits(priv->regmap, RG_EINT0HIRENB_ADDR, - RG_EINT0HIRENB_MASK_SFT, - BIT(RG_EINT0HIRENB_SFT)); + /* ESD switches off */ + regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, 1 << 8, 0); + if (priv->caps & ACCDET_PMIC_EINT0) { + /* enable RG_EINT0CONFIGACCDET */ + regmap_update_bits(priv->regmap, RG_EINT0CONFIGACCDET_ADDR, + RG_EINT0CONFIGACCDET_MASK_SFT, + BIT(RG_EINT0CONFIGACCDET_SFT)); + } else if (priv->caps & ACCDET_PMIC_EINT1) { + /* enable RG_EINT1CONFIGACCDET */ + regmap_update_bits(priv->regmap, RG_EINT1CONFIGACCDET_ADDR, + RG_EINT1CONFIGACCDET_MASK_SFT, + BIT(RG_EINT1CONFIGACCDET_SFT)); } + /*select 500k, use internal resistor */ + regmap_update_bits(priv->regmap, RG_EINT0HIRENB_ADDR, + RG_EINT0HIRENB_MASK_SFT, BIT(RG_EINT0HIRENB_SFT)); return 0; } @@ -123,18 +114,14 @@ static unsigned int adjust_eint_digital_setting(struct mt6359_accdet *priv) ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, 0); } - if (priv->data->eint_detect_mode == 0x4) { - if (priv->caps & ACCDET_PMIC_EINT0) { - /* set DA stable signal */ - regmap_update_bits(priv->regmap, - ACCDET_DA_STABLE_ADDR, - ACCDET_EINT0_CEN_STABLE_MASK_SFT, 0); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - /* set DA stable signal */ - regmap_update_bits(priv->regmap, - ACCDET_DA_STABLE_ADDR, - ACCDET_EINT1_CEN_STABLE_MASK_SFT, 0); - } + if (priv->caps & ACCDET_PMIC_EINT0) { + /* set DA stable signal */ + regmap_update_bits(priv->regmap, ACCDET_DA_STABLE_ADDR, + ACCDET_EINT0_CEN_STABLE_MASK_SFT, 0); + } else if (priv->caps & ACCDET_PMIC_EINT1) { + /* set DA stable signal */ + regmap_update_bits(priv->regmap, ACCDET_DA_STABLE_ADDR, + ACCDET_EINT1_CEN_STABLE_MASK_SFT, 0); } return 0; } @@ -159,27 +146,19 @@ static unsigned int mt6359_accdet_jd_setting(struct mt6359_accdet *priv) static void recover_eint_analog_setting(struct mt6359_accdet *priv) { - if (priv->data->eint_detect_mode == 0x3 || - priv->data->eint_detect_mode == 0x4) { - /* ESD switches on */ - regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, - 1 << 8, 1 << 8); - } - if (priv->data->eint_detect_mode == 0x4) { - if (priv->caps & ACCDET_PMIC_EINT0) { - /* disable RG_EINT0CONFIGACCDET */ - regmap_update_bits(priv->regmap, - RG_EINT0CONFIGACCDET_ADDR, - RG_EINT0CONFIGACCDET_MASK_SFT, 0); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - /* disable RG_EINT1CONFIGACCDET */ - regmap_update_bits(priv->regmap, - RG_EINT1CONFIGACCDET_ADDR, - RG_EINT1CONFIGACCDET_MASK_SFT, 0); - } - regmap_update_bits(priv->regmap, RG_EINT0HIRENB_ADDR, - RG_EINT0HIRENB_MASK_SFT, 0); + /* ESD switches on */ + regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, 1 << 8, 1 << 8); + if (priv->caps & ACCDET_PMIC_EINT0) { + /* disable RG_EINT0CONFIGACCDET */ + regmap_update_bits(priv->regmap, RG_EINT0CONFIGACCDET_ADDR, + RG_EINT0CONFIGACCDET_MASK_SFT, 0); + } else if (priv->caps & ACCDET_PMIC_EINT1) { + /* disable RG_EINT1CONFIGACCDET */ + regmap_update_bits(priv->regmap, RG_EINT1CONFIGACCDET_ADDR, + RG_EINT1CONFIGACCDET_MASK_SFT, 0); } + regmap_update_bits(priv->regmap, RG_EINT0HIRENB_ADDR, + RG_EINT0HIRENB_MASK_SFT, 0); } static void recover_eint_digital_setting(struct mt6359_accdet *priv) @@ -193,37 +172,30 @@ static void recover_eint_digital_setting(struct mt6359_accdet *priv) ACCDET_EINT1_M_SW_EN_ADDR, ACCDET_EINT1_M_SW_EN_MASK_SFT, 0); } - if (priv->data->eint_detect_mode == 0x4) { + if (priv->caps & ACCDET_PMIC_EINT0) { /* enable eint0cen */ - if (priv->caps & ACCDET_PMIC_EINT0) { - /* enable eint0cen */ - regmap_update_bits(priv->regmap, - ACCDET_DA_STABLE_ADDR, - ACCDET_EINT0_CEN_STABLE_MASK_SFT, - BIT(ACCDET_EINT0_CEN_STABLE_SFT)); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - /* enable eint1cen */ - regmap_update_bits(priv->regmap, - ACCDET_DA_STABLE_ADDR, - ACCDET_EINT1_CEN_STABLE_MASK_SFT, - BIT(ACCDET_EINT1_CEN_STABLE_SFT)); - } + regmap_update_bits(priv->regmap, ACCDET_DA_STABLE_ADDR, + ACCDET_EINT0_CEN_STABLE_MASK_SFT, + BIT(ACCDET_EINT0_CEN_STABLE_SFT)); + } else if (priv->caps & ACCDET_PMIC_EINT1) { + /* enable eint1cen */ + regmap_update_bits(priv->regmap, ACCDET_DA_STABLE_ADDR, + ACCDET_EINT1_CEN_STABLE_MASK_SFT, + BIT(ACCDET_EINT1_CEN_STABLE_SFT)); } - if (priv->data->eint_detect_mode != 0x1) { - if (priv->caps & ACCDET_PMIC_EINT0) { - /* enable inverter */ - regmap_update_bits(priv->regmap, - ACCDET_EINT0_INVERTER_SW_EN_ADDR, - ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, - BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT)); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - /* enable inverter */ - regmap_update_bits(priv->regmap, - ACCDET_EINT1_INVERTER_SW_EN_ADDR, - ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, - BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT)); - } + if (priv->caps & ACCDET_PMIC_EINT0) { + /* enable inverter */ + regmap_update_bits(priv->regmap, + ACCDET_EINT0_INVERTER_SW_EN_ADDR, + ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, + BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT)); + } else if (priv->caps & ACCDET_PMIC_EINT1) { + /* enable inverter */ + regmap_update_bits(priv->regmap, + ACCDET_EINT1_INVERTER_SW_EN_ADDR, + ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, + BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT)); } } @@ -534,13 +506,6 @@ static int mt6359_accdet_parse_dt(struct mt6359_accdet *priv) priv->data->hp_eint_high = of_property_read_bool(node, "mediatek,hp-eint-high"); - ret = of_property_read_u32(node, "mediatek,eint-detect-mode", - &priv->data->eint_detect_mode); - if (ret) { - /* eint detection mode equals to EINT HW Mode */ - priv->data->eint_detect_mode = 0x4; - } - ret = of_property_read_u32(node, "mediatek,eint-num", &tmp); if (ret) tmp = 0; @@ -592,31 +557,16 @@ static void config_digital_init_by_mode(struct mt6359_accdet *priv) /* enable PWM */ regmap_write(priv->regmap, ACCDET_CMP_PWM_EN_ADDR, 0x67); /* enable inverter detection */ - if (priv->data->eint_detect_mode == 0x1) { - /* disable inverter detection */ - if (priv->caps & ACCDET_PMIC_EINT0) { - regmap_update_bits(priv->regmap, - ACCDET_EINT0_INVERTER_SW_EN_ADDR, - ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, - 0); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - regmap_update_bits(priv->regmap, - ACCDET_EINT1_INVERTER_SW_EN_ADDR, - ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, - 0); - } - } else { - if (priv->caps & ACCDET_PMIC_EINT0) { - regmap_update_bits(priv->regmap, - ACCDET_EINT0_INVERTER_SW_EN_ADDR, - ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, - BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT)); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - regmap_update_bits(priv->regmap, - ACCDET_EINT1_INVERTER_SW_EN_ADDR, - ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, - BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT)); - } + if (priv->caps & ACCDET_PMIC_EINT0) { + regmap_update_bits(priv->regmap, + ACCDET_EINT0_INVERTER_SW_EN_ADDR, + ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, + BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT)); + } else if (priv->caps & ACCDET_PMIC_EINT1) { + regmap_update_bits(priv->regmap, + ACCDET_EINT1_INVERTER_SW_EN_ADDR, + ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, + BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT)); } if (priv->data->hp_eint_high) { @@ -649,28 +599,10 @@ static void config_eint_init_by_mode(struct mt6359_accdet *priv) regmap_update_bits(priv->regmap, RG_NCP_PDDIS_EN_ADDR, RG_NCP_PDDIS_EN_MASK_SFT, BIT(RG_NCP_PDDIS_EN_SFT)); - if (priv->data->eint_detect_mode == 0x1 || - priv->data->eint_detect_mode == 0x2 || - priv->data->eint_detect_mode == 0x3) { - if (priv->caps & ACCDET_PMIC_EINT0) { - regmap_update_bits(priv->regmap, - RG_EINT0CONFIGACCDET_ADDR, - RG_EINT0CONFIGACCDET_MASK_SFT, - BIT(RG_EINT0CONFIGACCDET_SFT)); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - regmap_update_bits(priv->regmap, - RG_EINT1CONFIGACCDET_ADDR, - RG_EINT1CONFIGACCDET_MASK_SFT, - BIT(RG_EINT1CONFIGACCDET_SFT)); - } - } - - if (priv->data->eint_detect_mode != 0x1) { - /* current detect set 0.25uA */ - regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, - 0x3 << RG_ACCDETSPARE_SFT, - 0x3 << RG_ACCDETSPARE_SFT); - } + /* current detect set 0.25uA */ + regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, + 0x3 << RG_ACCDETSPARE_SFT, + 0x3 << RG_ACCDETSPARE_SFT); regmap_write(priv->regmap, RG_EINTCOMPVTH_ADDR, val | priv->data->eint_comp_vth << RG_EINTCOMPVTH_SFT); } diff --git a/sound/soc/codecs/mt6359-accdet.h b/sound/soc/codecs/mt6359-accdet.h index 287201eebe0330fa170093fd6192bf5694c30469..ff5cd6ea1b06f045b6e1b9f6bc53ef80d78e3b92 100644 --- a/sound/soc/codecs/mt6359-accdet.h +++ b/sound/soc/codecs/mt6359-accdet.h @@ -54,7 +54,6 @@ struct dts_data { unsigned int mic_vol; unsigned int mic_mode; bool hp_eint_high; - unsigned int eint_detect_mode; unsigned int eint_comp_vth; }; From patchwork Wed Mar 5 18:58:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 870730 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 061D2255E30; Wed, 5 Mar 2025 19:00:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741201248; cv=none; b=Uv0I0099tB+SYZZSlSXrW1tVN6rroATN9BYaWWwKsh2Vjj6DRQMtX3I3t99VqkLtTAI8m3EfaY1zmz9JGBJCpGRhfZbxG6Pl22v8zjKNgh6ixLjuGR1lkVpMdRQa7nzrZtF2RRtH6Mp8e5uFDmLbyWXtoqWfRvJOujbj+1TPr6Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741201248; c=relaxed/simple; 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s=mail; t=1741201245; bh=rBci4f69I/d/dQvGhQC94bd2AW9ZiKT0dsBk2rxvf9k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MeHRO+Ne0zhBlmqoR48VPl3x64Upn/204cmF/N3fkcX9Hjh1eQwCuvD5/4/qqfEX1 63v11+lJcN2qcNAVWOJhnqRUfET9r6y4TPkNYqYzW2gZkNSMKy5x55VHMyvzkKbEpi KSB8uj+PXwSy62vtOV1s6GY3h2eGXb54FRC12mtyA9tlH+McOsAf5Fu66h6aiCEpyS 224p1W1vPb1ljbZoHUOO/3VVJ31KmAGFXhU90cHKSXfXZw7XuXnpU+dWLhOzlur18L gyBrCeMKiPKBlHinGE4vUJweItwJhlHS/onQl1XcGFOg5L8BGWgGKQK06AGRb+ssXg DmQPvUMLTqd6g== Received: from [192.168.0.47] (unknown [IPv6:2804:14c:1a9:53ee::1004]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 3170117E0147; Wed, 5 Mar 2025 20:00:40 +0100 (CET) From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= Date: Wed, 05 Mar 2025 15:58:30 -0300 Subject: [PATCH v4 15/19] ASoC: mediatek: mt6359-accdet: Always configure hardware as mic-mode 2 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250305-mt6359-accdet-dts-v4-15-e5ffa5ee9991@collabora.com> References: <20250305-mt6359-accdet-dts-v4-0-e5ffa5ee9991@collabora.com> In-Reply-To: <20250305-mt6359-accdet-dts-v4-0-e5ffa5ee9991@collabora.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Jaroslav Kysela , Takashi Iwai , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Mailer: b4 0.14.2 The driver currently reads a mediatek,mic-mode property from DT to determine certain register configurations. Since there are no current users of the property, the property doesn't directly reflect the hardware and the default value (2) is known to work on multiple boards, remove the code handling this property and instead always configure the hardware according to the known to work default. This property can be properly introduced in the binding in the future if it really turns out that different boards need different configurations. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nícolas F. R. A. Prado --- sound/soc/codecs/mt6359-accdet.c | 43 ++++++---------------------------------- sound/soc/codecs/mt6359-accdet.h | 5 ----- 2 files changed, 6 insertions(+), 42 deletions(-) diff --git a/sound/soc/codecs/mt6359-accdet.c b/sound/soc/codecs/mt6359-accdet.c index a31e084560c7643b14fb71871699e3167075d9d9..12697b02faff1be39317116cd7d8ffa359f2cd4e 100644 --- a/sound/soc/codecs/mt6359-accdet.c +++ b/sound/soc/codecs/mt6359-accdet.c @@ -494,11 +494,6 @@ static int mt6359_accdet_parse_dt(struct mt6359_accdet *priv) if (!node) return -EINVAL; - ret = of_property_read_u32(node, "mediatek,mic-mode", - &priv->data->mic_mode); - if (ret) - priv->data->mic_mode = 2; - priv->data->hp_eint_high = of_property_read_bool(node, "mediatek,hp-eint-high"); ret = of_property_read_u32(node, "mediatek,eint-num", &tmp); @@ -658,38 +653,12 @@ static void mt6359_accdet_init(struct mt6359_accdet *priv) RG_AUDMICBIAS1LOWPEN_MASK_SFT); /* mic mode setting */ regmap_read(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, ®); - if (priv->data->mic_mode == HEADSET_MODE_1) { - /* ACC mode*/ - regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, - reg | RG_ACCDET_MODE_ANA11_MODE1); - /* enable analog fast discharge */ - regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR, - RG_ANALOGFDEN_MASK_SFT, - BIT(RG_ANALOGFDEN_SFT)); - regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, - 0x3 << 11, 0x3 << 11); - } else if (priv->data->mic_mode == HEADSET_MODE_2) { - /* DCC mode Low cost mode without internal bias */ - regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, - reg | RG_ACCDET_MODE_ANA11_MODE2); - /* enable analog fast discharge */ - regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR, - 0x3 << RG_ANALOGFDEN_SFT, - 0x3 << RG_ANALOGFDEN_SFT); - } else if (priv->data->mic_mode == HEADSET_MODE_6) { - /* DCC mode Low cost mode with internal bias, - * bit8 = 1 to use internal bias - */ - regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, - reg | RG_ACCDET_MODE_ANA11_MODE6); - regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, - RG_AUDMICBIAS1DCSW1PEN_MASK_SFT, - BIT(RG_AUDMICBIAS1DCSW1PEN_SFT)); - /* enable analog fast discharge */ - regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR, - 0x3 << RG_ANALOGFDEN_SFT, - 0x3 << RG_ANALOGFDEN_SFT); - } + /* DCC mode Low cost mode without internal bias */ + regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, + reg | RG_ACCDET_MODE_ANA11_MODE2); + /* enable analog fast discharge */ + regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR, + 0x3 << RG_ANALOGFDEN_SFT, 0x3 << RG_ANALOGFDEN_SFT); config_eint_init_by_mode(priv); config_digital_init_by_mode(priv); diff --git a/sound/soc/codecs/mt6359-accdet.h b/sound/soc/codecs/mt6359-accdet.h index 46dcd4759230a5190434b9b7c785e8b9ed12fd3d..579373807c414130b2a7384db4978e01cf1d046c 100644 --- a/sound/soc/codecs/mt6359-accdet.h +++ b/sound/soc/codecs/mt6359-accdet.h @@ -12,10 +12,6 @@ #define ACCDET_DEVNAME "accdet" -#define HEADSET_MODE_1 (1) -#define HEADSET_MODE_2 (2) -#define HEADSET_MODE_6 (6) - #define MT6359_ACCDET_NUM_BUTTONS 4 #define MT6359_ACCDET_JACK_MASK (SND_JACK_HEADPHONE | \ SND_JACK_HEADSET | \ @@ -51,7 +47,6 @@ enum { }; struct dts_data { - unsigned int mic_mode; bool hp_eint_high; unsigned int eint_comp_vth; }; From patchwork Wed Mar 5 18:58:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 870729 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52F0525D53A; Wed, 5 Mar 2025 19:00:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741201260; cv=none; b=muMDFu9uSwpD4UchI3jVx5Dv7iR2g3s5UEEGCd2SgInXVjYdyQkMtsdgEejcyVuynp5D4h3Brr8gsUZW91iIanHRp1O/zXDT4uHyNaaDcnRDtHTTjqvsuKboYucZIlTkJ3e49PkVAlSgXOqFtJ1VQr9k7tdHi/q/8UcAnNg/uG8= ARC-Message-Signature: i=1; a=rsa-sha256; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1741201256; bh=wjZmjmhM6PnilSdM4uO4ct3TDNZO044budbRnrFXjT8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ISNG8ZiTf1EZqXrPOGc3dX2beGSO99sRgCdoFefvRb3ktXWf7jWdmNiuRqQ4jBg33 CjYMNviP1e8021oHLyNgluyAn+GGe6V4MmTW9PPJAXnsmtmJzDjoP6aquYutEE4B5A t08rkuupDRV/BqYrJ0E3FQEbJ1ZYllk46OfQH8Sz4JpL1Ls8rFNyvvcS+EgDjThHjG 40FbFU8ruAImXYDRjDAZq3ozeCCJtI+NSJRHRJf9f/oFQJh4oldmZYabLsrlAyG3Au GLZGpl3rDYhDdrrJeg+pU6QqneDYkNeBBV44ZkBAOyLGZSH2FMJZkv/eSI0ytNXPrg EXKbH47A+GDJA== Received: from [192.168.0.47] (unknown [IPv6:2804:14c:1a9:53ee::1004]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 581DA17E0147; Wed, 5 Mar 2025 20:00:51 +0100 (CET) From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= Date: Wed, 05 Mar 2025 15:58:32 -0300 Subject: [PATCH v4 17/19] ASoC: mediatek: mt6359-accdet: Always use EINT0 IRQ Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250305-mt6359-accdet-dts-v4-17-e5ffa5ee9991@collabora.com> References: <20250305-mt6359-accdet-dts-v4-0-e5ffa5ee9991@collabora.com> In-Reply-To: <20250305-mt6359-accdet-dts-v4-0-e5ffa5ee9991@collabora.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Jaroslav Kysela , Takashi Iwai , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Mailer: b4 0.14.2 The ACCDET block can generate two distinct EINT interrupts: EINT0 and EINT1, and which is enabled is currently determined by mediatek,eint-num property in DT. However, only EINT0 is used on the boards that are known to have working ACCDET. Since there are no current users of the property, remove its handling and instead always enable EINT0. The property can be properly introduced in the binding in the future if it really turns out that other boards require EINT1. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nícolas F. R. A. Prado --- sound/soc/codecs/mt6359-accdet.c | 187 +++++++++------------------------------ sound/soc/codecs/mt6359-accdet.h | 1 - 2 files changed, 43 insertions(+), 145 deletions(-) diff --git a/sound/soc/codecs/mt6359-accdet.c b/sound/soc/codecs/mt6359-accdet.c index 3f6a97e8de8d174e59e512d53135fadc5765b5c1..b1e63f3f7fa44687b1cac47c0e33f68a28e15a47 100644 --- a/sound/soc/codecs/mt6359-accdet.c +++ b/sound/soc/codecs/mt6359-accdet.c @@ -31,10 +31,6 @@ #define REGISTER_VAL(x) ((x) - 1) /* mt6359 accdet capability */ -#define ACCDET_PMIC_EINT0 BIT(2) -#define ACCDET_PMIC_EINT1 BIT(3) -#define ACCDET_PMIC_BI_EINT BIT(4) - #define ACCDET_PMIC_RSV_EINT BIT(7) #define ACCDET_RSV_KEY BIT(11) @@ -84,17 +80,10 @@ static unsigned int adjust_eint_analog_setting(struct mt6359_accdet *priv) { /* ESD switches off */ regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, 1 << 8, 0); - if (priv->caps & ACCDET_PMIC_EINT0) { - /* enable RG_EINT0CONFIGACCDET */ - regmap_update_bits(priv->regmap, RG_EINT0CONFIGACCDET_ADDR, - RG_EINT0CONFIGACCDET_MASK_SFT, - BIT(RG_EINT0CONFIGACCDET_SFT)); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - /* enable RG_EINT1CONFIGACCDET */ - regmap_update_bits(priv->regmap, RG_EINT1CONFIGACCDET_ADDR, - RG_EINT1CONFIGACCDET_MASK_SFT, - BIT(RG_EINT1CONFIGACCDET_SFT)); - } + /* enable RG_EINT0CONFIGACCDET */ + regmap_update_bits(priv->regmap, RG_EINT0CONFIGACCDET_ADDR, + RG_EINT0CONFIGACCDET_MASK_SFT, + BIT(RG_EINT0CONFIGACCDET_SFT)); /*select 500k, use internal resistor */ regmap_update_bits(priv->regmap, RG_EINT0HIRENB_ADDR, RG_EINT0HIRENB_MASK_SFT, BIT(RG_EINT0HIRENB_SFT)); @@ -103,27 +92,13 @@ static unsigned int adjust_eint_analog_setting(struct mt6359_accdet *priv) static unsigned int adjust_eint_digital_setting(struct mt6359_accdet *priv) { - if (priv->caps & ACCDET_PMIC_EINT0) { - /* disable inverter */ - regmap_update_bits(priv->regmap, - ACCDET_EINT0_INVERTER_SW_EN_ADDR, - ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, 0); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - /* disable inverter */ - regmap_update_bits(priv->regmap, - ACCDET_EINT1_INVERTER_SW_EN_ADDR, - ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, 0); - } + /* disable inverter */ + regmap_update_bits(priv->regmap, ACCDET_EINT0_INVERTER_SW_EN_ADDR, + ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, 0); - if (priv->caps & ACCDET_PMIC_EINT0) { - /* set DA stable signal */ - regmap_update_bits(priv->regmap, ACCDET_DA_STABLE_ADDR, - ACCDET_EINT0_CEN_STABLE_MASK_SFT, 0); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - /* set DA stable signal */ - regmap_update_bits(priv->regmap, ACCDET_DA_STABLE_ADDR, - ACCDET_EINT1_CEN_STABLE_MASK_SFT, 0); - } + /* set DA stable signal */ + regmap_update_bits(priv->regmap, ACCDET_DA_STABLE_ADDR, + ACCDET_EINT0_CEN_STABLE_MASK_SFT, 0); return 0; } @@ -149,55 +124,26 @@ static void recover_eint_analog_setting(struct mt6359_accdet *priv) { /* ESD switches on */ regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, 1 << 8, 1 << 8); - if (priv->caps & ACCDET_PMIC_EINT0) { - /* disable RG_EINT0CONFIGACCDET */ - regmap_update_bits(priv->regmap, RG_EINT0CONFIGACCDET_ADDR, - RG_EINT0CONFIGACCDET_MASK_SFT, 0); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - /* disable RG_EINT1CONFIGACCDET */ - regmap_update_bits(priv->regmap, RG_EINT1CONFIGACCDET_ADDR, - RG_EINT1CONFIGACCDET_MASK_SFT, 0); - } + /* disable RG_EINT0CONFIGACCDET */ + regmap_update_bits(priv->regmap, RG_EINT0CONFIGACCDET_ADDR, + RG_EINT0CONFIGACCDET_MASK_SFT, 0); regmap_update_bits(priv->regmap, RG_EINT0HIRENB_ADDR, RG_EINT0HIRENB_MASK_SFT, 0); } static void recover_eint_digital_setting(struct mt6359_accdet *priv) { - if (priv->caps & ACCDET_PMIC_EINT0) { - regmap_update_bits(priv->regmap, - ACCDET_EINT0_M_SW_EN_ADDR, - ACCDET_EINT0_M_SW_EN_MASK_SFT, 0); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - regmap_update_bits(priv->regmap, - ACCDET_EINT1_M_SW_EN_ADDR, - ACCDET_EINT1_M_SW_EN_MASK_SFT, 0); - } - if (priv->caps & ACCDET_PMIC_EINT0) { - /* enable eint0cen */ - regmap_update_bits(priv->regmap, ACCDET_DA_STABLE_ADDR, - ACCDET_EINT0_CEN_STABLE_MASK_SFT, - BIT(ACCDET_EINT0_CEN_STABLE_SFT)); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - /* enable eint1cen */ - regmap_update_bits(priv->regmap, ACCDET_DA_STABLE_ADDR, - ACCDET_EINT1_CEN_STABLE_MASK_SFT, - BIT(ACCDET_EINT1_CEN_STABLE_SFT)); - } - - if (priv->caps & ACCDET_PMIC_EINT0) { - /* enable inverter */ - regmap_update_bits(priv->regmap, - ACCDET_EINT0_INVERTER_SW_EN_ADDR, - ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, - BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT)); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - /* enable inverter */ - regmap_update_bits(priv->regmap, - ACCDET_EINT1_INVERTER_SW_EN_ADDR, - ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, - BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT)); - } + regmap_update_bits(priv->regmap, ACCDET_EINT0_M_SW_EN_ADDR, + ACCDET_EINT0_M_SW_EN_MASK_SFT, 0); + /* enable eint0cen */ + regmap_update_bits(priv->regmap, ACCDET_DA_STABLE_ADDR, + ACCDET_EINT0_CEN_STABLE_MASK_SFT, + BIT(ACCDET_EINT0_CEN_STABLE_SFT)); + + /* enable inverter */ + regmap_update_bits(priv->regmap, ACCDET_EINT0_INVERTER_SW_EN_ADDR, + ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, + BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT)); } static void recover_eint_setting(struct mt6359_accdet *priv) @@ -486,10 +432,8 @@ static irqreturn_t mt6359_accdet_irq(int irq, void *data) static int mt6359_accdet_parse_dt(struct mt6359_accdet *priv) { - int ret; struct device *dev = priv->dev; struct device_node *node = NULL; - unsigned int tmp = 0; node = of_get_child_by_name(dev->parent->of_node, "accdet"); if (!node) @@ -497,16 +441,6 @@ static int mt6359_accdet_parse_dt(struct mt6359_accdet *priv) priv->data->hp_eint_high = of_property_read_bool(node, "mediatek,hp-eint-high"); - ret = of_property_read_u32(node, "mediatek,eint-num", &tmp); - if (ret) - tmp = 0; - if (tmp == 0) - priv->caps |= ACCDET_PMIC_EINT0; - else if (tmp == 1) - priv->caps |= ACCDET_PMIC_EINT1; - else if (tmp == 2) - priv->caps |= ACCDET_PMIC_BI_EINT; - of_node_put(node); dev_warn(priv->dev, "accdet caps=%x\n", priv->caps); @@ -520,13 +454,8 @@ static void config_digital_init_by_mode(struct mt6359_accdet *priv) (ACCDET_EINT_CMPMEN_PWM_WIDTH_400MS << 4 | ACCDET_EINT_CMPMEN_PWM_THRESH_2MS)); /* DA signal stable */ - if (priv->caps & ACCDET_PMIC_EINT0) { - regmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR, - ACCDET_EINT0_STABLE_VAL); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - regmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR, - ACCDET_EINT1_STABLE_VAL); - } + regmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR, + ACCDET_EINT0_STABLE_VAL); /* after receive n+1 number, interrupt issued. */ regmap_update_bits(priv->regmap, ACCDET_EINT_M_PLUG_IN_NUM_ADDR, ACCDET_EINT_M_PLUG_IN_NUM_MASK_SFT, @@ -543,17 +472,9 @@ static void config_digital_init_by_mode(struct mt6359_accdet *priv) /* enable PWM */ regmap_write(priv->regmap, ACCDET_CMP_PWM_EN_ADDR, 0x67); /* enable inverter detection */ - if (priv->caps & ACCDET_PMIC_EINT0) { - regmap_update_bits(priv->regmap, - ACCDET_EINT0_INVERTER_SW_EN_ADDR, - ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, - BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT)); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - regmap_update_bits(priv->regmap, - ACCDET_EINT1_INVERTER_SW_EN_ADDR, - ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, - BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT)); - } + regmap_update_bits(priv->regmap, ACCDET_EINT0_INVERTER_SW_EN_ADDR, + ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, + BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT)); if (priv->data->hp_eint_high) { /* EINT polarity inverse */ @@ -571,13 +492,8 @@ static void config_eint_init_by_mode(struct mt6359_accdet *priv) { unsigned int val = 0; - if (priv->caps & ACCDET_PMIC_EINT0) { - regmap_update_bits(priv->regmap, RG_EINT0EN_ADDR, - RG_EINT0EN_MASK_SFT, BIT(RG_EINT0EN_SFT)); - } else if (priv->caps & ACCDET_PMIC_EINT1) { - regmap_update_bits(priv->regmap, RG_EINT1EN_ADDR, - RG_EINT1EN_MASK_SFT, BIT(RG_EINT1EN_SFT)); - } + regmap_update_bits(priv->regmap, RG_EINT0EN_ADDR, RG_EINT0EN_MASK_SFT, + BIT(RG_EINT0EN_SFT)); /* ESD switches on */ regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR, 1 << 8, 1 << 8); @@ -727,35 +643,18 @@ static int mt6359_accdet_probe(struct platform_device *pdev) } } - if (priv->caps & ACCDET_PMIC_EINT0) { - priv->accdet_eint0 = platform_get_irq(pdev, 1); - if (priv->accdet_eint0 >= 0) { - ret = devm_request_threaded_irq(&pdev->dev, - priv->accdet_eint0, - NULL, mt6359_accdet_irq, - IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - "ACCDET_EINT0", priv); - if (ret) { - dev_err(&pdev->dev, - "Failed to request eint0 IRQ (%d)\n", - ret); - return ret; - } - } - } else if (priv->caps & ACCDET_PMIC_EINT1) { - priv->accdet_eint1 = platform_get_irq(pdev, 2); - if (priv->accdet_eint1 >= 0) { - ret = devm_request_threaded_irq(&pdev->dev, - priv->accdet_eint1, - NULL, mt6359_accdet_irq, - IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - "ACCDET_EINT1", priv); - if (ret) { - dev_err(&pdev->dev, - "Failed to request eint1 IRQ (%d)\n", - ret); - return ret; - } + priv->accdet_eint0 = platform_get_irq(pdev, 1); + if (priv->accdet_eint0 >= 0) { + ret = devm_request_threaded_irq(&pdev->dev, + priv->accdet_eint0, + NULL, mt6359_accdet_irq, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, + "ACCDET_EINT0", priv); + if (ret) { + dev_err(&pdev->dev, + "Failed to request eint0 IRQ (%d)\n", + ret); + return ret; } } diff --git a/sound/soc/codecs/mt6359-accdet.h b/sound/soc/codecs/mt6359-accdet.h index 288b8fbf7c5efaee6520a2c0a5845e156f3b805d..4156cbc7f0a1744226d5f28746bd13fec6c615b4 100644 --- a/sound/soc/codecs/mt6359-accdet.h +++ b/sound/soc/codecs/mt6359-accdet.h @@ -58,7 +58,6 @@ struct mt6359_accdet { unsigned int caps; int accdet_irq; int accdet_eint0; - int accdet_eint1; struct mutex res_lock; /* lock protection */ bool jack_plugged; unsigned int jack_type; From patchwork Wed Mar 5 18:58:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 870728 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B943B2566D5; Wed, 5 Mar 2025 19:01:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741201271; cv=none; b=u2if/i+VF4TH8NM0N1pi/yNEKMHDcflmYgACRG2LN61789Btsyp+BSAzXHAdP2w/NwpMhT1Ydjs2YDk4wZvko/YaIXgjNK8TRmNeKpP7wtZrj5y9vXxwHvNuBWpZYZ800Q9aH0mTjkVj5wjpxzlr35cd9Cf8UbEInIvwc49C7Q4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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d=collabora.com; s=mail; t=1741201268; bh=SY9RMAoowz8kStVuJuN4tunjUBmeihKNe9Rk0kme8RY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=PQtIzf62eW0GlpOSlr5Fgk291A6n8EhTi8vPORawuClgGOblg8Q9uqZwpCPCc4t7F aLRAxH850zcBKyzivPA3cQPYjHwYOJ7T9nil4op27shlLSzzqv1skvuSPfRQnLSlvG c1Klb5PfBA7rEv+dSKx7jUT3M+Bcip4S7ieqptpX7WwWlC3JXeCbju5dtvLT6dQX4c jMN295cwo4Kbflu7zDKmVJXRhV7F/0amm92o2ah+CTZJ0jdQcN50Wf5TZK3O41t2KO vc39RdsHr2VE9A7dX6fVyoRxJjrFkgDsDS9kR0IkWwfFstV2xNeH3hG33KAt5yH209 kdiW6rg17VoVA== Received: from [192.168.0.47] (unknown [IPv6:2804:14c:1a9:53ee::1004]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 0511B17E0147; Wed, 5 Mar 2025 20:01:02 +0100 (CET) From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= Date: Wed, 05 Mar 2025 15:58:34 -0300 Subject: [PATCH v4 19/19] arm64: defconfig: Enable MT6359 ACCDET Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250305-mt6359-accdet-dts-v4-19-e5ffa5ee9991@collabora.com> References: <20250305-mt6359-accdet-dts-v4-0-e5ffa5ee9991@collabora.com> In-Reply-To: <20250305-mt6359-accdet-dts-v4-0-e5ffa5ee9991@collabora.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Jaroslav Kysela , Takashi Iwai , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Mailer: b4 0.14.2 Enable support for the ACCDET block in the MT6359 PMIC, which provides jack detection capabilities to MediaTek platforms. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nícolas F. R. A. Prado --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 3a3706db29822036d25a7228f8936e2ad613b208..d4a6eeec8ba0db110dd831e146716a0e50cc294f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1066,6 +1066,7 @@ CONFIG_SND_SOC_WM8978=m CONFIG_SND_SOC_WSA881X=m CONFIG_SND_SOC_WSA883X=m CONFIG_SND_SOC_WSA884X=m +CONFIG_SND_SOC_MT6359_ACCDET=m CONFIG_SND_SOC_NAU8822=m CONFIG_SND_SOC_LPASS_WSA_MACRO=m CONFIG_SND_SOC_LPASS_VA_MACRO=m