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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c103290sm2339957f8f.87.2025.03.06.07.47.42 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:47:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 01/54] qemu/compiler: Absorb 'clang-tsa.h' Date: Thu, 6 Mar 2025 16:46:43 +0100 Message-ID: <20250306154737.70886-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We already have "qemu/compiler.h" for compiler-specific arrangements, automatically included by "qemu/osdep.h" for each source file. No need to explicitly include a header for a Clang particularity. Suggested-by: Pierrick Bouvier Reviewed-by: Pierrick Bouvier Reviewed-by: Alex Bennée Reviewed-by: Kevin Wolf Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250117170201.91182-1-philmd@linaro.org> --- bsd-user/qemu.h | 1 - include/block/block_int-common.h | 1 - include/block/graph-lock.h | 2 - include/exec/page-protection.h | 2 - include/qemu/clang-tsa.h | 114 ------------------------------- include/qemu/compiler.h | 96 ++++++++++++++++++++++++++ include/qemu/thread.h | 1 - block/create.c | 1 - tests/unit/test-bdrv-drain.c | 1 - tests/unit/test-block-iothread.c | 1 - util/qemu-thread-posix.c | 1 - 11 files changed, 96 insertions(+), 125 deletions(-) delete mode 100644 include/qemu/clang-tsa.h diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index 3eaa14f3f56..4e97c796318 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -40,7 +40,6 @@ extern char **environ; #include "target.h" #include "exec/gdbstub.h" #include "exec/page-protection.h" -#include "qemu/clang-tsa.h" #include "accel/tcg/vcpu-state.h" #include "qemu-os.h" diff --git a/include/block/block_int-common.h b/include/block/block_int-common.h index bb91a0f62fa..ebb4e56a503 100644 --- a/include/block/block_int-common.h +++ b/include/block/block_int-common.h @@ -28,7 +28,6 @@ #include "block/block-common.h" #include "block/block-global-state.h" #include "block/snapshot.h" -#include "qemu/clang-tsa.h" #include "qemu/iov.h" #include "qemu/rcu.h" #include "qemu/stats64.h" diff --git a/include/block/graph-lock.h b/include/block/graph-lock.h index dc8d9491843..2c26c721081 100644 --- a/include/block/graph-lock.h +++ b/include/block/graph-lock.h @@ -20,8 +20,6 @@ #ifndef GRAPH_LOCK_H #define GRAPH_LOCK_H -#include "qemu/clang-tsa.h" - /** * Graph Lock API * This API provides a rwlock used to protect block layer diff --git a/include/exec/page-protection.h b/include/exec/page-protection.h index bae3355f62c..3e0a8a03331 100644 --- a/include/exec/page-protection.h +++ b/include/exec/page-protection.h @@ -40,8 +40,6 @@ #ifdef CONFIG_USER_ONLY -#include "qemu/clang-tsa.h" - void TSA_NO_TSA mmap_lock(void); void TSA_NO_TSA mmap_unlock(void); bool have_mmap_lock(void); diff --git a/include/qemu/clang-tsa.h b/include/qemu/clang-tsa.h deleted file mode 100644 index ba06fb8c924..00000000000 --- a/include/qemu/clang-tsa.h +++ /dev/null @@ -1,114 +0,0 @@ -#ifndef CLANG_TSA_H -#define CLANG_TSA_H - -/* - * Copyright 2018 Jarkko Hietaniemi - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without - * limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -/* http://clang.llvm.org/docs/ThreadSafetyAnalysis.html - * - * TSA is available since clang 3.6-ish. - */ -#ifdef __clang__ -# define TSA(x) __attribute__((x)) -#else -# define TSA(x) /* No TSA, make TSA attributes no-ops. */ -#endif - -/* TSA_CAPABILITY() is used to annotate typedefs: - * - * typedef pthread_mutex_t TSA_CAPABILITY("mutex") tsa_mutex; - */ -#define TSA_CAPABILITY(x) TSA(capability(x)) - -/* TSA_GUARDED_BY() is used to annotate global variables, - * the data is guarded: - * - * Foo foo TSA_GUARDED_BY(mutex); - */ -#define TSA_GUARDED_BY(x) TSA(guarded_by(x)) - -/* TSA_PT_GUARDED_BY() is used to annotate global pointers, the data - * behind the pointer is guarded. - * - * Foo* ptr TSA_PT_GUARDED_BY(mutex); - */ -#define TSA_PT_GUARDED_BY(x) TSA(pt_guarded_by(x)) - -/* The TSA_REQUIRES() is used to annotate functions: the caller of the - * function MUST hold the resource, the function will NOT release it. - * - * More than one mutex may be specified, comma-separated. - * - * void Foo(void) TSA_REQUIRES(mutex); - */ -#define TSA_REQUIRES(...) TSA(requires_capability(__VA_ARGS__)) -#define TSA_REQUIRES_SHARED(...) TSA(requires_shared_capability(__VA_ARGS__)) - -/* TSA_EXCLUDES() is used to annotate functions: the caller of the - * function MUST NOT hold resource, the function first acquires the - * resource, and then releases it. - * - * More than one mutex may be specified, comma-separated. - * - * void Foo(void) TSA_EXCLUDES(mutex); - */ -#define TSA_EXCLUDES(...) TSA(locks_excluded(__VA_ARGS__)) - -/* TSA_ACQUIRE() is used to annotate functions: the caller of the - * function MUST NOT hold the resource, the function will acquire the - * resource, but NOT release it. - * - * More than one mutex may be specified, comma-separated. - * - * void Foo(void) TSA_ACQUIRE(mutex); - */ -#define TSA_ACQUIRE(...) TSA(acquire_capability(__VA_ARGS__)) -#define TSA_ACQUIRE_SHARED(...) TSA(acquire_shared_capability(__VA_ARGS__)) - -/* TSA_RELEASE() is used to annotate functions: the caller of the - * function MUST hold the resource, but the function will then release it. - * - * More than one mutex may be specified, comma-separated. - * - * void Foo(void) TSA_RELEASE(mutex); - */ -#define TSA_RELEASE(...) TSA(release_capability(__VA_ARGS__)) -#define TSA_RELEASE_SHARED(...) TSA(release_shared_capability(__VA_ARGS__)) - -/* TSA_NO_TSA is used to annotate functions. Use only when you need to. - * - * void Foo(void) TSA_NO_TSA; - */ -#define TSA_NO_TSA TSA(no_thread_safety_analysis) - -/* - * TSA_ASSERT() is used to annotate functions: This function will assert that - * the lock is held. When it returns, the caller of the function is assumed to - * already hold the resource. - * - * More than one mutex may be specified, comma-separated. - */ -#define TSA_ASSERT(...) TSA(assert_capability(__VA_ARGS__)) -#define TSA_ASSERT_SHARED(...) TSA(assert_shared_capability(__VA_ARGS__)) - -#endif /* #ifndef CLANG_TSA_H */ diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index d904408e5ed..496dac5ac11 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -207,6 +207,102 @@ # define QEMU_USED #endif +/* + * http://clang.llvm.org/docs/ThreadSafetyAnalysis.html + * + * TSA is available since clang 3.6-ish. + */ +#ifdef __clang__ +# define TSA(x) __attribute__((x)) +#else +# define TSA(x) /* No TSA, make TSA attributes no-ops. */ +#endif + +/* + * TSA_CAPABILITY() is used to annotate typedefs: + * + * typedef pthread_mutex_t TSA_CAPABILITY("mutex") tsa_mutex; + */ +#define TSA_CAPABILITY(x) TSA(capability(x)) + +/* + * TSA_GUARDED_BY() is used to annotate global variables, + * the data is guarded: + * + * Foo foo TSA_GUARDED_BY(mutex); + */ +#define TSA_GUARDED_BY(x) TSA(guarded_by(x)) + +/* + * TSA_PT_GUARDED_BY() is used to annotate global pointers, the data + * behind the pointer is guarded. + * + * Foo* ptr TSA_PT_GUARDED_BY(mutex); + */ +#define TSA_PT_GUARDED_BY(x) TSA(pt_guarded_by(x)) + +/* + * The TSA_REQUIRES() is used to annotate functions: the caller of the + * function MUST hold the resource, the function will NOT release it. + * + * More than one mutex may be specified, comma-separated. + * + * void Foo(void) TSA_REQUIRES(mutex); + */ +#define TSA_REQUIRES(...) TSA(requires_capability(__VA_ARGS__)) +#define TSA_REQUIRES_SHARED(...) TSA(requires_shared_capability(__VA_ARGS__)) + +/* + * TSA_EXCLUDES() is used to annotate functions: the caller of the + * function MUST NOT hold resource, the function first acquires the + * resource, and then releases it. + * + * More than one mutex may be specified, comma-separated. + * + * void Foo(void) TSA_EXCLUDES(mutex); + */ +#define TSA_EXCLUDES(...) TSA(locks_excluded(__VA_ARGS__)) + +/* + * TSA_ACQUIRE() is used to annotate functions: the caller of the + * function MUST NOT hold the resource, the function will acquire the + * resource, but NOT release it. + * + * More than one mutex may be specified, comma-separated. + * + * void Foo(void) TSA_ACQUIRE(mutex); + */ +#define TSA_ACQUIRE(...) TSA(acquire_capability(__VA_ARGS__)) +#define TSA_ACQUIRE_SHARED(...) TSA(acquire_shared_capability(__VA_ARGS__)) + +/* + * TSA_RELEASE() is used to annotate functions: the caller of the + * function MUST hold the resource, but the function will then release it. + * + * More than one mutex may be specified, comma-separated. + * + * void Foo(void) TSA_RELEASE(mutex); + */ +#define TSA_RELEASE(...) TSA(release_capability(__VA_ARGS__)) +#define TSA_RELEASE_SHARED(...) TSA(release_shared_capability(__VA_ARGS__)) + +/* + * TSA_NO_TSA is used to annotate functions. Use only when you need to. + * + * void Foo(void) TSA_NO_TSA; + */ +#define TSA_NO_TSA TSA(no_thread_safety_analysis) + +/* + * TSA_ASSERT() is used to annotate functions: This function will assert that + * the lock is held. When it returns, the caller of the function is assumed to + * already hold the resource. + * + * More than one mutex may be specified, comma-separated. + */ +#define TSA_ASSERT(...) TSA(assert_capability(__VA_ARGS__)) +#define TSA_ASSERT_SHARED(...) TSA(assert_shared_capability(__VA_ARGS__)) + /* * Ugly CPP trick that is like "defined FOO", but also works in C * code. Useful to replace #ifdef with "if" statements; assumes diff --git a/include/qemu/thread.h b/include/qemu/thread.h index 7eba27a7049..6f800aad31a 100644 --- a/include/qemu/thread.h +++ b/include/qemu/thread.h @@ -3,7 +3,6 @@ #include "qemu/processor.h" #include "qemu/atomic.h" -#include "qemu/clang-tsa.h" typedef struct QemuCond QemuCond; typedef struct QemuSemaphore QemuSemaphore; diff --git a/block/create.c b/block/create.c index 72abafb4c12..6b23a216753 100644 --- a/block/create.c +++ b/block/create.c @@ -24,7 +24,6 @@ #include "qemu/osdep.h" #include "block/block_int.h" -#include "qemu/clang-tsa.h" #include "qemu/job.h" #include "qemu/main-loop.h" #include "qapi/qapi-commands-block-core.h" diff --git a/tests/unit/test-bdrv-drain.c b/tests/unit/test-bdrv-drain.c index 98ad89b390c..7410e6f3528 100644 --- a/tests/unit/test-bdrv-drain.c +++ b/tests/unit/test-bdrv-drain.c @@ -28,7 +28,6 @@ #include "system/block-backend.h" #include "qapi/error.h" #include "qemu/main-loop.h" -#include "qemu/clang-tsa.h" #include "iothread.h" static QemuEvent done_event; diff --git a/tests/unit/test-block-iothread.c b/tests/unit/test-block-iothread.c index 7324ea4a68d..2b358eaaa82 100644 --- a/tests/unit/test-block-iothread.c +++ b/tests/unit/test-block-iothread.c @@ -29,7 +29,6 @@ #include "system/block-backend.h" #include "qapi/error.h" #include "qobject/qdict.h" -#include "qemu/clang-tsa.h" #include "qemu/main-loop.h" #include "iothread.h" diff --git a/util/qemu-thread-posix.c b/util/qemu-thread-posix.c index 6fff4162ac6..b2e26e21205 100644 --- a/util/qemu-thread-posix.c +++ b/util/qemu-thread-posix.c @@ -17,7 +17,6 @@ #include "qemu-thread-common.h" #include "qemu/tsan.h" #include "qemu/bitmap.h" -#include "qemu/clang-tsa.h" #ifdef CONFIG_PTHREAD_SET_NAME_NP #include From patchwork Thu Mar 6 15:46:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870831 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp331472wri; Thu, 6 Mar 2025 07:48:32 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVbd099x0A/0sWcnJjRii5PkRjvv5T3Zf/ooVntNBFLvRYt3XTngcpkcVUKCjUR8rTSDgOjgA==@linaro.org X-Google-Smtp-Source: AGHT+IE7wqXHxmokZgFmtPcsw0+RsesGKuE4FfHeu+BZj2LT1d42EcSfegp45IUn1+AmeWRolcIl X-Received: by 2002:a05:6214:ca7:b0:6e8:903c:6e5b with SMTP id 6a1803df08f44-6e8f46e46f0mr47797776d6.9.1741276112066; Thu, 06 Mar 2025 07:48:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276112; cv=none; d=google.com; s=arc-20240605; b=Y9JjXQMMozjO1GInQJ4s6aaoY1DgtkJwFRiWeF+P/R6wk8MBiSJge4SD4GXb9cdYw1 Hv9+M97iNVsM7Mhktk0ZlSOcmmBiPp3woRwmYUQd4i/3v9kwsqZvrpEVmqc6wKU24OIg 5HQ09tgWjl8YwgwWsAEAKvu7Q/olkFNCtleMYGMHIWTKfC978fpvKHPMru3uossaCyGI gOOMqDVL4bgc5+PUxBz9UJ0TYlTJa5gHVshf8XDYePt8pQCyo3DvvPvN8LLUiByHzOEu BGT/yEMwpaXNeM/oyVtuayl0SMNugJborfTyZnfoYPbs8k9rxRI66sHnkE69XjBwnkfK IYjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ps7cd0cxm4BakNCXqH/ls7rCDQIclvSwSBPha/6qx+g=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=jmXzd8CasT0JT+VHGfUEwfJZFfdnAZOFma4vPg7AVhu/yDT8/hiSsBOfXx0WFG+hBp gJfYnjf0t0LJjdEc49qSeNo2ymGUIhlLM7KqoibhCnLkMWYeydQe6yC0uUdSb5y/R8TW boauAJtwF/c6L3oieHVFU/IWvnpOthXQUHA9SprGc5k/wbL6BBylwex5Uxpe0NHTPri7 nYkhKaYsMY8dBdAjwP66pM+wdwvm0Bs1FYGG+3gqZ7bSHbapTM1xpkaiLewwNw0eoYQf 9RBG/+KjoJ7wUJ9FxxVY8bFM0MY5fxRYr7DQZwbEXeTdNk19+3afGoR0MWF/7yXQ8TpU +lkQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MJR5X6KW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd42c55e6sm53006655e9.23.2025.03.06.07.47.47 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:47:47 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 02/54] gdbstub: Clarify no more than @gdb_num_core_regs can be accessed Date: Thu, 6 Mar 2025 16:46:44 +0100 Message-ID: <20250306154737.70886-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Both CPUClass::gdb_read_register() and CPUClass::gdb_write_register() handlers are called from common gdbstub code, and won't be called with register index over CPUClass::gdb_num_core_regs: int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) { CPUClass *cc = CPU_GET_CLASS(cpu); if (reg < cc->gdb_num_core_regs) { return cc->gdb_read_register(cpu, buf, reg); } ... } static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg) { CPUClass *cc = CPU_GET_CLASS(cpu); if (reg < cc->gdb_num_core_regs) { return cc->gdb_write_register(cpu, mem_buf, reg); } ... } Clarify that in CPUClass docstring, and remove unreachable code on the microblaze and openrisc implementations. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-Id: <20250122093028.52416-3-philmd@linaro.org> --- include/hw/core/cpu.h | 2 ++ target/microblaze/gdbstub.c | 5 ----- target/openrisc/gdbstub.c | 5 ----- 3 files changed, 2 insertions(+), 10 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fb397cdfc53..7b6b22c431b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -124,7 +124,9 @@ struct SysemuCPUOps; * @get_pc: Callback for getting the Program Counter register. * As above, with the semantics of the target architecture. * @gdb_read_register: Callback for letting GDB read a register. + * No more than @gdb_num_core_regs registers can be read. * @gdb_write_register: Callback for letting GDB write a register. + * No more than @gdb_num_core_regs registers can be written. * @gdb_adjust_breakpoint: Callback for adjusting the address of a * breakpoint. Used by AVR to handle a gdb mis-feature with * its Harvard architecture split code and data. diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 09d74e164d0..d493681d38d 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -110,14 +110,9 @@ int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *mem_buf, int n) int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - CPUClass *cc = CPU_GET_CLASS(cs); CPUMBState *env = cpu_env(cs); uint32_t tmp; - if (n > cc->gdb_num_core_regs) { - return 0; - } - tmp = ldl_p(mem_buf); switch (n) { diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c index c2a77d5d4d5..45bba80d878 100644 --- a/target/openrisc/gdbstub.c +++ b/target/openrisc/gdbstub.c @@ -47,14 +47,9 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - CPUClass *cc = CPU_GET_CLASS(cs); CPUOpenRISCState *env = cpu_env(cs); uint32_t tmp; - if (n > cc->gdb_num_core_regs) { - return 0; - } - tmp = ldl_p(mem_buf); if (n < 32) { From patchwork Thu Mar 6 15:46:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870830 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp331305wri; Thu, 6 Mar 2025 07:48:12 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWKQ2qLeyNIUlgd1Mypt7fLAJD2SNYHogTUMhtaurB/CkX+5otWe9nbdnrOEV1G8C0tS3HLOw==@linaro.org X-Google-Smtp-Source: AGHT+IHNtAgQkEGXArhPBazsA/Ocn+seMF3yM0MMJqB4ZkQpYD/aPmcKzg4z7IPhDKW14p+VVdgu X-Received: by 2002:a05:6214:d0c:b0:6e8:96aa:6034 with SMTP id 6a1803df08f44-6e8e6d13ee7mr105860726d6.3.1741276092649; Thu, 06 Mar 2025 07:48:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276092; cv=none; d=google.com; s=arc-20240605; b=eVlulAgv/NQjOmd/NsKTYntSsE+e9cOkcJeoSR69DZxjhLBBttz3CTJr8JxE6nGeGX FdAxgn6lPUP01T76Ez8x75hMwhAjEnwTEgc1IJa9A3iirvLN2fLhxzBJZwX3y5+xEciG GFY3z72SNnY+cwD0U8xUyGm1IggVaCia4TdOhMX4nsBEXjW/5Kd3H8V5UQP0Oijphm+4 efdRWSRkGz/79fLp2iq5sYUGk7d2wpx0LXsbB8pAGxOVuP755B6zn6hFpqcVMmYR9KtW Fi94I3bK8kodQjUPTkQwyLGwFa7ZZpNS250MHI29zhj196zSbDU57GC5KDQsEJ1GTlpE rrfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=keumHK/xGB74dShNqulk/5Z/c6mVK2UvLucS0OMjfzY=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=bTOO5gB7M2vJA0SSMzFRbxhd/FVqMe9+OgVl78NUpHqwtcyHsuncSld2vlxPsZgDqU fdlyhwTnngI7NbCm/YqXINmwgJIaRzxNXGnFz9pUIb55olcl0iDSG/42XzwENFMLl9cs eMba7m6zggUG03RHu4NyeAIm7zaywx8D2TN26RSkUDn/JCSCl8nm+Mr6mb6WlwtpkE/j fsEeY6fFX/gaK74fZLA+5MPrvHW3lGFjzmVV7K97V4lpKE/DN2rypsEtON8HmGMOK6wx +6SlH18Oy2zts9W4zDia5bCWSDUfckRxmGhNc4wOMdzwLYsIOCLqpGceidV88ExWlMYu Ye2g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mfOo+0B7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfba66esm2442214f8f.18.2025.03.06.07.47.51 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:47:52 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 03/54] gdbstub: Check for TCG before calling tb_flush() Date: Thu, 6 Mar 2025 16:46:45 +0100 Message-ID: <20250306154737.70886-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use the tcg_enabled() check so the compiler can elide the call when TCG isn't available, allowing to remove the tb_flush() stub. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20250123234415.59850-4-philmd@linaro.org> --- accel/stubs/tcg-stub.c | 4 ---- gdbstub/system.c | 5 ++++- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index 7f4208fddf2..b2b9881bdfb 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -14,10 +14,6 @@ #include "exec/tb-flush.h" #include "exec/exec-all.h" -void tb_flush(CPUState *cpu) -{ -} - G_NORETURN void cpu_loop_exit(CPUState *cpu) { g_assert_not_reached(); diff --git a/gdbstub/system.c b/gdbstub/system.c index 8ce79fa88cf..7f047a285c8 100644 --- a/gdbstub/system.c +++ b/gdbstub/system.c @@ -22,6 +22,7 @@ #include "system/cpus.h" #include "system/runstate.h" #include "system/replay.h" +#include "system/tcg.h" #include "hw/core/cpu.h" #include "hw/cpu/cluster.h" #include "hw/boards.h" @@ -171,7 +172,9 @@ static void gdb_vm_state_change(void *opaque, bool running, RunState state) } else { trace_gdbstub_hit_break(); } - tb_flush(cpu); + if (tcg_enabled()) { + tb_flush(cpu); + } ret = GDB_SIGNAL_TRAP; break; case RUN_STATE_PAUSED: From patchwork Thu Mar 6 15:46:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870833 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp331634wri; Thu, 6 Mar 2025 07:48:57 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWU2qzU8fNtljHjbF59QpR2JgJCamrtua2RMyhs1yG4pKM7SOFoeWz+t63tHPN0WTVHx+pXmg==@linaro.org X-Google-Smtp-Source: AGHT+IF9+crjGFhfGBDPSACv1S1t04llDvJJL+Nyi/v9rGfAabhs16/We8jiIV5Oym4nKunbDbH+ X-Received: by 2002:a05:6214:e4b:b0:6e6:61a5:aa57 with SMTP id 6a1803df08f44-6e8e6d19537mr112013196d6.14.1741276137465; Thu, 06 Mar 2025 07:48:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276137; cv=none; d=google.com; s=arc-20240605; b=MUmLikA2GpV+/3iYpN0kFqx2Udcx35hp4wQ2FxUf88HFDVmG38j3gfgd3jhH/xhwL3 KO9HAM7NudCc8kTvQctWLvD0hyIoDe1cu8WeZHmb4rGNsV2nQsA7AGBWxNiRg47V4yHJ cZCpEe5sowNOFIiPj2mq+eBAg/Mh/T03s6qw2oSUc8A0LSasmwAhWnbo5JzGb9DG4yvZ YVabLDHna+FPBr9OjU6KaPVwGDB7qbzYrYwYzcrq9dBY813Jzo8uz57wMjDsRjwrE1CE NdMvnEM+36/oa47J1W6vpBw+wYeZ0FVfFPNYVCfa1w1UeUxBimtjzv9qHk/MpE6R8QWQ TqBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ibKdWczve1piqobnZ/7eakxu3MNnTBDuUSaIAp0/9Gg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=U//HkT5NSrxpVS/4UPOmHWTx/ZYSUcDh7P1m4CrCVsZ0pyVj+vNuzzi5Gx3U+DB9JC Dg7SCXIkU2qh1kxAcmlPz/2Idl05NYc2dHrbjr0BsnEW7YnTGEMpccIwk7Y2LzVw9pEb IBbxQtYwuPPXMwdSALCDEoEXkgrLNLLxJdWlF3+GyOFLQSbvrgMEv45iJUuTh+UfbZ8G lj5DHwdtIuGge2tmilnLFp9pxZDTBOdsRKcobtSut+vJPX6mhHQkgA68uBAM1sONUlHj 0YeR42+jv+bZoHPV5s4+9w3GscpuUx8Kk5bzX97TZl7tGLyuzIN5cBY6ep07KxRVPj9E /tjg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M34fM6l8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd4291cb9sm53396655e9.13.2025.03.06.07.47.56 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:47:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 04/54] cpus: Cache CPUClass early in instance_init() handler Date: Thu, 6 Mar 2025 16:46:46 +0100 Message-ID: <20250306154737.70886-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Cache CPUClass as early as possible, when the instance is initialized. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250123234415.59850-5-philmd@linaro.org> --- cpu-target.c | 3 --- hw/core/cpu-common.c | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index 667688332c9..89874496a41 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -134,9 +134,6 @@ const VMStateDescription vmstate_cpu_common = { bool cpu_exec_realizefn(CPUState *cpu, Error **errp) { - /* cache the cpu class for the hotpath */ - cpu->cc = CPU_GET_CLASS(cpu); - if (!accel_cpu_common_realize(cpu, errp)) { return false; } diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index cb79566cc51..ff605059c15 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -238,6 +238,9 @@ static void cpu_common_initfn(Object *obj) { CPUState *cpu = CPU(obj); + /* cache the cpu class for the hotpath */ + cpu->cc = CPU_GET_CLASS(cpu); + gdb_init_cpu(cpu); cpu->cpu_index = UNASSIGNED_CPU_INDEX; cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX; From patchwork Thu Mar 6 15:46:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870832 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp331507wri; Thu, 6 Mar 2025 07:48:36 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCV3LRqjpHfjfYbCfZJJyc3SDEUGhQ9O5oSX+minYn5PoTR4H+Oal+7my2uwsg1I7zx/+Xk5SA==@linaro.org X-Google-Smtp-Source: AGHT+IFoCy/rOSLa7GiJzmIQlkAN4uzmO2hnn3N9qlX8+Nzd/VtMU0KO1BIVShtZf+jex8Ui0LR3 X-Received: by 2002:a05:622a:1311:b0:474:f14a:dc with SMTP id d75a77b69052e-4750b4482e9mr99843571cf.21.1741276116373; Thu, 06 Mar 2025 07:48:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276116; cv=none; d=google.com; s=arc-20240605; b=kvDJBAPpqHmRiLI7psOPNtZixbGa6MdRNC2qHwWBaRBJ05bg2XrkblEl2inu8HvmKT MocH0PnvL9p9e4h8CsEYnSW9y1aPoHq494JWrRGyOFoGJ/KJlHmkNNQXOTVoEpXWPwt6 JFb3kRvPIu61ZyFhhmeSxSgTnpTr1/g0Jx3DDHoHfRjFRX1C28IqC73Y4DuLBWtR6iDs XaNHUVpk+FY9zxuF+Ze47dfneYYA2PIxYDrKlOeDtU6b1vmqyZEQ2aAqNGdusIABLvdf 2o42M0UP4laY8aUhKym2mWI38eOHdro979c+PWX3AJaNokdcuFvxpO8boP7EXpeWSn+s ZBSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xl77zu7UFkgjzNSNZL8yu/Xtui1L+RH1bzoJQrDO/y0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=cBynZtI+XLqqdiKWwnmSsMN5yVf1LXEDhn1ZwlAmTxqpFU/7Cs5WO+aL0WyN604qK8 /OfQSl2+gFrhvBt/VGx1XjcV1YRP2w1aHOMdmBs/rYjfLsDm1n5KIYdFmqmza8dpBbhf tOmxbECieYew0I+OtAnkkbU4LXAET2j1cuNWOtiQqNjeo2Z6PDRI8GnZgx6WOhcPI8Bb mD55bXbffq5CHxGtXjVRPNb/KWLzmD3TsDdwMbj+pQL8MoIUJF33I5r/4yckQl9hmHUK jkJ5qQ2qogg31uZP0rKwEgetnZvAF13i+m5oczQYmH5IhsBiv3NWS1dwRYUJyDB3iEIp ylgQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UtpyE253; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfba87csm2457133f8f.17.2025.03.06.07.48.00 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:48:00 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 05/54] cpus: Keep default fields initialization in cpu_common_initfn() Date: Thu, 6 Mar 2025 16:46:47 +0100 Message-ID: <20250306154737.70886-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org cpu_common_initfn() is our target agnostic initializer, while cpu_exec_initfn() is the target specific one. The %as and %num_ases fields are not target specific, so initialize them in the common helper. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250123234415.59850-6-philmd@linaro.org> --- cpu-target.c | 3 --- hw/core/cpu-common.c | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index 89874496a41..75501a909df 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -234,9 +234,6 @@ void cpu_class_init_props(DeviceClass *dc) void cpu_exec_initfn(CPUState *cpu) { - cpu->as = NULL; - cpu->num_ases = 0; - #ifndef CONFIG_USER_ONLY cpu->memory = get_system_memory(); object_ref(OBJECT(cpu->memory)); diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index ff605059c15..71425cb7422 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -244,6 +244,8 @@ static void cpu_common_initfn(Object *obj) gdb_init_cpu(cpu); cpu->cpu_index = UNASSIGNED_CPU_INDEX; cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX; + cpu->as = NULL; + cpu->num_ases = 0; /* user-mode doesn't have configurable SMP topology */ /* the default value is changed by qemu_init_vcpu() for system-mode */ cpu->nr_threads = 1; From patchwork Thu Mar 6 15:46:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870836 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp331958wri; Thu, 6 Mar 2025 07:49:48 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXNxuLFQWTLHudVeKCjGEMXjTv6DJJO44W4MOFfsKdYmvkl1sBPZg05BzczNESYwA8eGabSgw==@linaro.org X-Google-Smtp-Source: AGHT+IGG56ZOffJ0oLjB2XZ0sinyRLyKhVppK4J2YZzQyN9M1wDgttkNfsT8kfvQaae+FaoobrVi X-Received: by 2002:a05:6214:4008:b0:6e6:64e8:28e7 with SMTP id 6a1803df08f44-6e8e6cce0cdmr100159876d6.15.1741276188091; Thu, 06 Mar 2025 07:49:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276188; cv=none; d=google.com; s=arc-20240605; b=RILT42zdLE+JIpfQyeLjdFyD/r50JUNl0DGH7CItwkTopON7/X8o4mMr1OHbPVDZ4t hHEDreqQh6AQsqOtBfFQy2A1bLcIrsTemcmpxOS45JHdWXj8AFq8kx00nzO+K3jiWvty IflIPpd3q9TOIYtQKk0y1kvVuBpz03jIEo0dTV/RD7cHmDqD8IB31NzU6DO2RcYwRKpS F9Pw71tAoHO8hnE7KNK3dCgr/uDVkaSCMyoap8FDhwO0HEXy13c+rQOd12m7/fzJ3Y5Z 8nqr0cgxr1M3YQYaZ0ACvvp1COnBcz7glINiNHDe84X1RAzZynkXPOilyxPUV2eGSza1 2T2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jYtwJvU4r0akXgP5T1pK8wv7rwtoSTLrcOo1FyW8tGY=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=AcmbysXglJtM7VpbSWR7RtrOuAPIKKaqX9jb7kViLcspvUZzzRWZweD/ycuIsAsYtm h2DlYKabj31tE35k1XtPnb+5ey1qdEvwczJ112hVuvuwlu0QTX9vmbFwB0qdPYgI27Hf s8hNv7vyEoS8PLMOmUiHnxvOOLA7M0VeDU3GxPQUE9YGgFHqS2CjlD18oY1Oi4UZ8Rt8 kqzNk14e6xCbL6nuds///h3tu08DkUe7iNuZ3MxSYvLB8w9hXa647lfjfU6YVBSguqjx Jek61NraYS4f6xoptfx7W6XZrBDaTbMqoFUeYBziZShqnZ8V8vxU7gsVo0FrTTTX/CZq 79bw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AjKpw0Qb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd4352fa3sm53125305e9.30.2025.03.06.07.48.04 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:48:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 06/54] accel/accel: Make TYPE_ACCEL abstract Date: Thu, 6 Mar 2025 16:46:48 +0100 Message-ID: <20250306154737.70886-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé There is no generic acceleration, we have to use specific implementations. Make the base class abstract. Fixes: b14a0b7469fa ("accel: Use QOM classes for accel types") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cornelia Huck Message-Id: <20200129212345.20547-3-philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- accel/accel-target.c | 1 + 1 file changed, 1 insertion(+) diff --git a/accel/accel-target.c b/accel/accel-target.c index 08626c00c2d..3236d6335b1 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -38,6 +38,7 @@ static const TypeInfo accel_type = { .parent = TYPE_OBJECT, .class_size = sizeof(AccelClass), .instance_size = sizeof(AccelState), + .abstract = true, }; /* Lookup AccelClass from opt_name. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfba66esm2442919f8f.18.2025.03.06.07.48.09 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:48:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 07/54] accel/tcg: Remove pointless initialization of cflags_next_tb Date: Thu, 6 Mar 2025 16:46:49 +0100 Message-ID: <20250306154737.70886-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org cflags_next_tb is always re-initialized in the CPU Reset() handler in cpu_common_reset_hold(), no need to initialize it in cpu_common_initfn(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240427155714.53669-13-philmd@linaro.org> --- hw/core/cpu-common.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 71425cb7422..d5cd227fe6d 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -249,7 +249,6 @@ static void cpu_common_initfn(Object *obj) /* user-mode doesn't have configurable SMP topology */ /* the default value is changed by qemu_init_vcpu() for system-mode */ cpu->nr_threads = 1; - cpu->cflags_next_tb = -1; /* allocate storage for thread info, initialise condition variables */ cpu->thread = g_new0(QemuThread, 1); From patchwork Thu Mar 6 15:46:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870834 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp331881wri; Thu, 6 Mar 2025 07:49:37 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVngpkC4sFoHgioDa0zHfvZPSzl6RXK5EZy71ztFdcu/8mraxI932QLINCegd7t6rxLRSU++w==@linaro.org X-Google-Smtp-Source: AGHT+IFnpzyoAmtGI1ZcS+z2T0Vqf9szs2tAwVBzu/Hp+FOeM6J/WQGWcE3gbTE7j3/U0xiHoQvb X-Received: by 2002:a05:620a:2791:b0:7c0:a075:3d93 with SMTP id af79cd13be357-7c3d8b8f9a0mr1080379285a.0.1741276177144; Thu, 06 Mar 2025 07:49:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276177; cv=none; d=google.com; s=arc-20240605; b=WZ29D+hYEBTk0CUjb2LiDxHejIWFgJXkzcULEY/qxPdVTz6fPfEjFCBnDqc/u9iPfL rXhfm/KjbIVe9d9umHF/Xmar+dly5UWeB9K0ST5S5je6NP6riqPcjpBU55ktMoVNidVV iB8afJ8q5hDXEJ3RVvu0i9gOeDxiDY5GtOCYmKWZ4S0n9EzkQegZExegd45jwC+4cae0 wWjOxSJarlcqx3WFNP325fr3JlGg4A4ML1eKCFNbXrGTY0cOB5FdiWoN8CXI/2y6/uZs oPIGF+gRRL9krNlkntMC/wASc6kS7Wu+GSTApOuTZ4O6cdUdzbv7idDBNVgTYQQryLsk iwQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=M9A95hGDz5OZUoNsympsnyo0yFXJkzG7hpn3X+K4ObM=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=ZxqISRfJ3TBhteXn2iUudEa2mYSH5pfhxa7PZLVT4w6UQuUfMDDiAKvUXugyQbmo8y 4lFo0J948okPfZAt7AkHtrboBH3tTfn8F0Lb2eEeuKVOjyFHFrlOXuySKf69PKDqkRlQ 6ZZ0xFQGYILqx+XQeHcRJRg6d7YzuQ7O0WXyhchl0dRlcxWKXlWRZ/LWC0ooyYjhIyY9 1jXvWR7rykneviN3sieFNl5vJLG8pzrcdOerKR5u17nhEpjdmibXrmcvdrr//T+1gAwJ S+nLAxfjzv/HlHvX4GQaxGlBTmoPm0hB+vgDihvMswDbAsgPVEfgTvN25WoHhn3RqAsd Yt5Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dAbFVFq7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd42c5b33sm55877805e9.22.2025.03.06.07.48.13 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:48:13 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 08/54] accel/tcg: Build tcg_flags helpers as common code Date: Thu, 6 Mar 2025 16:46:50 +0100 Message-ID: <20250306154737.70886-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org While cpu-exec.c is build for each target,tcg_flags helpers aren't target specific. Move them to cpu-exec-common.c to build them once. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250123234415.59850-8-philmd@linaro.org> --- accel/tcg/cpu-exec-common.c | 33 +++++++++++++++++++++++++++++++++ accel/tcg/cpu-exec.c | 32 -------------------------------- 2 files changed, 33 insertions(+), 32 deletions(-) diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index 6ecfc4e7c21..100746d555a 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "exec/log.h" #include "system/cpus.h" #include "system/tcg.h" #include "qemu/plugin.h" @@ -25,6 +26,38 @@ bool tcg_allowed; +bool tcg_cflags_has(CPUState *cpu, uint32_t flags) +{ + return cpu->tcg_cflags & flags; +} + +void tcg_cflags_set(CPUState *cpu, uint32_t flags) +{ + cpu->tcg_cflags |= flags; +} + +uint32_t curr_cflags(CPUState *cpu) +{ + uint32_t cflags = cpu->tcg_cflags; + + /* + * Record gdb single-step. We should be exiting the TB by raising + * EXCP_DEBUG, but to simplify other tests, disable chaining too. + * + * For singlestep and -d nochain, suppress goto_tb so that + * we can log -d cpu,exec after every TB. + */ + if (unlikely(cpu->singlestep_enabled)) { + cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | CF_SINGLE_STEP | 1; + } else if (qatomic_read(&one_insn_per_tb)) { + cflags |= CF_NO_GOTO_TB | 1; + } else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { + cflags |= CF_NO_GOTO_TB; + } + + return cflags; +} + /* exit the current TB, but without causing any exception to be raised */ void cpu_loop_exit_noexc(CPUState *cpu) { diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8b773d88478..be2ba199d3d 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -148,38 +148,6 @@ static void init_delay_params(SyncClocks *sc, const CPUState *cpu) } #endif /* CONFIG USER ONLY */ -bool tcg_cflags_has(CPUState *cpu, uint32_t flags) -{ - return cpu->tcg_cflags & flags; -} - -void tcg_cflags_set(CPUState *cpu, uint32_t flags) -{ - cpu->tcg_cflags |= flags; -} - -uint32_t curr_cflags(CPUState *cpu) -{ - uint32_t cflags = cpu->tcg_cflags; - - /* - * Record gdb single-step. We should be exiting the TB by raising - * EXCP_DEBUG, but to simplify other tests, disable chaining too. - * - * For singlestep and -d nochain, suppress goto_tb so that - * we can log -d cpu,exec after every TB. - */ - if (unlikely(cpu->singlestep_enabled)) { - cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | CF_SINGLE_STEP | 1; - } else if (qatomic_read(&one_insn_per_tb)) { - cflags |= CF_NO_GOTO_TB | 1; - } else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - cflags |= CF_NO_GOTO_TB; - } - - return cflags; -} - struct tb_desc { vaddr pc; uint64_t cs_base; From patchwork Thu Mar 6 15:46:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870835 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp331931wri; Thu, 6 Mar 2025 07:49:44 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVn0/Lw+axbYl+guuIRLec0BygtTa8jqI9ypP4GYL9Q/MpOaMNXd69NqAtUbp/9FYGuxh8zgA==@linaro.org X-Google-Smtp-Source: AGHT+IEhtA6JYyh+M+ABxbeBHuobTq2jJNWoPjBqyiCRXoBPplmSoWoOLHy+HuvgP9I4JIVj6Mq5 X-Received: by 2002:a05:620a:2603:b0:7c3:d6a7:6eea with SMTP id af79cd13be357-7c3d8decc96mr1354751885a.21.1741276184252; Thu, 06 Mar 2025 07:49:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276184; cv=none; d=google.com; s=arc-20240605; b=hKfZbRkzR0mb7sCcDZVTGiqrNXYo2PN93sso9MjORsDDs00lLqgFDhRNSEaaSLTQ1c MP+9HGLsjfPjW0+2K2g8gpUaV7eUJkyiXdCW7alzQME5mMSXi625qtmHUfFkUhnBR/QD vFRNrtMKHKIomDkYa5m/P029sWdh19agpt4pSYrj6Pjdj/l23pzTwFTUGxt3N/DDTg0C fqzfgpNDlEzeyblDwz7enbNGFWtn5puz4EjDHdacv9ASdAWnr+S7FQjM7uA4qD4YsK/g Ubb73RtsNxFLkvIWjXsQJXcZ1L9QCYkXYBSMAJbb2TNTHsvaksza86h30WLdi2l5ruH2 sxJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wVOS1vvZMQwjXlRVCMeomIHaHZpl7bu5hN5ReN6ps3U=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Jew4oh+VkB9gpQ9b3VEcmd+ydvxuR+3hWqQFbMGWehVqS27ce/2jPFpn84R7zbSw4w DUwk6h7r1tpkGSaLWhEUZCKulHNuXT71NPLUP12ObMTwHoD8SnLkf8jD3d+cCCHwD/Ox piDczDM3A5aRU7N9fONXVM9JEb/4umL7O8s2ij1qOsnXv1qTkk3xwTVKKJqpI9IYBZHa NMYV7MsLlDNMDJAX9NkRhYQKFnTpTRKz1YocDyWIcYpeLOZ9WV9fSaQzJIaXcR/+M4M2 Vbn4gJDN38TPus54l1U50TzDS1GxKWfpbrjmn29o/D3mh2sjru+7NPBkyuIP7HbuHOCr dFYw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="NXWrxB1/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdff57sm2466547f8f.37.2025.03.06.07.48.17 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:48:18 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 09/54] accel/tcg: Restrict tlb_init() / destroy() to TCG Date: Thu, 6 Mar 2025 16:46:51 +0100 Message-ID: <20250306154737.70886-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move CPU TLB related methods to accel/tcg/ scope, in "internal-common.h". Suggested-by: Richard Henderson Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250123234415.59850-9-philmd@linaro.org> --- accel/tcg/internal-common.h | 11 +++++++++++ include/exec/exec-all.h | 16 ---------------- accel/tcg/user-exec-stub.c | 11 +++++++++++ 3 files changed, 22 insertions(+), 16 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index c8d714256cb..d3186721839 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -53,6 +53,17 @@ TranslationBlock *tb_link_page(TranslationBlock *tb); void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t host_pc); +/** + * tlb_init - initialize a CPU's TLB + * @cpu: CPU whose TLB should be initialized + */ +void tlb_init(CPUState *cpu); +/** + * tlb_destroy - destroy a CPU's TLB + * @cpu: CPU whose TLB should be destroyed + */ +void tlb_destroy(CPUState *cpu); + bool tcg_exec_realizefn(CPUState *cpu, Error **errp); void tcg_exec_unrealizefn(CPUState *cpu); diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index d9045c9ac4c..8eb0df48f94 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -29,16 +29,6 @@ #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* cputlb.c */ -/** - * tlb_init - initialize a CPU's TLB - * @cpu: CPU whose TLB should be initialized - */ -void tlb_init(CPUState *cpu); -/** - * tlb_destroy - destroy a CPU's TLB - * @cpu: CPU whose TLB should be destroyed - */ -void tlb_destroy(CPUState *cpu); /** * tlb_flush_page: * @cpu: CPU whose TLB should be flushed @@ -223,12 +213,6 @@ void tlb_set_page(CPUState *cpu, vaddr addr, hwaddr paddr, int prot, int mmu_idx, vaddr size); #else -static inline void tlb_init(CPUState *cpu) -{ -} -static inline void tlb_destroy(CPUState *cpu) -{ -} static inline void tlb_flush_page(CPUState *cpu, vaddr addr) { } diff --git a/accel/tcg/user-exec-stub.c b/accel/tcg/user-exec-stub.c index 4fbe2dbdc88..1d52f48226a 100644 --- a/accel/tcg/user-exec-stub.c +++ b/accel/tcg/user-exec-stub.c @@ -1,6 +1,7 @@ #include "qemu/osdep.h" #include "hw/core/cpu.h" #include "exec/replay-core.h" +#include "internal-common.h" void cpu_resume(CPUState *cpu) { @@ -18,6 +19,16 @@ void cpu_exec_reset_hold(CPUState *cpu) { } +/* User mode emulation does not support softmmu yet. */ + +void tlb_init(CPUState *cpu) +{ +} + +void tlb_destroy(CPUState *cpu) +{ +} + /* User mode emulation does not support record/replay yet. */ bool replay_exception(void) From patchwork Thu Mar 6 15:46:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870845 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp333923wri; Thu, 6 Mar 2025 07:54:57 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXubGmWKmJdCXTYjVnSuQ+kV1IFTTz+UwrYXOWIDM5wEVdEYwqVqftuAk/NXHEyUv+ddz3QOA==@linaro.org X-Google-Smtp-Source: AGHT+IGVP+FHMjx1zj2B0ArwS1B4Dg5NiGj9GHyemYwrxOxD8vB/ZweED/fcOOWMVPMhBdom24yn X-Received: by 2002:a05:6214:dc8:b0:6e8:fcc6:35b6 with SMTP id 6a1803df08f44-6e8fcc63c59mr16438276d6.2.1741276497385; Thu, 06 Mar 2025 07:54:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276497; cv=none; d=google.com; s=arc-20240605; b=dDAMH+yaWJ7b6ruRTfuY4mkzhSbnaFOhCcRHA2WCbAmP9gujvAsOtYagSCrljzy+l+ ZzK/BE1wWsMcx2AoyTBGmuguSUxcEY8yzEZqO3w3YjcQdUnKmOcZRKeKFxKX4vQVtcs7 UYCo7sfCvdu7qM081G0lOGshg8nFRfDyprgrb+9DRKfsH2yRO4QiW8kadqqS7eMWMDGe /VGpm8OfMh77d6rgRVdHD11nnRg4uGLhubBuVp/pdDh0sZBuVCSORj76Jmi+betoda0P 29eUsLGvJW+twuRvBV37R7grlRahjRDY2VEdC6OON4y5RTQ8mlad8NWtFAHUJGJ7VdQv OJ3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0uHoLbJKeoI2RLyZ0VsturTTj7TY2KrFP8jv6ZyXsKo=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=GfOgMO7X9KlwJIh5UxbqDHCviBipq04+Rt9YK14KcO9bOMzfIsBJxgDYz/zr7MohOW /EdKitZL92gyM0Ra+Uf8Sd0UfE36gqwI5o7DPIcIE2d7LQlHeYd069d/ny1Ki1628rsX OG7g9eJNpf832u6cS4qZKYVpRGniD3frnLknoXH7sZ4YALRmPazeIaXNSBE26tRXG1xA HsZs+nqS5TrIEJfH01vMOwajwzsnhkIoOjed+fT5r+mcYubFUoyQc9NY5uwMXy2fmR9a ynhxpd/Fpm2z15HjwhT3dwCOV17gvvIl/+LzHjPwtSzLWv+bi4L2TYpxGoqjJKuDQiTk YfHg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Uv/IIi1L"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd831719sm25094075e9.0.2025.03.06.07.48.22 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:48:22 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 10/54] accel/tcg: Restrict 'icount_align_option' global to TCG Date: Thu, 6 Mar 2025 16:46:52 +0100 Message-ID: <20250306154737.70886-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since commit 740b1759734 ("cpu-timers, icount: new modules") we don't need to expose icount_align_option to all the system code, we can restrict it to TCG. Since it is used as a boolean, declare it as 'bool' type. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250123234415.59850-10-philmd@linaro.org> --- accel/tcg/internal-common.h | 2 ++ include/system/cpus.h | 2 -- accel/tcg/icount-common.c | 2 ++ system/globals.c | 1 - 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index d3186721839..7ef620d9631 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -17,6 +17,8 @@ extern int64_t max_advance; extern bool one_insn_per_tb; +extern bool icount_align_option; + /* * Return true if CS is not running in parallel with other cpus, either * because there are no other cpus or we are within an exclusive context. diff --git a/include/system/cpus.h b/include/system/cpus.h index 3d8fd368f32..1cffeaaf5c4 100644 --- a/include/system/cpus.h +++ b/include/system/cpus.h @@ -38,8 +38,6 @@ void resume_all_vcpus(void); void pause_all_vcpus(void); void cpu_stop_current(void); -extern int icount_align_option; - /* Unblock cpu */ void qemu_cpu_kick_self(void); diff --git a/accel/tcg/icount-common.c b/accel/tcg/icount-common.c index b178dccec45..402d3e3f4e8 100644 --- a/accel/tcg/icount-common.c +++ b/accel/tcg/icount-common.c @@ -48,6 +48,8 @@ static bool icount_sleep = true; /* Arbitrarily pick 1MIPS as the minimum allowable speed. */ #define MAX_ICOUNT_SHIFT 10 +bool icount_align_option; + /* Do not count executed instructions */ ICountMode use_icount = ICOUNT_DISABLED; diff --git a/system/globals.c b/system/globals.c index 316623bd20a..9640c9511e9 100644 --- a/system/globals.c +++ b/system/globals.c @@ -58,7 +58,6 @@ unsigned int nb_prom_envs; const char *prom_envs[MAX_PROM_ENVS]; uint8_t *boot_splash_filedata; int only_migratable; /* turn it off unless user states otherwise */ -int icount_align_option; /* The bytes in qemu_uuid are in the order specified by RFC4122, _not_ in the * little-endian "wire format" described in the SMBIOS 2.6 specification. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c015a29sm2358327f8f.42.2025.03.06.07.48.27 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:48:27 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 11/54] accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h' Date: Thu, 6 Mar 2025 16:46:53 +0100 Message-ID: <20250306154737.70886-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org TCGCPUOps structure makes more sense in the accelerator context rather than hardware emulation. Move it under the accel/tcg/ scope. Mechanical change doing: $ sed -i -e 's,hw/core/tcg-cpu-ops.h,accel/tcg/cpu-ops.h,g' \ $(git grep -l hw/core/tcg-cpu-ops.h) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250123234415.59850-11-philmd@linaro.org> --- MAINTAINERS | 2 +- include/{hw/core/tcg-cpu-ops.h => accel/tcg/cpu-ops.h} | 0 accel/tcg/cpu-exec.c | 2 +- accel/tcg/cputlb.c | 2 +- accel/tcg/translate-all.c | 2 +- accel/tcg/user-exec.c | 2 +- accel/tcg/watchpoint.c | 2 +- bsd-user/signal.c | 2 +- hw/mips/jazz.c | 2 +- linux-user/signal.c | 2 +- system/physmem.c | 2 +- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/arm/tcg/cpu-v7m.c | 2 +- target/arm/tcg/cpu32.c | 2 +- target/arm/tcg/mte_helper.c | 2 +- target/arm/tcg/sve_helper.c | 2 +- target/avr/cpu.c | 2 +- target/avr/helper.c | 2 +- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/cpu_helper.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/s390x/tcg/mem_helper.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 37 files changed, 36 insertions(+), 36 deletions(-) rename include/{hw/core/tcg-cpu-ops.h => accel/tcg/cpu-ops.h} (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 692628cd780..2d9ba810851 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -175,7 +175,7 @@ F: include/exec/helper-info.c.inc F: include/exec/page-protection.h F: include/system/cpus.h F: include/system/tcg.h -F: include/hw/core/tcg-cpu-ops.h +F: include/accel/tcg/cpu-ops.h F: host/include/*/host/cpuinfo.h F: util/cpuinfo-*.c F: include/tcg/ diff --git a/include/hw/core/tcg-cpu-ops.h b/include/accel/tcg/cpu-ops.h similarity index 100% rename from include/hw/core/tcg-cpu-ops.h rename to include/accel/tcg/cpu-ops.h diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index be2ba199d3d..3a3c45f52ed 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -22,7 +22,7 @@ #include "qapi/error.h" #include "qapi/type-helpers.h" #include "hw/core/cpu.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "trace.h" #include "disas/disas.h" #include "exec/cpu-common.h" diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ad158050a13..c8761683a0a 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/memory.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index d4189c73860..786e2f6f1a7 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -58,7 +58,7 @@ #include "system/cpu-timers.h" #include "system/tcg.h" #include "qapi/error.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0561c4f6dc7..c4454100ad7 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -17,7 +17,7 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "disas/disas.h" #include "exec/exec-all.h" #include "tcg/tcg.h" diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c index af57d182d5b..40112b2b2e7 100644 --- a/accel/tcg/watchpoint.c +++ b/accel/tcg/watchpoint.c @@ -26,7 +26,7 @@ #include "tb-internal.h" #include "system/tcg.h" #include "system/replay.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "hw/core/cpu.h" #include "internal-common.h" diff --git a/bsd-user/signal.c b/bsd-user/signal.c index ff2ccbbf605..ab1d9ddd50f 100644 --- a/bsd-user/signal.c +++ b/bsd-user/signal.c @@ -29,7 +29,7 @@ #include "gdbstub/user.h" #include "signal-common.h" #include "trace.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "host-signal.h" /* target_siginfo_t must fit in gdbstub's siginfo save area. */ diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index c89610639a9..1700c3765de 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -50,7 +50,7 @@ #include "qemu/error-report.h" #include "qemu/help_option.h" #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #endif /* CONFIG_TCG */ #include "cpu.h" diff --git a/linux-user/signal.c b/linux-user/signal.c index 81a98c6d02f..4799b79dede 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -21,7 +21,7 @@ #include "qemu/cutils.h" #include "gdbstub/user.h" #include "exec/page-protection.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include #include diff --git a/system/physmem.c b/system/physmem.c index eff8b55c2dd..8c1736f84ee 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -28,7 +28,7 @@ #include "qemu/lockable.h" #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #endif /* CONFIG_TCG */ #include "exec/exec-all.h" diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index f5dd7449876..57e41fcd784 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -227,7 +227,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = { }; #endif -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps alpha_tcg_ops = { .initialize = alpha_translate_init, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 656070afb59..ac1ceec2110 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -29,7 +29,7 @@ #include "cpu.h" #ifdef CONFIG_TCG #include "exec/translation-block.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #endif /* CONFIG_TCG */ #include "internals.h" #include "cpu-features.h" diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 03acdf83e00..29a41fde694 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -10,7 +10,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "internals.h" #if !defined(CONFIG_USER_ONLY) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 0f1c5bc87e8..2c45b7eddda 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -10,7 +10,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "internals.h" #include "target/arm/idau.h" #if !defined(CONFIG_USER_ONLY) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index f72ce2ae0d4..5d6d8a17ae8 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -31,7 +31,7 @@ #endif #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "qapi/error.h" #include "qemu/guest-random.h" #include "mte_helper.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index c206ca65ceb..d786b4b1118 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -28,7 +28,7 @@ #include "tcg/tcg.h" #include "vec_internal.h" #include "sve_ldst_internal.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #ifdef CONFIG_USER_ONLY #include "user/page-protection.h" #endif diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 8a126ff3222..5a0e21465e5 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -203,7 +203,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = { .get_phys_page_debug = avr_cpu_get_phys_page_debug, }; -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps avr_tcg_ops = { .initialize = avr_cpu_tcg_init, diff --git a/target/avr/helper.c b/target/avr/helper.c index 345708a1b39..9ea6870e44d 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -22,7 +22,7 @@ #include "qemu/log.h" #include "qemu/error-report.h" #include "cpu.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 0b7fc98f6ce..238e63bcea4 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -321,7 +321,7 @@ static void hexagon_cpu_init(Object *obj) { } -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps hexagon_tcg_ops = { .initialize = hexagon_translate_init, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 5655677431c..4bb5cff624e 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -245,7 +245,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops = { }; #endif -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps hppa_tcg_ops = { .initialize = hppa_translate_init, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 14ee038079a..f09ee813ac9 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -105,7 +105,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) } #endif -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps x86_tcg_ops = { .initialize = tcg_x86_init, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ac514a15fba..b4b82425b18 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -857,7 +857,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) } #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps loongarch_tcg_ops = { .initialize = loongarch_translate_init, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 2617d8f6ede..eedda07c2ab 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -582,7 +582,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = { }; #endif /* !CONFIG_USER_ONLY */ -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps m68k_tcg_ops = { .initialize = m68k_tcg_init, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f114789abd8..13d194cef88 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -419,7 +419,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = { }; #endif -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps mb_tcg_ops = { .initialize = mb_tcg_init, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 47cd7cfdcef..0b267d2e507 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -544,7 +544,7 @@ static const Property mips_cpu_properties[] = { }; #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps mips_tcg_ops = { .initialize = mips_tcg_init, .translate_code = mips_translate_code, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b7bab0d7abf..0669ba2fd10 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -232,7 +232,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { }; #endif -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps openrisc_tcg_ops = { .initialize = openrisc_translate_init, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 062a6e85fba..425049ab093 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7430,7 +7430,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = { #endif #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps ppc_tcg_ops = { .initialize = ppc_translate_init, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3f5fd861a80..34092f372df 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -27,7 +27,7 @@ #include "exec/page-protection.h" #include "instmap.h" #include "tcg/tcg-op.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "trace.h" #include "semihosting/common-semi.h" #include "system/cpu-timers.h" diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f1d971eec1f..70f4c7984aa 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -31,7 +31,7 @@ #include "qemu/error-report.h" #include "qemu/log.h" #include "hw/core/accel-cpu.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" #ifndef CONFIG_USER_ONLY #include "hw/boards.h" diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 37a6fdd569b..7d5fcbf76ac 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -200,7 +200,7 @@ static const struct SysemuCPUOps rx_sysemu_ops = { }; #endif -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps rx_tcg_ops = { .initialize = rx_translate_init, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 97d41c23de7..3bea014f9ee 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -322,7 +322,7 @@ static const Property s390x_cpu_properties[] = { #endif #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index c6ab2901e5a..ea9fa64d6b4 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -28,7 +28,7 @@ #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" #include "qemu/int128.h" #include "qemu/atomic128.h" diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index ccfe222bdf3..22cdf9b4e12 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -256,7 +256,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = { }; #endif -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps superh_tcg_ops = { .initialize = sh4_translate_init, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index fbd38ec334a..e3b46137178 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -992,7 +992,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops = { #endif #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps sparc_tcg_ops = { .initialize = sparc_tcg_init, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 95202fadbfd..eb794674c8d 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -168,7 +168,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = { .get_phys_page_debug = tricore_cpu_get_phys_page_debug, }; -#include "hw/core/tcg-cpu-ops.h" +#include "accel/tcg/cpu-ops.h" static const TCGCPUOps tricore_tcg_ops = { .initialize = tricore_tcg_init, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 4eb699d1f45..efbfe73fcfb 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -228,7 +228,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { }; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfe0004sm2358411f8f.40.2025.03.06.07.48.31 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:48:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 12/54] accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h' Date: Thu, 6 Mar 2025 16:46:54 +0100 Message-ID: <20250306154737.70886-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org AccelCPUClass is for accelerator to initialize target specific features of a vCPU. Not really related to hardware emulation, rename "hw/core/accel-cpu.h" as "accel/accel-cpu-target.h" (using the explicit -target suffix). More importantly, target specific header often access the target specific definitions which are in each target/FOO/cpu.h header, usually included generically as "cpu.h" relative to target/FOO/. However, there is already a "cpu.h" in hw/core/ which takes precedence. This change allows "accel-cpu-target.h" to include a target "cpu.h". Mechanical change doing: $ git mv include/hw/core/accel-cpu.h \ include/accel/accel-cpu-target.h $ sed -i -e 's,hw/core/accel-cpu.h,accel/accel-cpu-target.h,' \ $(git grep -l hw/core/accel-cpu.h) and renaming header guard 'ACCEL_CPU_TARGET_H'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250123234415.59850-12-philmd@linaro.org> --- MAINTAINERS | 2 +- include/{hw/core/accel-cpu.h => accel/accel-cpu-target.h} | 4 ++-- accel/accel-target.c | 2 +- cpu-target.c | 2 +- target/i386/hvf/hvf-cpu.c | 2 +- target/i386/kvm/kvm-cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/ppc/kvm.c | 2 +- target/riscv/kvm/kvm-cpu.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- 10 files changed, 11 insertions(+), 11 deletions(-) rename include/{hw/core/accel-cpu.h => accel/accel-cpu-target.h} (95%) diff --git a/MAINTAINERS b/MAINTAINERS index 2d9ba810851..a0e462d03ca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -499,7 +499,7 @@ R: Paolo Bonzini S: Maintained F: include/qemu/accel.h F: include/system/accel-*.h -F: include/hw/core/accel-cpu.h +F: include/accel/accel-cpu-target.h F: accel/accel-*.c F: accel/Makefile.objs F: accel/stubs/Makefile.objs diff --git a/include/hw/core/accel-cpu.h b/include/accel/accel-cpu-target.h similarity index 95% rename from include/hw/core/accel-cpu.h rename to include/accel/accel-cpu-target.h index 24dad45ab9e..0a8e518600d 100644 --- a/include/hw/core/accel-cpu.h +++ b/include/accel/accel-cpu-target.h @@ -8,8 +8,8 @@ * See the COPYING file in the top-level directory. */ -#ifndef ACCEL_CPU_H -#define ACCEL_CPU_H +#ifndef ACCEL_CPU_TARGET_H +#define ACCEL_CPU_TARGET_H /* * This header is used to define new accelerator-specific target-specific diff --git a/accel/accel-target.c b/accel/accel-target.c index 3236d6335b1..83587274626 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -27,7 +27,7 @@ #include "qemu/accel.h" #include "cpu.h" -#include "hw/core/accel-cpu.h" +#include "accel/accel-cpu-target.h" #ifndef CONFIG_USER_ONLY #include "accel-system.h" diff --git a/cpu-target.c b/cpu-target.c index 75501a909df..f97f3a14751 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -44,7 +44,7 @@ #include "exec/tb-flush.h" #include "exec/translation-block.h" #include "exec/log.h" -#include "hw/core/accel-cpu.h" +#include "accel/accel-cpu-target.h" #include "trace/trace-root.h" #include "qemu/accel.h" diff --git a/target/i386/hvf/hvf-cpu.c b/target/i386/hvf/hvf-cpu.c index 560b5a05940..b5f4c80028f 100644 --- a/target/i386/hvf/hvf-cpu.c +++ b/target/i386/hvf/hvf-cpu.c @@ -14,7 +14,7 @@ #include "system/system.h" #include "hw/boards.h" #include "system/hvf.h" -#include "hw/core/accel-cpu.h" +#include "accel/accel-cpu-target.h" #include "hvf-i386.h" static void hvf_cpu_max_instance_init(X86CPU *cpu) diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index 1bda403f88b..6269fa80452 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -15,7 +15,7 @@ #include "hw/boards.h" #include "kvm_i386.h" -#include "hw/core/accel-cpu.h" +#include "accel/accel-cpu-target.h" static void kvm_set_guest_phys_bits(CPUState *cs) { diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index f09ee813ac9..b8aff825eec 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "helper-tcg.h" #include "qemu/accel.h" -#include "hw/core/accel-cpu.h" +#include "accel/accel-cpu-target.h" #include "exec/translation-block.h" #include "tcg-cpu.h" diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 966c2c65723..216638dee40 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -49,7 +49,7 @@ #include "elf.h" #include "system/kvm_int.h" #include "system/kvm.h" -#include "hw/core/accel-cpu.h" +#include "accel/accel-cpu-target.h" #include CONFIG_DEVICES diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 7f3b59cb72c..4ffeeaa1c95 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -32,7 +32,7 @@ #include "system/kvm_int.h" #include "cpu.h" #include "trace.h" -#include "hw/core/accel-cpu.h" +#include "accel/accel-cpu-target.h" #include "hw/pci/pci.h" #include "exec/memattrs.h" #include "exec/address-spaces.h" diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 70f4c7984aa..5aef9eef366 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -30,7 +30,7 @@ #include "qemu/accel.h" #include "qemu/error-report.h" #include "qemu/log.h" -#include "hw/core/accel-cpu.h" +#include "accel/accel-cpu-target.h" #include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" #ifndef CONFIG_USER_ONLY From patchwork Thu Mar 6 15:46:55 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd4352ed7sm53288995e9.26.2025.03.06.07.48.36 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:48:36 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 13/54] accel: Forward-declare AccelOpsClass in 'qemu/typedefs.h' Date: Thu, 6 Mar 2025 16:46:55 +0100 Message-ID: <20250306154737.70886-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The heavily imported "system/cpus.h" header includes "accel-ops.h" to get AccelOpsClass type declaration. Reduce headers pressure by forward declaring it in "qemu/typedefs.h", where we already declare the AccelCPUState type. Reduce "system/cpus.h" inclusions by only including "system/accel-ops.h" when necessary. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250123234415.59850-14-philmd@linaro.org> --- include/qemu/typedefs.h | 1 + include/system/accel-ops.h | 1 - include/system/cpus.h | 2 -- accel/accel-system.c | 1 + accel/hvf/hvf-accel-ops.c | 1 + accel/kvm/kvm-accel-ops.c | 1 + accel/qtest/qtest.c | 1 + accel/tcg/cpu-exec-common.c | 1 - accel/tcg/cpu-exec.c | 1 - accel/tcg/monitor.c | 1 - accel/tcg/tcg-accel-ops.c | 1 + accel/tcg/translate-all.c | 1 - accel/xen/xen-all.c | 1 + cpu-common.c | 1 - cpu-target.c | 1 + gdbstub/system.c | 1 + system/cpus.c | 1 + target/i386/nvmm/nvmm-accel-ops.c | 1 + target/i386/whpx/whpx-accel-ops.c | 1 + 19 files changed, 12 insertions(+), 8 deletions(-) diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 3d84efcac47..465cc501773 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -22,6 +22,7 @@ * Please keep this list in case-insensitive alphabetical order. */ typedef struct AccelCPUState AccelCPUState; +typedef struct AccelOpsClass AccelOpsClass; typedef struct AccelState AccelState; typedef struct AddressSpace AddressSpace; typedef struct AioContext AioContext; diff --git a/include/system/accel-ops.h b/include/system/accel-ops.h index 137fb96d444..4c99d25aeff 100644 --- a/include/system/accel-ops.h +++ b/include/system/accel-ops.h @@ -17,7 +17,6 @@ #define TYPE_ACCEL_OPS "accel" ACCEL_OPS_SUFFIX #define ACCEL_OPS_NAME(name) (name "-" TYPE_ACCEL_OPS) -typedef struct AccelOpsClass AccelOpsClass; DECLARE_CLASS_CHECKERS(AccelOpsClass, ACCEL_OPS, TYPE_ACCEL_OPS) /** diff --git a/include/system/cpus.h b/include/system/cpus.h index 1cffeaaf5c4..3226c765d01 100644 --- a/include/system/cpus.h +++ b/include/system/cpus.h @@ -1,8 +1,6 @@ #ifndef QEMU_CPUS_H #define QEMU_CPUS_H -#include "system/accel-ops.h" - /* register accel-specific operations */ void cpus_register_accel(const AccelOpsClass *i); diff --git a/accel/accel-system.c b/accel/accel-system.c index a7596aef59d..5df49fbe831 100644 --- a/accel/accel-system.c +++ b/accel/accel-system.c @@ -26,6 +26,7 @@ #include "qemu/osdep.h" #include "qemu/accel.h" #include "hw/boards.h" +#include "system/accel-ops.h" #include "system/cpus.h" #include "qemu/error-report.h" #include "accel-system.h" diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 945ba720513..12fc30c2761 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -54,6 +54,7 @@ #include "exec/exec-all.h" #include "gdbstub/enums.h" #include "hw/boards.h" +#include "system/accel-ops.h" #include "system/cpus.h" #include "system/hvf.h" #include "system/hvf_int.h" diff --git a/accel/kvm/kvm-accel-ops.c b/accel/kvm/kvm-accel-ops.c index a81e8f3b03b..54ea60909e2 100644 --- a/accel/kvm/kvm-accel-ops.c +++ b/accel/kvm/kvm-accel-ops.c @@ -16,6 +16,7 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" +#include "system/accel-ops.h" #include "system/kvm.h" #include "system/kvm_int.h" #include "system/runstate.h" diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c index ad7e3441a5a..7fae80f6a1b 100644 --- a/accel/qtest/qtest.c +++ b/accel/qtest/qtest.c @@ -18,6 +18,7 @@ #include "qemu/option.h" #include "qemu/config-file.h" #include "qemu/accel.h" +#include "system/accel-ops.h" #include "system/qtest.h" #include "system/cpus.h" #include "qemu/guest-random.h" diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index 100746d555a..c5c513f1e4a 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include "exec/log.h" -#include "system/cpus.h" #include "system/tcg.h" #include "qemu/plugin.h" #include "internal-common.h" diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 3a3c45f52ed..ef3d967e3af 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -33,7 +33,6 @@ #include "qemu/rcu.h" #include "exec/log.h" #include "qemu/main-loop.h" -#include "system/cpus.h" #include "exec/cpu-all.h" #include "system/cpu-timers.h" #include "exec/replay-core.h" diff --git a/accel/tcg/monitor.c b/accel/tcg/monitor.c index ae1dbeb79f8..eeb38a4d9ce 100644 --- a/accel/tcg/monitor.c +++ b/accel/tcg/monitor.c @@ -13,7 +13,6 @@ #include "qapi/type-helpers.h" #include "qapi/qapi-commands-machine.h" #include "monitor/monitor.h" -#include "system/cpus.h" #include "system/cpu-timers.h" #include "system/tcg.h" #include "tcg/tcg.h" diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 6e3f1fa92b2..132c5d14613 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -26,6 +26,7 @@ */ #include "qemu/osdep.h" +#include "system/accel-ops.h" #include "system/tcg.h" #include "system/replay.h" #include "system/cpu-timers.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 786e2f6f1a7..0914d6e98b2 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -54,7 +54,6 @@ #include "qemu/cacheinfo.h" #include "qemu/timer.h" #include "exec/log.h" -#include "system/cpus.h" #include "system/cpu-timers.h" #include "system/tcg.h" #include "qapi/error.h" diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c index 852e9fbe5fe..7aa28b9ab93 100644 --- a/accel/xen/xen-all.c +++ b/accel/xen/xen-all.c @@ -18,6 +18,7 @@ #include "hw/xen/xen_igd.h" #include "chardev/char.h" #include "qemu/accel.h" +#include "system/accel-ops.h" #include "system/cpus.h" #include "system/xen.h" #include "system/runstate.h" diff --git a/cpu-common.c b/cpu-common.c index 4248b2d727e..f5dcc2d136b 100644 --- a/cpu-common.c +++ b/cpu-common.c @@ -21,7 +21,6 @@ #include "qemu/main-loop.h" #include "exec/cpu-common.h" #include "hw/core/cpu.h" -#include "system/cpus.h" #include "qemu/lockable.h" #include "trace/trace-root.h" diff --git a/cpu-target.c b/cpu-target.c index f97f3a14751..20933bde7d4 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -35,6 +35,7 @@ #include "exec/address-spaces.h" #include "exec/memory.h" #endif +#include "system/accel-ops.h" #include "system/cpus.h" #include "system/tcg.h" #include "exec/tswap.h" diff --git a/gdbstub/system.c b/gdbstub/system.c index 7f047a285c8..416c1dbe1e9 100644 --- a/gdbstub/system.c +++ b/gdbstub/system.c @@ -19,6 +19,7 @@ #include "gdbstub/commands.h" #include "exec/hwaddr.h" #include "exec/tb-flush.h" +#include "system/accel-ops.h" #include "system/cpus.h" #include "system/runstate.h" #include "system/replay.h" diff --git a/system/cpus.c b/system/cpus.c index 37e5892c240..2cc5f887ab5 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -31,6 +31,7 @@ #include "qapi/qapi-events-run-state.h" #include "qapi/qmp/qerror.h" #include "exec/gdbstub.h" +#include "system/accel-ops.h" #include "system/hw_accel.h" #include "exec/cpu-common.h" #include "qemu/thread.h" diff --git a/target/i386/nvmm/nvmm-accel-ops.c b/target/i386/nvmm/nvmm-accel-ops.c index e7b56662fee..4e4e63de78e 100644 --- a/target/i386/nvmm/nvmm-accel-ops.c +++ b/target/i386/nvmm/nvmm-accel-ops.c @@ -10,6 +10,7 @@ #include "qemu/osdep.h" #include "system/kvm_int.h" #include "qemu/main-loop.h" +#include "system/accel-ops.h" #include "system/cpus.h" #include "qemu/guest-random.h" diff --git a/target/i386/whpx/whpx-accel-ops.c b/target/i386/whpx/whpx-accel-ops.c index ab2e014c9ea..81fdd06e487 100644 --- a/target/i386/whpx/whpx-accel-ops.c +++ b/target/i386/whpx/whpx-accel-ops.c @@ -11,6 +11,7 @@ #include "qemu/osdep.h" #include "system/kvm_int.h" #include "qemu/main-loop.h" +#include "system/accel-ops.h" #include "system/cpus.h" #include "qemu/guest-random.h" From patchwork Thu Mar 6 15:46:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870838 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp332034wri; Thu, 6 Mar 2025 07:49:57 -0800 (PST) X-Forwarded-Encrypted: i=2; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd4353003sm56112775e9.28.2025.03.06.07.48.40 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:48:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 14/54] accel/accel-cpu-target.h: Include missing 'cpu.h' header Date: Thu, 6 Mar 2025 16:46:56 +0100 Message-ID: <20250306154737.70886-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPU_RESOLVING_TYPE is declared per target in "cpu.h". Include it (along with "qom/object.h") to avoid when moving code around: include/accel/accel-cpu-target.h:26:50: error: expected ')' 26 | DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU) | ^ include/accel/accel-cpu-target.h:23:33: note: expanded from macro 'TYPE_ACCEL_CPU' 23 | #define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE | ^ include/accel/accel-cpu-target.h:26:1: note: to match this '(' 26 | DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU) | ^ include/qom/object.h:196:14: note: expanded from macro 'DECLARE_CLASS_CHECKERS' 196 | { return OBJECT_GET_CLASS(ClassType, obj, TYPENAME); } \ | ^ include/qom/object.h:558:5: note: expanded from macro 'OBJECT_GET_CLASS' 558 | OBJECT_CLASS_CHECK(class, object_get_class(OBJECT(obj)), name) | ^ include/qom/object.h:544:74: note: expanded from macro 'OBJECT_CLASS_CHECK' 544 | ((class_type *)object_class_dynamic_cast_assert(OBJECT_CLASS(class), (name), \ | ^ Signed-off-by: Philippe Mathieu-Daudé Acked-by: Richard Henderson Message-Id: <20250123234415.59850-13-philmd@linaro.org> --- include/accel/accel-cpu-target.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/accel/accel-cpu-target.h b/include/accel/accel-cpu-target.h index 0a8e518600d..37dde7fae3e 100644 --- a/include/accel/accel-cpu-target.h +++ b/include/accel/accel-cpu-target.h @@ -20,6 +20,9 @@ * subclasses in target/, or the accel implementation itself in accel/ */ +#include "qom/object.h" +#include "cpu.h" + #define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE #define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU) typedef struct AccelCPUClass AccelCPUClass; From patchwork Thu Mar 6 15:46:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870858 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp335198wri; Thu, 6 Mar 2025 07:58:09 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVGGsMSKQ7KqsX/uvf7xNJHB1cOl9PUR96PWfD8QB54RALK1wkP1lIVx6hpuZMSKsoYKsqT0w==@linaro.org X-Google-Smtp-Source: AGHT+IHVPwK7G5EQbvNHvP9SY1+CB8i8jXfttbnqaKC2RN8PchSjmz8Vuh9dwuVLMcNBEvMJGH8j X-Received: by 2002:a05:622a:1ba7:b0:474:fada:48c8 with SMTP id d75a77b69052e-4750b4e7d57mr101906361cf.51.1741276689558; Thu, 06 Mar 2025 07:58:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276689; cv=none; d=google.com; s=arc-20240605; b=FJTNZh6+t5WJsyXdIPi3xt3mgsgMmdZHh5s+1w/16xVN49yleOk4YsOmseVLyCGGBa HjRR6p8k4ysvKvIrzQ9zg/CwAvsdaG/ll7M2AxOwTk0S1l6xBZ0Cdd/0gPacauXSUhnZ Br08qjkXoMEpRaIo8wDXkbNhBjjU5YGWPiTxN2sC4z8VFIJXWKFe55yAbeShbQI09FZ9 5rZbuuiu07qoYMLZvTNwmpDGp2IDl3S+glHhK6jLe76H0ZaXWkQIz/eNgTKvnsgC6Fm7 qxlkVqDURXK+u+i5vopmkuRjDlfvKG7VIHwXw5Rs5ZbARoBAXL+pmXtjP5LUYFaz05IH MU4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tpYVdS1VQrRLJn+AtzliasS5gEtN/QTYnA/EkOtkTRg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=YFwHAUIPSGa/IhpYQK1tvzKlxyjlMhJuQvDzz9Pe/FbrkHU7jzagKngBlpGDSnGJSG bz9Z+9zuVmIpWd+rmORdHW0zukiWE/DF0CbzbNNcADabU2g4vjN9xXGVGrqqpSG/AFDG TQlduhtQOGez8u69o6YIhOwZyao3KQ8aivp1x820d2QhSW32KZJuXbFEbPXH4EhTSwDp qjEtlq+nJiLDXgKlB8kT9e5imPpCc5+7xgiruvMUZJibAYRKoPDTabhoCQPlNWoN9cQI Li8Noi0itjFRCz7CY+3E5wVkLrAnSbIGiGYU/LEqu35p8wPJ5sYQ990kewD8Leh0ib// nkFw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cupCHcmM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd8b0461sm25054045e9.4.2025.03.06.07.48.45 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:48:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 15/54] accel/tcg: Include missing bswap headers in user-exec.c Date: Thu, 6 Mar 2025 16:46:57 +0100 Message-ID: <20250306154737.70886-16-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Commit 35c653c4029 ("tcg: Add 128-bit guest memory primitives") introduced the use of bswap128() which is declared in "qemu/int128.h", commit de95016dfbf ("accel/tcg: Implement helper_{ld,st}*_mmu for user-only") introduced the other bswap*() uses, which are declared in "qemu/bswap.h". Include the missing headers. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250217130610.18313-3-philmd@linaro.org> --- accel/tcg/user-exec.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index c4454100ad7..9d53c9440ea 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -30,6 +30,8 @@ #include "exec/page-protection.h" #include "exec/helper-proto.h" #include "qemu/atomic128.h" +#include "qemu/bswap.h" +#include "qemu/int128.h" #include "trace.h" #include "tcg/tcg-ldst.h" #include "internal-common.h" From patchwork Thu Mar 6 15:46:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870837 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp331966wri; Thu, 6 Mar 2025 07:49:49 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWcFHLxTo6oboxwes6ZYYeHLrcVySV08DzTzSNVSX6zt5z3v4vVFRKL+xVtBbi0WByuQNBOvw==@linaro.org X-Google-Smtp-Source: AGHT+IGiRA0uPUAfbf4hQwpqQda0WStYvxFUuZg55OVV58VNZ8RguAmqnwcWm9kUO2AelIq3jWHL X-Received: by 2002:a05:620a:278b:b0:7c3:9cd1:c9d3 with SMTP id af79cd13be357-7c3d8a50b19mr1149196385a.0.1741276188986; Thu, 06 Mar 2025 07:49:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276188; cv=none; d=google.com; s=arc-20240605; b=P18SQDYpK4qTGZUrmHlAsgvd4HWmNjAmfRlaFrEMn7WMgL9VL95rB7liAFmb4VFoNf uDASkqvQim3wGGzJXSTi6dkYMNkTlXftI4yyT9r7WDhbF9uvtT17MUstcvFVEUsCu169 CU19srHnSTT2rRSDtkbDgQHtA4OGAxYQ3ZsnuowAzCnGJLnSi8MmoZ4SLAhjt1r6DMTq p/Z79A8/4TCl6Xr945xAqpMSaxrjq16I82NYELrXygGLw+rstuTqYII7yf9Wu3901B51 fdW4aO7OR16hX+hiX1K/qe1JQaR41G9p6NNknizms3AQh8kVirLct7tPUCb2SFXtsM2e 1uKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vBqWCN5asMJDU7YX+TXWWAjMjDHkesNYFUgdbjXa4FQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=DSeiIzKIKwJCqSevDKSz3Fg7zGzMIjvyipC+EwXPif2QAUcEdIYvK0W+Ldm61wC0Nt nFTL8oaMN50Wu0QqRBsxS+Ej5kPH4rpNOv6OeLh/FRrjUqdh0RJcB6VnoUnuR8wl/2Pq DVSAjrkghGwJ2FqonBmGQvp6j8EibOGMv2KIDpZQN0B2CHvoDbjmsfZeoqB1tReYLxgT fnzJg3QNYiE/RvtbhJtzijSZI/0UXrFOeOILlp1IyWSkEBVwZNsTZk7mbKwwzPiX1bWy MsIZTK4TkoPWLFn3ci5TRv9sQprHfJyDRgxBKPWifUMDUQvUuiyW2mW3TLve3Ywvb7y7 sUUA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sHTDxQxQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd4292b06sm53431265e9.14.2025.03.06.07.48.50 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:48:50 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 16/54] accel/tcg: Take mmap lock in the whole cpu_memory_rw_debug() function Date: Thu, 6 Mar 2025 16:46:58 +0100 Message-ID: <20250306154737.70886-17-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Simplify user implementation of cpu_memory_rw_debug() by taking the mmap lock globally. See commit 87ab2704296 ("linux-user: Allow gdbstub to ignore page protection") for why this lock is necessary. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250217130610.18313-4-philmd@linaro.org> --- cpu-target.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index 20933bde7d4..b5230ce1837 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -380,6 +380,8 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, int ret = -1; int fd = -1; + mmap_lock(); + while (len > 0) { page = addr & TARGET_PAGE_MASK; l = (page + TARGET_PAGE_SIZE) - addr; @@ -414,11 +416,9 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, * be under mmap_lock() in order to prevent the creation of * another TranslationBlock in between. */ - mmap_lock(); tb_invalidate_phys_range(addr, addr + l - 1); written = pwrite(fd, buf, l, (off_t)(uintptr_t)g2h_untagged(addr)); - mmap_unlock(); if (written != l) { goto out_close; } @@ -454,6 +454,8 @@ out_close: close(fd); } out: + mmap_unlock(); + return ret; } #endif From patchwork Thu Mar 6 15:46:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870875 Delivered-To: patch@linaro.org Received: by 2002:a5d:6c6a:0:b0:391:30e0:ffa5 with SMTP id r10csp102917wrz; Thu, 6 Mar 2025 08:03:43 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWBFWJbJYRmdWx6qloMwGZpZLH0YCDEtlq2D2oyzGGXbioxbzOVzcWe9mjqJmXWWLa/k5jDDA==@linaro.org X-Google-Smtp-Source: AGHT+IEKzAsVU+CzH+//Zk9/95Re1j/uiXIYXsdiAPWx8sVlL3I8SrnjbZhtIvnU53Sz4NkRTh7T X-Received: by 2002:a05:620a:1aa3:b0:7c3:d921:68f3 with SMTP id af79cd13be357-7c3d921691fmr997689785a.0.1741277023479; Thu, 06 Mar 2025 08:03:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741277023; cv=none; d=google.com; s=arc-20240605; b=a6YE4DCIILpr+kH3nDI+FJh9+lbBlFHr6JIHh1CVvU4gNrro/L0oHhFcN9fzFXfPeR IdB54iZGylskMxQ4Wt+/X4lOMFjES0tS0DGVJHMff2V1b+RWOLFHMyFeudhWw/3+1FNf D4xPE5xYy5QSBKTVRnd5MckKdeNyo11LaMCVnVW3D+GRZGJ8fgpSPbqZMlepEue7fJ13 erHWUKBDxChxMGlTAjm1BnqQu45/8PMSVf6SxeSXogeilATAw4IZ+sG8BvvmAB8K7z2N ZaVmuN8ZIf2h3xmjO9wba++5zICQ8SYmMxTv+Mn65KExN0oDf4CpttHlAhcH8OtHUseP G05A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tTLBFu22G8ChNwnUUuiiV0/VSwHr+qaXgLj/hapvjNA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=VPPhPq8gHmcxqJ72XswGPZfNKALJRtPQUoxNZbG8w7ehUSrXeT1Gm82e8Q5/Dq+U+D Wv3RS20IEjbRfT+bwWyBW/GAjeb/gjjOcWarODOdbeQgCGbrBq9erK3gC6yuqcrT1V06 RbvZQ3yh634pR48SjVqa+rfq7B7SXcM7je+sGYsG43SSV9Q3aTGfuzuglsBygZTFAxIj ulTlalFc2bKTYlAE6Up+aOhQEeilFKdij0HYbpcUcy8V54sYqpWdNF99BdribyX/0Ykh xNzC7U/d+4qLz65jVgJ9sIEatLjYo0ORgOZolatwHfMgl4aMEzn3bQw0DaZ0hffdMdG8 1zDg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U1vgWMQx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd426c01bsm54378555e9.2.2025.03.06.07.48.54 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:48:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 17/54] accel/tcg: Avoid using lock_user() in cpu_memory_rw_debug() Date: Thu, 6 Mar 2025 16:46:59 +0100 Message-ID: <20250306154737.70886-18-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We checked the page flags with page_get_flags(), so locking the page is superfluous. Remove the lock_user() calls and directly use g2h() in place. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250217130610.18313-5-philmd@linaro.org> --- cpu-target.c | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index b5230ce1837..3892ce12229 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -374,7 +374,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, { int flags; vaddr l, page; - void * p; uint8_t *buf = ptr; ssize_t written; int ret = -1; @@ -393,13 +392,7 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, } if (is_write) { if (flags & PAGE_WRITE) { - /* XXX: this code should not depend on lock_user */ - p = lock_user(VERIFY_WRITE, addr, l, 0); - if (!p) { - goto out_close; - } - memcpy(p, buf, l); - unlock_user(p, addr, l); + memcpy(g2h(cpu, addr), buf, l); } else { /* Bypass the host page protection using ptrace. */ if (fd == -1) { @@ -424,13 +417,7 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, } } } else if (flags & PAGE_READ) { - /* XXX: this code should not depend on lock_user */ - p = lock_user(VERIFY_READ, addr, l, 1); - if (!p) { - goto out_close; - } - memcpy(buf, p, l); - unlock_user(p, addr, 0); + memcpy(buf, g2h(cpu, addr), l); } else { /* Bypass the host page protection using ptrace. */ if (fd == -1) { From patchwork Thu Mar 6 15:47:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870848 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp334474wri; Thu, 6 Mar 2025 07:56:15 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX2ax6eCKAMWWdijwfu8l43sg+Xuu/LAhsx8uxPJ14Ac6pL5tuQzSSp5wqMBBSzWKVgXRpzhg==@linaro.org X-Google-Smtp-Source: AGHT+IGr86Oz2hM4ltbQ2gfiqPc8kpN4LZZMeWOYTIv+KhpsoAEVGsGaPCptTH4Szmddyh0VDTUQ X-Received: by 2002:ac8:5715:0:b0:471:eca0:113c with SMTP id d75a77b69052e-4750b4c3d2bmr93429051cf.42.1741276575615; Thu, 06 Mar 2025 07:56:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276575; cv=none; d=google.com; s=arc-20240605; b=THGydWA5sQD/fpENkUGVUsKxowf/5Jyf/0FjEye+52zpfAV7GgZnVp7tqiMBSce+MZ +mdQOldZwnGd2HWNlY3BVlKPxvGFC9siMR9YrRqYLKbPIZpVNUwtAp5+3aSRg9bmQWeR qSOfuIBz0LYY3QYspLouN+vtS/SF7+lUZTXV2xcdk3mHKHiVVvgciOxhl4grACv4lh7a 7tOuMwJv43TOs23wUjpeMsWKtdC2vz2ZZQhDqnuQ55kBMceYkiv077lGbh+8a+JxJ2Tt X4S42AVdCgaHACRVsD+qzJ6NiVvN8GUAnQZLFraQsY0KmUSAPrbhVmW8eWkYZzYtoFxb qtEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XYt4cBWZWrjpH5G+9fvDDbmKK0hy/czETSnD+S9rJr4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=BPdGGeRupdFXW5oSJB6pKQ/QLqiVK0HrUd137kjQzkMJpN97//lzMn2Lx92hXD9CqS v3Epzn+5HyNZrj0jJ71sVjFCzddTkvW4HCoo0MzMZIjPDt1ICepGCt9190jqiWRaCuO3 fa4rAew7CZmycXBwtUztew/785vfdS2eT3eIvzxO8tCucq3OWwxG4BReG1N/NrvHi2s4 L5jltIulANwMwOhK4GUwUXl5/4gPFkiIbYktFxxh3VXBuPvcu90nBinpPtl3B8vd1o3P 4AyXdmwwRemxt2zWJrBPqNlCSxRYnbeVBE72bDoU3kd20LJKNSdZcequ5JBEknmscbdN bWJA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Ca0M/kKk"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd93c9d6sm23236255e9.26.2025.03.06.07.48.59 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:48:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 18/54] accel/tcg: Move cpu_memory_rw_debug() user implementation to user-exec.c Date: Thu, 6 Mar 2025 16:47:00 +0100 Message-ID: <20250306154737.70886-19-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org cpu_memory_rw_debug() system implementation is defined in system/physmem.c. Move the user one to accel/tcg/user-exec.c to simplify cpu-target.c maintenance. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250217130610.18313-6-philmd@linaro.org> --- accel/tcg/user-exec.c | 80 ++++++++++++++++++++++++++++++++++++++ cpu-target.c | 90 +------------------------------------------ 2 files changed, 82 insertions(+), 88 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 9d53c9440ea..2322181b151 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "accel/tcg/cpu-ops.h" #include "disas/disas.h" +#include "exec/vaddr.h" #include "exec/exec-all.h" #include "tcg/tcg.h" #include "qemu/bitops.h" @@ -971,6 +972,85 @@ static void *cpu_mmu_lookup(CPUState *cpu, vaddr addr, return ret; } +/* physical memory access (slow version, mainly for debug) */ +int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, + void *ptr, size_t len, bool is_write) +{ + int flags; + vaddr l, page; + uint8_t *buf = ptr; + ssize_t written; + int ret = -1; + int fd = -1; + + mmap_lock(); + + while (len > 0) { + page = addr & TARGET_PAGE_MASK; + l = (page + TARGET_PAGE_SIZE) - addr; + if (l > len) { + l = len; + } + flags = page_get_flags(page); + if (!(flags & PAGE_VALID)) { + goto out_close; + } + if (is_write) { + if (flags & PAGE_WRITE) { + memcpy(g2h(cpu, addr), buf, l); + } else { + /* Bypass the host page protection using ptrace. */ + if (fd == -1) { + fd = open("/proc/self/mem", O_WRONLY); + if (fd == -1) { + goto out; + } + } + /* + * If there is a TranslationBlock and we weren't bypassing the + * host page protection, the memcpy() above would SEGV, + * ultimately leading to page_unprotect(). So invalidate the + * translations manually. Both invalidation and pwrite() must + * be under mmap_lock() in order to prevent the creation of + * another TranslationBlock in between. + */ + tb_invalidate_phys_range(addr, addr + l - 1); + written = pwrite(fd, buf, l, + (off_t)(uintptr_t)g2h_untagged(addr)); + if (written != l) { + goto out_close; + } + } + } else if (flags & PAGE_READ) { + memcpy(buf, g2h(cpu, addr), l); + } else { + /* Bypass the host page protection using ptrace. */ + if (fd == -1) { + fd = open("/proc/self/mem", O_RDONLY); + if (fd == -1) { + goto out; + } + } + if (pread(fd, buf, l, + (off_t)(uintptr_t)g2h_untagged(addr)) != l) { + goto out_close; + } + } + len -= l; + buf += l; + addr += l; + } + ret = 0; +out_close: + if (fd != -1) { + close(fd); + } +out: + mmap_unlock(); + + return ret; +} + #include "ldst_atomicity.c.inc" static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, diff --git a/cpu-target.c b/cpu-target.c index 3892ce12229..83688f1d508 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -19,18 +19,12 @@ #include "qemu/osdep.h" #include "qapi/error.h" - -#include "exec/target_page.h" -#include "exec/page-protection.h" #include "hw/qdev-core.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "migration/vmstate.h" -#ifdef CONFIG_USER_ONLY -#include "qemu.h" -#include "user/page-protection.h" -#else +#ifndef CONFIG_USER_ONLY #include "hw/core/sysemu-cpu-ops.h" #include "exec/address-spaces.h" #include "exec/memory.h" @@ -43,11 +37,11 @@ #include "exec/cpu-common.h" #include "exec/exec-all.h" #include "exec/tb-flush.h" -#include "exec/translation-block.h" #include "exec/log.h" #include "accel/accel-cpu-target.h" #include "trace/trace-root.h" #include "qemu/accel.h" +#include "hw/core/cpu.h" #ifndef CONFIG_USER_ONLY static int cpu_common_post_load(void *opaque, int version_id) @@ -367,86 +361,6 @@ void cpu_abort(CPUState *cpu, const char *fmt, ...) abort(); } -/* physical memory access (slow version, mainly for debug) */ -#if defined(CONFIG_USER_ONLY) -int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, - void *ptr, size_t len, bool is_write) -{ - int flags; - vaddr l, page; - uint8_t *buf = ptr; - ssize_t written; - int ret = -1; - int fd = -1; - - mmap_lock(); - - while (len > 0) { - page = addr & TARGET_PAGE_MASK; - l = (page + TARGET_PAGE_SIZE) - addr; - if (l > len) - l = len; - flags = page_get_flags(page); - if (!(flags & PAGE_VALID)) { - goto out_close; - } - if (is_write) { - if (flags & PAGE_WRITE) { - memcpy(g2h(cpu, addr), buf, l); - } else { - /* Bypass the host page protection using ptrace. */ - if (fd == -1) { - fd = open("/proc/self/mem", O_WRONLY); - if (fd == -1) { - goto out; - } - } - /* - * If there is a TranslationBlock and we weren't bypassing the - * host page protection, the memcpy() above would SEGV, - * ultimately leading to page_unprotect(). So invalidate the - * translations manually. Both invalidation and pwrite() must - * be under mmap_lock() in order to prevent the creation of - * another TranslationBlock in between. - */ - tb_invalidate_phys_range(addr, addr + l - 1); - written = pwrite(fd, buf, l, - (off_t)(uintptr_t)g2h_untagged(addr)); - if (written != l) { - goto out_close; - } - } - } else if (flags & PAGE_READ) { - memcpy(buf, g2h(cpu, addr), l); - } else { - /* Bypass the host page protection using ptrace. */ - if (fd == -1) { - fd = open("/proc/self/mem", O_RDONLY); - if (fd == -1) { - goto out; - } - } - if (pread(fd, buf, l, - (off_t)(uintptr_t)g2h_untagged(addr)) != l) { - goto out_close; - } - } - len -= l; - buf += l; - addr += l; - } - ret = 0; -out_close: - if (fd != -1) { - close(fd); - } -out: - mmap_unlock(); - - return ret; -} -#endif - bool target_words_bigendian(void) { return TARGET_BIG_ENDIAN; From patchwork Thu Mar 6 15:47:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870853 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp334965wri; Thu, 6 Mar 2025 07:57:32 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWbtUCzDzn8oMNPG693YzEQqq3lihobzrxSrNTsn6o+AKY0UASUYEpvyKokNZX7V8q+cUZvqw==@linaro.org X-Google-Smtp-Source: AGHT+IGQZTHiEcDdh8Ixo9S077rQPK0gepb76jj6Kn+rjgK6COvYDA8c1tgfw7g/sO7gnmstwvId X-Received: by 2002:a05:622a:ce:b0:474:ed6e:39f2 with SMTP id d75a77b69052e-4750b4e7dacmr88485811cf.44.1741276651539; Thu, 06 Mar 2025 07:57:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276651; cv=none; d=google.com; s=arc-20240605; b=FjDtBmw9rILltPEUCM0AWKmpeZ3G1Ci4KHjhdxva0mhn1a0qxvRxjL6w49ZtNjY9h4 gMGa9gjY8YHNNeZSQD+TsdC/oJ8MYreLEHMHQzGYZoByphquh5jsgKUkjo0iJ8Rr76U3 jqZUfMf0yNLYjIPpfY3gGvBdjBM7JkCjISfqRIRwnDAj82M81XrFr58EFWB4KRZ9aZ1G rJXuKP9Q/SeYam2OHTxdrqLNLy+qTJcGTHuokTISrZHn7QxurQURF64DhJaajXIEu0fp t9M6ng1ct9Sy2rtvL/eAAfNmZV22q3fL6AiXYbWjTFBVYQWnr65kRZWhWJjduIxrkB3A eLGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MUTTZ9ZjMGE0zesMow2iRN4HqaCDCLVgPrmD8dOYeq0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=VfVjuA69+Zyb7DhDgsl8K77x9nt/r6ayamyHjJ7qokP5AwaiDhnfy+Tjoer7z89EcE +P+Ro8+sJs9f5gDo6aL05TiMs3h77oRzU7vFhW7zEE3x4meMPLm7+JptXLL9zwZ3wcas f1eFOiYioiXmH1U1BUaAWj2q01Kn/TR1+acbMVL3Eu05d84PayaG8zWN8necHylfNnwn siv32vRK1Csw4/I5gir0eDxHXetHY75llDo4kjDaQspZD9t4kUXb68SIFTV/Q1SNG7y/ 43xbjHaFGb1FaKjmUfhiwwp+QDVab1aHY0vpYUB74YPkodIW5R4JlQh9v9F17guW64Kt PWTQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LbJ29HbZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bcbcc0c39sm66381085e9.0.2025.03.06.07.49.03 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:49:03 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 19/54] accel/kvm: Remove unused 'system/cpus.h' header in kvm-cpus.h Date: Thu, 6 Mar 2025 16:47:01 +0100 Message-ID: <20250306154737.70886-20-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Missed in commit b86f59c7155 ("accel: replace struct CpusAccel with AccelOpsClass") which removed the single CpusAccel use. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250123234415.59850-7-philmd@linaro.org> --- accel/kvm/kvm-cpus.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h index b5435286e42..688511151c8 100644 --- a/accel/kvm/kvm-cpus.h +++ b/accel/kvm/kvm-cpus.h @@ -10,8 +10,6 @@ #ifndef KVM_CPUS_H #define KVM_CPUS_H -#include "system/cpus.h" - int kvm_init_vcpu(CPUState *cpu, Error **errp); int kvm_cpu_exec(CPUState *cpu); void kvm_destroy_vcpu(CPUState *cpu); From patchwork Thu Mar 6 15:47:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870871 Delivered-To: patch@linaro.org Received: by 2002:a5d:6c6a:0:b0:391:30e0:ffa5 with SMTP id r10csp102153wrz; Thu, 6 Mar 2025 08:02:52 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU/+QprXBwyMz3XzsohnVJnHNYjgh8CoJnLPOv0BtR+LlKSAdbjRtn3dOZi1NiErrDgtaDuUw==@linaro.org X-Google-Smtp-Source: AGHT+IHy28GFsR7F9EPSf9/gg58uJNnGX+b8Vha2gq8vPHa5aBb66+7yWXUrCx28syqDH4QLC8CO X-Received: by 2002:a05:6122:8297:b0:51b:a11f:cbdb with SMTP id 71dfb90a1353d-523e4172c0amr25926e0c.4.1741276971183; Thu, 06 Mar 2025 08:02:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276971; cv=none; d=google.com; s=arc-20240605; b=aBod9UzhsKhT/GqfGSXPbLcfwbRcsH0Xzw2XNdHTOYDdnIoXEpVRSI9x7j8mXr7nBF 6Xlt/42I9nH/ABExRW6qpoPPv1N5nIzjumm5o3qY9aBiOLZbgCwSiyOYlqglMDXCBhm6 DWbAvfqW32zLDwkwv0ajAlqT41AX2M5+KIUNSJepaGLYl5vGF6dKxXZnpwOpgXnTG3Ht N32dMkZbyhd6pqodu1tts6WvTzj066IKLtvpqHTatOSQEwoeF2EtDBI2V9AE30mpCqIo 6+3iD2P+l2j9VxP/4kOr6H/kP19IJOAjtt/Gbyw1+5gKD6k96mLNHiUNIMNLRoZ8zwaN F58A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=d6J+LsLjSWQlqsq7ooik8ElyF+HqmtBS26XCNLHBy/I=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=grnAN9xXi8+/rfqNRAgokcjYpo6tPp0MHk5XNA1R7yBbeDdOAnYtRnp+tm9rPucIu0 pWJqgoRDcv0IhiBaGNvXv9OEy4NlF9/QS2MawWb35XLLjS/rQ02/QGB7lM+CaRNajpT1 cBqtR0fbdsHKz0vC9EbnazqIxQOmYy+cLcSDwwngUlKjT4o++CajsULtvTce3vqA7GwX 8Tyk4w8vVdNJfTnvVi1tUq5zNNs9FWQqTo8CUpzg8/UAfiLR6Fb9Luwsa7TKa/MG1kOC xQWhAMlLFTB3KCdX3A4VqXlz5sLbMXnXDeRfMqzm/rzgtHPIR9/dJ0U8vxc/QUFCLrVa vdzA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UisdJWTc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd41c7cc7sm56999535e9.0.2025.03.06.07.49.07 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:49:08 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 20/54] cpus: Fix style in cpu-target.c Date: Thu, 6 Mar 2025 16:47:02 +0100 Message-ID: <20250306154737.70886-21-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Fix style on code we are going to modify. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250123234415.59850-16-philmd@linaro.org> --- cpu-target.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index 83688f1d508..b925b9391e8 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -48,12 +48,15 @@ static int cpu_common_post_load(void *opaque, int version_id) { CPUState *cpu = opaque; - /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the - version_id is increased. */ + /* + * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the + * version_id is increased. + */ cpu->interrupt_request &= ~0x01; tlb_flush(cpu); - /* loadvm has just updated the content of RAM, bypassing the + /* + * loadvm has just updated the content of RAM, bypassing the * usual mechanisms that ensure we flush TBs for writes to * memory we've translated code from. So we must flush all TBs, * which will now be stale. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c0e2b8bsm2418916f8f.64.2025.03.06.07.49.12 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:49:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 21/54] cpus: Restrict cpu_common_post_load() code to TCG Date: Thu, 6 Mar 2025 16:47:03 +0100 Message-ID: <20250306154737.70886-22-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPU_INTERRUPT_EXIT was removed in commit 3098dba01c7 ("Use a dedicated function to request exit from execution loop"), tlb_flush() and tb_flush() are related to TCG accelerator. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250123234415.59850-17-philmd@linaro.org> --- cpu-target.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index b925b9391e8..48446c90212 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -46,22 +46,25 @@ #ifndef CONFIG_USER_ONLY static int cpu_common_post_load(void *opaque, int version_id) { - CPUState *cpu = opaque; + if (tcg_enabled()) { + CPUState *cpu = opaque; - /* - * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the - * version_id is increased. - */ - cpu->interrupt_request &= ~0x01; - tlb_flush(cpu); + /* + * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the + * version_id is increased. + */ + cpu->interrupt_request &= ~0x01; - /* - * loadvm has just updated the content of RAM, bypassing the - * usual mechanisms that ensure we flush TBs for writes to - * memory we've translated code from. So we must flush all TBs, - * which will now be stale. - */ - tb_flush(cpu); + tlb_flush(cpu); + + /* + * loadvm has just updated the content of RAM, bypassing the + * usual mechanisms that ensure we flush TBs for writes to + * memory we've translated code from. So we must flush all TBs, + * which will now be stale. + */ + tb_flush(cpu); + } return 0; } From patchwork Thu Mar 6 15:47:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870863 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp335829wri; Thu, 6 Mar 2025 07:59:53 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUxxTebRnf4TcG3GSaCzlNZ+D3T45SVC7SdsmgSfMKrclgoiQt+BzpMb0TlHQEz5yBEv1l0LQ==@linaro.org X-Google-Smtp-Source: AGHT+IHgKg3r2rgE4j3uqjpWGY+ASggjcopdjj1Wz4MvATq6alGf++I6QO7b07FQGz4zZ/49Bv/G X-Received: by 2002:ac8:5a4c:0:b0:472:3a5:683c with SMTP id d75a77b69052e-475bb81b272mr43201cf.14.1741276793749; Thu, 06 Mar 2025 07:59:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276793; cv=none; d=google.com; s=arc-20240605; b=B2OFItmCCt2P5veZhzQ4dVxN+tPvUnc0iUVVMexm18G7Xq+K7CHKRfHxX6xyPQlhOz bzgDC5B3vIvpzbO7DIq/T8mItHy7zgdTJgVa7SCtb2DcP7Zl9XAIbxwtE6UGsWOjsYga ksASX5Z8Qi/TVWWRvIHEcYwiFrfJsSk/TUIfIjdbCgw214vmgAS2IKCSeJOKLF7pQ/a/ VUvFCcjxzg25pZrJlBHgrkkmUrRo8UamfEM7fLriXxV/Zyy0gdjIPkWTsgS3KGXZbEir v4my5p1DaNaT8B14Yt0HOGsouKXb1WfEqUHIyLWD3M6b3+fMZElVl3PAv+eIIAXatHja OL9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=X8Saq/dqG9xCUSyrkXOExGdZvozj3jjUcX+27h5Z2go=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=g89jBpjllyuTp0SGZ3s7kVT3f8ZG/6oe/A1lG/Ph0IutWDodHw8dc89xFMpSPmq2XN iSuouEBPz9qyBwH55/bSbzXV246xRGzUtsj/EXoFH6nPdU3GZBVY5mm7BcDy5w64bAuY JN/nlNfeTW9LYF3zUn0QD06EF+LvGc5i7sEUXmprlCmwW7qAZmlNWo0cAqBlTrRZQ01+ SIv5CVFxNJXdxMQv7eR4dkK7RZ+XrXnT+O3fXjdIji+UdMc7Q17SOPVoZX2nty9UfFH/ aJ8ZeeZXh5nUVqsX+7xsrgjXPPDiUCUhigRLH+e/60HSc5z9cBV9Z2ohdb6nS1eQdowK i/mw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bP07UptF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c0e2f39sm2374704f8f.80.2025.03.06.07.49.16 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:49:16 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 22/54] cpus: Have cpu_class_init_props() per user / system emulation Date: Thu, 6 Mar 2025 16:47:04 +0100 Message-ID: <20250306154737.70886-23-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rather than maintaining a mix of system / user code for CPU class properties, move system properties to cpu-system.c and user ones to the new cpu-user.c unit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250123234415.59850-18-philmd@linaro.org> --- MAINTAINERS | 1 + cpu-target.c | 58 -------------------------------------------- hw/core/cpu-system.c | 40 ++++++++++++++++++++++++++++++ hw/core/cpu-user.c | 27 +++++++++++++++++++++ hw/core/meson.build | 5 +++- 5 files changed, 72 insertions(+), 59 deletions(-) create mode 100644 hw/core/cpu-user.c diff --git a/MAINTAINERS b/MAINTAINERS index a0e462d03ca..1d1fadc3bc9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3791,6 +3791,7 @@ Overall usermode emulation M: Riku Voipio S: Maintained F: accel/tcg/user-exec*.c +F: hw/core/cpu-user.c F: include/user/ F: common-user/ diff --git a/cpu-target.c b/cpu-target.c index 48446c90212..f4c834fd26a 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -19,15 +19,12 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "hw/qdev-core.h" -#include "hw/qdev-properties.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "migration/vmstate.h" #ifndef CONFIG_USER_ONLY #include "hw/core/sysemu-cpu-ops.h" #include "exec/address-spaces.h" -#include "exec/memory.h" #endif #include "system/accel-ops.h" #include "system/cpus.h" @@ -178,61 +175,6 @@ void cpu_exec_unrealizefn(CPUState *cpu) accel_cpu_common_unrealize(cpu); } -/* - * This can't go in hw/core/cpu.c because that file is compiled only - * once for both user-mode and system builds. - */ -static const Property cpu_common_props[] = { -#ifdef CONFIG_USER_ONLY - /* - * Create a property for the user-only object, so users can - * adjust prctl(PR_SET_UNALIGN) from the command-line. - * Has no effect if the target does not support the feature. - */ - DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState, - prctl_unalign_sigbus, false), -#else - /* - * Create a memory property for system CPU object, so users can - * wire up its memory. The default if no link is set up is to use - * the system address space. - */ - DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, - MemoryRegion *), -#endif -}; - -#ifndef CONFIG_USER_ONLY -static bool cpu_get_start_powered_off(Object *obj, Error **errp) -{ - CPUState *cpu = CPU(obj); - return cpu->start_powered_off; -} - -static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp) -{ - CPUState *cpu = CPU(obj); - cpu->start_powered_off = value; -} -#endif - -void cpu_class_init_props(DeviceClass *dc) -{ -#ifndef CONFIG_USER_ONLY - ObjectClass *oc = OBJECT_CLASS(dc); - - /* - * We can't use DEFINE_PROP_BOOL in the Property array for this - * property, because we want this to be settable after realize. - */ - object_class_property_add_bool(oc, "start-powered-off", - cpu_get_start_powered_off, - cpu_set_start_powered_off); -#endif - - device_class_set_props(dc, cpu_common_props); -} - void cpu_exec_initfn(CPUState *cpu) { #ifndef CONFIG_USER_ONLY diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index 6e307c89597..1310b4203fd 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -20,7 +20,10 @@ #include "qemu/osdep.h" #include "qapi/error.h" +#include "exec/memory.h" #include "exec/tswap.h" +#include "hw/qdev-core.h" +#include "hw/qdev-properties.h" #include "hw/core/sysemu-cpu-ops.h" bool cpu_paging_enabled(const CPUState *cpu) @@ -147,3 +150,40 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) } return res; } + +static const Property cpu_system_props[] = { + /* + * Create a memory property for system CPU object, so users can + * wire up its memory. The default if no link is set up is to use + * the system address space. + */ + DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, + MemoryRegion *), +}; + +static bool cpu_get_start_powered_off(Object *obj, Error **errp) +{ + CPUState *cpu = CPU(obj); + return cpu->start_powered_off; +} + +static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp) +{ + CPUState *cpu = CPU(obj); + cpu->start_powered_off = value; +} + +void cpu_class_init_props(DeviceClass *dc) +{ + ObjectClass *oc = OBJECT_CLASS(dc); + + /* + * We can't use DEFINE_PROP_BOOL in the Property array for this + * property, because we want this to be settable after realize. + */ + object_class_property_add_bool(oc, "start-powered-off", + cpu_get_start_powered_off, + cpu_set_start_powered_off); + + device_class_set_props(dc, cpu_system_props); +} diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c new file mode 100644 index 00000000000..e5ccf6bf13a --- /dev/null +++ b/hw/core/cpu-user.c @@ -0,0 +1,27 @@ +/* + * QEMU CPU model (user specific) + * + * Copyright (c) Linaro, Ltd. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/qdev-core.h" +#include "hw/qdev-properties.h" +#include "hw/core/cpu.h" + +static const Property cpu_user_props[] = { + /* + * Create a property for the user-only object, so users can + * adjust prctl(PR_SET_UNALIGN) from the command-line. + * Has no effect if the target does not support the feature. + */ + DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState, + prctl_unalign_sigbus, false), +}; + +void cpu_class_init_props(DeviceClass *dc) +{ + device_class_set_props(dc, cpu_user_props); +} diff --git a/hw/core/meson.build b/hw/core/meson.build index 65a1698ed1f..b5a545a0edd 100644 --- a/hw/core/meson.build +++ b/hw/core/meson.build @@ -46,4 +46,7 @@ system_ss.add(files( 'vm-change-state-handler.c', 'clock-vmstate.c', )) -user_ss.add(files('qdev-user.c')) +user_ss.add(files( + 'cpu-user.c', + 'qdev-user.c', +)) From patchwork Thu Mar 6 15:47:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870881 Delivered-To: patch@linaro.org Received: by 2002:ab3:6e57:0:b0:290:25b2:841c with SMTP id w23csp532157ltm; Thu, 6 Mar 2025 08:06:39 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVLNIlNEwuPneJsf8hSfFX1c3Giz/egoCHHEBQyiw7siSOTtqmxGWHXDClXY32EEZQ/MIjiyw==@linaro.org X-Google-Smtp-Source: AGHT+IHMHKKGwWKcO9Pc+iQzAih3ho5VOjhTcYRoyhdWTN548gzK5aMARqOUihLD7vrYJYlop+pR X-Received: by 2002:a05:6214:202b:b0:6e6:5b8e:7604 with SMTP id 6a1803df08f44-6e8ff765209mr653756d6.12.1741277199383; Thu, 06 Mar 2025 08:06:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741277199; cv=none; d=google.com; s=arc-20240605; b=Wlnd7mMs7uyHFGBuY6I/EneF/QkJq9Qp6kb5+lV3fsdjPf+uz2ik+Y7nCzBxVu/r9t lTgtuwIT0+opxN7VeVNOAeo3GGncBR4Zv09LqMnvapm3qChxxxtWu0MDwB28g0PsWN6R sa5KW+xPLV9VklVZ/yjqscsQmn+wwH2LerzGVpWXWL/jYhp+UcO8Cs6JwWdoBAIHIgVX IzN+s3HGNB0Eq1yAGBjJYpZXv3SLCleM9qNDd/N5QKH2SY7fdvF7c52fYDiBl0AAt7GH PELO1wR7FTOX/W2VRyDL3FvontSnEuMwUu2LyKaeWXu0/ZhD47K3jXz/Z2diT1L0b9Ji 54Lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7gQL+fUXOizsPvaDiR2QJscVtgRbEO+e68iNhkxG0Ak=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=b9ITvJGGpy57ef1Xhr4n3YIwkIPSFdACsvucya2kdu/nAl9XBF7pNqn3H94XgvqeqW ZAuT41cGY1oPKVZSXqjXB95k358SMal/U7JYyoDiJO1pVK10tex140K8Csj1qhEnGZ8d 06j8OHGhdPTYCC0ndwC3FFdMPT1G0bo4IESjbPwOmP9EirUA1NE5wbCe3q4YpTIw9X/z 8Pw0t9LN5PpJxbXsewLn0+tgO8q7GcfMa2beZ++0NBJxlZnXqTCXwqD9TE/76PZCfDyK PAINTJMAaKM+scRvzWJsSyDpi6oSnBP+S2tjb7TWBA1vQjxCsiMgHTvM0kyGt9ADlazm rdWg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=klKKoksQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c103f57sm2411276f8f.91.2025.03.06.07.49.21 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:49:21 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 23/54] cpus: Have cpu_exec_initfn() per user / system emulation Date: Thu, 6 Mar 2025 16:47:05 +0100 Message-ID: <20250306154737.70886-24-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Slighly simplify cpu-target.c again by extracting cpu_exec_initfn() to cpu-{system,user}.c, adding an empty stub for user emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250123234415.59850-19-philmd@linaro.org> --- cpu-target.c | 9 --------- hw/core/cpu-system.c | 7 +++++++ hw/core/cpu-user.c | 5 +++++ 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index f4c834fd26a..5aa6c4b0c63 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -24,7 +24,6 @@ #include "migration/vmstate.h" #ifndef CONFIG_USER_ONLY #include "hw/core/sysemu-cpu-ops.h" -#include "exec/address-spaces.h" #endif #include "system/accel-ops.h" #include "system/cpus.h" @@ -175,14 +174,6 @@ void cpu_exec_unrealizefn(CPUState *cpu) accel_cpu_common_unrealize(cpu); } -void cpu_exec_initfn(CPUState *cpu) -{ -#ifndef CONFIG_USER_ONLY - cpu->memory = get_system_memory(); - object_ref(OBJECT(cpu->memory)); -#endif -} - char *cpu_model_from_type(const char *typename) { const char *suffix = "-" CPU_RESOLVING_TYPE; diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index 1310b4203fd..e511507e13b 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" +#include "exec/address-spaces.h" #include "exec/memory.h" #include "exec/tswap.h" #include "hw/qdev-core.h" @@ -187,3 +188,9 @@ void cpu_class_init_props(DeviceClass *dc) device_class_set_props(dc, cpu_system_props); } + +void cpu_exec_initfn(CPUState *cpu) +{ + cpu->memory = get_system_memory(); + object_ref(OBJECT(cpu->memory)); +} diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c index e5ccf6bf13a..cdd8de2fefa 100644 --- a/hw/core/cpu-user.c +++ b/hw/core/cpu-user.c @@ -25,3 +25,8 @@ void cpu_class_init_props(DeviceClass *dc) { device_class_set_props(dc, cpu_user_props); } + +void cpu_exec_initfn(CPUState *cpu) +{ + /* nothing to do */ +} From patchwork Thu Mar 6 15:47:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870840 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp332114wri; Thu, 6 Mar 2025 07:50:08 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVKVg3mi+TG7V5kzv5Tm1nwrs3z3jhBH459DbrHKfZN+Ih3ZJQw0GStaIlW9/33YdAk2v5mjg==@linaro.org X-Google-Smtp-Source: AGHT+IFKRyibBcHIAu57nPBZzTSK6ZH8LD7EhxyTYStDjVdDujF7VqGWC16T11lFqqtb/oJtXMiM X-Received: by 2002:a05:620a:4892:b0:7c0:c822:c4e8 with SMTP id af79cd13be357-7c3d8eebc27mr1224808285a.57.1741276208375; Thu, 06 Mar 2025 07:50:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276208; cv=none; d=google.com; s=arc-20240605; b=l1Ms19iPQLSrfDuN5wk73bVsowzCV6wQsvx0tClEKBYbNrbtTFmmFQmBge7ygUefY4 t9CLeInlksnD0QrCasL6pDvxeev09XNrX3jNp2qTk/92hhgc1TfUAIkD5Y/axYauBbL5 Yx14E9RscNnNGHMs4Gv3CV+lMmymZdgt9njhZzyhiUu+Y0kyDs9z9z33say3b2rVzFqr 37ggBtZ3HxksLVyZYXFiQ3SXF6ZQ8lkddJmIuJdpBVUmNJxbSCBCUDDUjHu65n/NufDl cSfxAWbep9PvTx7rloM7VU0ng83syLSPDv8udpgHTPlu6nivcccGtw+TmgfKJQwiddqK sXtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4sVC2TkF7qXS2mJBLOLW8I7WhvYkgMOlFC0u4MR1LHM=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=XfGqtwDYS81ZUvIABsBPXWvm31JbeaC4VXvbY3EpmJhxQJX7onnD2CvJtHTwN2Ce0M CgT0CTOptlB6VBU8di39rcXZbxD0Kc2TvGmcAAU/o1JbrXSu7ImbwG7l2VAmhseY5c+j 5RPDDjdZoS7AHLF2dD4qyTmbAoL4SD7iG4QABLG+JcorsZCNQAFIx4JsQd2TW5jXXITB iq/2e0qMM9AQuHP2efBN2kGcKoQJofqCZrHkEqIzQwBAfxj+M6N8u12n6dYYLf+I5v+1 9t8ZHXoMMmydDREKqEr63ceKaT8xVQlArmLwXocYkbSHpKXreynPeQT2QpxhDaMBDKEq Q0+A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K242bB1o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c0e2b8bsm2419446f8f.64.2025.03.06.07.49.25 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:49:25 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 24/54] cpus: Restrict cpu_get_memory_mapping() to system emulation Date: Thu, 6 Mar 2025 16:47:06 +0100 Message-ID: <20250306154737.70886-25-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250121142341.17001-5-philmd@linaro.org> --- include/hw/core/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 7b6b22c431b..9dd6ac7c763 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -616,6 +616,8 @@ extern bool mttcg_enabled; */ bool cpu_paging_enabled(const CPUState *cpu); +#if !defined(CONFIG_USER_ONLY) + /** * cpu_get_memory_mapping: * @cpu: The CPU whose memory mappings are to be obtained. @@ -627,8 +629,6 @@ bool cpu_paging_enabled(const CPUState *cpu); bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, Error **errp); -#if !defined(CONFIG_USER_ONLY) - /** * cpu_write_elf64_note: * @f: pointer to a function that writes memory to a file From patchwork Thu Mar 6 15:47:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870870 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp336377wri; Thu, 6 Mar 2025 08:00:45 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUmghXCiLaHPYXQjdcc9JZ/KZdTCflEaFcfQJZBdE7+vPRFeJwYNfgvG/uAJe3MNxk/KAClyg==@linaro.org X-Google-Smtp-Source: AGHT+IHzOeFw1JK5rqRX5fen3RNZlZQcZJGsIHO84Hd6Kl6E74UpNXYQNDRt4NjV845eCQ5f/wCN X-Received: by 2002:a05:6122:54b:b0:520:420a:a07a with SMTP id 71dfb90a1353d-523e414404cmr2615e0c.8.1741276845116; Thu, 06 Mar 2025 08:00:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276845; cv=none; d=google.com; s=arc-20240605; b=jXgriMkCgS8DQrz9PaSPSRzNcDm6gFa5F78vda3RAV+ENh4MCYody3IYGWctFTkY1W ROTKGEra9O0iGCm7xas4F8sgYYz/vhP+WNIaT5Kqug1llTbK6V9eH7Bzg/gLBx/zk8Ia 3labFI+AmngMzHAnH7YIjXGJCQ1ZCFibEkvxqGsckSMs49RtM9Cjlo3VuMUBji+xeNaa dEr/4q+UnlO3wtqXCfKpTsVSumlaimfjiZnZj3VM6A9nbHhNstrb8kdb0pBNsDWHSMXJ hTqEzo5vaFxbeYKumxZcmYKu5bZuct6q19ioODdtAv2bVpWSI3L4pXPNEFIB6NoYdcPQ 2xbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=T9ZPZ0rakYtLgiZY4tLzbdV2MvyXhoEkkzhYQQC1PVU=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=BJapdLuHZuA9vhlpHIn73BJ0E/t7T5VY0kI42TkUtUo4Xr1pOff9yOV4lThL5qXeUh EfzyHYmKcqngPQl2U1JMOzoy514CJElzMzKFWu3/ILnYBQ8NUU9gLVjjuqxpM1oDthsW Og+UTxZMXEard073MWqgDpULnEvddrWXaWNcPoEwQoFb2N4TzyglNxaKE7EI7pbGaZf2 qFz9yvgWn2shsFDnvpxq2SftzcSL7miP0xlMHe6DSOYe+A03MCzjD5KWD3d05HJU1b8j ucKdmTX7TuIStw7SWSi4GSycXnZu6NVBqfL3kvcrgysz69NZ0ePUJKAC//aK1vyeg5BM Iweg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dizTG2Hw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd91338cesm41488605e9.7.2025.03.06.07.49.30 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:49:30 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 25/54] hw/core/generic-loader: Do not open-code cpu_set_pc() Date: Thu, 6 Mar 2025 16:47:07 +0100 Message-ID: <20250306154737.70886-26-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Directly call cpu_set_pc() instead of open-coding it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250122093028.52416-2-philmd@linaro.org> --- hw/core/generic-loader.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index d9f5c2e8325..d3a426a1a26 100644 --- a/hw/core/generic-loader.c +++ b/hw/core/generic-loader.c @@ -47,11 +47,8 @@ static void generic_loader_reset(void *opaque) GenericLoaderState *s = GENERIC_LOADER(opaque); if (s->set_pc) { - CPUClass *cc = CPU_GET_CLASS(s->cpu); cpu_reset(s->cpu); - if (cc) { - cc->set_pc(s->cpu, s->addr); - } + cpu_set_pc(s->cpu, s->addr); } if (s->data_len) { From patchwork Thu Mar 6 15:47:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870862 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp335761wri; Thu, 6 Mar 2025 07:59:41 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXaalY6GC2EsIL9ywxdaSrwz0BLq/UfhjTJy3rHLDkT44O5hf276k/z+vgdgHYRnzGRdUOjAw==@linaro.org X-Google-Smtp-Source: AGHT+IGFhqzJLeTuWHosVK2SmRzhdjthQQvoML0381Pw5aBJe0MCf/Zhr1HZ+URmqj/DNh1qHq94 X-Received: by 2002:a05:622a:1a1e:b0:475:5f2:d445 with SMTP id d75a77b69052e-4750b442ef5mr95030011cf.19.1741276781766; Thu, 06 Mar 2025 07:59:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276781; cv=none; d=google.com; s=arc-20240605; b=jTyywJyzpe2UBu89Ylcy3aCzg5XfwbRIqq98n5ppe/iEhRm0dlNL17XbQQmxfGOqQC HE/q3zTuAbyUro084GwzmvJzSVtRGnNabqQ9IX1RYB8xbvANRj0K7CTYn1Cg+ujXSM90 UU0SEj1xFMHOLQUMUbLf+rxg1I4G+YpMpeNw14FKCXeR07ZXwStBQvcAsoqZAhaAwYiI gJFdMPBrHuTa0RsK4KJEwUErnkS5H8APxsH8DjN1UQ95ge0A13sksK9zr4MnB01op+kr SW43iAZuBkjw1ybDCWW6ThQ8eTmmx78u72CX71gbnc0HDb3Q+GPl7i5y7ybPDxBpK8Au W5Jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=c1VlvOtxLHbEwfuyvRPb+ktDAXmv1s+XhzIa2Um25I8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=EKIVU9R+WD7L8xFbmG3Fg/mQGu5QJvHv7nKpYZmqkpagmnS1eRRE29b/qKxbpvx9qM zh4bHDQwo7vzwBsCcu8AGAbtUW2B52PgfkqoSi98uXe3Q2Q8nP3/NCZeKO0YR3WWx1BZ VQJ1fjAp1rbb0UMN8OI9/n+qEJP6zbuA7KUEn1c1W+TsGeM6zR+jzpHt9/RPpkzey89I bXatcf6MxJPUH5uP8xL02zUEb0rHYjnlCOeOMmQRmRXWoCaNyRxj7WVaWa2misNmQlBK VdzfkqMNpLyMVXWcrNYfObbSZhSvR5zliqj9TwJnsWJpxUEY0nXraIKS1DQXYgqQhtzJ 5cyA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UmD5xqVi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdfe61sm2440970f8f.38.2025.03.06.07.49.34 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:49:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 26/54] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx Date: Thu, 6 Mar 2025 16:47:08 +0100 Message-ID: <20250306154737.70886-27-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Extract the implicit MO_TE definition in order to replace it by runtime variable in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/microblaze); \ done Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20241105130431.22564-14-philmd@linaro.org> --- target/microblaze/translate.c | 36 +++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 24005f05b21..86efabb83b5 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -780,13 +780,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg) static bool trans_lhu(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } static bool trans_lhur(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); } static bool trans_lhuea(DisasContext *dc, arg_typea *arg) @@ -798,26 +798,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); #endif } static bool trans_lhui(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } static bool trans_lw(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } static bool trans_lwr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); } static bool trans_lwea(DisasContext *dc, arg_typea *arg) @@ -829,14 +829,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); #endif } static bool trans_lwi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } static bool trans_lwx(DisasContext *dc, arg_typea *arg) @@ -846,7 +846,7 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); + tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL); tcg_gen_mov_tl(cpu_res_addr, addr); if (arg->rd) { @@ -930,13 +930,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg) static bool trans_sh(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } static bool trans_shr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); } static bool trans_shea(DisasContext *dc, arg_typea *arg) @@ -948,26 +948,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); #endif } static bool trans_shi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } static bool trans_sw(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } static bool trans_swr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); } static bool trans_swea(DisasContext *dc, arg_typea *arg) @@ -979,14 +979,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); #endif } static bool trans_swi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } static bool trans_swx(DisasContext *dc, arg_typea *arg) @@ -1015,7 +1015,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, reg_for_write(dc, arg->rd), - dc->mem_index, MO_TEUL); + dc->mem_index, MO_TE | MO_UL); tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); From patchwork Thu Mar 6 15:47:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870854 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp335148wri; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdfca1sm2348714f8f.22.2025.03.06.07.49.38 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:49:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 27/54] target/microblaze: Set MO_TE once in do_load() / do_store() Date: Thu, 6 Mar 2025 16:47:09 +0100 Message-ID: <20250306154737.70886-28-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All callers of do_load() / do_store() set MO_TE flag. Set it once in the callees. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241105130431.22564-15-philmd@linaro.org> --- target/microblaze/translate.c | 36 +++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 86efabb83b5..0d51b2c468c 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -713,6 +713,8 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, { MemOp size = mop & MO_SIZE; + mop |= MO_TE; + /* * When doing reverse accesses we need to do two things. * @@ -780,13 +782,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg) static bool trans_lhu(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } static bool trans_lhur(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, true); } static bool trans_lhuea(DisasContext *dc, arg_typea *arg) @@ -798,26 +800,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false); #endif } static bool trans_lhui(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } static bool trans_lw(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } static bool trans_lwr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, true); } static bool trans_lwea(DisasContext *dc, arg_typea *arg) @@ -829,14 +831,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false); #endif } static bool trans_lwi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } static bool trans_lwx(DisasContext *dc, arg_typea *arg) @@ -863,6 +865,8 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, { MemOp size = mop & MO_SIZE; + mop |= MO_TE; + /* * When doing reverse accesses we need to do two things. * @@ -930,13 +934,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg) static bool trans_sh(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } static bool trans_shr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, true); } static bool trans_shea(DisasContext *dc, arg_typea *arg) @@ -948,26 +952,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false); #endif } static bool trans_shi(DisasContext *dc, arg_typeb *arg) { TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } static bool trans_sw(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } static bool trans_swr(DisasContext *dc, arg_typea *arg) { TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, true); } static bool trans_swea(DisasContext *dc, arg_typea *arg) @@ -979,14 +983,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg) return true; #else TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdfcdasm2369930f8f.23.2025.03.06.07.49.43 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:49:43 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 28/54] target/microblaze: Introduce mo_endian() helper Date: Thu, 6 Mar 2025 16:47:10 +0100 Message-ID: <20250306154737.70886-29-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org mo_endian() returns the target endianness, currently static. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241105130431.22564-16-philmd@linaro.org> --- target/microblaze/translate.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0d51b2c468c..b5389d65b2e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -708,12 +708,17 @@ static void record_unaligned_ess(DisasContext *dc, int rd, } #endif +static inline MemOp mo_endian(DisasContext *dc) +{ + return MO_TE; +} + static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, int mem_index, bool rev) { MemOp size = mop & MO_SIZE; - mop |= MO_TE; + mop |= mo_endian(dc); /* * When doing reverse accesses we need to do two things. @@ -848,7 +853,8 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL); + tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, + mo_endian(dc) | MO_UL); tcg_gen_mov_tl(cpu_res_addr, addr); if (arg->rd) { @@ -865,7 +871,7 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, { MemOp size = mop & MO_SIZE; - mop |= MO_TE; + mop |= mo_endian(dc); /* * When doing reverse accesses we need to do two things. @@ -1019,7 +1025,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg) tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, reg_for_write(dc, arg->rd), - dc->mem_index, MO_TE | MO_UL); + dc->mem_index, mo_endian(dc) | MO_UL); tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); From patchwork Thu Mar 6 15:47:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870857 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp335197wri; Thu, 6 Mar 2025 07:58:09 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXwKqiy6UOunsa949VGZrwXHX+prH5lVkHLPpbPyrpvIzwL3qvQhBITtWv5d8F9KEdsoiCZOg==@linaro.org X-Google-Smtp-Source: AGHT+IHxvVSw3jOH9ah3b4lkLRh3tVCDvhpY3qE/nSEuxB9qp6ZgTXf82XzoeAeB2GPbtlykIzQ6 X-Received: by 2002:a05:620a:6404:b0:7c0:a0fd:7b42 with SMTP id af79cd13be357-7c3d8ba8131mr1142809685a.0.1741276689430; Thu, 06 Mar 2025 07:58:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276689; cv=none; d=google.com; s=arc-20240605; b=IUSUpDeRexjgbLpHxmnDZIe/fH4srYWVrTEeKcXc4UwMwTp3KNw9D4spzqzMvKkA7C aQYk2hG+IsWY7Yl8CI6CaitohSC9hny9uHDWva1uBpKPn4X4nmaGf3GLOpyzmr6TF+XG M+rrd/k5ivpmW/gjhxdORuwvByakIU9V1n/aTP8DSneodHuPjipEipbSmCyFUVD8At8e TTj3f+tr58lohhDwTrEGxC7vjjVFGCcYWTb1AxVl6JXYNb+vDz5tdFu7aSwc8hsnRn4y k5FTT2HyFsY032SJKcG4s1Iuf36tW2xYIPVfheXMsncaqAnIhtXzEXvY6ciViZ9GJ/OJ Vz9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tN8MUCR59yT1PPc6yhlXwubOk3u9382+22fqIhPwV6Q=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=bm78xVN9hfdOWJGsftX9QtebblITMz+eLdsciLnMzvl15RDHvETZTD0+Fg0Ys8u31r PcBK0irm+einpf0+gk3nYmCClP6Rvm4ZotIowpn54d1d8RDzlLOh5fTQ7z5dvL10lvMP Whl/563y9vPjQkxSNmOGaOCuoBqaU5aVKpFO4/RUJeouqsnJ1L1ASdRUN61qYDmjkO6y UjLSrEDn6/k339h2XvNaJzgVmC15KmwgkE03wJXmqEw4S+UAGoLTOYefcvol7W/bPsHs UF2p/VhxhrlrxhDrDS7769a8F1NG9Iri08ziLYPvGWqo0ewbKoQboUbZEKpkcLJvDIVh kiWw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F1+dCZfx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c103035sm2380215f8f.88.2025.03.06.07.49.47 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:49:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 29/54] target/microblaze: Consider endianness while translating code Date: Thu, 6 Mar 2025 16:47:11 +0100 Message-ID: <20250306154737.70886-30-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Consider the CPU ENDI bit, swap instructions when the CPU endianness doesn't match the binary one. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20241105130431.22564-17-philmd@linaro.org> --- target/microblaze/cpu.h | 7 +++++++ target/microblaze/translate.c | 5 +++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index f6879eee352..e44ddd53078 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -414,6 +414,13 @@ void mb_translate_code(CPUState *cs, TranslationBlock *tb, /* Ensure there is no overlap between the two masks. */ QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); +static inline bool mb_cpu_is_big_endian(CPUState *cs) +{ + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + + return !cpu->cfg.endi; +} + static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index b5389d65b2e..b54e5ac4b2f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -710,7 +710,7 @@ static void record_unaligned_ess(DisasContext *dc, int rd, static inline MemOp mo_endian(DisasContext *dc) { - return MO_TE; + return dc->cfg->endi ? MO_LE : MO_BE; } static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, @@ -1647,7 +1647,8 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) dc->tb_flags_to_set = 0; - ir = translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_next); + ir = translator_ldl_swap(cpu_env(cs), &dc->base, dc->base.pc_next, + mb_cpu_is_big_endian(cs) != TARGET_BIG_ENDIAN); if (!decode(dc, ir)) { trap_illegal(dc, true); } From patchwork Thu Mar 6 15:47:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870878 Delivered-To: patch@linaro.org Received: by 2002:ab3:6e57:0:b0:290:25b2:841c with SMTP id w23csp530744ltm; Thu, 6 Mar 2025 08:05:25 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXoxsM0Q8EvkLXGDZdANf27VuBZfyHj9i35NVZJ/t/s6xTc93ZCJTlwPxt2kwL2JA2ExJKE6Q==@linaro.org X-Google-Smtp-Source: AGHT+IE0Vgr8mkw6uo+3LlffzryTuyH1uKoirNdW4sPFBMKyr4lRHSJhyQ17hjunHQnp5XldPSYd X-Received: by 2002:a05:6102:943:b0:4c1:abaa:ad93 with SMTP id ada2fe7eead31-4c2e27fb7bemr5190051137.14.1741277122737; Thu, 06 Mar 2025 08:05:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741277122; cv=none; d=google.com; s=arc-20240605; b=aGZBpxyDMRzc46gZfZwJuJHcQ7u2Ni/hNqaf5cfNyD5wGPrz7HqBdeKCzr193MNkTr Ae9iL+nlX/Wg/9M4jiM0/v4I9RN6OjX1bRsaMtsmyZYJeqltw9AkW9a1Tl6Q37i1NYjj yILbCxiIQrXTrA/5HuiYwT8dI/ztz1FnrAAYXrhau/JRuEtj8qrFqfMnPrzq6Kre3AqV BIKQkg3GjuiCyOBMe43jEKmEefVgpRzPEhJ6UhHRtGAHh1V/OGSlEyDoalr2CspED3iX N0hnKiG70eDMOGZ0vrKxfbGyInBPQnNJreHusrXLiQNLo6c/6Swo3sRqg8FGMT6ba67O xlHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LYWY2vE23XQ8tYGl52Ly1mLv0cHxN8U1e33vECpnZa0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=kR9oJ7/hlJz/PonBW4JyZqWB4oNliNN+ZvoEazhyMR1gNK/0wDGBAISzUxp4GX8daS vXl5+hZFwvp76//gb6sh8Vjj36UZWsC69qRTOYSvMPTQjW/YK92J3xaVLyYaFh+YCLuk xDVzrtVp0g3Fh8uClJtFTTXZUXwd4/r96tcD+UTrJBmeEWPg95og6EEVQcEieF1tmDYI UA80Ki1fJTFBrCzZhjLrWC/50zWfO+TThgUo37n6xEKp2d/yMs1vVkFrYYJgjx7inbF4 AVG6OrHhJG/VDdaOAYiLfs7dtOi/AK6KxsJ7aKKAP7SCemDds3GIcDKhPZZEtgmGXstM PgBA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WoDq2h8W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfba679sm2381963f8f.8.2025.03.06.07.49.52 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:49:52 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 30/54] target/i386/hvf: Variable type fixup in decoder Date: Thu, 6 Mar 2025 16:47:12 +0100 Message-ID: <20250306154737.70886-31-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Phil Dennis-Jordan decode_bytes reads 1, 2, 4, or 8 bytes at a time. The destination variable should therefore be a uint64_t, not a target_ulong. Signed-off-by: Phil Dennis-Jordan Fixes: ff2de1668c9 ("i386: hvf: remove addr_t") Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20241209203629.74436-9-phil@philjordan.eu> Signed-off-by: Philippe Mathieu-Daudé --- target/i386/hvf/x86_decode.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_decode.c index d6d5894e54b..5fea2dd3cc0 100644 --- a/target/i386/hvf/x86_decode.c +++ b/target/i386/hvf/x86_decode.c @@ -61,8 +61,8 @@ uint64_t sign(uint64_t val, int size) static inline uint64_t decode_bytes(CPUX86State *env, struct x86_decode *decode, int size) { - target_ulong val = 0; - + uint64_t val = 0; + switch (size) { case 1: case 2: From patchwork Thu Mar 6 15:47:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870859 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp335307wri; Thu, 6 Mar 2025 07:58:26 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXmXcJytQAyhdvkgVHgbPbB+w9vYiMSkWQc+G6KTLByIPtiPtz7s3SSdwx1/yvotWSPSGKDdQ==@linaro.org X-Google-Smtp-Source: AGHT+IGBfU1Sxl8/LejT5txqWVDlgYRT+zq7mrn7YOD7mmN7GuTOzBu8u6VQbLKLi5HeY520xKvA X-Received: by 2002:a05:622a:1801:b0:475:985:c88b with SMTP id d75a77b69052e-4750b465343mr95794521cf.29.1741276706697; Thu, 06 Mar 2025 07:58:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276706; cv=none; d=google.com; s=arc-20240605; b=KTPnU+gocEkBcop1cG5JDw22KNvjc71dO23et1xOwhcVAAXtvRPJaBRG54TAl05zMe gGpEuNDhgcn+mof9Zb+nCgg4+BqjkueYPP6ycFZv50blZfCodBTYn/O1VDRhnA3DAP+N F97I3cuiaAOiJ7Xi/fzguzkdIRERtFLe7Qo3WOBnjyuCbOsapVXeZxA3simUN8sBNtjR pIidzQhF/chcpy1WJ68oWws4LrCjGPO0GUe6BG7Jpma3/SYjWdBS2QBcjB/NoFNm06d4 AeWtjJv6YkcX0TrUhcxL5B9X4PXs6DXBjznt680un0EmwNjYtkK3GiNW8Ibahs+Od9Hg MfMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0UFUf/+4qSNn3mLvNY6YFKF7Ib0WjHNATMofJQT7dhg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=QeE5TfUnZn4ftSPYBW4t6tf/TUveFonq6JcN4U4KkSI0kMzXBMw7oLOi1Le5hFy+w/ s3LTq5xpJm+3RJCCGM4JAY1eDYJ7YUdzX7F23bvPagi53qiSSE/dn3sA5EHkdzpxhe2q tHnr+GRtDwk1J5Jbo8oKeNTLeBsFskh6G+0LSFJxtle0kz7MfJAm4r0jUe8waHKh20u2 HrF7dl6RbP2u8gI4lJqr4Krzij5Lk9DUscIHhJn7e6tPZMm2QKS5HrScP+l4hDk98f+8 Q+B7l2lCxYp+y5QHcGC9vJNREBbd8OmtNrApQVSuVBibsnYe2BCZwX4/VArfIICRFgK2 6LEQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QGcalyBp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdfc96sm2444270f8f.31.2025.03.06.07.49.56 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:49:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 31/54] target/openrisc: Call cpu_openrisc_clock_init() in cpu_realize() Date: Thu, 6 Mar 2025 16:47:13 +0100 Message-ID: <20250306154737.70886-32-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org OpenRISC timer is architecturally tied to the CPU. It doesn't belong to the machine init() code to instanciate it: move its creation when a vCPU is realized (after being created). Reported-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daudé Acked-by: Richard Henderson Message-Id: <20250114231304.77150-1-philmd@linaro.org> --- hw/openrisc/openrisc_sim.c | 2 -- hw/openrisc/virt.c | 2 -- target/openrisc/cpu.c | 4 ++++ 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index d9e0744922a..83d7c2a8afc 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -306,8 +306,6 @@ static void openrisc_sim_init(MachineState *machine) exit(1); } - cpu_openrisc_clock_init(cpus[n]); - qemu_register_reset(main_cpu_reset, cpus[n]); } diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c index 9afe407b00a..3055306783e 100644 --- a/hw/openrisc/virt.c +++ b/hw/openrisc/virt.c @@ -487,8 +487,6 @@ static void openrisc_virt_init(MachineState *machine) exit(1); } - cpu_openrisc_clock_init(cpus[n]); - qemu_register_reset(main_cpu_reset, cpus[n]); } diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 0669ba2fd10..785b065b513 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -165,6 +165,10 @@ static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); cpu_reset(cs); +#ifndef CONFIG_USER_ONLY + cpu_openrisc_clock_init(OPENRISC_CPU(dev)); +#endif + occ->parent_realize(dev, errp); } From patchwork Thu Mar 6 15:47:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870849 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp334683wri; Thu, 6 Mar 2025 07:56:47 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWjumQl9iaDJsPHQmwKLJaGwx9F7yZj3HydThshvubrk5ZNKAJf/ReryoIsRGwLZCx5eTydmw==@linaro.org X-Google-Smtp-Source: AGHT+IGAQSBjyHlUc3rorxE+2+AO4rVW8ktQzfecNHvIcZLxhfnwWeHbAFUs0I4X8yGVABD07aZA X-Received: by 2002:a05:622a:1212:b0:472:5ac:48bb with SMTP id d75a77b69052e-4750b45f130mr95871681cf.29.1741276607129; Thu, 06 Mar 2025 07:56:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276607; cv=none; d=google.com; s=arc-20240605; b=Ep46BjA/M1pC9V/UeIwyDCiKVyJhGA/ScHyrUWZqdRfAs5oIzQoOKsCeWfFkWRJdK4 BDVQsIbsKOv9aCfXYQAbR7ad4UIn3u8IB+8JK/xYWXlDl0xDvHbR53HGE+QPqy40s5Pa RkVbCgas2dfaSW6NB41EGMv1Osdq86l5DcFGVJqVtN3ZHQcC7ZtZac9+VU5d4XemMdE0 b1dIq2mXWwG4syKHm+A5rPdOMWqr3idEofPAAFJVUuyaE6Z7TlDzvUvcHsGhLCCUDn5r XlFoOMVeAmdrzppoa9t36rkf/wpr3QbPf/0Vzc+D0ISyi296/p1zypqtCm57kg0b637u DTaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yLBo67sH6HjRZEuxvMy622hl56JAycvhfKaomqodUXg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=VwmQ1CYznxHIJrmrxOdMowqNZ+Kd97MZOeoY4L2k09nNFLAeffS4DqfvQngMARkUra dXfUu6NbVpi0FJB9SjhQ2QU7xAtPz6rCgmb0PHrVfcbDqsFdNx5w7okQ5CcJb8S9R5mC 6E8XvodV/sN+b4JRm3pyX8cHGS043pgtX4brTu9ZK1woXbbjU8tucsXcVtIOJAMK9aDH tygfe+VG2Jf81ixotJIuP7pVUhr23QJFIwNTuYlqlms1qa8X6HxWc5pVJNhh6o8yclpp iPkVUH1eIXemfPBSJAorzCA9d04FfldhDNC77UojVNRB7XGjDFmXUgvaOPr8IQJoO98k O5KQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=epkeGtII; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd94913fsm22808915e9.37.2025.03.06.07.50.01 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:50:01 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 32/54] target/hexagon: Ensure not being build on system emulation Date: Thu, 6 Mar 2025 16:47:14 +0100 Message-ID: <20250306154737.70886-33-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently only user emulation is supported. Assert no target code is built for system emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Brian Cain Message-Id: <20250121142341.17001-2-philmd@linaro.org> --- target/hexagon/cpu.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 79e60d4bfa1..f78c8f9c2a0 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -26,6 +26,10 @@ #include "mmvec/mmvec.h" #include "hw/registerfields.h" +#ifndef CONFIG_USER_ONLY +#error "Hexagon does not support system emulation" +#endif + #define NUM_PREGS 4 #define TOTAL_PER_THREAD_REGS 64 From patchwork Thu Mar 6 15:47:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870865 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp335894wri; Thu, 6 Mar 2025 08:00:01 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXjtVSAcAqjT56I/VDcDXvA0B/XmPX5zl+Iqm1l/e6A6CCSayThK8d2m/fuO0tT13WL+CUB9A==@linaro.org X-Google-Smtp-Source: AGHT+IFEBiYTNqDFjarlrMJepbWZERNVl9Q/hzXrFRDLKOwYTAUNR5HlGDQc03dMYWtDZAsx/+w2 X-Received: by 2002:a05:6214:518b:b0:6e4:4011:9df7 with SMTP id 6a1803df08f44-6e8e6d19443mr102109626d6.16.1741276800909; Thu, 06 Mar 2025 08:00:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276800; cv=none; d=google.com; s=arc-20240605; b=ghfmkVy/4cGZp1y2+cHTb3UWwBP/wu8q1HINY25wsjFnwFS6251HkwJ/dA8Pdl9BFZ yODdlyBhOeL9W4dgWsKQ1OzKch+bPYQgP3RJ94dN0gZlliKjTbShyrp/4R15wuhriOxd pRWm7j4tMHvnWBBsIMce7YSftXJyiY6sF+ZL2Rusmu8eAJXpIRzAjpkOj5jnng3tdiUm c4DLpEwTYV6izTFrSqvz+foMPe3GGAz7deJIl4SCOc4NTT/bScvz79eH5bMXYLv/QOYn Xs92K3YBrEUPCAwPQs+Vdjh4HJOdG17JO96MjhTpk+lJeLVtJ0YZiwUPabNSD0XSQQtV z4Lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6AGaZhzI7b9cA8ZVzToMlsrK1z7aXcYWITqf5Z8tBA0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Led0z4Mz0gQspQPD/rSt3dQEaajF0dEFhtD8Hf6WU+LlqhibSrquzJzWw0R0YeQ4lu eKIaRC68q6jDlS44Pnj1mqZsGwKYkdDpRyB6xpx9Yg1d7IKG38zqq5ozfq+5NhX6yXn+ pEbbOSegMOkPOcpdHQ7PWbKEQDZ2oZ/XyVFh7qioVhZwfmpQ4uxx24ZcEwAv/EbpkWP8 xOFsO3PmI+7rAxwU6TnGuVqejc6PeF9WddHUIMXMZMY8jNxsEArEvkBGD+V33pOUkRUo zFNt9AiWcY7bkVP88V5bZ77C/coqDb6W2zODzmi7RLoKlp2GmJ6oVcXsrlwdHRxGF8In WBZA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ymQ0FTDl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd93c9b6sm23352175e9.29.2025.03.06.07.50.05 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:50:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 33/54] target/rx: Ensure not being build on user emulation Date: Thu, 6 Mar 2025 16:47:15 +0100 Message-ID: <20250306154737.70886-34-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently only system emulation is supported. Assert no target code is built for user emulation. Remove #ifdef'ry since more work is required before being able to emulate a user process. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250121142341.17001-3-philmd@linaro.org> --- target/rx/cpu.h | 6 ++++-- target/rx/cpu.c | 6 ------ target/rx/helper.c | 4 ---- 3 files changed, 4 insertions(+), 12 deletions(-) diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 5ba1874bd76..349d61c4e40 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -26,6 +26,10 @@ #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" +#ifdef CONFIG_USER_ONLY +#error "RX does not support user mode emulation" +#endif + /* PSW define */ REG32(PSW, 0) FIELD(PSW, C, 0, 1) @@ -129,11 +133,9 @@ struct RXCPUClass { #define CPU_RESOLVING_TYPE TYPE_RX_CPU const char *rx_crname(uint8_t cr); -#ifndef CONFIG_USER_ONLY void rx_cpu_do_interrupt(CPUState *cpu); bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -#endif /* !CONFIG_USER_ONLY */ void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 7d5fcbf76ac..17ede51cd11 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -192,13 +192,11 @@ static void rx_cpu_init(Object *obj) qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); } -#ifndef CONFIG_USER_ONLY #include "hw/core/sysemu-cpu-ops.h" static const struct SysemuCPUOps rx_sysemu_ops = { .get_phys_page_debug = rx_cpu_get_phys_page_debug, }; -#endif #include "accel/tcg/cpu-ops.h" @@ -209,11 +207,9 @@ static const TCGCPUOps rx_tcg_ops = { .restore_state_to_opc = rx_restore_state_to_opc, .tlb_fill = rx_cpu_tlb_fill, -#ifndef CONFIG_USER_ONLY .cpu_exec_interrupt = rx_cpu_exec_interrupt, .cpu_exec_halt = rx_cpu_has_work, .do_interrupt = rx_cpu_do_interrupt, -#endif /* !CONFIG_USER_ONLY */ }; static void rx_cpu_class_init(ObjectClass *klass, void *data) @@ -235,9 +231,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data) cc->set_pc = rx_cpu_set_pc; cc->get_pc = rx_cpu_get_pc; -#ifndef CONFIG_USER_ONLY cc->sysemu_ops = &rx_sysemu_ops; -#endif cc->gdb_read_register = rx_cpu_gdb_read_register; cc->gdb_write_register = rx_cpu_gdb_write_register; cc->disas_set_info = rx_cpu_disas_set_info; diff --git a/target/rx/helper.c b/target/rx/helper.c index 80912e8dcb4..7f28e729891 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -40,8 +40,6 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte) env->psw_c = FIELD_EX32(psw, PSW, C); } -#ifndef CONFIG_USER_ONLY - #define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR) void rx_cpu_do_interrupt(CPUState *cs) { @@ -146,5 +144,3 @@ hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { return addr; } - -#endif /* !CONFIG_USER_ONLY */ From patchwork Thu Mar 6 15:47:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870847 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp334432wri; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd8c324csm23300605e9.12.2025.03.06.07.50.10 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:50:11 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 34/54] target/tricore: Ensure not being build on user emulation Date: Thu, 6 Mar 2025 16:47:16 +0100 Message-ID: <20250306154737.70886-35-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently only system emulation is supported. Assert no target code is built for user emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250121142341.17001-4-philmd@linaro.org> --- target/tricore/cpu.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 8e431d79222..cf9dbc6df8e 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -26,6 +26,10 @@ #include "qemu/cpu-float.h" #include "tricore-defs.h" +#ifdef CONFIG_USER_ONLY +#error "TriCore does not support user mode emulation" +#endif + typedef struct CPUArchState { /* GPR Register */ uint32_t gpr_a[16]; From patchwork Thu Mar 6 15:47:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870850 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp334731wri; Thu, 6 Mar 2025 07:56:55 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCW7kN7HSyIzZ/ApO/zNWaLNHc5x3szqT/3hzNGYrgZwHBsIBDE67X4h0oyuQ3I+4QQr+WJNkQ==@linaro.org X-Google-Smtp-Source: AGHT+IHuR2/u98aIpzsIdHQZdVtqDcj3iXsQI2iUZwMXJIqob4D5S4QXEVQPvHfJ6t9O3EQ/2u/N X-Received: by 2002:a05:6214:2027:b0:6e8:fabd:ddd with SMTP id 6a1803df08f44-6e8fabd1133mr32204986d6.1.1741276615516; Thu, 06 Mar 2025 07:56:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276615; cv=none; d=google.com; s=arc-20240605; b=TXfQP8S/NFUFxDFN5FkBznAqxa/RxrTUT5NVU7Vxq+q5Njhiv7QSH8o6QPXHejwHgw 6k+qpquBEa8VQIhAtqdKG3hnZgz8KorWHBQQk1KiTlxiqJOrz2VLOtBc6JybwQ5fAjIq 9HHlEyRUzswlayStZ1y05003VBjtXj541wijO1m6cK+cVO9qJDPhKQm3vSo2lpdEsVIs KQSMoaaSNdh7eY8yo57is0e0O4azIFrNi24tWZX55vahESvDC++BsZCYcI45AHkop8wT vGAO6i/JaJcjWrXhkfQc+lXKI5e+WEqPfvhAr2+M1hbQ0++OxQxTEW69kmkDTu6ab1JS tQ1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SnfT7DORVv/itpA6HOJTnRR+mH0KMqcNOFRFeDG2Dgs=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=D42o8jw8WWpyzQzpLK+RGEMjmkdII2zhD7xkisukigl+VCycGZmUB3RgPZBA1vze/t KYGAZoQFSY4XcIGF2mStuUFLXigQQuDUGtIh3tJF8BCxcp40GkAjfbowmnQpAjNLwo8e FC5pZlZgEQeSLLWEzNsjWb6j0IiPs0fPg223q2ihGidv1KCi6DVye7UhlAMHjHxiPiji RxtxrRpaAkb+8BpAmrdnaEG7mdBcKgI92YbVkzMSMBcmYN716x00cmuGtR9BohVhLoLE DvWBYC65/3lJKw5mQ7yfeiEFu0+9zqAFyuAtXXW/GEulTnjeCJ+8wPzQD+GtjcG4+5hc DuMg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Yj7K6hgr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd8db6c7sm23249105e9.22.2025.03.06.07.50.15 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:50:15 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 35/54] target/mips: Fix possible MSA int overflow Date: Thu, 6 Mar 2025 16:47:17 +0100 Message-ID: <20250306154737.70886-36-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Denis Rastyogin Fix possible overflow in 1 << (DF_BITS(df) - 2) when DF_BITS(df) is 64 by using a 64-bit integer for the shift operation. Found by Linux Verification Center (linuxtesting.org) with SVACE. Reported-by: Dmitriy Fedin Signed-off-by: Denis Rastyogin Reviewed-by: Peter Maydell Message-ID: <20250124122707.54264-1-gerben@altlinux.org> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index ec38d9fde5e..74fb80cc256 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -5577,7 +5577,7 @@ static inline int64_t msa_mulr_q_df(uint32_t df, int64_t arg1, int64_t arg2) { int64_t q_min = DF_MIN_INT(df); int64_t q_max = DF_MAX_INT(df); - int64_t r_bit = 1 << (DF_BITS(df) - 2); + int64_t r_bit = 1LL << (DF_BITS(df) - 2); if (arg1 == q_min && arg2 == q_min) { return q_max; @@ -5685,7 +5685,7 @@ static inline int64_t msa_maddr_q_df(uint32_t df, int64_t dest, int64_t arg1, int64_t q_max = DF_MAX_INT(df); int64_t q_min = DF_MIN_INT(df); - int64_t r_bit = 1 << (DF_BITS(df) - 2); + int64_t r_bit = 1LL << (DF_BITS(df) - 2); q_prod = arg1 * arg2; q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod + r_bit) >> (DF_BITS(df) - 1); @@ -5700,7 +5700,7 @@ static inline int64_t msa_msubr_q_df(uint32_t df, int64_t dest, int64_t arg1, int64_t q_max = DF_MAX_INT(df); int64_t q_min = DF_MIN_INT(df); - int64_t r_bit = 1 << (DF_BITS(df) - 2); + int64_t r_bit = 1LL << (DF_BITS(df) - 2); q_prod = arg1 * arg2; q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod + r_bit) >> (DF_BITS(df) - 1); From patchwork Thu Mar 6 15:47:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870851 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp334851wri; Thu, 6 Mar 2025 07:57:16 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU8Xg7x3Lgy99iSqh1DLuNiT5DYr39UmEO3W7mt9QILPsFWbvjlSKgzunuRqBcbYvKsqD8fNA==@linaro.org X-Google-Smtp-Source: AGHT+IFNHCQOSCy7NzjliufHkzUhKoSCKhku8I8WT5KvtzbdTRPetOx3sZpT7eW801NgBgRy7I35 X-Received: by 2002:a05:620a:6a04:b0:7c3:d316:1d8e with SMTP id af79cd13be357-7c3d8ed8f4dmr1322282185a.53.1741276635873; Thu, 06 Mar 2025 07:57:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276635; cv=none; d=google.com; s=arc-20240605; b=GLWC5sxtXp3dSMCFktUuhAn8D9ka/l90XjRBmcFyIzL8/4TyQsEpSO0eFDS93CZCCK TXJeIoEuRbnKFHF+DVFB3GYg8/gftd7g9WcAC/Thw5AvaJM1oqwl1pXHLopV8KNkLX71 UbOVlgBchOzTC5Z9qMw9gFfuoSnSTKD78fwgr1dKd5T36784jdQa0994+e7KhsZXeRWt fR2pkKU9WAQIaGotA6gFy3s7pZQ4vPViZWgCkrDXgjDy91rLUQIvBfw8dbaBG3ddqP+I 7CZm47AYUAEiXzpquCWGL+qNwRw6xJqfUTYMVvPrCZkj0muSumQja/xJ3jAZ/7z8SylT EuJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ry6/HgwBxYCoKXfN3GlNL4j5WQBtuJxwtVuKKIpyAK8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Mri7sImFx5hVt2OC2buz5c5ou0pHQCkW9bd5rEyRyV9Lno3L92aWSyYDmP7vZpk7E6 IXm5rFzcP5faBv1c9AQKKkT49Ke2IzOD5ZTyJKIIyMsBMQ/mXTV+6En5JbWv2UVkJq3l RRz+Wgzyh22VdC69tKZoBUK4q0jqifzChPH3uJDS/PJLAeqxcMP+rB1Ia1e7IzbNr9t5 PizBirAi8+N/UVoBV78rek4p4IsxLiSr9GoARf0YewTl04P5/19N4e6pc2IUgHHcTN3R C5XrDR6KE41esjtNtUF6NCQoyr4/evlfwnNu8V94Nd6sjJc947wDO2BvIyIiGk4qdFgR x+lQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o3TpJpR+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdfad7sm2393099f8f.26.2025.03.06.07.50.19 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:50:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 36/54] target: Set disassemble_info::endian value for little-endian targets Date: Thu, 6 Mar 2025 16:47:18 +0100 Message-ID: <20250306154737.70886-37-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field for little-endian targets. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-Id: <20250210212931.62401-2-philmd@linaro.org> --- target/alpha/cpu.c | 1 + target/avr/cpu.c | 1 + target/hexagon/cpu.c | 1 + target/i386/cpu.c | 1 + target/loongarch/cpu.c | 1 + target/rx/cpu.c | 1 + 6 files changed, 6 insertions(+) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 57e41fcd784..2eabd7724df 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -85,6 +85,7 @@ static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch) static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) { + info->endian = BFD_ENDIAN_LITTLE; info->mach = bfd_mach_alpha_ev6; info->print_insn = print_insn_alpha; } diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5a0e21465e5..2871d30540a 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -102,6 +102,7 @@ static void avr_cpu_reset_hold(Object *obj, ResetType type) static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) { + info->endian = BFD_ENDIAN_LITTLE; info->mach = bfd_arch_avr; info->print_insn = avr_print_insn; } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 238e63bcea4..a9beb9a1757 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -293,6 +293,7 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type) static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) { info->print_insn = print_insn_hexagon; + info->endian = BFD_ENDIAN_LITTLE; } static void hexagon_cpu_realize(DeviceState *dev, Error **errp) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0cd9b70938d..ab328485acc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8691,6 +8691,7 @@ static void x86_disas_set_info(CPUState *cs, disassemble_info *info) X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; + info->endian = BFD_ENDIAN_LITTLE; info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 : bfd_mach_i386_i8086); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index b4b82425b18..d2e739a029f 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -624,6 +624,7 @@ static void loongarch_cpu_reset_hold(Object *obj, ResetType type) static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) { + info->endian = BFD_ENDIAN_LITTLE; info->print_insn = print_insn_loongarch; } diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 17ede51cd11..1c40c8977e7 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -168,6 +168,7 @@ static void rx_cpu_set_irq(void *opaque, int no, int request) static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) { + info->endian = BFD_ENDIAN_LITTLE; info->mach = bfd_mach_rx; info->print_insn = print_insn_rx; } From patchwork Thu Mar 6 15:47:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870842 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp333314wri; Thu, 6 Mar 2025 07:53:17 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXAwK2/yZVREyi88tTY4lm9T/NFxAKwFK1FZEWOIrBB5mY9TAciD7Z2tr9cCtHgyrWBN99cqQ==@linaro.org X-Google-Smtp-Source: AGHT+IH1JUdjCmfB0iJyTlL09gIwSgIhvjoo0Yh/WFAXG5f36lT5nL13aCjqr1JfPPev0hD6Gzyd X-Received: by 2002:ac8:5852:0:b0:471:fec8:846e with SMTP id d75a77b69052e-4750b4e4bd8mr113753701cf.44.1741276396911; Thu, 06 Mar 2025 07:53:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276396; cv=none; d=google.com; s=arc-20240605; b=k5dma0O+2XE358b/TmQ3R8YZ86R08SXYSQ8YnwzdTXm1tf11fHvpCl8IloUZwlAwZj +Wh0ZdkMrh7zhxAk7IC9yfz8vyWOEd3K6nPuoagqpoHHoACfrd5C1lmO3koKW8WyaC0G tBwusJ7/G/hFHQn/Mwp5CUXNJf+dTm1i7E6aO00Ebe5v6lLECJCcg+Hdk3YIhjwxg6+X jiM8YhSAhjYrjv4LcE7MooWAHKkNUJAhuIKID2HP2lAvlxuNjM2/OT1V2NsgrcPYhQpC reJxZsNlezOURKPAyQ4E8YrVmpttPQtHn0AZZwcJX2HHb8XeoMyW7jLDrhDLjixKKPBq 7Tvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BUX6zYPG6f15eLnBlXMyTHI0pnIpQboe8CXPknmBs/s=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=fKXfo6fRMyyTjj+AB7rsSgOItWwRzAbK6wuQRa+9MWgsI8SjUNlFbVHdthnxPOCCXQ qBXpukXSOUSJkilCX9QdIP8ab5kK0K1bwvyUcMq0dIKYiHlqmZqwlMZSdAXl2nw5Fp0s tIF+1YSRbD0LoTkaivCagHq7tQN08FVEFJIoYgnqLHu8si3xOe7GqQ5O0Os5qYMmsPG1 8OrJ4do78DX9mcm5J+GJEEbDyG6YlfnyCavml9UplYwvKdzh1xzFkk8liZDSXuQchKx1 eAn9cWq6FVVuZ6T1wtD/BNglwJ0VS9Hi/i0LTRq72A3uV5CNoeV96NgdVtj03m6TxgYp eApQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kEjyKDT0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd435c88esm52884005e9.36.2025.03.06.07.50.24 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:50:24 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 37/54] target: Set disassemble_info::endian value for big-endian targets Date: Thu, 6 Mar 2025 16:47:19 +0100 Message-ID: <20250306154737.70886-38-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field for big-endian targets. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-Id: <20250210212931.62401-3-philmd@linaro.org> --- target/hppa/cpu.c | 1 + target/m68k/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sparc/cpu.c | 1 + 5 files changed, 5 insertions(+) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 4bb5cff624e..d15f8c9c217 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -150,6 +150,7 @@ static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch) static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) { info->mach = bfd_mach_hppa20; + info->endian = BFD_ENDIAN_BIG; info->print_insn = print_insn_hppa; } diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index eedda07c2ab..df8b9c53fca 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -157,6 +157,7 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) static void m68k_cpu_disas_set_info(CPUState *s, disassemble_info *info) { info->print_insn = print_insn_m68k; + info->endian = BFD_ENDIAN_BIG; info->mach = 0; } diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 785b065b513..e8c357ae836 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -83,6 +83,7 @@ static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) { + info->endian = BFD_ENDIAN_BIG; info->print_insn = print_insn_or1k; } diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 3bea014f9ee..972d265478d 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -243,6 +243,7 @@ static void s390_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) { info->mach = bfd_mach_s390_64; info->cap_arch = CS_ARCH_SYSZ; + info->endian = BFD_ENDIAN_BIG; info->cap_insn_unit = 2; info->cap_insn_split = 6; } diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index e3b46137178..9fd222e4c82 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -106,6 +106,7 @@ static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info) { info->print_insn = print_insn_sparc; + info->endian = BFD_ENDIAN_BIG; #ifdef TARGET_SPARC64 info->mach = bfd_mach_sparc_v9b; #endif From patchwork Thu Mar 6 15:47:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870874 Delivered-To: patch@linaro.org Received: by 2002:a5d:6c6a:0:b0:391:30e0:ffa5 with SMTP id r10csp102375wrz; Thu, 6 Mar 2025 08:03:05 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVXSNT5m4A+nYtGtDYR8EtTq4a8BqruM4Gk5mO2e7RyKX5Fzhq+Xh/pXcPe+YBX7okDUGnZKA==@linaro.org X-Google-Smtp-Source: AGHT+IFhuXXYHNxPrU9YTkvvQ/SlEpcTX/wEza7lAU8ZTW49IRC/n0UczA/dSLvrxBlOJZ8bnP2b X-Received: by 2002:a05:6102:2ac2:b0:4bb:d962:62b with SMTP id ada2fe7eead31-4c2e2944837mr5521926137.24.1741276984323; Thu, 06 Mar 2025 08:03:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276984; cv=none; d=google.com; s=arc-20240605; b=e8dzDqgPMZFeeLhGrjcQ4EsXg1+vuwkd6ZBa0gP8gll08u1ErR+SCO9utDXoiwX6Sy cil7lYgNdNWQTvGt0NHaIULZV30EGtPteJQpOP7+Q6kAz++neIj5P97Vq5J6E5xeWK8A CjSfVPZxKEkaf1G6IEpRKI/vk2d14/2IvQMwLzQoxmrieGb0x6ZdM3oN0jeZuwtUZS8I QmlszFDk3t4egBWRLu+LFesAz5BMftbgFJD4ShOyh/R4bqzvkczcqji7geNG37syO9aV c16Nxz/2+Peh3ECXtmhIH4elSTHADGKa/+1leex4o3PGLHFl8b8oRR3446jiztGCyvwa X/sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1WCMtYnB/Q/FPr4quB+y9Nf8Ulz7xJ98JX+NEB2sY0o=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=C0QXr2+MWxNPOS61yAaCvql2hH6fLh/411aViSaJdWOKTqTAlRK69G6auXXNvdpTh/ OP5Vhu/a66V+K0mR5uYwlpkcfTSohwGmmh+hhKgIJdlVkGo7SyF70oMM0cHG3ozjalzn sfy9rCke6und2/xph+miWJgCCeUbKDY8gQeSIJpAwQZiajOcykqaMuKKgiXD7F6EkN5I eZ+TqlJ5Gpi62okkX7Plb6olYOcVIPtzXgkAcnZ5NHIs214qAHCzXW6uaDjI4jKjb24S BiLnNCC7tUBT9mYGQqbezc+n6v0LNfdapwx8s6Tdz7KT8BwMfIhwHZdnTmrA8f1f8Y+g pxqw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XmbW7AgO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd4292b06sm53471455e9.14.2025.03.06.07.50.28 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:50:28 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 38/54] target/arm: Set disassemble_info::endian value in disas_set_info() Date: Thu, 6 Mar 2025 16:47:20 +0100 Message-ID: <20250306154737.70886-39-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250210212931.62401-4-philmd@linaro.org> --- target/arm/cpu.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ac1ceec2110..948defa3f5d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1171,7 +1171,7 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) { ARMCPU *ac = ARM_CPU(cpu); CPUARMState *env = &ac->env; - bool sctlr_b; + bool sctlr_b = arm_sctlr_b(env); if (is_a64(env)) { info->cap_arch = CS_ARCH_ARM64; @@ -1198,13 +1198,9 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) info->cap_mode = cap_mode; } - sctlr_b = arm_sctlr_b(env); + info->endian = BFD_ENDIAN_LITTLE; if (bswap_code(sctlr_b)) { -#if TARGET_BIG_ENDIAN - info->endian = BFD_ENDIAN_LITTLE; -#else - info->endian = BFD_ENDIAN_BIG; -#endif + info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; } info->flags &= ~INSN_ARM_BE32; #ifndef CONFIG_USER_ONLY From patchwork Thu Mar 6 15:47:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870855 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp335182wri; Thu, 6 Mar 2025 07:58:07 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVn80LTQ+gCFbgAgmuesOiQuvhIVztMeVwZcM8gASsVGBttGNldaoPdp6BUDUyOSFYVGARunQ==@linaro.org X-Google-Smtp-Source: AGHT+IGMuwis+YRkOh1XyrVgfM4eLSCJg+k+24w22AxRm6KpmeF4st2TiH+DEY4AsfpQ0uo3MktV X-Received: by 2002:ac8:7fcc:0:b0:475:7ce:2e9a with SMTP id d75a77b69052e-4750b232dccmr107961971cf.3.1741276687189; Thu, 06 Mar 2025 07:58:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276687; cv=none; d=google.com; s=arc-20240605; b=MrBg1jkbPw6T2Grh3Uq0akVm7FaPub2CKun+M5ag3g5/sea8wJoIqllC/0omhSmJ2l g3vqa0GNeE8l99N3Zm0p6GOvthXbCtH5CWnX2yMHNEbZGLOhrXAQhxFv8Rd3+EkycJXa AUjlidr6nB/tVI8GZeeL8FIKDUubVWyq+HY1zmUeCpQxiXFkYT69R5xuwa3XAHXvJIYy B+Pe6YB6EXWmq5RPJXIS0CJbdSx2nJzffcjEmBqfUoPVhkIS6CNYCEMlekBZ5XZlLni6 gxl+9r63oIvQNKBILgScABOqhAYZgliVfeDXufjDYl6onjk4diPQupCyPihJ8IobCoDe 18rA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OQjx41PTEPR3Oc8nlUx+93jp4JXIcOc6sQ64pqHRe5Y=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=JP2miIfZuo3Yv/WlzaEesmuqMHx4VXp6mibd1MqeIC5rkN9zTdgRXzP2wmoiP7k0pN kUdViLrn/m+a1mvCO9wVhgGkPE711PPyDtWisrXoOcwOmQx7EpuhNf+r0Mz5A8DO0+vO bn+dOJ4M4Cw8Wm6nFkxsbD+Ti8cp92XYa8qSpRhg/QcxG2jpoO44zc1V/YpZ9yN0JkFJ RVkcTSqZ7gUYEj2MlBCTJHGPGCKBS0wilKF6jYtE5vl2eHPcCJXWZAfbraptvquqgQqC LtCcasvV9NBAmM1x43+kl2gegi34tZMfr1BOjrdEjgxtey1RZujuiIw3ROH4VYigwLWj DnHA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gIm7r9vE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd435300esm53634645e9.29.2025.03.06.07.50.32 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:50:33 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 39/54] target/microblaze: Set disassemble_info::endian value in disas_set_info Date: Thu, 6 Mar 2025 16:47:21 +0100 Message-ID: <20250306154737.70886-40-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-Id: <20250210212931.62401-5-philmd@linaro.org> --- target/microblaze/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 13d194cef88..d5ee1244cad 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -224,6 +224,8 @@ static void mb_disas_set_info(CPUState *cpu, disassemble_info *info) { info->mach = bfd_arch_microblaze; info->print_insn = print_insn_microblaze; + info->endian = TARGET_BIG_ENDIAN ? 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdfb16sm2406334f8f.29.2025.03.06.07.50.37 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:50:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 40/54] target/mips: Set disassemble_info::endian value in disas_set_info() Date: Thu, 6 Mar 2025 16:47:22 +0100 Message-ID: <20250306154737.70886-41-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-Id: <20250210212931.62401-6-philmd@linaro.org> --- target/mips/cpu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 0b267d2e507..e76298699ab 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -428,13 +428,13 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type) static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) { if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) { -#if TARGET_BIG_ENDIAN - info->print_insn = print_insn_big_mips; -#else - info->print_insn = print_insn_little_mips; -#endif + info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG + : BFD_ENDIAN_LITTLE; + info->print_insn = TARGET_BIG_ENDIAN ? print_insn_big_mips + : print_insn_little_mips; } else { info->print_insn = print_insn_nanomips; + info->endian = BFD_ENDIAN_LITTLE; } } From patchwork Thu Mar 6 15:47:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870868 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp336051wri; Thu, 6 Mar 2025 08:00:16 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUpeJyPtVdlHcaO84LnKogUdj1skt029aYZknpnAhoBXu06nY5zd7xgx4extaFqZSTGMZ++0g==@linaro.org X-Google-Smtp-Source: AGHT+IG+ZIVewSK3qtiUlnQAZ/JRnG+QdGIknyvqlx5NiD0wGwb+X2bvnijpRfncfJivuLEhNWiG X-Received: by 2002:a05:622a:1212:b0:472:5ac:48bb with SMTP id d75a77b69052e-4750b45f130mr96049741cf.29.1741276815482; Thu, 06 Mar 2025 08:00:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276815; cv=none; d=google.com; s=arc-20240605; b=JeuS/TAYfS4f4YLqloO7ktlZ9tgmPPFEX00WcGNwohHTBdwEUONwwitI00khAu2dD0 3K4ooAEX0MQtpjZ5gaB5xlH4b8/JBGHYrOVVlcebu9lYMMFAPFYJXkC8tef4iw8zL7T9 BXaA+VkYAexDP/HHh8NutVhTY7WIBZmwJMLF6DqxBd4sqmIzGEHm35EXI8kR3T7ZHgeG 8+c61ni5f6kcuHk7b7AqXUHRAsHM6OUydwO8sqY+qshZcCElr9LjH3NwkIpcVuaXE9a0 J/ntM+AmXBUeK9zSv/QsCQddIGM0/2CjUTSbI7ZrVBb37Ilp+inIpjXABGKIxlnkjqHl 5KRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=45WEuwbwgt8FZLHCG0k1p7D7jWUaWTBOxeb41hpB4VI=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=iTM1nqitYPttgV+WZRmu4o15gXHr7YD8Ps4F8rorWwxXrp/IkA3pv9EMiV/YuCSSJ8 SEihU+mXPelH8ZafIK5ZfT2ka6xKXxgBAFmRh28LVQVJJmrkmMlg3UnH4g2ZbWK5Dhsi H98ZhWYthPbP0TM9sPgdo6kB99fm5QwKpb5pIkWPElruWJEbn00mNSUgpBtBqoGSX7YD gB2Stn0+kiM0giK1OLGZvibvYxApOW9Ge43X3bPQ9wAr6V/UqKneX90frEcmssR0FV7C ddSjbHk8c56g7CCGtHI76xDbMo5yH8ISZLXveyXX7rfjhvwSp36lxpOA9zF7AX6n9xb/ EQDA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oySksB7q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c103f41sm2369718f8f.85.2025.03.06.07.50.41 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:50:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 41/54] target/ppc: Set disassemble_info::endian value in disas_set_info() Date: Thu, 6 Mar 2025 16:47:23 +0100 Message-ID: <20250306154737.70886-42-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback always set\ the disassemble_info::endian field. Reviewed-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250210212931.62401-7-philmd@linaro.org> --- target/ppc/cpu_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 425049ab093..b9772c53ecc 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7401,6 +7401,8 @@ static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) if ((env->hflags >> MSR_LE) & 1) { info->endian = BFD_ENDIAN_LITTLE; + } else { + info->endian = BFD_ENDIAN_BIG; } info->mach = env->bfd_mach; if (!env->bfd_mach) { From patchwork Thu Mar 6 15:47:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870844 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp333331wri; Thu, 6 Mar 2025 07:53:18 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXZv6f46EZlNPRdsLs1J8ND4Sqhri48OmTw8nQ3xs/pe8WM6na8cq7VFuu51YT67KScWijbyg==@linaro.org X-Google-Smtp-Source: AGHT+IENJ8VfYjutMOxe2I9WYbbNwcBFw+od+Qw3MjmgGEXAlHsycDllMbMPleVnt9CRywFZQLPf X-Received: by 2002:a05:620a:2714:b0:7c0:a46d:fa8d with SMTP id af79cd13be357-7c3d8e705dcmr1162167385a.31.1741276398260; Thu, 06 Mar 2025 07:53:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276398; cv=none; d=google.com; s=arc-20240605; b=FwmJZ1iQzkhxbB61T/eJmSAdXPSbgvRgwhW7Q9GSzdA6iAs0agSkr7kCMI1FhuXI1s DB7vwzNFVwUcGjS1Uwmr/K7l7S5hWMR/zbYnAZwkkRMuDz2r/VWJ51Y2HyK4EJbdhtp7 3RQ/lM+HUMkB8sHtgfre16gFhs3b7NQsiAr6ykyaHr2YEymacH6f51jUkX0DfmQSF5Rm Arcoh//twow5CNSZw3ZZ2bJhnHNypp8+SpAESwEfkAVQs2tASZOA4eGdC3VrA3vvMIAh 9ALRgveYjlXIuUxZamUL0im2TTQ7ZaMXSMg2qA/pLqfG2858VPNaa2YtJiHGCSxbJgbA i+0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VfiQ2ykboMAdXTdejxhsHVQUrwF37vkEaR99lI8ZH/I=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=M4AgJqfpp1x1HvPAL2P1GO9ozqC3T1HWf0Nfsgrx33DlXcqZNvzJk8C3qZuT1/7hho mdtZSHR54jfhzPYz/R1h2Kf7BuKgi3kAvGuiu/x5sbHeOXY5nIPq/xVieqniWu8d+NdL 79kQJjFzDdrvM2qGivSguNH8UIvma3vseEJ6rgFpNSQhPEiDytLesayjbJw+dwGaaxl6 ssqA6XUEGYkRs+6695vm7yMq2g7//bq7aQq7M/5mQ9J0kCoYLOwEV67eL2i5gXYn6XJc Crg39/8Hes3MH4bjQyDqXi+SQpGrJiHPzpmMlDwVpE2vkQOxO2IFN/i6hunRjbC8TsTP Fsvw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y1hd3Rxq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c0195casm2438090f8f.53.2025.03.06.07.50.46 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:50:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 42/54] target/riscv: Set disassemble_info::endian value in disas_set_info() Date: Thu, 6 Mar 2025 16:47:24 +0100 Message-ID: <20250306154737.70886-43-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-Id: <20250210212931.62401-8-philmd@linaro.org> --- target/riscv/cpu.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 47424fd5e2a..6da391738f3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1152,6 +1152,15 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) CPURISCVState *env = &cpu->env; info->target_info = &cpu->cfg; + /* + * A couple of bits in MSTATUS set the endianness: + * - MSTATUS_UBE (User-mode), + * - MSTATUS_SBE (Supervisor-mode), + * - MSTATUS_MBE (Machine-mode) + * but we don't implement that yet. + */ + info->endian = BFD_ENDIAN_LITTLE; + switch (env->xl) { case MXL_RV32: info->print_insn = print_insn_riscv32; From patchwork Thu Mar 6 15:47:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870876 Delivered-To: patch@linaro.org Received: by 2002:a5d:6c6a:0:b0:391:30e0:ffa5 with SMTP id r10csp102927wrz; Thu, 6 Mar 2025 08:03:44 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWQ1PY2kmYhO7vFp4xZz2eTl34MSyphpV2tU2MEdiBQbG+pPzSSTvO0rUceJ/dAGnbVVr2IWA==@linaro.org X-Google-Smtp-Source: AGHT+IEl0BTgSnUh/toW5pZ9eITZRIFAN7kMVKEHK+YH+Y1VdvHJetDTj4sfmCV1dYFfwN6YOQlm X-Received: by 2002:a05:6102:943:b0:4c1:abaa:ad93 with SMTP id ada2fe7eead31-4c2e27fb7bemr5176490137.14.1741277023740; Thu, 06 Mar 2025 08:03:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741277023; cv=none; d=google.com; s=arc-20240605; b=GwfasM2FCSByE4jtbT6Ye38Uyb0KYb9XaLlvlXLRJQX/fMC/gnTXAQVgzWrPwifAV+ 2Fw7HsVY/LonMpL0kcpy9arw1agiAHjOyiNaNG+3rGdw3Tmzj4yCBFPdmc+hy3PG+9un WRym9SQVwHJ6cPZ0VjPBJe3zcKVM7pYECwBk9nu9v6bAQvTUvZmT2rlIZZ/LA22ZJ2kN aXEWsWO015wh29ZHTf3IKoPV4ffI/OGyNKHv6vmUtGS8tBo3/YfRF4upMTPi+KqzsWvV tH2gXRdPDYmQhsJqR69AjlRxyaiuK88Z5afZRqUXpK5kw9r6B9VuQkvGIZ/+X4bFjJQP pb9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5B/bpSAszS/Z+RxXmZ3jyXxyW08tQFInocZVZ8QKZ0I=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=IYatlF1VoN9OqVcDkenUnhVXy7xXVh5sX8K+lPKmtOLi2vgZOOkQnadqWuPQSfRHn/ NPnCxwG+yggkSNiJBCNBa7DaCOIOoYFzQ4ruKMMa5TXJzPqHK9zK2FKu0Vag+J9Uy1Aw wHaCHcgBplhTghYUEG3LRiYXFf6/zkHsJVZ/0ARk3hhdPNyxvdia5Mgs249Dc8zLYM1q 0p+z8W3ABydVsEVSzSvy/AG+3ZLX3jTLWnX32ObWrTiK5HzEh3UClEZnx5WzZpkNnwqx tjP3OIY8mq/3y7cX6awSCRc54SWCnqptk3JTt/UpChEdKlX4gQ+ecnABIjMVXkv6rMWP Ps7w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HmFTfqA0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd8da473sm23319515e9.18.2025.03.06.07.50.50 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:50:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 43/54] target/sh4: Set disassemble_info::endian value in disas_set_info() Date: Thu, 6 Mar 2025 16:47:25 +0100 Message-ID: <20250306154737.70886-44-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-Id: <20250210212931.62401-9-philmd@linaro.org> --- target/sh4/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 22cdf9b4e12..c2aaa40a037 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -143,6 +143,8 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type) static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) { + info->endian = TARGET_BIG_ENDIAN ? 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd8da473sm23321635e9.18.2025.03.06.07.50.55 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:50:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 44/54] target/xtensa: Set disassemble_info::endian value in disas_set_info() Date: Thu, 6 Mar 2025 16:47:26 +0100 Message-ID: <20250306154737.70886-45-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-Id: <20250210212931.62401-10-philmd@linaro.org> --- target/xtensa/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index efbfe73fcfb..f9e298ace45 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -159,6 +159,8 @@ static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) info->private_data = cpu->env.config->isa; info->print_insn = print_insn_xtensa; + info->endian = TARGET_BIG_ENDIAN ? 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c0e1d67sm2400812f8f.74.2025.03.06.07.51.01 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:51:01 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 45/54] disas: Remove target_words_bigendian() call in initialize_debug_target() Date: Thu, 6 Mar 2025 16:47:27 +0100 Message-ID: <20250306154737.70886-46-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All CPUClass implementating disas_set_info() must set the disassemble_info::endian value. Ensure that by setting %endian to BFD_ENDIAN_UNKNOWN before calling the CPUClass::disas_set_info() handler, then asserting %endian is not BFD_ENDIAN_UNKNOWN after the call. This allows removing the target_words_bigendian() call in disas/. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20250210212931.62401-11-philmd@linaro.org> --- disas/disas-common.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/disas/disas-common.c b/disas/disas-common.c index de61f6d8a12..ae3f9e46ea1 100644 --- a/disas/disas-common.c +++ b/disas/disas-common.c @@ -7,7 +7,6 @@ #include "disas/disas.h" #include "disas/capstone.h" #include "hw/core/cpu.h" -#include "exec/tswap.h" #include "disas-internal.h" @@ -61,15 +60,12 @@ void disas_initialize_debug_target(CPUDebug *s, CPUState *cpu) s->cpu = cpu; s->info.print_address_func = print_address; - if (target_words_bigendian()) { - s->info.endian = BFD_ENDIAN_BIG; - } else { - s->info.endian = BFD_ENDIAN_LITTLE; - } + s->info.endian = BFD_ENDIAN_UNKNOWN; CPUClass *cc = CPU_GET_CLASS(cpu); if (cc->disas_set_info) { cc->disas_set_info(cpu, &s->info); + g_assert(s->info.endian != BFD_ENDIAN_UNKNOWN); } } From patchwork Thu Mar 6 15:47:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870852 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp334891wri; Thu, 6 Mar 2025 07:57:22 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVOg2dpJi7vJoMXuoyfG++fvkMxfvWTzVmar7gPWTUcKiXyKBevXSzDYNP87tGLfD2J2S42YA==@linaro.org X-Google-Smtp-Source: AGHT+IHKmh/TSaolZznWxaGhcFT0V5kyN/QcNk90JBCPgRzyTqf5ZfQ33dYeOWe/Mc2DMZU6rSr4 X-Received: by 2002:a05:622a:180d:b0:474:e3b7:4843 with SMTP id d75a77b69052e-4750b4df759mr101407361cf.47.1741276642165; Thu, 06 Mar 2025 07:57:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276642; cv=none; d=google.com; s=arc-20240605; b=BrtHykmq0v1aC/hKqMtaXDZy/amNNDgFecQ47zSUcpftaEy9nSk1/Y6xe+TA4rNbU5 k3Ucq1pngIPNxvD4AJxP9ou4r/0cWG6xB2gIFuXgclleRbOw189IDPngN8jWiR8rLnlJ P2yCsiDL+MRohTNKoP29nF+dBF49VNq37QAss7bxG2PnWutq5g5SQmgBjrOj4/5+/1gX 7J6XCZfXKuKmaU/pHSLn2zQm3aBdQuV844HEE2lWbwvwRcmYh+2/tY9OaOwAFLWjLUrN gEak0iW4kePPWqXUx+LS6WxeBTgzAdhjXm5JIOFxXVjJHjGuXiPfU42mh3qb8pc1dFJ9 Iigg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/DxhRNL6h72ajthgv6sxFLibq8RyJHMeyPI1bV4pMio=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=F91sd4RAt2Kw5b+NIYUEU0Ar3W5gkXPfamWC6SGuV2abUQV5eeDnejYq9VBTnicSjC N/Ku1e35uTSNfCpPoZoaCgwwa//4feq0DAB2y4o5yI1HfVqalr0lGE9+FEQut+6w+s1K BEZw1uo0HEamjiJGYMC1OBcaYkBPzNrKh0D4TEACbv3yGDFhvl+SX0GdS79uQkiP1Hvn Jy2bugEh5FwEFYTeaE01qXjoFnLSQw6wFREdIYG+hj0Sw3axZntGLqwVk0Ixj91q/uIJ t0DQaxyLxTyDinasTc44Yv3gT1WBvsYoFB/xtg0l2Wh1R8r3K0n/MsKM5nITZhIMA9IK Bfdw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="s2STrUh/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfbab43sm2453993f8f.15.2025.03.06.07.51.05 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:51:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 46/54] target/i386: Constify X86CPUModel uses Date: Thu, 6 Mar 2025 16:47:28 +0100 Message-ID: <20250306154737.70886-47-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250210133134.90879-2-philmd@linaro.org> --- target/i386/cpu.h | 2 +- target/i386/cpu.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 10ce019e3f8..7882b63b9b6 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2327,7 +2327,7 @@ struct X86CPUClass { * CPU definition, automatically loaded by instance_init if not NULL. * Should be eventually replaced by subclass-specific property defaults. */ - X86CPUModel *model; + const X86CPUModel *model; bool host_cpuid_required; int ordering; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ab328485acc..b3e1c2bca49 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6563,7 +6563,7 @@ void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. */ -static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) +static void x86_cpu_apply_version_props(X86CPU *cpu, const X86CPUModel *model) { const X86CPUVersionDefinition *vdef; X86CPUVersion version = x86_cpu_model_resolve_version(model); @@ -6592,7 +6592,7 @@ static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) } static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, - X86CPUModel *model) + const X86CPUModel *model) { const X86CPUVersionDefinition *vdef; X86CPUVersion version = x86_cpu_model_resolve_version(model); @@ -6620,7 +6620,7 @@ static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, * Load data from X86CPUDefinition into a X86CPU object. * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. */ -static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) +static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model) { const X86CPUDefinition *def = model->cpudef; CPUX86State *env = &cpu->env; @@ -6690,7 +6690,7 @@ static const gchar *x86_gdb_arch_name(CPUState *cs) static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) { - X86CPUModel *model = data; + const X86CPUModel *model = data; X86CPUClass *xcc = X86_CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(oc); From patchwork Thu Mar 6 15:47:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870866 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp335932wri; Thu, 6 Mar 2025 08:00:04 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWDfnDPXU+knpHjVbI+07H3uPLV6cI/PmhTa5zQnscOS88eXGHYkt63pQVnLb6MKKUKr3SZFw==@linaro.org X-Google-Smtp-Source: AGHT+IHfAzAxqvG6eSAp0L3rPXC5j+hwzcgyWmR8HYNxPhuiFjHDvSZAcyquaLd+SGU1/r+bRzYj X-Received: by 2002:a05:620a:8018:b0:7c3:cf3c:6fc4 with SMTP id af79cd13be357-7c3d8ee49fdmr1326658885a.35.1741276804433; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bcc13b23asm53357865e9.1.2025.03.06.07.51.10 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:51:10 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 47/54] target/sparc: Constify SPARCCPUClass::cpu_def Date: Thu, 6 Mar 2025 16:47:29 +0100 Message-ID: <20250306154737.70886-48-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250210133134.90879-3-philmd@linaro.org> --- target/sparc/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index dda811503b5..462bcb6c0e6 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -574,7 +574,7 @@ struct SPARCCPUClass { DeviceRealize parent_realize; ResettablePhases parent_phases; - sparc_def_t *cpu_def; + const sparc_def_t *cpu_def; }; #ifndef CONFIG_USER_ONLY From patchwork Thu Mar 6 15:47:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870872 Delivered-To: patch@linaro.org Received: by 2002:a5d:6c6a:0:b0:391:30e0:ffa5 with SMTP id r10csp102366wrz; Thu, 6 Mar 2025 08:03:05 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUJRNO6AUpAwejfxF0tG/IqG/L2y3rQcGP4Zn/Ws9kPKR29JIT30flfxRshZdAKjcTlFbGRow==@linaro.org X-Google-Smtp-Source: AGHT+IGxom1v97TPfwZWcS2kS42fcE7U2/PNbCOpllJAHZeVrOMRPHC5MSPV9s6SU/s375/HyOQK X-Received: by 2002:a05:620a:4382:b0:7c3:d45b:f337 with SMTP id af79cd13be357-7c3d8e64de0mr1056342385a.16.1741276984196; Thu, 06 Mar 2025 08:03:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276984; cv=none; d=google.com; s=arc-20240605; b=CACB5Qj2Je/+YIc1IvOtnoodonlj8xEiOAXECEwFtkVWX8QmQzdv8UPG2tRQ27AeDg un1Ads3zPz421ocQZlp8RAhuHhyGper5dW/mPHzChu4r9RUEhYo4SJMRASJRXdni7qJ5 IgYWO9W1GS7rITvyNpab4pl0K0e6gZrRKh3xT6EG63l96VdgyLUzjBAu7FpgIwVtxIIs byeGWadpgyGzWELGPlK2jpH8WfEsRRhfeCt7iGlmvfxG6lq5rG8qOPRtwhIEajDfyDKA /x7HC7LU8Cer4xcR6O35SusV9IlJ+YjxsSNqZhMOvCxk/h3w2Z5xqkTZ5/kDSOsORegs wOlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lZf/YeQK4lOJ/RgUPpd1hWKDiWEJL3iQUsYLZBcJWdw=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=V5dyRV7GL87jJMV16NxoEHMzbZ/t6nPjzr3Mrhd8RazvejiSQMy+edATLAcBk/O80Z SLAS0fV9o9gnGbwIDwM+cVGHrXYA9suHYykfQIsWISKtmwb71SByPu/1BY9USoJFjB2T taR28KBh2OWwwSVlzaj3V0NN4Oz/XBIRwGwIMWfZr8MzsV9xYMDJynLVDQtQ0a1F7qAm dGp+MOPhR6ZycGQ+sEXs0QDz/qAYU/DbwmAaQMebw/xwMI4xyNu+1o0X+K8pOdk+slpz 5aDqM1c7kBYFrGy7THxtKNROtNopctUkjLiDP16WxrVzbi5rSei9uIp3/JvyoO/Rz6uy jnHg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wz0OYe+6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd6530f26sm49579485e9.4.2025.03.06.07.51.14 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:51:15 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 48/54] target/xtensa: Finalize config in xtensa_register_core() Date: Thu, 6 Mar 2025 16:47:30 +0100 Message-ID: <20250306154737.70886-49-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Make XtensaConfigList::config not const. Only modify XtensaConfig within xtensa_register_core(), when the class is registered, not when it is initialized. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Acked-by: Max Filippov Message-Id: <20250210133134.90879-4-philmd@linaro.org> --- target/xtensa/cpu.h | 2 +- target/xtensa/helper.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 0e6302c5bd3..8d70bfc0cd4 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -490,7 +490,7 @@ typedef struct XtensaConfig { } XtensaConfig; typedef struct XtensaConfigList { - const XtensaConfig *config; + XtensaConfig *config; struct XtensaConfigList *next; } XtensaConfigList; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 2978c471c1f..f64699b116d 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -173,9 +173,8 @@ static void xtensa_core_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc); - XtensaConfig *config = data; + const XtensaConfig *config = data; - xtensa_finalize_config(config); xcc->config = config; /* @@ -195,6 +194,8 @@ void xtensa_register_core(XtensaConfigList *node) .class_data = (void *)node->config, }; + xtensa_finalize_config(node->config); + node->next = xtensa_cores; xtensa_cores = node; type.name = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), node->config->name); From patchwork Thu Mar 6 15:47:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870877 Delivered-To: patch@linaro.org Received: by 2002:a5d:6c6a:0:b0:391:30e0:ffa5 with SMTP id r10csp103770wrz; Thu, 6 Mar 2025 08:04:44 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVUx0p5jFhdDv23mtDKmHNI2OnEyaT/i2oT7VtRzjaocaULouitnHC69pDDwlytsF0ZGkkQRA==@linaro.org X-Google-Smtp-Source: AGHT+IGDGJLxbDc3lrsbf5ItOEodBRhXVLatqLOwau2NQNjIsV4k0Jwfozgh/kmO4rkMtE0jvHdE X-Received: by 2002:a05:620a:2696:b0:7c3:d64b:a434 with SMTP id af79cd13be357-7c3d8ee1be2mr1157090385a.41.1741277083938; Thu, 06 Mar 2025 08:04:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741277083; cv=none; d=google.com; s=arc-20240605; b=Fcjk8OjY8nA1YMLqvyx8DwkcuqoVFYdGIZcTehkVUejRfUem0JQ3WSSUx/Or+Lkh8C vGsCskqLesttwVIIZD+5D5/J+im1J3s229bSzBf20aA6grDUmJFoI+EdI682iSuiKj0E h/6zBWFdsq422dYnlOPs0LNImnCEE3wcNEfQ55v0YkfP8wqUif/cTaC0r65GKNB+IlIg eEKHgw3X0Wj60Ms9LmRy/2xrSAOxO/0m2pknj4XRPqEccIBLRG7mQB0Z9djK8zIp+tHM LFvIALVr1IhMrv6J0NFYJ8DqBGncmhi+Lbe8mLPBP40yxrYwdAE+XXMNShPPfYpQ4evL rtGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MMBWRuSyGswvYNYlsgr7kSCVcGseu6BMoO5K2Fo6R7M=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=c7c81BHHhKzx/X/3SyFDttAT1cNjRQ1dfdc4Uz3mY+1rX5YFc8/CfLhtYMADRJX1kO zu6j+6IsjFOb6064nPSlcbGH4bu7Psh8uRKpI8W1u3jlrwX7MDaF+lbYI+v4qmC3OFaR 0iGNN792EXMNuUwDoVqGeYhJ2diyBVLth542mbzbvwZ5U/iDUKso2b81l4N1tCNPtgJ0 kRJ+OWJKrOzFZ/g7huIe4freeMQRzhFhFxEoMtexBDMF/yXf4o8Nm3ynNOSLVAcgere+ SfCXtqhS6tr1ws+SQMrk83xUrn0yDEpe5lpajInA8S+gq7uL1+sqRdfsS6JtkG6DtyxK Xktw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Tzlg1UvG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfb79adsm2400486f8f.7.2025.03.06.07.51.19 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:51:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 49/54] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Date: Thu, 6 Mar 2025 16:47:31 +0100 Message-ID: <20250306154737.70886-50-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250210133134.90879-5-philmd@linaro.org> --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 616c3bdc1c2..7de19b41836 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -539,7 +539,7 @@ struct RISCVCPUClass { DeviceRealize parent_realize; ResettablePhases parent_phases; - uint32_t misa_mxl_max; /* max mxl for this cpu */ + RISCVMXL misa_mxl_max; /* max mxl for this cpu */ }; static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6da391738f3..d4f01965dfa 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3056,7 +3056,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); - mcc->misa_mxl_max = (uint32_t)(uintptr_t)data; + mcc->misa_mxl_max = (RISCVMXL)(uintptr_t)data; riscv_cpu_validate_misa_mxl(mcc); } From patchwork Thu Mar 6 15:47:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870861 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp335741wri; Thu, 6 Mar 2025 07:59:37 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXQcLINQBcq/2qjUNNa7HyFxmaz4HLZ1cfcwmvF6ZwCi18t6sVXpsKwkLLh3fcv27vZWTyykw==@linaro.org X-Google-Smtp-Source: AGHT+IGhAvtI6oKeTvi9WOiO5izZvHtXN7WmYD85wJ1U4TKwyoOSN/1xWlkNFWXGnJPFQAhFwvQ2 X-Received: by 2002:a05:620a:4389:b0:7b6:d7be:2e4 with SMTP id af79cd13be357-7c3e3a3375bmr520920985a.26.1741276777586; Thu, 06 Mar 2025 07:59:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276777; cv=none; d=google.com; s=arc-20240605; b=YknGtzRqH6kzgW4eSRetwvy4MeSqkZV3JfhL4y6jHU/Pi+HuzL4vrMFEBab226GztG 5EDLUZovIROQDDby31H32qYAlyTyZ48ArW3x3nUXNLvcoh8OIk5yzKhJvQ+pfnhhc38q lkofnsKrdr9LwGh7Bz+hf0D5a4Zq46WBZflyRrdG+oCHBXs0cedRqvI569n8W+EOT6Pb c2jilq8KdyfR1a0M5+YoQwwQhDbXLYI6XHgua8qSlVWSw54xffFJa+6No5GNdYmU/ISH oTVq4HPRMbP0lUfuq701LvKY9hz/aoFHW7DsxO0ju3fDu7JXrP12N25jxHKMq8kqLFYw a4eg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yJRJRFRnJa+ZW9IwcRJGqVmfoDv1z7czBgbZuXOAeZE=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=N/KkpjO/AjPJn49uY/OAv3Dmu/j56/mht/uuyL2QEGz1R9/07hk4Jyhl+ojKW/JyIX ykGMymMwMNNG/Ou03mmztB3h8fvfwBUEKSlzfQ66pRN0o/X+5XtGm2cd/0xQCTrkj4/i KMKj0+/Eed6uL4QMDyDmJX8bbzWTQVRZAlmlU/KgcqSk7AiHgTUUa3zKfJfEnftGxCHF 2kWZukC0PTrZ/SmkDWyQIjsVWdH7JeAWPmVwFA7tPydJJ+z0RA9ohrx6B1MjuCrHjXNy KKOZmKlidgLbaLDLWgzKTsTEXouA7Y3oAy7QlB5rQpBANngfRis7ozQf6gu5wsp3CwH6 Axug==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jsMDJvmp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c019557sm2508708f8f.50.2025.03.06.07.51.23 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:51:24 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 50/54] target/riscv: Convert misa_mxl_max using GLib macros Date: Thu, 6 Mar 2025 16:47:32 +0100 Message-ID: <20250306154737.70886-51-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use GLib conversion macros to pass misa_mxl_max as riscv_cpu_class_init() class data. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250210133134.90879-6-philmd@linaro.org> --- target/riscv/cpu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d4f01965dfa..6db2252aac7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3056,7 +3056,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); - mcc->misa_mxl_max = (RISCVMXL)(uintptr_t)data; + mcc->misa_mxl_max = (RISCVMXL)GPOINTER_TO_UINT(data); riscv_cpu_validate_misa_mxl(mcc); } @@ -3158,7 +3158,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename) .parent = TYPE_RISCV_DYNAMIC_CPU, \ .instance_init = (initfn), \ .class_init = riscv_cpu_class_init, \ - .class_data = (void *)(misa_mxl_max) \ + .class_data = GUINT_TO_POINTER(misa_mxl_max) \ } #define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \ @@ -3167,7 +3167,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename) .parent = TYPE_RISCV_VENDOR_CPU, \ .instance_init = (initfn), \ .class_init = riscv_cpu_class_init, \ - .class_data = (void *)(misa_mxl_max) \ + .class_data = GUINT_TO_POINTER(misa_mxl_max) \ } #define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \ @@ -3176,7 +3176,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename) .parent = TYPE_RISCV_BARE_CPU, \ .instance_init = (initfn), \ .class_init = riscv_cpu_class_init, \ - .class_data = (void *)(misa_mxl_max) \ + .class_data = GUINT_TO_POINTER(misa_mxl_max) \ } #define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \ @@ -3185,7 +3185,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename) .parent = TYPE_RISCV_BARE_CPU, \ .instance_init = (initfn), \ .class_init = riscv_cpu_class_init, \ - .class_data = (void *)(misa_mxl_max) \ + .class_data = GUINT_TO_POINTER(misa_mxl_max) \ } static const TypeInfo riscv_cpu_type_infos[] = { From patchwork Thu Mar 6 15:47:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870869 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp336095wri; Thu, 6 Mar 2025 08:00:21 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXscUgRQX8GNu0Up6P6WDdyZuzUgxJ2wKdhKjF0JqWCoxvfbveAp8sMCOXzPcsfdzWEq6B51A==@linaro.org X-Google-Smtp-Source: AGHT+IEQg/YlwWhLnvKzgWEy8oUwEbmicTGKyhg6DqrbfSAVk7E9fNgJyLk3PtR0AZK/EPqZBIWX X-Received: by 2002:a05:622a:4cd:b0:474:f8d9:f3dd with SMTP id d75a77b69052e-4750b4eb781mr84859381cf.51.1741276820693; Thu, 06 Mar 2025 08:00:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276820; cv=none; d=google.com; s=arc-20240605; b=HQq1vx/8BWPxs3LmgPrtlF3IRE6l2T/7432EL2Idchi4RGZVyjri4Rk/nS/bplbJjS h+YWIcUEvY5L0aUfbyPEUcpznfXZk4Jx586wKgifSMFG1iUHZUyjg56ZGyVxAnRbcwnQ tppkhFDz/CIvDJ3+/aHB9WySMI9U36pn8rcByaJrZW9fmyMuoUsiGaGkVX7S9G2kucrd VrzgEiKy/dt8ZeQDDuUnbVSeMFEzOggFoXjkR9qMOYcO+4TvtYXU/LFBhkmCBJGAsMjf sfBpRUF/OQ5HHARejgG7iLc9jsSIkXj/2LvpjveJYXyakiI4a1I6QivlPQslDHYaFINW IjnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Q/XxsDfHOS1Wk77anKxnWzNd9TMtmnv8t/Ha/8QCoUc=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=N4JdU5f193xGM6NCfrWsADw6CV9GLdEcyA76w18hSHRIOvjN+Z9mS/K8PuW9eO7bNl z6Fh2JGoa+Jie/HvKDrgddhMwX9EqPXxFnMGokG+789yRiqGaOwlBUahmym7t8jYfxTW txlSTzIg7/y0vpfFnaLOFzbKgVUneHeXu+eyxZuB2g/7xMi9MsIoVIwzQGxfgdCLMSZW CPWY5L6PcT884VavflxA17qUn6XGt+sZFvWZznb/2yG9CfQKWadPoD+md/RieJqdbUGb XgtxMeZYbTyqqXXa5wi8UfQGVoWD5NwPda2A4zqeJp5OVGVvCR+DNhy4gT/BaqaC3Nkp 0hDA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rVjt2CuK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c103f41sm2371624f8f.85.2025.03.06.07.51.28 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:51:28 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 51/54] target/alpha: Do not mix exception flags and FPCR bits Date: Thu, 6 Mar 2025 16:47:33 +0100 Message-ID: <20250306154737.70886-52-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org get_float_exception_flags() returns exception flags, which are distinct from the FPCR bits used as error code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250211162604.83446-1-philmd@linaro.org> --- target/alpha/fpu_helper.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/target/alpha/fpu_helper.c b/target/alpha/fpu_helper.c index f810a9b6a47..6aefb9b851a 100644 --- a/target/alpha/fpu_helper.c +++ b/target/alpha/fpu_helper.c @@ -455,29 +455,28 @@ static uint64_t do_cvttq(CPUAlphaState *env, uint64_t a, int roundmode) { float64 fa; int64_t ret; - uint32_t exc; + uint32_t exc = 0; + int flags; fa = t_to_float64(a); ret = float64_to_int64_modulo(fa, roundmode, &FP_STATUS); - exc = get_float_exception_flags(&FP_STATUS); - if (unlikely(exc)) { + flags = get_float_exception_flags(&FP_STATUS); + if (unlikely(flags)) { set_float_exception_flags(0, &FP_STATUS); /* We need to massage the resulting exceptions. */ - if (exc & float_flag_invalid_cvti) { + if (flags & float_flag_invalid_cvti) { /* Overflow, either normal or infinity. */ if (float64_is_infinity(fa)) { exc = FPCR_INV; } else { exc = FPCR_IOV | FPCR_INE; } - } else if (exc & float_flag_invalid) { + } else if (flags & float_flag_invalid) { exc = FPCR_INV; - } else if (exc & float_flag_inexact) { + } else if (flags & float_flag_inexact) { exc = FPCR_INE; - } else { - exc = 0; } } env->error_code = exc; From patchwork Thu Mar 6 15:47:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870873 Delivered-To: patch@linaro.org Received: by 2002:a5d:6c6a:0:b0:391:30e0:ffa5 with SMTP id r10csp102365wrz; Thu, 6 Mar 2025 08:03:05 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVSWxeHzxAIk99cBb0/Ez/5GjE1L32/2iqBMIzWS+IOiS5FdrhdlDFORPNJX/2htohuxm1b5w==@linaro.org X-Google-Smtp-Source: AGHT+IE+Zx5SA28x8n/7rBAjJ2mrrRIe3JNxCiFe3PzbqDKkQdMHCKBjKOSdzLw+x5wg8qDwerp1 X-Received: by 2002:a05:6102:3a0c:b0:4c1:8bbd:7611 with SMTP id ada2fe7eead31-4c2e28d14f0mr5187348137.18.1741276984169; Thu, 06 Mar 2025 08:03:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741276984; cv=none; d=google.com; s=arc-20240605; b=fOjYPqe82DV1HQBtQd+4eNEMO76o+Ju0M9YPvrmglUwsDYjZfMKwFQzdTVY8Nu/Flj 0/k20xKW6h9wdRAkTc4+NcQPjFePCUy+Gh/jcSySG3Q5Okrv3TAO9g2zTkJ913bbHhXa k72lt5lPNSM5tFlUVQoox8CUnKCuo8mbO7fPT50lIoRzwD4Y5XWtSKk5y/45bmxOkizj lbMpNBKu0ODesbE7oLztbCA2Mp+GYOfD755rG7P15d/ZE3bjiyqgjU/enRp+9FJCz+FD 9dCa388UvgPpp6kZiS7I1AIi/pVAS51yE+8sxK5jMGrWaRKAvcD9qQkZUPcO0+kXQTJ/ fGHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8iAMOsd7yhgOQOkZMNXOMWl45bAeyqtgN6CSQKPbqzQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Vvzi6u6jL0KLrM+H1CXeuu+z+CZilwcSUfPbm6vtgk1dqqkzMOvJQA2Op18hfkDI5p xIDmT4kKBNmH9ttnDusGWaKSsexSKz0/PmU38R1i1FTVi3FREAsfOKZLl5LdtJniHOmX Q/1s/S2Iea7GQUXdVeB5Zh4V+K97OatjQGIrjYOb2zPS554kmwgsOd9XvbLB0b09bCtz hx7w1BE+nxEffYC0/cCTP+8j970NfM8iRlfSbh+yAi/xBfvl9PRKSjH1Fjd8rfSKOgrG R9xTGx+LQ+zA43BdhuUq6oo5veWh6KG/M9K8Pt0kc57BGbTD1QGjlt9WuvgVAQJwgIKs zlTg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QtUAL6MI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c0195bfsm2411546f8f.48.2025.03.06.07.51.32 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:51:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 52/54] target/i386: Mark WHPX APIC region as little-endian Date: Thu, 6 Mar 2025 16:47:34 +0100 Message-ID: <20250306154737.70886-53-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This device is only used by the x86 targets, which are only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTLE_ENDIAN. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250212113938.38692-6-philmd@linaro.org> --- target/i386/whpx/whpx-apic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/whpx/whpx-apic.c b/target/i386/whpx/whpx-apic.c index 4245ab68a27..630a9616d71 100644 --- a/target/i386/whpx/whpx-apic.c +++ b/target/i386/whpx/whpx-apic.c @@ -231,7 +231,7 @@ static void whpx_apic_mem_write(void *opaque, hwaddr addr, static const MemoryRegionOps whpx_apic_io_ops = { .read = whpx_apic_mem_read, .write = whpx_apic_mem_write, - .endianness = DEVICE_NATIVE_ENDIAN, + .endianness = DEVICE_LITTLE_ENDIAN, }; static void whpx_apic_reset(APICCommonState *s) From patchwork Thu Mar 6 15:47:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870879 Delivered-To: patch@linaro.org Received: by 2002:ab3:6e57:0:b0:290:25b2:841c with SMTP id w23csp530894ltm; Thu, 6 Mar 2025 08:05:33 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXBNBDxWuDQx3uBnfKEpZ2RG0VTnucGH4OLpURkgSrQjOiV/kDRM39tcHb+tiDHPsq8FOSiIA==@linaro.org X-Google-Smtp-Source: AGHT+IETgF+JV44QBLaNX5ry2CqNXjv/46C1wu7CcvUF5pj6hURFQeu8EQUaROfGdfsuaBLGJlDi X-Received: by 2002:a05:622a:1446:b0:474:efcd:535 with SMTP id d75a77b69052e-4750b43c17amr118857991cf.16.1741277133176; Thu, 06 Mar 2025 08:05:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741277133; cv=none; d=google.com; s=arc-20240605; b=dJxu/DQKt/g7Day/PASJDcoR5k5OJpvGdUaoGwhdU1llOZolF5AyZsO53y+kQYLvkU Fm5DkwsyvurQ9jFBwk9lM+g1uWXtthAOisnLY8q3ZZTNKfA4LnhlwFhCIzYeVfKL4eTd q78cQHzSfVDoDRvC48cl8yFkYiMmuFkjl2yK+yFTrbt+oEKZiOqbO1EthPaBKxwRWcg9 kYlxOvKq/qI7N94HvzFMcwwAZt0Y7lB1Cc7uiFzkO/56m0KWkUD5wf4M37o/11hGPqMU gPKEv/ZSa8QbPO4+z3sDjXu+JKjvuvgQsu5R261HusVlQ1UVD7I+KlhoyS1ZDHyeJwpe WAjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=isFVV4mWD6JRdhzxnOMLbfC93cakN53tVgpDr87aOmk=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=b5nE6mKIUxjj3vORFuwfZqDqwaxXGibRVQYBWotwacNyTZsHFDstsoP1TXQToddugc 4n4KpUwA5sqgnF0LwqlAeEnyBs8taAKp/Jiv48hav3PpJz3rg9u20bmb9PwQKUWNvuBk WDTV3bmO8dPcIf4bymFCWe6wwYFdBgaGir1rOQviDPN98emivKFEwpwte81gtZoKLGoH ix7dP/kCbIi9cxVsVdzCuPkoSfmdCKvdjulFZB63jFlnsS1Fwg/odS7Qmne+4qE7oJTO YKBOdvxFLl+PXd6BE/ZEnBXaEXbEkFp6S1I8cjMicROrbdVcIh1AW/Hi9FmtyZB4Mcl0 TcUw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vUBfsgaU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfbab43sm2455333f8f.15.2025.03.06.07.51.37 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:51:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 53/54] system: Open-code qemu_init_arch_modules() using target_name() Date: Thu, 6 Mar 2025 16:47:35 +0100 Message-ID: <20250306154737.70886-54-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Mostly revert commit c80cafa0c73 ("system: Add qemu_init_arch_modules") but using target_name() instead of the target specific 'TARGET_NAME' definition. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250305005225.95051-3-philmd@linaro.org> --- include/system/arch_init.h | 2 -- system/arch_init.c | 9 --------- system/vl.c | 7 ++++++- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/system/arch_init.h b/include/system/arch_init.h index 5b1c1026f3a..d8b77440487 100644 --- a/include/system/arch_init.h +++ b/include/system/arch_init.h @@ -27,6 +27,4 @@ enum { extern const uint32_t arch_type; -void qemu_init_arch_modules(void); - #endif diff --git a/system/arch_init.c b/system/arch_init.c index d2c32f84887..b1baed18a30 100644 --- a/system/arch_init.c +++ b/system/arch_init.c @@ -22,7 +22,6 @@ * THE SOFTWARE. */ #include "qemu/osdep.h" -#include "qemu/module.h" #include "system/arch_init.h" #ifdef TARGET_SPARC @@ -40,11 +39,3 @@ int graphic_depth = 32; #endif const uint32_t arch_type = QEMU_ARCH; - -void qemu_init_arch_modules(void) -{ -#ifdef CONFIG_MODULES - module_init_info(qemu_modinfo); - module_allow_arch(TARGET_NAME); -#endif -} diff --git a/system/vl.c b/system/vl.c index 8f776684ec8..04f78466c41 100644 --- a/system/vl.c +++ b/system/vl.c @@ -26,6 +26,7 @@ #include "qemu/help-texts.h" #include "qemu/datadir.h" #include "qemu/units.h" +#include "qemu/module.h" #include "exec/cpu-common.h" #include "exec/page-vary.h" #include "hw/qdev-properties.h" @@ -78,6 +79,7 @@ #include "hw/block/block.h" #include "hw/i386/x86.h" #include "hw/i386/pc.h" +#include "hw/core/cpu.h" #include "migration/cpr.h" #include "migration/misc.h" #include "migration/snapshot.h" @@ -2885,7 +2887,10 @@ void qemu_init(int argc, char **argv) os_setup_limits(); - qemu_init_arch_modules(); +#ifdef CONFIG_MODULES + module_init_info(qemu_modinfo); + module_allow_arch(target_name()); +#endif qemu_init_subsystems(); From patchwork Thu Mar 6 15:47:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 870882 Delivered-To: patch@linaro.org Received: by 2002:ab3:6e57:0:b0:290:25b2:841c with SMTP id w23csp533863ltm; Thu, 6 Mar 2025 08:08:20 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX5JJ4sNckwdVIxVw2LMO0ERPMgL5/Ft1HwYOrpAznfAgz13ElYTVZRSAPgC7Lf5nXHPJbmxA==@linaro.org X-Google-Smtp-Source: AGHT+IEoF6YWEyArVUxsi8z8XKsYeJnDxDxWjWHuM9VWP0No2YZTJ2ouz+6sitqxrYpTMzme5zwM X-Received: by 2002:a05:6214:1c0b:b0:6e2:3761:71b0 with SMTP id 6a1803df08f44-6e8ff625563mr958656d6.5.1741277300093; Thu, 06 Mar 2025 08:08:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741277300; cv=none; d=google.com; s=arc-20240605; b=KIGBuxZa1tyxQNCksA7dghat1wMGKXEmPK258dC6LpF3Rsp6TotlM3sweNLbw3mcgP UJMTGEcIl84LBxtpxtSOZfduPkUlbxNuvonCKe4IUQkKksyoQZiiTsqyxWYoWZhubBRI u2Ehy/RufdTwsmWOZEikdszf5kl8Ua3NwIANj/7RlEOMi00PePjfCLTWQMkeStJ4DEIb V8NlU1qnwIcKoqyvBd2+Usw+abOEdLD23TkS/F/L7ZraWymvQWGRt1z9pBPvVW2TXqPi fqopbp+arWx/ygDD7C1IOPttGgjROyFtKiJGdJN4apPWPnWsiVqDzyq4pXkb1kOpVsLH BuNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xEi19GICoksLADKOo55mK0c9OwojgM4AwDlkdDj14C0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=jqezIdctnBFvrQ6LWt1yCtx8gElFZZiOR9KWwzd9rksl7OkjQCRCQ/jcSXiEODw8Q3 ih4OMVBk6asLt37EVfBvvz8VwAD58E6WLjMfwN3h9mMsmnLV++26NXWmLLoOZMCWJypo gOSuXUL5oYztrD4Cco6fh87lZrCufFq1ZZCZVCPZLH3iSyZqfzkVBPIZQ+e8erQK0XH4 7qeTRVqFNghL2peiw/HU7sHhdI/OsClC+6fHe7WcRhe5R8cAEHaIcaIsdJ+YcNWFeyeX 5eqEjk91O9fzo5GwZcMdLJpzJrTQgsdxxTiyFs8ugBIA4n7y+esAf2PIVqv5CcsrtII3 0pqA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Nf7FgUOi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c103808sm2438477f8f.97.2025.03.06.07.51.41 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Mar 2025 07:51:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 54/54] include: Poison TARGET_PHYS_ADDR_SPACE_BITS definition Date: Thu, 6 Mar 2025 16:47:36 +0100 Message-ID: <20250306154737.70886-55-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Ensure common code never use this target specific definition. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250305153929.43687-4-philmd@linaro.org> --- include/exec/poison.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/poison.h b/include/exec/poison.h index f4283f693af..d6d4832854e 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -48,6 +48,7 @@ #pragma GCC poison TARGET_PAGE_MASK #pragma GCC poison TARGET_PAGE_BITS #pragma GCC poison TARGET_PAGE_ALIGN +#pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS #pragma GCC poison CPU_INTERRUPT_HARD #pragma GCC poison CPU_INTERRUPT_EXITTB