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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd94913fsm23999905e9.37.2025.03.06.08.39.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Mar 2025 08:39:27 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/10] target/arm: Move A32_BANKED_REG_{GET, SET} macros to cpregs.h Date: Thu, 6 Mar 2025 16:39:15 +0000 Message-ID: <20250306163925.2940297-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250306163925.2940297-1-peter.maydell@linaro.org> References: <20250306163925.2940297-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The A32_BANKED_REG_{GET,SET} macros are only used inside target/arm; move their definitions to cpregs.h. There's no need to have them defined in all the code that includes cpu.h. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpregs.h | 28 ++++++++++++++++++++++++++++ target/arm/cpu.h | 27 --------------------------- 2 files changed, 28 insertions(+), 27 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 52377c6eb50..2183de8eda6 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -1157,4 +1157,32 @@ static inline bool arm_cpreg_traps_in_nv(const ARMCPRegInfo *ri) return ri->opc1 == 4 || ri->opc1 == 5; } +/* Macros for accessing a specified CP register bank */ +#define A32_BANKED_REG_GET(_env, _regname, _secure) \ + ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) + +#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ + do { \ + if (_secure) { \ + (_env)->cp15._regname##_s = (_val); \ + } else { \ + (_env)->cp15._regname##_ns = (_val); \ + } \ + } while (0) + +/* + * Macros for automatically accessing a specific CP register bank depending on + * the current secure state of the system. These macros are not intended for + * supporting instruction translation reads/writes as these are dependent + * solely on the SCR.NS bit and not the mode. + */ +#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ + A32_BANKED_REG_GET((_env), _regname, \ + (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) + +#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ + A32_BANKED_REG_SET((_env), _regname, \ + (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ + (_val)) + #endif /* TARGET_ARM_CPREGS_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 215845c7e25..c360b74ded9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2682,33 +2682,6 @@ static inline bool access_secure_reg(CPUARMState *env) return ret; } -/* Macros for accessing a specified CP register bank */ -#define A32_BANKED_REG_GET(_env, _regname, _secure) \ - ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) - -#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ - do { \ - if (_secure) { \ - (_env)->cp15._regname##_s = (_val); \ - } else { \ - (_env)->cp15._regname##_ns = (_val); \ - } \ - } while (0) - -/* Macros for automatically accessing a specific CP register bank depending on - * the current secure state of the system. These macros are not intended for - * supporting instruction translation reads/writes as these are dependent - * solely on the SCR.NS bit and not the mode. - */ -#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ - A32_BANKED_REG_GET((_env), _regname, \ - (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) - -#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ - A32_BANKED_REG_SET((_env), _regname, \ - (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ - (_val)) - uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint32_t cur_el, bool secure); From patchwork Thu Mar 6 16:39:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 870885 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp350734wri; Thu, 6 Mar 2025 08:40:18 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUhJ1HrKjHVCKZAc6qBHCovl9183TOzvOcFDoy3/qbImUiX9bTq6eCsEWc9wv8pxechc2RCLQ==@linaro.org X-Google-Smtp-Source: AGHT+IG02CihU0Ijrl1I86KEGoxrDTB/cXQwQIVoCh/n4Hr10pqLHM8JdUDmdKyIP4QwXonxFM5i X-Received: by 2002:a05:620a:269e:b0:7c0:a70e:b934 with SMTP id af79cd13be357-7c3d8e46626mr1320756085a.7.1741279217809; Thu, 06 Mar 2025 08:40:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741279217; cv=none; d=google.com; s=arc-20240605; b=VapnpzVjgKWV7g2YtYd4sXrtIPMOy1z6LJTmh1aC1ag8b93Zz5rROdeBC7Lpe/p17Z m/iZNuwcuFfADp8a8R1P4f+twIzDphFTuH6W+TdHy1gCbcaCtOhPNpAe26ia4mXqq34g dwTdek+reJpYizinwJKlSQvzDUf4LHHrmeOfHkfCPvs4eXA279dFET08S6ALrLDZ2ZYX +/P99ck3xzbaLlT6l+k8OQM8uDDHVxOVrb/fQt8tcXfD+LoN/twKCIqSSddt77Kh/win uHnv3bUb2d/mQP8lIimu99s/2Or53tERmjW5wNmZmorhyT8sO5OWDglsEfrgpZf7zFLi TXnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=E0hdGCsrUBN3Wc4QZ13PTDB9u8eo9z7EzbgSppoTB1E=; fh=CjTNEONa6LX5yyE8cm1NQOSrSh20+90Kgs/5e694QDA=; b=fVzzAa5MBA75NIgaQvKCkx3NwL0tqkkPwgFvrlp0PDMr+DsH2t1KFk/C7u0s33ARkJ KmKvTWDapmJChcnvcAOt3f0wQAYqgPAWPGNlqrIP57Us+E6xSWjaq/xuzKucsEHxFkDP tFXh0S+YlQj/Vuz16gdLoCL7Rq+WZP4HS4Qb2U/BQYv5DtLv3cA55G8l+HcoNvlIf3NI ft2RxK6Ej6GlKDWOGg9H9ufqxiOe3X0auSMAzYm0RS9iSiKUWaTuKEMHeJeL4Joboe9A 92mQw1yBaCCZub+by9Y5FhdsvBhovNI1WTgRDtEclM3eWA+doXoG/AsRJMWgLbr8fyrX aQ+A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lg828fm8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd94913fsm23999905e9.37.2025.03.06.08.39.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Mar 2025 08:39:28 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/10] target/arm: Un-inline access_secure_reg() Date: Thu, 6 Mar 2025 16:39:16 +0000 Message-ID: <20250306163925.2940297-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250306163925.2940297-1-peter.maydell@linaro.org> References: <20250306163925.2940297-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We would like to move arm_el_is_aa64() to internals.h; however, it is used by access_secure_reg(). Make that function not be inline, so that it can stay in cpu.h. access_secure_reg() is used only in two places: * in hflags.c * in the user-mode arm emulators, to decide whether to store the TLS value in the secure or non-secure banked field The second of these is not on a super-hot path that would care about the inlining (and incidentally will always use the NS banked field because our user-mode CPUs never set ARM_FEATURE_EL3); put the definition of access_secure_reg() in hflags.c, near its only use inside target/arm. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 12 +++--------- target/arm/tcg/hflags.c | 9 +++++++++ 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c360b74ded9..5ae40f32491 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2666,21 +2666,15 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) return aa64; } -/* Function for determining whether guest cp register reads and writes should +/* + * Function for determining whether guest cp register reads and writes should * access the secure or non-secure bank of a cp register. When EL3 is * operating in AArch32 state, the NS-bit determines whether the secure * instance of a cp register should be used. When EL3 is AArch64 (or if * it doesn't exist at all) then there is no register banking, and all * accesses are to the non-secure version. */ -static inline bool access_secure_reg(CPUARMState *env) -{ - bool ret = (arm_feature(env, ARM_FEATURE_EL3) && - !arm_el_is_aa64(env, 3) && - !(env->cp15.scr_el3 & SCR_NS)); - - return ret; -} +bool access_secure_reg(CPUARMState *env); uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint32_t cur_el, bool secure); diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 9e6a1869f94..8d79b8b7ae1 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -63,6 +63,15 @@ static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr) #endif } +bool access_secure_reg(CPUARMState *env) +{ + bool ret = (arm_feature(env, ARM_FEATURE_EL3) && + !arm_el_is_aa64(env, 3) && + !(env->cp15.scr_el3 & SCR_NS)); + + return ret; +} + static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, CPUARMTBFlags flags) From patchwork Thu Mar 6 16:39:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 870887 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp351289wri; Thu, 6 Mar 2025 08:41:41 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXc7oMZby9Iepnw0jFKhUFPgBTD/HZMq+h0nIGnDZhYiKtAy1MYmuAgzqHG+rxY6JGeWBldIQ==@linaro.org X-Google-Smtp-Source: AGHT+IE7I2F+eR3MNz7C9w20djewrgaRoRuUIyJGpyAld+s7jfKrNtvAPPwJ5A8jGiBK23kIGrGu X-Received: by 2002:ac8:5dc8:0:b0:472:5f9:1f71 with SMTP id d75a77b69052e-4750b24861dmr124950301cf.2.1741279301419; Thu, 06 Mar 2025 08:41:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741279301; cv=none; d=google.com; s=arc-20240605; b=b98KSGShn/STgzikdQBbY8Tw/LWHkhzRC6YWfB/d67Bzg4KG+GJt+9fotUBqjBDjP0 8WPKjQsZuHYE6RAQsa0rMz478DrBAIfgguH/2cBKuI8lhmQy+mFmmGKSDYENMFFhA2Mj JXNe5kRZR/zuGUcyrjOVx8oy7ycPsMpSR61ZLTM5f4vZFtouHyif+Cr5YQOjlCyPAqnU PqOcuwMist4JQCIMapmabShsZ19bg9UcBNqnM1qECaW+vYQQamQqIX9MX4xBja1AyIk8 wksTWvRE3I+s+wTcce6laNDYqNXvuiM+5mNR1Hu7tCmo5vQqdcX55Ax8sgOGy0P9CD+H PMKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=k5hIZtfWRRivBnmcIBAqfcb8VlTDxUApJC/AqX8qCP4=; fh=VshoAlqtqBhobhKzu0+imjKxUeQDsCkMxo3o1hV53cA=; b=QG3zXBsCxS1D3xwg2qP9AxxPuunK28r7um6dLf1UfBCv+TrWVKNkQK2SXJG+4dFHaR Nja9LO+UpWx5PbIfFy9CvM9zh0+tGECNWbDRk/isUPlxhCnsbr/4n5O3e4luEHxxMRPn JTJdmy5PxH2VwwhuHV9tYA7B28uEHuy3Caifi3kiyiK6gRYaDg9PN7tz3vxhggUIVTXO 7EOxaY2yi4Fnlh3MFr+JkmSeXTrg+Fsiao++wjMbl8srY3/vgWXriNFukWhFi0/R/hDQ /mcqsRPF7FWhzaFo1eUMfnLbToFeQwwE4qADbAAz688AJje3ZIKCPIEUQLrWIrKNavRz R1Ug==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aeCxaM4d; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd94913fsm23999905e9.37.2025.03.06.08.39.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Mar 2025 08:39:29 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/10] linux-user/aarch64: Remove unused get/put_user macros Date: Thu, 6 Mar 2025 16:39:17 +0000 Message-ID: <20250306163925.2940297-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250306163925.2940297-1-peter.maydell@linaro.org> References: <20250306163925.2940297-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org At the top of linux-user/aarch64/cpu_loop.c we define a set of macros for reading and writing data and code words, but we never use these macros. Delete them. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 48 ----------------------------------- 1 file changed, 48 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index c5d8a483a3f..fea43cefa6b 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -27,54 +27,6 @@ #include "target/arm/syndrome.h" #include "target/arm/cpu-features.h" -#define get_user_code_u32(x, gaddr, env) \ - ({ abi_long __r = get_user_u32((x), (gaddr)); \ - if (!__r && bswap_code(arm_sctlr_b(env))) { \ - (x) = bswap32(x); \ - } \ - __r; \ - }) - -#define get_user_code_u16(x, gaddr, env) \ - ({ abi_long __r = get_user_u16((x), (gaddr)); \ - if (!__r && bswap_code(arm_sctlr_b(env))) { \ - (x) = bswap16(x); \ - } \ - __r; \ - }) - -#define get_user_data_u32(x, gaddr, env) \ - ({ abi_long __r = get_user_u32((x), (gaddr)); \ - if (!__r && arm_cpu_bswap_data(env)) { \ - (x) = bswap32(x); \ - } \ - __r; \ - }) - -#define get_user_data_u16(x, gaddr, env) \ - ({ abi_long __r = get_user_u16((x), (gaddr)); \ - if (!__r && arm_cpu_bswap_data(env)) { \ - (x) = bswap16(x); \ - } \ - __r; \ - }) - -#define put_user_data_u32(x, gaddr, env) \ - ({ typeof(x) __x = (x); \ - if (arm_cpu_bswap_data(env)) { \ - __x = bswap32(__x); \ - } \ - put_user_u32(__x, (gaddr)); \ - }) - -#define put_user_data_u16(x, gaddr, env) \ - ({ typeof(x) __x = (x); \ - if (arm_cpu_bswap_data(env)) { \ - __x = bswap16(__x); \ - } \ - put_user_u16(__x, (gaddr)); \ - }) - /* AArch64 main loop */ void cpu_loop(CPUARMState *env) { From patchwork Thu Mar 6 16:39:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 870884 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp350728wri; Thu, 6 Mar 2025 08:40:17 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWgsJ0RauUOWplMcUI3gUMV31O2W2qPHD1U2z5NEYHIcZA5B5ftS38OS7fSz+pqdJrBkhvKyQ==@linaro.org X-Google-Smtp-Source: AGHT+IEdxfeUmvyUcqwG6E/ISSFS/l2nR5HOXFxmrSo6Ulf3Yikl2Es+MBDhn9NrzT+QxjknhAJ+ X-Received: by 2002:ac8:5852:0:b0:471:ea1a:da0 with SMTP id d75a77b69052e-4750b4e708fmr116270521cf.43.1741279216897; Thu, 06 Mar 2025 08:40:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741279216; cv=none; d=google.com; s=arc-20240605; b=YQq77OSUlg2qzk6yosLQEUo2YYu7IX6w5uBJy6+hNjYC/V8S7sf3DPSykFFQND5+gn A+kZ7vLVuUW5uaTZ4SDG6aFcsEPhgr5zv8Lp/Kt9rAHS487vHMBeHybi3dQSavWwrIUc zkRBXhfdje4ONrX77X82C8UqVHO6/0Z7FWb7+2lJmAp40SsbW9UtdETy6zby+Vr8WrDv VHDsBckBwOaNpoLiflFmxPmYPG2xNbCCsyBauH9N4e6Zz0C6NImtK3a1gLyVjf3ZBXrq rulrBG2SOiPTjhKpkvx8ZAgEtmVMYzY8ubWRKxCX+ow2aVLpT2izA4QYDn6UKtjR8XUH uMwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=boqObD7bZDYwU3C5F1au5ERTDSOIX+SOptk6jDi4Ufo=; fh=8JubuppKkgkQR2tJjP7aNgv2ZvPxxlpeqIasGfXIoUc=; b=BOli13AUeojNfM72QSXKVrwpF3F4qMT9TfFCEaga/N/p4PtVmRZgK8ulqp0tDQAKbH iEOP7v4aEGlqmFSWFTjtm6W2v5ggVcit6Tfe8wSnoOH5nnGlAehxxVL3X8C7K1BVcLc5 QTD7eVgFX/A59uThttz0fkDcU+bcjJKRL4qVWEDEaChYfK7V8ShaeBLBmAcg8a3ij0iU 1gd6zrmGA3DtVMdGxHEfeMTea/SxQ4n1Xo6cgSw/tk2SsIM73JbxLVT1eRY5TybMObd+ N3W4Uj9g0RHWteeyQBj1m1Fix5A+7yn9p0Yeg8nLR0d4OMPq8UOE8haRgAJBKMCcmaC0 +yzw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fL+74agP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd94913fsm23999905e9.37.2025.03.06.08.39.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Mar 2025 08:39:30 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/10] linux-user/arm: Remove unused get_put_user macros Date: Thu, 6 Mar 2025 16:39:18 +0000 Message-ID: <20250306163925.2940297-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250306163925.2940297-1-peter.maydell@linaro.org> References: <20250306163925.2940297-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In linux-user/arm/cpu_loop.c we define a full set of get/put macros for both code and data (since the endianness handling is different between the two). However the only one we actually use is get_user_code_u32(). Remove the rest. We leave a comment noting how data-side accesses should be handled for big-endian, because that's a subtle point and we just removed the macros that were effectively documenting it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- linux-user/arm/cpu_loop.c | 43 ++++----------------------------------- 1 file changed, 4 insertions(+), 39 deletions(-) diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 10d8561f9b9..7416e3216ea 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -36,45 +36,10 @@ __r; \ }) -#define get_user_code_u16(x, gaddr, env) \ - ({ abi_long __r = get_user_u16((x), (gaddr)); \ - if (!__r && bswap_code(arm_sctlr_b(env))) { \ - (x) = bswap16(x); \ - } \ - __r; \ - }) - -#define get_user_data_u32(x, gaddr, env) \ - ({ abi_long __r = get_user_u32((x), (gaddr)); \ - if (!__r && arm_cpu_bswap_data(env)) { \ - (x) = bswap32(x); \ - } \ - __r; \ - }) - -#define get_user_data_u16(x, gaddr, env) \ - ({ abi_long __r = get_user_u16((x), (gaddr)); \ - if (!__r && arm_cpu_bswap_data(env)) { \ - (x) = bswap16(x); \ - } \ - __r; \ - }) - -#define put_user_data_u32(x, gaddr, env) \ - ({ typeof(x) __x = (x); \ - if (arm_cpu_bswap_data(env)) { \ - __x = bswap32(__x); \ - } \ - put_user_u32(__x, (gaddr)); \ - }) - -#define put_user_data_u16(x, gaddr, env) \ - ({ typeof(x) __x = (x); \ - if (arm_cpu_bswap_data(env)) { \ - __x = bswap16(__x); \ - } \ - put_user_u16(__x, (gaddr)); \ - }) +/* + * Note that if we need to do data accesses here, they should do a + * bswap if arm_cpu_bswap_data() returns true. + */ /* * Similar to code in accel/tcg/user-exec.c, but outside the execution loop. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd94913fsm23999905e9.37.2025.03.06.08.39.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Mar 2025 08:39:31 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/10] target/arm: Move arm_cpu_data_is_big_endian() etc to internals.h Date: Thu, 6 Mar 2025 16:39:19 +0000 Message-ID: <20250306163925.2940297-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250306163925.2940297-1-peter.maydell@linaro.org> References: <20250306163925.2940297-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The arm_cpu_data_is_big_endian() and related functions are now used only in target/arm; they can be moved to internals.h. The motivation here is that we would like to move arm_current_el() to internals.h. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 48 ------------------------------------------ target/arm/internals.h | 48 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 48 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5ae40f32491..16c9083be61 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3030,47 +3030,6 @@ static inline bool arm_sctlr_b(CPUARMState *env) uint64_t arm_sctlr(CPUARMState *env, int el); -static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, - bool sctlr_b) -{ -#ifdef CONFIG_USER_ONLY - /* - * In system mode, BE32 is modelled in line with the - * architecture (as word-invariant big-endianness), where loads - * and stores are done little endian but from addresses which - * are adjusted by XORing with the appropriate constant. So the - * endianness to use for the raw data access is not affected by - * SCTLR.B. - * In user mode, however, we model BE32 as byte-invariant - * big-endianness (because user-only code cannot tell the - * difference), and so we need to use a data access endianness - * that depends on SCTLR.B. - */ - if (sctlr_b) { - return true; - } -#endif - /* In 32bit endianness is determined by looking at CPSR's E bit */ - return env->uncached_cpsr & CPSR_E; -} - -static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) -{ - return sctlr & (el ? SCTLR_EE : SCTLR_E0E); -} - -/* Return true if the processor is in big-endian mode. */ -static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) -{ - if (!is_a64(env)) { - return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); - } else { - int cur_el = arm_current_el(env); - uint64_t sctlr = arm_sctlr(env, cur_el); - return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); - } -} - #include "exec/cpu-all.h" /* @@ -3256,13 +3215,6 @@ static inline bool bswap_code(bool sctlr_b) #endif } -#ifdef CONFIG_USER_ONLY -static inline bool arm_cpu_bswap_data(CPUARMState *env) -{ - return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); -} -#endif - void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags); diff --git a/target/arm/internals.h b/target/arm/internals.h index a6ff228f9fd..70d1f88c20b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -392,6 +392,54 @@ static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode) return arm_rmode_to_sf_map[rmode]; } +static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, + bool sctlr_b) +{ +#ifdef CONFIG_USER_ONLY + /* + * In system mode, BE32 is modelled in line with the + * architecture (as word-invariant big-endianness), where loads + * and stores are done little endian but from addresses which + * are adjusted by XORing with the appropriate constant. So the + * endianness to use for the raw data access is not affected by + * SCTLR.B. + * In user mode, however, we model BE32 as byte-invariant + * big-endianness (because user-only code cannot tell the + * difference), and so we need to use a data access endianness + * that depends on SCTLR.B. + */ + if (sctlr_b) { + return true; + } +#endif + /* In 32bit endianness is determined by looking at CPSR's E bit */ + return env->uncached_cpsr & CPSR_E; +} + +static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) +{ + return sctlr & (el ? SCTLR_EE : SCTLR_E0E); +} + +/* Return true if the processor is in big-endian mode. */ +static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) +{ + if (!is_a64(env)) { + return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); + } else { + int cur_el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, cur_el); + return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); + } +} + +#ifdef CONFIG_USER_ONLY +static inline bool arm_cpu_bswap_data(CPUARMState *env) +{ + return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); +} +#endif + static inline void aarch64_save_sp(CPUARMState *env, int el) { if (env->pstate & PSTATE_SP) { From patchwork Thu Mar 6 16:39:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 870889 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp351501wri; Thu, 6 Mar 2025 08:42:08 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWl4SZCWAqrJ5m7INUzCiHyU5xQVAwb5l06t+eKZXJZYQp7pwB8kDstChrwVfdFUC2nLXttmQ==@linaro.org X-Google-Smtp-Source: AGHT+IGoIcpj4uigG59qcS4fw9kKXtvNLQ+JAOHvg1/cs3ZRnYLIOXVuU6W+/tW0JETzEU6YOu1T X-Received: by 2002:a05:6102:6cb:b0:4bb:9b46:3f87 with SMTP id ada2fe7eead31-4c2e27b34ecmr4813692137.6.1741279328521; Thu, 06 Mar 2025 08:42:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741279328; cv=none; d=google.com; s=arc-20240605; b=Inhs84i2FuTfQs2Vzfv2cWz0fZwI3NDzmSjXm377MYaj6ets9h+2sXQ12eJkWbs5ef jIsJJCTiJoCgp3z3L6vso5F+WWRyrPiYRmKsWnQWGBg3XcV/krG788MiXNWHnpR+2nSv cJBX2hGzpcopJ9Qhd02+T+1p354dS44zhpnddRMVxjeypE88tl7z6IvslUIR7LlHrYL9 EK+BwEw+LEo92guFcmuEumUOE3EOs8YTSRGvJNpoRHouZzBYUSrHynXbeOzsl6Yfpxku H6f62I/Zps9dzaDWoaUl46KKUJ3hRxcHcBZhj/bCl/BVJqD+lyKs8DlkCHHVHa3+3Sd8 4Qww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vxTSFCna0HuVCZNyrZWduZwQIOEnzTKyAVW239fxJio=; fh=5iZeHhzCGBo29vEF42sWi+mF4gVRJn3DB02HwJSNyxs=; b=FrT5IGsUInlduuCtj+EOD+THEWLaclL6n3+LoqW4xB/oxBVeT2BW+FWiz+oIhSx3/g BNsJAvCaUNZ72VGOrjFggf2WrzvNRddk7/vicPL/0KwJEaMmbhbsXfoFhoEKa0AbHeO2 PS5vX3Kx3/3rj6WcSI3X5wdpgZaGDoOOc8kWhROo9yWbbw4Pok9WlvJdDpKDVLNnSfvS a93Z8PHdLcUez1CbJN33gSr82IjXUPhyvkI0wlagxNNx5IY8za5YA5CDpJKH0PIjxXuT jNGKQgLOQI6pioucJgy8z1aPbKPWa+GbptvzBW72J2TkCjXfxLnvyQWFlWL0k/uvtFMW iEYA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KEPeZQXE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd94913fsm23999905e9.37.2025.03.06.08.39.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Mar 2025 08:39:32 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/10] target/arm: Move arm_current_el() and arm_el_is_aa64() to internals.h Date: Thu, 6 Mar 2025 16:39:20 +0000 Message-ID: <20250306163925.2940297-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250306163925.2940297-1-peter.maydell@linaro.org> References: <20250306163925.2940297-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The functions arm_current_el() and arm_el_is_aa64() are used only in target/arm and in hw/intc/arm_gicv3_cpuif.c. They're functions that query internal state of the CPU. Move them out of cpu.h and into internals.h. This means we need to include internals.h in arm_gicv3_cpuif.c, but this is justifiable because that file is implementing the GICv3 CPU interface, which really is part of the CPU proper; we just ended up implementing it in code in hw/intc/ for historical reasons. The motivation for this move is that we'd like to change arm_el_is_aa64() to add a condition that uses cpu_isar_feature(); but we don't want to include cpu-features.h in cpu.h. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 66 -------------------------------------- target/arm/internals.h | 67 +++++++++++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_cpuif.c | 1 + target/arm/arch_dump.c | 1 + 4 files changed, 69 insertions(+), 66 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 16c9083be61..a779fd5ae94 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2633,39 +2633,6 @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); uint64_t arm_hcr_el2_eff(CPUARMState *env); uint64_t arm_hcrx_el2_eff(CPUARMState *env); -/* Return true if the specified exception level is running in AArch64 state. */ -static inline bool arm_el_is_aa64(CPUARMState *env, int el) -{ - /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, - * and if we're not in EL0 then the state of EL0 isn't well defined.) - */ - assert(el >= 1 && el <= 3); - bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); - - /* The highest exception level is always at the maximum supported - * register width, and then lower levels have a register width controlled - * by bits in the SCR or HCR registers. - */ - if (el == 3) { - return aa64; - } - - if (arm_feature(env, ARM_FEATURE_EL3) && - ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { - aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); - } - - if (el == 2) { - return aa64; - } - - if (arm_is_el2_enabled(env)) { - aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); - } - - return aa64; -} - /* * Function for determining whether guest cp register reads and writes should * access the secure or non-secure bank of a cp register. When EL3 is @@ -2697,39 +2664,6 @@ static inline bool arm_v7m_is_handler_mode(CPUARMState *env) return env->v7m.exception != 0; } -/* Return the current Exception Level (as per ARMv8; note that this differs - * from the ARMv7 Privilege Level). - */ -static inline int arm_current_el(CPUARMState *env) -{ - if (arm_feature(env, ARM_FEATURE_M)) { - return arm_v7m_is_handler_mode(env) || - !(env->v7m.control[env->v7m.secure] & 1); - } - - if (is_a64(env)) { - return extract32(env->pstate, 2, 2); - } - - switch (env->uncached_cpsr & 0x1f) { - case ARM_CPU_MODE_USR: - return 0; - case ARM_CPU_MODE_HYP: - return 2; - case ARM_CPU_MODE_MON: - return 3; - default: - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { - /* If EL3 is 32-bit then all secure privileged modes run in - * EL3 - */ - return 3; - } - - return 1; - } -} - /** * write_list_to_cpustate * @cpu: ARMCPU diff --git a/target/arm/internals.h b/target/arm/internals.h index 70d1f88c20b..b3f732233f4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -392,6 +392,73 @@ static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode) return arm_rmode_to_sf_map[rmode]; } +/* Return true if the specified exception level is running in AArch64 state. */ +static inline bool arm_el_is_aa64(CPUARMState *env, int el) +{ + /* + * This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, + * and if we're not in EL0 then the state of EL0 isn't well defined.) + */ + assert(el >= 1 && el <= 3); + bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); + + /* + * The highest exception level is always at the maximum supported + * register width, and then lower levels have a register width controlled + * by bits in the SCR or HCR registers. + */ + if (el == 3) { + return aa64; + } + + if (arm_feature(env, ARM_FEATURE_EL3) && + ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { + aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); + } + + if (el == 2) { + return aa64; + } + + if (arm_is_el2_enabled(env)) { + aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); + } + + return aa64; +} + +/* + * Return the current Exception Level (as per ARMv8; note that this differs + * from the ARMv7 Privilege Level). + */ +static inline int arm_current_el(CPUARMState *env) +{ + if (arm_feature(env, ARM_FEATURE_M)) { + return arm_v7m_is_handler_mode(env) || + !(env->v7m.control[env->v7m.secure] & 1); + } + + if (is_a64(env)) { + return extract32(env->pstate, 2, 2); + } + + switch (env->uncached_cpsr & 0x1f) { + case ARM_CPU_MODE_USR: + return 0; + case ARM_CPU_MODE_HYP: + return 2; + case ARM_CPU_MODE_MON: + return 3; + default: + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + /* If EL3 is 32-bit then all secure privileged modes run in EL3 */ + return 3; + } + + return 1; + } +} + static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, bool sctlr_b) { diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 7f1d071c198..de37465bc87 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "target/arm/cpregs.h" #include "target/arm/cpu-features.h" +#include "target/arm/internals.h" #include "system/tcg.h" #include "system/qtest.h" diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 5c943dc27b5..c40df4e7fd7 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -23,6 +23,7 @@ #include "elf.h" #include "system/dump.h" #include "cpu-features.h" +#include "internals.h" /* struct user_pt_regs from arch/arm64/include/uapi/asm/ptrace.h */ struct aarch64_user_regs { From patchwork Thu Mar 6 16:39:21 2025 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd94913fsm23999905e9.37.2025.03.06.08.39.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Mar 2025 08:39:33 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 07/10] target/arm: SCR_EL3.RW should be treated as 1 if EL2 doesn't support AArch32 Date: Thu, 6 Mar 2025 16:39:21 +0000 Message-ID: <20250306163925.2940297-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250306163925.2940297-1-peter.maydell@linaro.org> References: <20250306163925.2940297-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The definition of SCR_EL3.RW says that its effective value is 1 if: - EL2 is implemented and does not support AArch32, and SCR_EL3.NS is 1 - the effective value of SCR_EL3.{EEL2,NS} is {1,0} (i.e. we are Secure and Secure EL2 is disabled) We implement the second of these in arm_el_is_aa64(), but forgot the first (because currently all our CPUs with AArch64 support AArch32 at all exception levels). Provide a new function arm_scr_rw_eff() to return the effective value of SCR_EL3.RW, and use it in arm_el_is_aa64() and the other places that currently look directly at the bit value. (scr_write() enforces that the RW bit is RAO/WI if neither EL1 nor EL2 have AArch32 support, but if EL1 does but EL2 does not then the bit must still be writeable.) This will mean that if code at EL3 attempts to perform an exception return to AArch32 EL2 when EL2 is AArch64-only we will correctly handle this as an illegal exception return: it will be caught by the "return to an EL which is configured for a different register width" check in HELPER(exception_return). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/internals.h | 24 +++++++++++++++++++++--- target/arm/helper.c | 4 ++-- 2 files changed, 23 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index b3f732233f4..82a0e1f785f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -392,6 +392,25 @@ static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode) return arm_rmode_to_sf_map[rmode]; } +/* Return the effective value of SCR_EL3.RW */ +static inline bool arm_scr_rw_eff(CPUARMState *env) +{ + /* + * SCR_EL3.RW has an effective value of 1 if: + * - we are NS and EL2 is implemented but doesn't support AArch32 + * - we are S and EL2 is enabled (in which case it must be AArch64) + */ + ARMCPU *cpu = env_archcpu(env); + bool ns_and_no_aarch32_el2 = arm_feature(env, ARM_FEATURE_EL2) && + (env->cp15.scr_el3 & SCR_NS) && + !cpu_isar_feature(aa64_aa32_el1, cpu); + bool s_and_el2_enabled = + (env->cp15.scr_el3 & (SCR_NS | SCR_EEL2)) == SCR_EEL2; + + return ns_and_no_aarch32_el2 || s_and_el2_enabled || + (env->cp15.scr_el3 & SCR_RW); +} + /* Return true if the specified exception level is running in AArch64 state. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) { @@ -411,9 +430,8 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) return aa64; } - if (arm_feature(env, ARM_FEATURE_EL3) && - ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { - aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); + if (arm_feature(env, ARM_FEATURE_EL3)) { + aa64 = aa64 && arm_scr_rw_eff(env); } if (el == 2) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 71dead7241b..1085bff0ec5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9609,7 +9609,7 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint64_t hcr_el2; if (arm_feature(env, ARM_FEATURE_EL3)) { - rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); + rw = arm_scr_rw_eff(env); } else { /* * Either EL2 is the highest EL (and so the EL2 register width @@ -10418,7 +10418,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) switch (new_el) { case 3: - is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; + is_aa64 = arm_scr_rw_eff(env); break; case 2: hcr = arm_hcr_el2_eff(env); From patchwork Thu Mar 6 16:39:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 870893 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp352339wri; Thu, 6 Mar 2025 08:44:05 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXKnMkJKwXgtKrV0DxFV6H7XKtP3D35k13k9t4C98AivPzl1IyRc95D/tmoPG50p/BOeYVBcg==@linaro.org X-Google-Smtp-Source: AGHT+IHvxvDjEhfdwiMBgJFjY8dWjN1I3DypiZ4GV7Eg7fosYTvgXSfFonSjfMRgWDaEdPjXZXOZ X-Received: by 2002:a05:620a:2b96:b0:7c3:ccf5:363e with SMTP id af79cd13be357-7c3d8dd04dcmr1254295285a.13.1741279445705; Thu, 06 Mar 2025 08:44:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741279445; cv=none; d=google.com; s=arc-20240605; b=a0eSqFXnwX6kqVRrZTToJsp2eveG3GJbWkxPqlPYUP/S+WAN44qk/eCdh07+/tV0lo IE4iLs8RGZ/7sEvb1ervGBRS7aQn/k6fslfSIUD1Tm2RKdaxsbofd39Tu56cfIRiTOnm l98ysUTBxVYfIp83kpC143NBrQrQutg1jvbSOH0O603pqKQEcCKpQUBUK2T2PHVpmTHg Ex9j5t8tMadpr+SOAV5PB2rv57YQ6H2w8zXHB9WIH0l6WeYfMwJlo806hHoNkLzlvCCw YY3AzkKW2Q3JW+4906OSRAyJA4n59gdvdgwzlJjN8fjegx08eNUBXkrIBZ+YXKIycSuJ JNwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0WIG0SaEOnTT7Vl+CcOLcRx6EDCmK/EJvLZA/gTBtzQ=; fh=VXWJj3eY3IYmsqiWU9bYySUNObPhZHMgXbbY6+YodPw=; b=O71tMaMdv249kydSvRYFCvmCEFh+ANcUjPtMkTK9rEVbmqa62ulOM3rPh0VcRUZC4x CzAF3hzhHkfRNkmlQEA5Lz3rtv3mwYSLbdT13Ci9L2tGol3vcf1tlk4WnAV2QfLWYEp+ YlDP/G8ifecHNeFkRgiVkzLZxwLXzNv2CKOCHtESmTd6IIWPiWAk0GNB5QwHbM8RR57Q NNKsZQ0ChSekZ++iQGwMTRMXvU/Z9TCAyQ+9Jf3Gz/kPpkzdErIwfobRWFdSqirsZBrH pMFfMwjBxzMndPhN+pKfVmeh2QB4nGaXQnN1LTfKh37zipfCvcC0malMHOWAy9jM7RoS aj3A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HOUs+GU0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd94913fsm23999905e9.37.2025.03.06.08.39.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Mar 2025 08:39:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/10] target/arm: HCR_EL2.RW should be RAO/WI if EL1 doesn't support AArch32 Date: Thu, 6 Mar 2025 16:39:22 +0000 Message-ID: <20250306163925.2940297-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250306163925.2940297-1-peter.maydell@linaro.org> References: <20250306163925.2940297-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When EL1 doesn't support AArch32, the HCR_EL2.RW bit is supposed to be RAO/WI. We don't enforce this. This isn't a problem yet because at the moment all of our CPU types with AArch64 support AArch32 at all exception levels, but in the future this is likely to no longer be true. Enforce the RAO/WI behaviour. Note that we handle "reset value should honour RES1 bits" in the same way that SCR_EL3 does, via a reset function. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1085bff0ec5..6dc6f3858fc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5167,6 +5167,11 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) /* Clear RES0 bits. */ value &= valid_mask; + /* RW is RAO/WI if EL1 is AArch64 only */ + if (!cpu_isar_feature(aa64_aa32_el1, cpu)) { + value |= HCR_RW; + } + /* * These bits change the MMU setup: * HCR_VM enables stage 2 translation @@ -5224,6 +5229,12 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); } +static void hcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* hcr_write will set the RES1 bits on an AArch64-only CPU */ + hcr_write(env, ri, 0); +} + /* * Return the effective value of HCR_EL2, at the given security state. * Bits that are not included here: @@ -5459,6 +5470,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), .nv2_redirect_offset = 0x78, + .resetfn = hcr_reset, .writefn = hcr_write, .raw_writefn = raw_write }, { .name = "HCR", .state = ARM_CP_STATE_AA32, .type = ARM_CP_ALIAS | ARM_CP_IO, From patchwork Thu Mar 6 16:39:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 870891 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp351697wri; Thu, 6 Mar 2025 08:42:32 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVctf8BkiQoGzcVvW+y5+wfebsOwhTUQGXnkn9aW93hCl0o1MSWL+ijlajmZNPzocYdf0IVDQ==@linaro.org X-Google-Smtp-Source: AGHT+IFOH6ytDCuHTdWBXDDbNcqlJAjiylF4GyH4EnB4296JVhQgdfKLmjSOERvYNUn1VXzPzpAe X-Received: by 2002:a05:6102:2911:b0:4c1:924e:1a1d with SMTP id ada2fe7eead31-4c2e2969e21mr5234145137.18.1741279352685; Thu, 06 Mar 2025 08:42:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741279352; cv=none; d=google.com; s=arc-20240605; b=Bk9OcNA3+0qkzldLlXVKV+y98xJuYjj1rct1mZJrCm7WltNqelfXghBLo2yI11ijJY YsCvb5wnsK8fb1ozEZfL32ojqlobUB/Yzvp2dxyqpHLfkbaIXBIS2iivk3hmO89UyI+Y K1ENA1dbkdwTGGxUlvSjsa7z8pqo5bvz03nd4mC+rky0fnnbufPkRVbd4CCe2W3I4HJK nJ4DJ2TVHKQxKXer0PJlH3VT3alJantwidlTIsFZUxhp2QW1x3RVSR+X07Uq+YdKBa5Q 8zM+deDKFmSp4CN+ZlUEg1nbz39aYoUze17vfiNGIX3aQQjXFecvMIjzURkLJP9jCenV 9nNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=drdpohR6Dj+KXd2wNLa0BIt2hP6cDbsQHnby3gMJcxE=; fh=3mRwEHPGBqqR5hazq8axEoqU1xMco4JMBEMS+Wkcu8Y=; b=NRvRI+jmz80Kr2iRHwSHstLl+SOv1eb/V9/ioM+pOtFQ4Jd1IHcMS8fGQ33rQlvsnX +6ExeDvqV3gbu6cqY18b2n8GbBR2KuRcP/FPI9A/5Hw8Q+iWXvh5CypuHtb5JjyXGQG6 k0B5pcJekLRv2CoRJ/SCbHAvXACFxH8TS2FUKy4Rx8Y49e1t/TrQy3hGmb2thLDbzGxR la5EHbSTWSOsBXHWzj4rxHdr1qR/VhvlMGwkgtw7PGiDpn0EAOsVCOXiOH2UJ9oGhSIg bRKnmiGGSztnuiX3bvuD2fgA0y5oeIrKBri/g6djhP6hxm4UTbA7nefazRQm1vZYUMSz nrlQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="GyzJ/WOv"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd94913fsm23999905e9.37.2025.03.06.08.39.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Mar 2025 08:39:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/10] target/arm: Add cpu local variable to exception_return helper Date: Thu, 6 Mar 2025 16:39:23 +0000 Message-ID: <20250306163925.2940297-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250306163925.2940297-1-peter.maydell@linaro.org> References: <20250306163925.2940297-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We already call env_archcpu() multiple times within the exception_return helper function, and we're about to want to add another use of the ARMCPU pointer. Add a local variable cpu so we can call env_archcpu() just once. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/helper-a64.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 32f0647ca4f..e2bdf07833d 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -631,6 +631,7 @@ static void cpsr_write_from_spsr_elx(CPUARMState *env, void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) { + ARMCPU *cpu = env_archcpu(env); int cur_el = arm_current_el(env); unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); uint32_t spsr = env->banked_spsr[spsr_idx]; @@ -682,7 +683,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } bql_lock(); - arm_call_pre_el_change_hook(env_archcpu(env)); + arm_call_pre_el_change_hook(cpu); bql_unlock(); if (!return_to_aa64) { @@ -710,7 +711,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) int tbii; env->aarch64 = true; - spsr &= aarch64_pstate_valid_mask(&env_archcpu(env)->isar); + spsr &= aarch64_pstate_valid_mask(&cpu->isar); pstate_write(env, spsr); if (!arm_singlestep_active(env)) { env->pstate &= ~PSTATE_SS; @@ -749,7 +750,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); bql_lock(); - arm_call_el_change_hook(env_archcpu(env)); + arm_call_el_change_hook(cpu); bql_unlock(); return; From patchwork Thu Mar 6 16:39:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 870890 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp351696wri; Thu, 6 Mar 2025 08:42:32 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWI9Bzb5PX3Z+tCwT2cUfEtAGjjgkwrvo7B6/pu8twd2wo6c0YodgC1WnFGzRQu7IB0TaChlQ==@linaro.org X-Google-Smtp-Source: AGHT+IFlD0cYINLpZ2CmITDeFe/+GPt0nPTd0J1w7FF5ZQWhwRzBgV2TnZ6hz9dWnQ5m9WhBe9OV X-Received: by 2002:a05:6102:3a09:b0:4c2:20d6:c6c3 with SMTP id ada2fe7eead31-4c2e27be28emr5782214137.10.1741279352590; Thu, 06 Mar 2025 08:42:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741279352; cv=none; d=google.com; s=arc-20240605; b=VbJZiBp3Mh54rGMOQLr6G3QIWOr/6N1e1z9b243ScO1zjS+FZaNMIJehSy6JAgQ2Lu Rlsv9iMkOKGTd3i29btonVhiSg+Ef+axhwboGzNZOV5v3b6OAjQeMB1pvnJdI1ZhTfuz v2VeRRTCuYkdzr0yujWc5U7gPpakSyxPA4ZPYaBAUSsoHsCgCCCRFa0dktPVgVBEMJT1 78LguPYlU4P5TB9823B6N8t7EoV0z5StwRFROI7/d5n5UBAx0L5xj3imPeKgZS1kDsXC 5smz2CTgGt4c1KKK45VzwPSDvtp6z3jp//eprdPLpDYj9puLGI93xW2Glr0L6F3FumPM FxMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Gn+iRr/DyOLW0klhx/+n+/C8SaHWZdNPyfpde7R5NiY=; fh=OwSLzW5jrsQDtzyT0Neao7JqdCvii+fKvS2ukEW65MY=; b=NVsgjsst98dPCE1GR+LTzoMk4KFsgcSwlNZT+v4bVcjmDyqKPWJlcl9anryACh2q2j E+7USpwqDydJl8Mg+dL+/rl8olZIYJrG1dUXGw6oH93kzwhfzGjCDXQeR1ozwVKH3/Iv qRcjcKHnbUi/AvdDZgd39/d3F8Nmqg+DLFucAJ7xPOFeW3DixVRtk8QxiJLFKpNgDky7 ViVn/aHI7zf5fKk2vo9QCTzW04ocICf5YfCZaH1ZuVahiAI/ivMyab1AlFzKMoxdIUXE Tej8MjCGuFWlTOkQMgxZa0fVU6iJ0lpBkXYE4sIXH6kgquceLPe7k5CnikZyysnVELQf fWvw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PnSqnbZS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd94913fsm23999905e9.37.2025.03.06.08.39.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Mar 2025 08:39:35 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/10] target/arm: Forbid return to AArch32 when CPU is AArch64-only Date: Thu, 6 Mar 2025 16:39:24 +0000 Message-ID: <20250306163925.2940297-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250306163925.2940297-1-peter.maydell@linaro.org> References: <20250306163925.2940297-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In the Arm ARM, rule R_TYTWB states that returning to AArch32 is an illegal exception return if: * AArch32 is not supported at any exception level * the target EL is configured for AArch64 via SCR_EL3.RW or HCR_EL2.RW or via CPU state at reset We check the second of these, but not the first (which can only be relevant for the case of a return to EL0, because if AArch32 is not supported at one of the higher ELs then the RW bits will have an effective value of 1 and the the "configured for AArch64" condition will hold also). Add the missing condition. This isn't currently a bug because all our CPUs support AArch32 at EL0, but future CPUs we add might be 64-bit only. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/helper-a64.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index e2bdf07833d..9244848efed 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -678,6 +678,11 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) goto illegal_return; } + if (!return_to_aa64 && !cpu_isar_feature(aa64_aa32, cpu)) { + /* Return to AArch32 when CPU is AArch64-only */ + goto illegal_return; + } + if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { goto illegal_return; }