From patchwork Fri Mar 7 05:22:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 871353 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2514218EFED; Fri, 7 Mar 2025 05:22:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741324977; cv=none; b=ROYyrlAA4vOvCWw9s6hBiSUYFzvQzPZh2IMtRJuB1XO6lOWfvtGdxeFUrYKANTFi5muX0ZN4x5LK/3+3s6k7mZiHfpanGNRbldorkEyzBuiLF99va1pImMzguIIkQB7hiCBL3emoqRvAcrRYUm1+TfvBIWtJE4HDKd6D2jv/xDw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741324977; c=relaxed/simple; bh=nuA1KkfUE7sKveeUOeLOX24K/lLByVSTTvCqOQomC4Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CHuXYLaR7HnvTTJ/M4ylbyvEYkIzYsw1Y/WwsP0Any5ufb2ttbERkGg613drRpz9YA97RwlBUgOT+L5lxFMNSHmd4bCcES+F85o3djPKBSGd/LJSrpkVELx3XP9JzSlewuwJE8N3CB37wr7GZoZGhgr7TJSADdeFGNafIY/4h5c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=BmSLVKxo; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="BmSLVKxo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741324975; x=1772860975; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nuA1KkfUE7sKveeUOeLOX24K/lLByVSTTvCqOQomC4Y=; b=BmSLVKxodt2bmLRFm9tq8o7I0e8pucWO9ifJebU9p0TH6x4N7uH2CCC+ WH4ldaCbpL+mtirFEHyGJOphINpZAnccQjNahJHKHNLsM5m9DjU8PpFJ4 IngNTcI87+01Nzs3rmdPzW0GhRW+J8g5i6PLBmWKt5Anz2NfA7U9GA8Kk wCNvE4eufyN2CEtP9u7f67rl+UA7q0EVWKh4CvqxdXW8NSHbN6aRXO2IV Sj8a+8WOoHLpT2VoiF392Kk4CB7wN9XXYqRbf1lPjWcPBIcbIoYfF3wCp LFZV7v5Hvzt32ssDxOaSVVMOkWR/YXRZLzclfFaXwyoJvXN0MRkzWxQcN Q==; X-CSE-ConnectionGUID: TXUnovGRR+qY0yS7naaOTQ== X-CSE-MsgGUID: oNLCEz/6R1i4wG44E0GJqA== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="46292942" X-IronPort-AV: E=Sophos;i="6.14,228,1736841600"; d="scan'208";a="46292942" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 21:22:54 -0800 X-CSE-ConnectionGUID: 9y5STP6KSbC5wRzSLlDi7w== X-CSE-MsgGUID: AkLMPpC9S+CdeJh15aKx1g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,228,1736841600"; d="scan'208";a="119232149" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by fmviesa007.fm.intel.com with ESMTP; 06 Mar 2025 21:22:51 -0800 From: Raag Jadav To: lee@kernel.org, giometti@enneenne.com, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, raymond.tan@intel.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Raag Jadav Subject: [PATCH v3 1/5] mfd: intel_ehl_pse_gpio: Introduce Intel Elkhart Lake PSE GPIO and TIO Date: Fri, 7 Mar 2025 10:52:27 +0530 Message-Id: <20250307052231.551737-2-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250307052231.551737-1-raag.jadav@intel.com> References: <20250307052231.551737-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Intel Elkhart Lake Programmable Service Engine (PSE) includes two PCI devices that expose two different capabilities of GPIO and Timed I/O as a single PCI function through shared MMIO. Signed-off-by: Raag Jadav Reviewed-by: Andy Shevchenko --- MAINTAINERS | 5 ++ drivers/mfd/Kconfig | 12 ++++ drivers/mfd/Makefile | 1 + drivers/mfd/intel_ehl_pse_gpio.c | 100 +++++++++++++++++++++++++++++++ 4 files changed, 118 insertions(+) create mode 100644 drivers/mfd/intel_ehl_pse_gpio.c diff --git a/MAINTAINERS b/MAINTAINERS index d4280facbe51..eb216eebb3a6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11604,6 +11604,11 @@ F: drivers/gpu/drm/xe/ F: include/drm/intel/ F: include/uapi/drm/xe_drm.h +INTEL EHL PSE GPIO MFD DRIVER +M: Raag Jadav +S: Supported +F: drivers/mfd/intel_ehl_pse_gpio.c + INTEL ETHERNET DRIVERS M: Tony Nguyen M: Przemek Kitszel diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 6b0682af6e32..36eac5245179 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -597,6 +597,18 @@ config MFD_HI655X_PMIC help Select this option to enable Hisilicon hi655x series pmic driver. +config MFD_INTEL_EHL_PSE_GPIO + tristate "Intel Elkhart Lake PSE GPIO MFD" + depends on PCI && (X86 || COMPILE_TEST) + select MFD_CORE + help + This MFD provides support for GPIO and TIO that exist on Intel + Elkhart Lake PSE as a single PCI device. It splits the two I/O + devices to their respective I/O drivers. + + To compile this driver as a module, choose M here: the module will + be called intel_ehl_pse_gpio. + config MFD_INTEL_QUARK_I2C_GPIO tristate "Intel Quark MFD I2C GPIO" depends on PCI diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 9220eaf7cf12..8f7d257856db 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -196,6 +196,7 @@ obj-$(CONFIG_MFD_TIMBERDALE) += timberdale.o obj-$(CONFIG_PMIC_ADP5520) += adp5520.o obj-$(CONFIG_MFD_ADP5585) += adp5585.o obj-$(CONFIG_MFD_KEMPLD) += kempld-core.o +obj-$(CONFIG_MFD_INTEL_EHL_PSE_GPIO) += intel_ehl_pse_gpio.o obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o obj-$(CONFIG_LPC_SCH) += lpc_sch.o obj-$(CONFIG_LPC_ICH) += lpc_ich.o diff --git a/drivers/mfd/intel_ehl_pse_gpio.c b/drivers/mfd/intel_ehl_pse_gpio.c new file mode 100644 index 000000000000..6a6ad1390a7b --- /dev/null +++ b/drivers/mfd/intel_ehl_pse_gpio.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel MFD driver for Elkhart Lake - Programmable Service Engine + * (PSE) GPIO & TIO + * + * Copyright (c) 2025 Intel Corporation + * + * Intel Elkhart Lake PSE includes two PCI devices that expose two + * different capabilities of GPIO and Timed I/O as a single PCI + * function through shared MMIO. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PSE_GPIO_OFFSET 0x0000 +#define PSE_GPIO_SIZE 0x0134 + +#define PSE_TIO_OFFSET 0x1000 +#define PSE_TIO_SIZE 0x06B0 + +static struct resource ehl_pse_gpio_resources[] = { + DEFINE_RES_MEM(PSE_GPIO_OFFSET, PSE_GPIO_SIZE), + DEFINE_RES_IRQ(0), +}; + +static struct resource ehl_pse_tio_resources[] = { + DEFINE_RES_MEM(PSE_TIO_OFFSET, PSE_TIO_SIZE), + DEFINE_RES_IRQ(1), +}; + +static struct mfd_cell ehl_pse_gpio_devs[] = { + { + .name = "gpio-elkhartlake", + .num_resources = ARRAY_SIZE(ehl_pse_gpio_resources), + .resources = ehl_pse_gpio_resources, + .ignore_resource_conflicts = true, + }, + { + .name = "pps-gen-tio", + .num_resources = ARRAY_SIZE(ehl_pse_tio_resources), + .resources = ehl_pse_tio_resources, + .ignore_resource_conflicts = true, + }, +}; + +static int ehl_pse_gpio_probe(struct pci_dev *pci, const struct pci_device_id *id) +{ + int ret; + + ret = pcim_enable_device(pci); + if (ret) + return ret; + + pci_set_master(pci); + + ret = pci_alloc_irq_vectors(pci, 2, 2, PCI_IRQ_ALL_TYPES); + if (ret < 0) + return ret; + + ret = mfd_add_devices(&pci->dev, PLATFORM_DEVID_AUTO, ehl_pse_gpio_devs, + ARRAY_SIZE(ehl_pse_gpio_devs), pci_resource_n(pci, 0), + pci_irq_vector(pci, 0), NULL); + if (ret) + pci_free_irq_vectors(pci); + + return ret; +} + +static void ehl_pse_gpio_remove(struct pci_dev *pdev) +{ + mfd_remove_devices(&pdev->dev); + pci_free_irq_vectors(pdev); +} + +static const struct pci_device_id ehl_pse_gpio_ids[] = { + { PCI_VDEVICE(INTEL, 0x4b88) }, + { PCI_VDEVICE(INTEL, 0x4b89) }, + {} +}; +MODULE_DEVICE_TABLE(pci, ehl_pse_gpio_ids); + +static struct pci_driver ehl_pse_gpio_driver = { + .probe = ehl_pse_gpio_probe, + .remove = ehl_pse_gpio_remove, + .id_table = ehl_pse_gpio_ids, + .name = "ehl_pse_gpio", +}; +module_pci_driver(ehl_pse_gpio_driver); + +MODULE_AUTHOR("Raymond Tan "); +MODULE_AUTHOR("Raag Jadav "); +MODULE_DESCRIPTION("Intel MFD for Elkhart Lake PSE GPIO & TIO"); +MODULE_LICENSE("GPL"); From patchwork Fri Mar 7 05:22:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 871994 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE406196C7B; Fri, 7 Mar 2025 05:22:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741324979; cv=none; b=Hf7jNAT6CRYeogiK5BTrdRhaOBHYVR1vgnKk554/QjIMnA+gApoWzYNaTlcyyRDsdZCVe5BozqkLOmWbySes9Kd+sgKtTkNYEcV7V7FjSrvbwQelhL3lG1G6ESOtTertQUXynN+ggelqFiSeVduLx+HWNWugaveAGYQIUohpbsM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741324979; c=relaxed/simple; bh=VXAdkYmjkjtd/iVVlCqAfnvOuaPvFBMXREQn4tbP4bk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fTaF9iHg5nTJsL7nnJUvO5BJt51eaIZbUcBSwXhK8D7PsIBaJhICVqaFgS3+IjqTZJeuAAwfUhl0/CDpP4pRBdWeBTWNboRZST+CsHapV4/R6rzMTZAbqP0WnROt5cBceSMSLyg1+d0EA8FWRGFpKd8zWAHbyAhe0RbNDdIpbZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jffJaBvG; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jffJaBvG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741324978; x=1772860978; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VXAdkYmjkjtd/iVVlCqAfnvOuaPvFBMXREQn4tbP4bk=; b=jffJaBvGyPLimtnY3O4MA1EbMmHmI+tAbIaSgMBmpJ+6tdVLFhWSvwSv A962ySZw1+6lBGnCVJxnInCvJK0OBSX7whNMWCrFIv7LaqiK0yEEkvGsB tdSkcF+CAAoxfd7osJKANYS9DTgRCN8UnGYRF6XJ25HIPaFAFvrDBrVDb okfEaUH0kL6HOv96fZ/tgqXcjhagmV2zFnQ+LpVaWPg64mDlZK5r9FpXl I8RubhDRxatXh5lF3j5Wvdy0L0cLR1KhKAmn3c3lWBVj+m+hNjmekqC+m oQDfaYY2RUykDnyh4kpzykOXPP1G99lDum4LrVtRRJfa9uzaD15a9pw+u Q==; X-CSE-ConnectionGUID: bhfjyUv/ShyObNu4WsM4sA== X-CSE-MsgGUID: wkV5va8jQ3GSyAJ9VS3glw== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="46292947" X-IronPort-AV: E=Sophos;i="6.14,228,1736841600"; d="scan'208";a="46292947" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 21:22:57 -0800 X-CSE-ConnectionGUID: uQCtNXvCQgScJ20ODtNs2g== X-CSE-MsgGUID: ICLIhZsLTNe9wl/tXOqACw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,228,1736841600"; d="scan'208";a="119232155" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by fmviesa007.fm.intel.com with ESMTP; 06 Mar 2025 21:22:55 -0800 From: Raag Jadav To: lee@kernel.org, giometti@enneenne.com, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, raymond.tan@intel.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Raag Jadav Subject: [PATCH v3 2/5] gpio: elkhartlake: depend on MFD_INTEL_EHL_PSE_GPIO Date: Fri, 7 Mar 2025 10:52:28 +0530 Message-Id: <20250307052231.551737-3-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250307052231.551737-1-raag.jadav@intel.com> References: <20250307052231.551737-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Now that we have Intel MFD driver for PSE GPIO, depend on it. Signed-off-by: Raag Jadav --- drivers/gpio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 98b4d1633b25..232ef211ef38 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1372,7 +1372,7 @@ config HTC_EGPIO config GPIO_ELKHARTLAKE tristate "Intel Elkhart Lake PSE GPIO support" - depends on X86 || COMPILE_TEST + depends on (X86 || COMPILE_TEST) && MFD_INTEL_EHL_PSE_GPIO select GPIO_TANGIER help Select this option to enable GPIO support for Intel Elkhart Lake From patchwork Fri Mar 7 05:22:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 871352 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65AFF199235; Fri, 7 Mar 2025 05:23:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741324982; cv=none; b=VinMAnLFA62KB44OsIvomkN9H3yLA3MCK2atat58uck33GqCblIhrIbeZUzBuKLE070WS+fylKMDFk66yU7BKgnRqRGYnE4nVM3yxqoeH2si/uTfkc0Wr3c5PVppRf7yJSk2+ak0fR8fYnyRTsT/yruA4segRP/RWrHs5DEMYuc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741324982; c=relaxed/simple; bh=ly2+UQPrNEC+dhK+lw2hYNlNtYQJW3WWubbEtSJyOss=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HyW5CM1SMCztUXVt+sJevMSV9/qkPjXdLwP4lm6jorWDkNhIxP3hvgy95lYbsJ66MyoZnrkWdI97IMrW/n6SQqi6cr6Z9v+vDr5pBbFG4yL8/qqpNWJUHX2ZZDoA0cmfkzKHq5FF4XCTybHEWsBhesWNhnE/8TkRg74Swvw3MwY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gOBTSd0y; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gOBTSd0y" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741324980; x=1772860980; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ly2+UQPrNEC+dhK+lw2hYNlNtYQJW3WWubbEtSJyOss=; b=gOBTSd0yDW3eO0eJFVZMq04wGhSWwYOR4kcM9tRV2A8BTYvShWeATCNK InLxt0XGai+1HYTq+MI4FPWFFrK2GOJnsjnHqJQDgCZwNsWkMBIqb6Nw7 4KCzVMlT1ZLwTnS8Jk2vtpi9AjhQPPecU/XQ+T3dCGRpjwyrzxY+TgXqx eWWc/QzGnbqVNvF1mEbuztw/vwB2LFLJJ8kZgcJAXNtwi2hDfnfTr7s6z 5nhiZAj4taoc6p1akqnkETMy2zgDUaZZNbXGQoNjmA1Pox9K1vynWxInF sCJdmmQoMu9UcQ4lzOsd+15erI+3Aglp8qlmn22WaDsmdhYcV4fPDZ841 g==; X-CSE-ConnectionGUID: iMWFpdZSRiiWEoDY+QhrpQ== X-CSE-MsgGUID: 9sMEvpY+Q46A7hH9vQAx6g== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="46292951" X-IronPort-AV: E=Sophos;i="6.14,228,1736841600"; d="scan'208";a="46292951" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 21:23:00 -0800 X-CSE-ConnectionGUID: FFKrmnI2RIGY2kFG6XLzsQ== X-CSE-MsgGUID: LTKRDJU5RV6KvAn3IWb5lQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,228,1736841600"; d="scan'208";a="119232162" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by fmviesa007.fm.intel.com with ESMTP; 06 Mar 2025 21:22:57 -0800 From: Raag Jadav To: lee@kernel.org, giometti@enneenne.com, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, raymond.tan@intel.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Raag Jadav Subject: [PATCH v3 3/5] pps: generators: tio: split pps_gen_tio.h Date: Fri, 7 Mar 2025 10:52:29 +0530 Message-Id: <20250307052231.551737-4-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250307052231.551737-1-raag.jadav@intel.com> References: <20250307052231.551737-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Split macros and structure definition to header file for better maintainability. Signed-off-by: Raag Jadav Acked-by: Rodolfo Giometti Reviewed-by: Andy Shevchenko --- drivers/pps/generators/pps_gen_tio.c | 30 +---------------- drivers/pps/generators/pps_gen_tio.h | 49 ++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 29 deletions(-) create mode 100644 drivers/pps/generators/pps_gen_tio.h diff --git a/drivers/pps/generators/pps_gen_tio.c b/drivers/pps/generators/pps_gen_tio.c index 6c46b46c66cd..7f2aab1219af 100644 --- a/drivers/pps/generators/pps_gen_tio.c +++ b/drivers/pps/generators/pps_gen_tio.c @@ -5,8 +5,6 @@ * Copyright (C) 2024 Intel Corporation */ -#include -#include #include #include #include @@ -21,33 +19,7 @@ #include -#define TIOCTL 0x00 -#define TIOCOMPV 0x10 -#define TIOEC 0x30 - -/* Control Register */ -#define TIOCTL_EN BIT(0) -#define TIOCTL_DIR BIT(1) -#define TIOCTL_EP GENMASK(3, 2) -#define TIOCTL_EP_RISING_EDGE FIELD_PREP(TIOCTL_EP, 0) -#define TIOCTL_EP_FALLING_EDGE FIELD_PREP(TIOCTL_EP, 1) -#define TIOCTL_EP_TOGGLE_EDGE FIELD_PREP(TIOCTL_EP, 2) - -/* Safety time to set hrtimer early */ -#define SAFE_TIME_NS (10 * NSEC_PER_MSEC) - -#define MAGIC_CONST (NSEC_PER_SEC - SAFE_TIME_NS) -#define ART_HW_DELAY_CYCLES 2 - -struct pps_tio { - struct pps_gen_source_info gen_info; - struct pps_gen_device *pps_gen; - struct hrtimer timer; - void __iomem *base; - u32 prev_count; - spinlock_t lock; - struct device *dev; -}; +#include "pps_gen_tio.h" static inline u32 pps_tio_read(u32 offset, struct pps_tio *tio) { diff --git a/drivers/pps/generators/pps_gen_tio.h b/drivers/pps/generators/pps_gen_tio.h new file mode 100644 index 000000000000..5033d5efdf92 --- /dev/null +++ b/drivers/pps/generators/pps_gen_tio.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel PPS signal Generator Driver + * + * Copyright (C) 2025 Intel Corporation + */ + +#ifndef _PPS_GEN_TIO_H_ +#define _PPS_GEN_TIO_H_ + +#include +#include +#include +#include +#include +#include +#include + +struct device; + +#define TIOCTL 0x00 +#define TIOCOMPV 0x10 +#define TIOEC 0x30 + +/* Control Register */ +#define TIOCTL_EN BIT(0) +#define TIOCTL_DIR BIT(1) +#define TIOCTL_EP GENMASK(3, 2) +#define TIOCTL_EP_RISING_EDGE FIELD_PREP(TIOCTL_EP, 0) +#define TIOCTL_EP_FALLING_EDGE FIELD_PREP(TIOCTL_EP, 1) +#define TIOCTL_EP_TOGGLE_EDGE FIELD_PREP(TIOCTL_EP, 2) + +/* Safety time to set hrtimer early */ +#define SAFE_TIME_NS (10 * NSEC_PER_MSEC) + +#define MAGIC_CONST (NSEC_PER_SEC - SAFE_TIME_NS) +#define ART_HW_DELAY_CYCLES 2 + +struct pps_tio { + struct pps_gen_source_info gen_info; + struct pps_gen_device *pps_gen; + struct hrtimer timer; + void __iomem *base; + u32 prev_count; + spinlock_t lock; + struct device *dev; +}; + +#endif /* _PPS_GEN_TIO_H_ */ From patchwork Fri Mar 7 05:22:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 871993 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6190F19C566; Fri, 7 Mar 2025 05:23:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741324985; cv=none; b=Xy/WcEBJhV1vJM4ER4Xv+CGRb8W3853EQmy9jTR0cex3djBBa7FtZ0XqjCXMvwbr+y8KCl9jUMqK9kAt7ov1a9BhfmZqZOJPTuDDKdpPVQRZBDHR3fV9fhTaseGdCn+slJnvD3r84YejjbWbvGklRSIRgmnFc+BtcfQKCGhF0yM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741324985; c=relaxed/simple; bh=hFUryWsDI/x1+UyJwD1J1wtnUu6+KwV5oMs/3+d9nec=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fzDAxv3LrOKXkQtCQA1Vr5NH6ccXd5nv+Vd3whg2lJ+F1QPRzCPW6A0nKF/jOIQY3wy0MrzrFU6qwuJ8GgdoVj6XNLSTIw1LLth105qiscEVsePoVFudPUSTF2DbqbDR3W0ME+9R/S2nWo3t2QEArZveYis+BvcjGtITRaXAmHA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=BiOxcBQF; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="BiOxcBQF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741324983; x=1772860983; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hFUryWsDI/x1+UyJwD1J1wtnUu6+KwV5oMs/3+d9nec=; b=BiOxcBQFgFgm5C6YLeCCTRANp6Pawufr8vMNB1F0mCrLPIYnybEbLiih F6DhUwB4JRcQ99cYQs6S7jmdq5EagJvpA2y327qVf+51BwkyNS31+myD/ TZ2YydWQoiEWmb1BKmBNAXnbdu2uwOaJ3nZkV+cFnOMHIk8A/N9DgzHjd mD2iX0hDsC/JI5CBJOPkpU+GtiaKN6Qt7q3cR4T6nq2MRWqwJlLfWvEH3 kPXuFjlPkTLNo0Yz+rfrB2JYtW/IFnJrxFDj9iW4wdrH+QhjSzhaGs21/ mwWtRSR7qOnlwbqZiHksoqGEbTVEzYt9hmByG1rlS5AEZmcaW/vFlCp4T Q==; X-CSE-ConnectionGUID: 12Thrk1GTyumCSZQM1f+hw== X-CSE-MsgGUID: RQAkLRrcRRCOSyzpw2P/VA== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="46292956" X-IronPort-AV: E=Sophos;i="6.14,228,1736841600"; d="scan'208";a="46292956" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 21:23:03 -0800 X-CSE-ConnectionGUID: +TapA2RkSEObncd1Q65a0g== X-CSE-MsgGUID: OI9zxtdQRYyG57yj89qtJg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,228,1736841600"; d="scan'208";a="119232167" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by fmviesa007.fm.intel.com with ESMTP; 06 Mar 2025 21:23:00 -0800 From: Raag Jadav To: lee@kernel.org, giometti@enneenne.com, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, raymond.tan@intel.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Raag Jadav Subject: [PATCH v3 4/5] pps: generators: tio: move to match_data() model Date: Fri, 7 Mar 2025 10:52:30 +0530 Message-Id: <20250307052231.551737-5-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250307052231.551737-1-raag.jadav@intel.com> References: <20250307052231.551737-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use device_get_match_data() which allows configuring platform specific data like number of pins and MMIO registers for TIO. Signed-off-by: Raag Jadav Acked-by: Rodolfo Giometti Reviewed-by: Andy Shevchenko --- drivers/pps/generators/pps_gen_tio.c | 33 ++++++++++++++++++++-------- drivers/pps/generators/pps_gen_tio.h | 19 +++++++++++++--- 2 files changed, 40 insertions(+), 12 deletions(-) diff --git a/drivers/pps/generators/pps_gen_tio.c b/drivers/pps/generators/pps_gen_tio.c index 7f2aab1219af..6e3a4b198259 100644 --- a/drivers/pps/generators/pps_gen_tio.c +++ b/drivers/pps/generators/pps_gen_tio.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -28,7 +29,7 @@ static inline u32 pps_tio_read(u32 offset, struct pps_tio *tio) static inline void pps_ctl_write(u32 value, struct pps_tio *tio) { - writel(value, tio->base + TIOCTL); + writel(value, tio->base + tio->regs.ctl); } /* @@ -37,7 +38,7 @@ static inline void pps_ctl_write(u32 value, struct pps_tio *tio) */ static inline void pps_compv_write(u64 value, struct pps_tio *tio) { - hi_lo_writeq(value, tio->base + TIOCOMPV); + hi_lo_writeq(value, tio->base + tio->regs.compv); } static inline ktime_t first_event(struct pps_tio *tio) @@ -49,7 +50,7 @@ static u32 pps_tio_disable(struct pps_tio *tio) { u32 ctrl; - ctrl = pps_tio_read(TIOCTL, tio); + ctrl = pps_tio_read(tio->regs.ctl, tio); pps_compv_write(0, tio); ctrl &= ~TIOCTL_EN; @@ -63,7 +64,7 @@ static void pps_tio_enable(struct pps_tio *tio) { u32 ctrl; - ctrl = pps_tio_read(TIOCTL, tio); + ctrl = pps_tio_read(tio->regs.ctl, tio); ctrl |= TIOCTL_EN; pps_ctl_write(ctrl, tio); tio->pps_gen->enabled = true; @@ -112,7 +113,7 @@ static enum hrtimer_restart hrtimer_callback(struct hrtimer *timer) * Check if any event is missed. * If an event is missed, TIO will be disabled. */ - event_count = pps_tio_read(TIOEC, tio); + event_count = pps_tio_read(tio->regs.ec, tio); if (tio->prev_count && tio->prev_count == event_count) goto err; tio->prev_count = event_count; @@ -172,6 +173,7 @@ static int pps_tio_get_time(struct pps_gen_device *pps_gen, static int pps_gen_tio_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + const struct pps_tio_data *data; struct pps_tio *tio; if (!(cpu_feature_enabled(X86_FEATURE_TSC_KNOWN_FREQ) && @@ -184,6 +186,11 @@ static int pps_gen_tio_probe(struct platform_device *pdev) if (!tio) return -ENOMEM; + data = device_get_match_data(dev); + if (!data) + return -ENODEV; + + tio->regs = data->regs; tio->gen_info.use_system_clock = true; tio->gen_info.enable = pps_tio_gen_enable; tio->gen_info.get_time = pps_tio_get_time; @@ -216,11 +223,19 @@ static void pps_gen_tio_remove(struct platform_device *pdev) pps_gen_unregister_source(tio->pps_gen); } +static const struct pps_tio_data pmc_data = { + .regs = { + .ctl = TIOCTL_PMC, + .compv = TIOCOMPV_PMC, + .ec = TIOEC_PMC, + }, +}; + static const struct acpi_device_id intel_pmc_tio_acpi_match[] = { - { "INTC1021" }, - { "INTC1022" }, - { "INTC1023" }, - { "INTC1024" }, + { "INTC1021", (kernel_ulong_t)&pmc_data }, + { "INTC1022", (kernel_ulong_t)&pmc_data }, + { "INTC1023", (kernel_ulong_t)&pmc_data }, + { "INTC1024", (kernel_ulong_t)&pmc_data }, {} }; MODULE_DEVICE_TABLE(acpi, intel_pmc_tio_acpi_match); diff --git a/drivers/pps/generators/pps_gen_tio.h b/drivers/pps/generators/pps_gen_tio.h index 5033d5efdf92..4329b6dbd598 100644 --- a/drivers/pps/generators/pps_gen_tio.h +++ b/drivers/pps/generators/pps_gen_tio.h @@ -18,9 +18,10 @@ struct device; -#define TIOCTL 0x00 -#define TIOCOMPV 0x10 -#define TIOEC 0x30 +/* PMC Registers */ +#define TIOCTL_PMC 0x00 +#define TIOCOMPV_PMC 0x10 +#define TIOEC_PMC 0x30 /* Control Register */ #define TIOCTL_EN BIT(0) @@ -36,9 +37,21 @@ struct device; #define MAGIC_CONST (NSEC_PER_SEC - SAFE_TIME_NS) #define ART_HW_DELAY_CYCLES 2 +struct pps_tio_regs { + u32 ctl; + u32 compv; + u32 ec; +}; + +struct pps_tio_data { + struct pps_tio_regs regs; + u32 num_pins; +}; + struct pps_tio { struct pps_gen_source_info gen_info; struct pps_gen_device *pps_gen; + struct pps_tio_regs regs; struct hrtimer timer; void __iomem *base; u32 prev_count; From patchwork Fri Mar 7 05:22:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 871351 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B0CC193409; Fri, 7 Mar 2025 05:23:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741324988; cv=none; b=E39zaF959JxeSG98CeIaMbaatmP/Xwk+zKBDxCRz1hSbfaiP/PdSG/ahLfNUVY8i7wMGaDb1JKWeO8/MrFMVCbIcy9+quwg+6FGD1Rzi1u1MaNQJKnDXaln3PPM1GoRoOMYnw7KHC/LCELvCVZ197FopE1Xe87nZ6vA6jPiifW4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741324988; c=relaxed/simple; bh=yRACNcqql97q+efeIS5QfsCUY4jQh++OfyCum2WBK0A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gsdqTSkv9WZn+Zd/t2Bpwl92qsjbCQ8CuzYSLi5vpXByYCjrjy5V9J6bHZK01sz+aMXBlEzeBp6ilYuj+ZDq8CFaCXCYjGjL8sRaZC2LPjxxG995KMnNrO1jVWcsVfgzmztasU9/nH+Va7ZX54xwAetC9XPfHV6wi9WxppEkP70= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MtSl7cvB; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MtSl7cvB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741324986; x=1772860986; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yRACNcqql97q+efeIS5QfsCUY4jQh++OfyCum2WBK0A=; b=MtSl7cvBmnE7tV3sO950CtfBBq/JpZE9OMRT26ngrw7MYJKcgzzQCoG3 HkBGFmbN4xuphKfaUNy5Kla9wzKOXuRcpHjBjkgIzwY3aQj2R2QGMSafT tz4c8oW9I+D5yjA4ny5NxbtpPRE4Yw6qMp73htkNtSOjzFknRmnohG9fw cJQA0CdYwIgd2fi4/D90/iWry89JgR0JcbVlmDNleKfl1eSvvXZtB9g+n 5HUy8QqUo9WHheJnhA/gwOyH0r0kSA6cxx1mx/7nSuGWgI3qnFm2b210x JCcUiMDw6GlHeX3WSUIeWVUhjpvkImyXLgZRUs0PXIODxqPhiI+oe0v0u Q==; X-CSE-ConnectionGUID: ZSATlldmSw65pA8XP8pjGg== X-CSE-MsgGUID: CDGAnqwbR6eMAdc06XZAfg== X-IronPort-AV: E=McAfee;i="6700,10204,11365"; a="46292963" X-IronPort-AV: E=Sophos;i="6.14,228,1736841600"; d="scan'208";a="46292963" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2025 21:23:06 -0800 X-CSE-ConnectionGUID: KFZj6rGqS0+RorPTls+kaQ== X-CSE-MsgGUID: wh4osHZlSeaf1+qOrRfr4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,228,1736841600"; d="scan'208";a="119232193" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by fmviesa007.fm.intel.com with ESMTP; 06 Mar 2025 21:23:03 -0800 From: Raag Jadav To: lee@kernel.org, giometti@enneenne.com, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, raymond.tan@intel.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Raag Jadav Subject: [PATCH v3 5/5] pps: generators: tio: Introduce Intel Elkhart Lake PSE TIO Date: Fri, 7 Mar 2025 10:52:31 +0530 Message-Id: <20250307052231.551737-6-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250307052231.551737-1-raag.jadav@intel.com> References: <20250307052231.551737-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add initial support for Intel Elkhart Lake PSE TIO controller. Signed-off-by: Raag Jadav Acked-by: Rodolfo Giometti Reviewed-by: Andy Shevchenko --- drivers/pps/generators/Kconfig | 2 +- drivers/pps/generators/pps_gen_tio.c | 17 ++++++++++++++++- drivers/pps/generators/pps_gen_tio.h | 5 +++++ 3 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/pps/generators/Kconfig b/drivers/pps/generators/Kconfig index b3f340ed3163..83aada693ad2 100644 --- a/drivers/pps/generators/Kconfig +++ b/drivers/pps/generators/Kconfig @@ -33,7 +33,7 @@ config PPS_GENERATOR_PARPORT config PPS_GENERATOR_TIO tristate "TIO PPS signal generator" - depends on X86 && CPU_SUP_INTEL + depends on X86 && CPU_SUP_INTEL && MFD_INTEL_EHL_PSE_GPIO help If you say yes here you get support for a PPS TIO signal generator which generates a pulse at a prescribed time based on the system clock. diff --git a/drivers/pps/generators/pps_gen_tio.c b/drivers/pps/generators/pps_gen_tio.c index 6e3a4b198259..a2a23cdc2568 100644 --- a/drivers/pps/generators/pps_gen_tio.c +++ b/drivers/pps/generators/pps_gen_tio.c @@ -231,6 +231,14 @@ static const struct pps_tio_data pmc_data = { }, }; +static const struct pps_tio_data ehl_pse_data = { + .regs = { + .ctl = TIOCTL_PSE, + .compv = TIOCOMPV_PSE, + .ec = TIOEC_PSE, + }, +}; + static const struct acpi_device_id intel_pmc_tio_acpi_match[] = { { "INTC1021", (kernel_ulong_t)&pmc_data }, { "INTC1022", (kernel_ulong_t)&pmc_data }, @@ -240,9 +248,16 @@ static const struct acpi_device_id intel_pmc_tio_acpi_match[] = { }; MODULE_DEVICE_TABLE(acpi, intel_pmc_tio_acpi_match); +static const struct platform_device_id pps_gen_tio_ids[] = { + { "pps-gen-tio", (kernel_ulong_t)&ehl_pse_data }, + { } +}; +MODULE_DEVICE_TABLE(platform, pps_gen_tio_ids); + static struct platform_driver pps_gen_tio_driver = { .probe = pps_gen_tio_probe, .remove = pps_gen_tio_remove, + .id_table = pps_gen_tio_ids, .driver = { .name = "intel-pps-gen-tio", .acpi_match_table = intel_pmc_tio_acpi_match, @@ -255,5 +270,5 @@ MODULE_AUTHOR("Lakshmi Sowjanya D "); MODULE_AUTHOR("Pandith N "); MODULE_AUTHOR("Thejesh Reddy T R "); MODULE_AUTHOR("Subramanian Mohan "); -MODULE_DESCRIPTION("Intel PMC Time-Aware IO Generator Driver"); +MODULE_DESCRIPTION("Intel Time-Aware IO Generator Driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/pps/generators/pps_gen_tio.h b/drivers/pps/generators/pps_gen_tio.h index 4329b6dbd598..509bd2633dfb 100644 --- a/drivers/pps/generators/pps_gen_tio.h +++ b/drivers/pps/generators/pps_gen_tio.h @@ -18,6 +18,11 @@ struct device; +/* EHL PSE Registers */ +#define TIOCTL_PSE 0x00 +#define TIOCOMPV_PSE 0x04 +#define TIOEC_PSE 0x24 + /* PMC Registers */ #define TIOCTL_PMC 0x00 #define TIOCOMPV_PMC 0x10