From patchwork Mon Mar 10 14:52:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 872338 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A00322D790 for ; Mon, 10 Mar 2025 14:52:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618361; cv=none; b=Npm6YZFoKG7CNFpa4eeae9iVkHwY4paern8L7z+MRHpUPXzOIv3LtDFe8NRWlI2CEFUIlpAORdeO0BAQ5CFB1EvaevnETkfiANAhKZpG9XSJhXRjjosPGQPNzQlX0Nzyy8bWrOwzGNet42B3n4xj86ug3Z+pJhAq/WL5yTF38kw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618361; c=relaxed/simple; bh=DjlSjyKZg5L1RJtFrw9Awsbe+InTSaQHdJt80sHp1pA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sb/PnSysuBAYGza7NrTskLSPNthQ1oJf6tNZBZQSuOcw4De87y1Tw8dODc7mfA2fe7HGu5tmEjG2162JYBKzSmvKL2owV4dNSiUh2Du4Ex5o7l8oSdIn5irGxh8RQeCe0ve23aoVvTln8epv8NbD5ix+ecpk3z8KhsGNwu6RlAU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=fpB+ZLEG; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="fpB+ZLEG" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-224019ad9edso99084365ad.1 for ; Mon, 10 Mar 2025 07:52:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741618358; x=1742223158; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kHEXIimjUTXAyC0fOzh8XAkym19Q72QcmDI6hc+cq4k=; b=fpB+ZLEGGOr4HB1489JPrDqL88yR4qlhADmJ5wM0+L0MyptC5pY5oC6/0Wxm5lFI20 F1wpaZLQpsV5dGmdI0JwDL8/6rhwvenzHT+/6E+ntF/4Hy7/AkPqjjYwxQ80BGfp8Bhx fYWDPd+QRQwPq/LVuWC0p4Os/OVHNnHVk7k1cOHtsDsdIm8OIVUdi0orf+oWwYi48xJS 0mWMd2QFO98Yk6JHt/hmWniv92TPVN51o4KC+0uorSmlU3UB6YJuKH6QBif9RRA/A1cx 8RAAkElNPNwwOG5AhaYIRyNPqC6lh38HLwqu9npFfAHL0cMJnp6gOuZ+NjyzntEe4nTF 4J6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741618358; x=1742223158; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kHEXIimjUTXAyC0fOzh8XAkym19Q72QcmDI6hc+cq4k=; b=jZ1jsVxl43L1udPRWIaseN/9c+mJhirfklDoKvxc7xLIGg1OPlGk1P5yZHKSfLoAbJ xOcXk+r2hLYDRDpFTUSG83oqAvJ15q8ALubJPbdUJVxKl+k70hNW4tmieWcUhMWZEHcF OjRgYHWzFO2mghhzfyKP3QHJ7K/5i72t6kPWSCr8+MsKMZKaNlg/Mom0Ldtu1HvS+R26 LFZGqn51ZhTDmXbI2dKt+XNueyRg087uf6/I2gGWoBk4gHajwqb0QcJvk5lommM+Rz9n nxdS3pJIm+SVXhFhwKBg6Cvh53va0TPKmrElOxzELMTWddUxABo+Xc+zQcXSIOxNLc9I IonQ== X-Forwarded-Encrypted: i=1; AJvYcCVw9r+4MqS8kpgUK3/1A29dV+Gat5N8eHAKtuu/vaYKng+fkUas/FrJ8oKWsV78pzlXAl8dKv9cBf2tGhfuV5U=@vger.kernel.org X-Gm-Message-State: AOJu0YwOVH0LMnzO3uPPJONw8h46fP8iql+UxoKrmour9FqjtI81x1i0 da3b/vLsO0qcJqp33PG3mT7dqOH67Vly76vyjkqpMpGGWYsmpCJbQmcrc792oLY= X-Gm-Gg: ASbGnctPh1N16XLsKWk3TtoQDe3wBS6IaWzi9OMR+Jlu8nuCKgtL0TKNO4PfChGDiis BtWZOFJFVZTZIDrEE12S4j4kW3s9XUdghGUIAsKSy4j0/Tp8AVkbYnAd1pzJFeN8nSf1fbE2pC3 w96985jAAYs8vkwFO/c46jU5jXxQTm/irESkq9dm3g2vOURu6ZG7qPOFvWr062lc/HckaJ60inY fGTgd9xRIdXhzhA3wYbtbaiq+bD7Rk+yLZkhtkPFutWgr6hN6Gveu5Vh1ylrCCjWpPGqQds0+Mm eidj07FksqXwdAz6Z+jlE6LE19mUEqRYa62FmClHF97ldAwujaDxu88= X-Google-Smtp-Source: AGHT+IHtkwbPi3YsMJ6A8ZQyEy1VJS3fRxtZo4fUkREMtAJmz9IifioPXZ2s22L3uz4hyDnWUTIX/g== X-Received: by 2002:a05:6a21:2d08:b0:1ee:d687:c39b with SMTP id adf61e73a8af0-1f544c37a63mr24132640637.7.1741618357489; Mon, 10 Mar 2025 07:52:37 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736d11d4600sm2890275b3a.116.2025.03.10.07.52.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Mar 2025 07:52:37 -0700 (PDT) From: Deepak Gupta Date: Mon, 10 Mar 2025 07:52:24 -0700 Subject: [PATCH v11 02/27] dt-bindings: riscv: zicfilp and zicfiss in dt-bindings (extensions.yaml) Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250310-v5_user_cfi_series-v11-2-86b36cbfb910@rivosinc.com> References: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> In-Reply-To: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 Make an entry for cfi extensions in extensions.yaml. Signed-off-by: Deepak Gupta Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/riscv/extensions.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index a63b994e0763..9b9024dbc8d2 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -426,6 +426,20 @@ properties: The standard Zicboz extension for cache-block zeroing as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + - const: zicfilp + description: | + The standard Zicfilp extension for enforcing forward edge + control-flow integrity as ratified in commit 3f8e450 ("merge + pull request #227 from ved-rivos/0709") of riscv-cfi + github repo. + + - const: zicfiss + description: | + The standard Zicfiss extension for enforcing backward edge + control-flow integrity as ratified in commit 3f8e450 ("merge + pull request #227 from ved-rivos/0709") of riscv-cfi + github repo. + - const: zicntr description: The standard Zicntr extension for base counters and timers, as From patchwork Mon Mar 10 14:52:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 872337 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 219D122D7BD for ; Mon, 10 Mar 2025 14:52:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618366; cv=none; b=pu9DE9oUtwILNfZ74rrg6u6GxAhxjrNmZnkrICRF2vMDWltk/S+D6b+beoCPl6M2uy5ZWRVMEjX0a1wm5P6lnu7QGKQ0GEvNGz6am/aD/LLsE4Wk8yTSW1yJgYmTuaqQgUREayITt0uQ5lXgUJvC+xK1iwviCT7juGkx4m64StM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618366; c=relaxed/simple; bh=f+s1qRILk5w2zoTzbSGEFuSk9CM1mNXrrF3BbhojAEc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=M55FBo/5wHlyoeY6ED+uUQ1CUnbGEzkzSSdmrZPjyDMph1pYVamoBifCSZ2hsA2gReoKq/VPLxIi2bXxZIpLBTIIjZdC4V656XMYcC1ZgKjoea9YXLLIgc5uVhoEZBj7oYOAAtAaXLMhWhj0KsNPmu/cdevtCs84j/vx1EQKMCQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=EydyJ0Bp; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="EydyJ0Bp" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-22355618fd9so78425105ad.3 for ; Mon, 10 Mar 2025 07:52:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741618362; x=1742223162; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=n3DM8zy+WllPP0TujEXFZ0Ycc0zGrpNRrMRWPkPmGZc=; b=EydyJ0BpriCvs2qPsub39795edQPTmKCu8O/B5RPJ2VjhMQbBwGyf6jq0uvq53HTCW WRaxFAFaGjW4k0qSvC2Yjp0AnrYP3DQmtvZo1gcp0sH43DC3wwlYj33e/XhfKTlrrSkj yRxeSqP5c98EfTLk9y7Or+5sq4xzgJebDPwitoM3VRx3tCUYbaxqrEjf85/2OAXR1rQp z+v4zwakubW62pee6309vt/IY07dxbb9dJ0h+ooMzyKB3NlVlHVcf61RTyOsSLkqB38c TbWLbveGzTPnj6b+3VOKwf0UwCG3+uHNrvdXnbzMuyr3B3Y+dn52A5RigiexhFCFhWRE GEWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741618362; x=1742223162; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n3DM8zy+WllPP0TujEXFZ0Ycc0zGrpNRrMRWPkPmGZc=; b=I4+2MAtpIv54HJlLrw1Kkb0Xa6LBklUPSkhsq+1pei5h46FQ5yC93GCuuanlXqEZEN K28zWuOqgpCbw8QQp9XY9lGYkhg6IdvrjOCfrT10piy8BzMiQ9pDwomjph0PKiQiUOLZ a1XbZGEnajf+6HWcUGLXcTu1bBcLedy+4n/thj3idImzVDHwQwNPb/oLjONpBD9VdZg6 a5wuNgbZq8+H/P/rpOdg7ecIZjhDI6FAyPx5xFToLLip0V9yeoyqaDgjtTZJpXnPBnnO 01G4VHP+Sme0gxbS/7PPZiibzlSBt8S1wFkCf8NHvyVLzsCmXcHDINgQNuIrnkDYBchu +phA== X-Forwarded-Encrypted: i=1; AJvYcCXW6XZgW85we4EiOjtu1je5FqDs9TgCYcLvv1brLOwXgjqU+Xg00xhQUUF2WJiDnFuM2R+CoWmEjyNv2zrNV8Y=@vger.kernel.org X-Gm-Message-State: AOJu0YxzbLbrj/cj0tNN9SwRDFRDWPIkg/1fyTMmG2LFva6WjgEMA31C N2N7puGOg8ElkMBgk+9lsmaPI2ocRvBrYySqlXDAfaa4XFVgk3IBYrSFA69zk9U= X-Gm-Gg: ASbGncsuwsGc5hHP0fpgl/bvg1kCsU4LULxQ0uQUL1CRBJCCrk2hYBMVhxBmPAoDsNI n4JYJxN5t/gV1iEpaKyDAGWFnrucenAdEC6LP6hG5n2FP4UvlWvy9dYFd2w5UHaSW0KQ7Ch6fLf hCMxXBdX0Yo5uDDg5c1yhbLUF3fy8jRS1gdkn4tTHPL2AeGprPRZ8B4EvvnZlfLg/ebh6d/ga0h 7vgqrcIlyaXGMveH3il0mut6+yUbjVc3k7hKHgQMsM/EwO3yOJoM1cGJjba10m2DxrhgUhzY2N1 RpUY07kmHm/97Mm6s+bgbQCp5exV5hoe8UukRx/gEz2OIRFfsRVJFqM= X-Google-Smtp-Source: AGHT+IHEgbV38+kdB/KuKTC/ngiL6naw+4KBErVaQq0wSwONUo1ce4xmBDTiHE9RxDA/IFBRpdqZjA== X-Received: by 2002:a05:6a21:1fc5:b0:1f5:6878:1a43 with SMTP id adf61e73a8af0-1f58cb239e0mr144294637.14.1741618362407; Mon, 10 Mar 2025 07:52:42 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736d11d4600sm2890275b3a.116.2025.03.10.07.52.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Mar 2025 07:52:42 -0700 (PDT) From: Deepak Gupta Date: Mon, 10 Mar 2025 07:52:26 -0700 Subject: [PATCH v11 04/27] riscv: zicfiss / zicfilp extension csr and bit definitions Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250310-v5_user_cfi_series-v11-4-86b36cbfb910@rivosinc.com> References: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> In-Reply-To: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 zicfiss and zicfilp extension gets enabled via b3 and b2 in *envcfg CSR. menvcfg controls enabling for S/HS mode. henvcfg control enabling for VS while senvcfg controls enabling for U/VU mode. zicfilp extension extends *status CSR to hold `expected landing pad` bit. A trap or interrupt can occur between an indirect jmp/call and target instr. `expected landing pad` bit from CPU is recorded into xstatus CSR so that when supervisor performs xret, `expected landing pad` state of CPU can be restored. zicfiss adds one new CSR - CSR_SSP: CSR_SSP contains current shadow stack pointer. Signed-off-by: Deepak Gupta Reviewed-by: Charlie Jenkins --- arch/riscv/include/asm/csr.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 6fed42e37705..2f49b9663640 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -18,6 +18,15 @@ #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ +/* zicfilp landing pad status bit */ +#define SR_SPELP _AC(0x00800000, UL) +#define SR_MPELP _AC(0x020000000000, UL) +#ifdef CONFIG_RISCV_M_MODE +#define SR_ELP SR_MPELP +#else +#define SR_ELP SR_SPELP +#endif + #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ #define SR_FS_OFF _AC(0x00000000, UL) #define SR_FS_INITIAL _AC(0x00002000, UL) @@ -212,6 +221,8 @@ #define ENVCFG_PMM_PMLEN_16 (_AC(0x3, ULL) << 32) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) +#define ENVCFG_LPE (_AC(1, UL) << 2) +#define ENVCFG_SSE (_AC(1, UL) << 3) #define ENVCFG_CBIE_SHIFT 4 #define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT) #define ENVCFG_CBIE_ILL _AC(0x0, UL) @@ -230,6 +241,11 @@ #define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT) #define SMSTATEEN0_SSTATEEN0_SHIFT 63 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) +/* + * zicfiss user mode csr + * CSR_SSP holds current shadow stack pointer. + */ +#define CSR_SSP 0x011 /* mseccfg bits */ #define MSECCFG_PMM ENVCFG_PMM From patchwork Mon Mar 10 14:52:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 872336 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC83B22D4DA for ; Mon, 10 Mar 2025 14:52:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618370; cv=none; b=lbdj0NouhO5CAwaTgWCvsMVDk+ta/n5ABc5SNggR79qdoPI/ngKJkc1NMmnt+Hca5c0iphBCk4gRcl+C5zPY9Hd5cpdSFSlSQGVrAnIl8E5mL2TRTiGVU/B7VlipbbJ30XAaHWn64OIydixp0IOLNVDHkFJ+fd/IbXYcQoXvaHo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618370; c=relaxed/simple; bh=toOY3g5UWbhyzFvpokgMbtCDrGwGLK+0MjdImo2Zc6U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DabaMDGbQJCuN99T7qvNQeXWWMCVsHFufc9CU5FkGv22LeD6Z0RbCc+MMmwf2rJ/seh5k8WZBKMf7Y/dFRDa4649W46A5i2faQZd8TwGmqz5/5PIf8VDNQD+xrErcXKJxcukoq3H+M52TgRy3KqF8+arEsGgxCqdyQ+IyHX+9U4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=rtfYbo3Z; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="rtfYbo3Z" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-22185cddbffso95162195ad.1 for ; Mon, 10 Mar 2025 07:52:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741618367; x=1742223167; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1e5RgGuqZS+AKw5oTSgp47pWFJ0GDjWFc7jT6Xd5TJc=; b=rtfYbo3ZMjS4PdVSBQWDC5p1T/pOIaBfq2YNoEcmO+YC3yhQju2V7Wv5bK3jDzEvg7 +01FCieRoO3iF3j6f2LHLI0vWsHhLx2KvLmAdbP92ODPXlinr7YWaA552N+Q/5+TAPpa FBMoqoXB0nsWfPPuMsTJy5K8a27BladbspWBE0hxSAZM1Qc7l+qhBs74elmn1DjtjIWU XuKNKYd9W/n+9wROB6XefLQn5ZxAN7bJ9tL1P0qFZala1O3/np9QFBOsbkZoE28ZrFZl s5VYRl1O5pGDjY80G7asnJZoWi0/M7tKewGDOElmXBC9mz6H609keBZc2yy/1MoRkCUh 7ViQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741618367; x=1742223167; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1e5RgGuqZS+AKw5oTSgp47pWFJ0GDjWFc7jT6Xd5TJc=; b=dNtGX8oNvd6/0t8fyF4UDi3+JUKprntXx+ODOEeq27+QiAOI1fhJ/RpXV0IqVbF9Db 74CGO28Y0JDgDF161Mj/Xaxaja32Ces9wYJVwB0mmNYocCAC+P3UlUCmSrWGdiZU3k6t YfyUZaWAp2QG9RVP8rANQobxwf2raPzntNriJRkqjgTeRBWpgakxVODLWb5AiRLoRnne n0CMpzrcqK7lHPExdisYy6Tqi798bAhEXHFc57h0582XqfeITdq7feB7RwyiNB/UMS+O zWsy4PMNsu9r2vq/S8ca1axteNUwFJ0oc3VEpsQlsdOOKSvJsKZQWOpxTNIt8P2tZ4C5 aeEA== X-Forwarded-Encrypted: i=1; AJvYcCV9REvNkuN4xshQlUXLD2T/RRnSZzDrsIDRZ90my1f/Hr0vn6MZpX/Fe56bihAnQmbxSI8XhOqj+gLJnQGJcqk=@vger.kernel.org X-Gm-Message-State: AOJu0Yy2qAxF6U3KkS8h0qESp+ZlqeHp+6Dz+cCH7HRxdUjYXBZ92a1y wdbRdqgwvsvaT2UeXgJCSTQQGSifyR+uqR862clZvxj7HxLlQ+a11ljSt5sKk9I= X-Gm-Gg: ASbGnctXfii7CcYCsE81hlea3K+yySYw7V6qqBfgUFl4t11gM6WwkFOEUbUXQKJLg8L 2Lt1L80TDpiFTROjX/b79tDcVNlSc9sT49n9WfH8Aavbl8dQ+mvj7arsa4fTGi9f/wu8AIa2WJJ hb8UHl5CX/FaDV6L3ICeR42u1UWMk0m4SDFtArbsUTpUDhlcReaRjqcmZZNEronOCbRiPk93Ylq zspZ1InoFG+BpbQwPMTYeHJ/H19RJtL0uPAIIdYfwNfuqa1U5vAjjfwHAVdpQlGG92apazNRmsw vIpqEgujTmeQmKH6prGbRtyl4co7DSEJIqfWKR7s/REN/Lmrl4MfEk0= X-Google-Smtp-Source: AGHT+IGncZQFemH+Tqb/7Cg0gaGakZGYufPeZUJHTPz51xcsHifa9ayQ0v/V99iUl8be0Qgt8Ur5MQ== X-Received: by 2002:a05:6a00:8506:b0:727:39a4:30cc with SMTP id d2e1a72fcca58-736bbf433d9mr12618993b3a.1.1741618367246; Mon, 10 Mar 2025 07:52:47 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736d11d4600sm2890275b3a.116.2025.03.10.07.52.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Mar 2025 07:52:46 -0700 (PDT) From: Deepak Gupta Date: Mon, 10 Mar 2025 07:52:28 -0700 Subject: [PATCH v11 06/27] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250310-v5_user_cfi_series-v11-6-86b36cbfb910@rivosinc.com> References: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> In-Reply-To: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 `arch_calc_vm_prot_bits` is implemented on risc-v to return VM_READ | VM_WRITE if PROT_WRITE is specified. Similarly `riscv_sys_mmap` is updated to convert all incoming PROT_WRITE to (PROT_WRITE | PROT_READ). This is to make sure that any existing apps using PROT_WRITE still work. Earlier `protection_map[VM_WRITE]` used to pick read-write PTE encodings. Now `protection_map[VM_WRITE]` will always pick PAGE_SHADOWSTACK PTE encodings for shadow stack. Above changes ensure that existing apps continue to work because underneath kernel will be picking `protection_map[VM_WRITE|VM_READ]` PTE encodings. Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/mman.h | 25 +++++++++++++++++++++++++ arch/riscv/include/asm/pgtable.h | 1 + arch/riscv/kernel/sys_riscv.c | 10 ++++++++++ arch/riscv/mm/init.c | 2 +- 4 files changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/mman.h b/arch/riscv/include/asm/mman.h new file mode 100644 index 000000000000..392c9c2d2e78 --- /dev/null +++ b/arch/riscv/include/asm/mman.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MMAN_H__ +#define __ASM_MMAN_H__ + +#include +#include +#include + +static inline unsigned long arch_calc_vm_prot_bits(unsigned long prot, + unsigned long pkey __always_unused) +{ + unsigned long ret = 0; + + /* + * If PROT_WRITE was specified, force it to VM_READ | VM_WRITE. + * Only VM_WRITE means shadow stack. + */ + if (prot & PROT_WRITE) + ret = (VM_READ | VM_WRITE); + return ret; +} + +#define arch_calc_vm_prot_bits(prot, pkey) arch_calc_vm_prot_bits(prot, pkey) + +#endif /* ! __ASM_MMAN_H__ */ diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 050fdc49b5ad..8c528cd7347a 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -178,6 +178,7 @@ extern struct pt_alloc_ops pt_ops __meminitdata; #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ _PAGE_EXEC | _PAGE_WRITE) +#define PAGE_SHADOWSTACK __pgprot(_PAGE_BASE | _PAGE_WRITE) #define PAGE_COPY PAGE_READ #define PAGE_COPY_EXEC PAGE_READ_EXEC diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index d77afe05578f..43a448bf254b 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -7,6 +7,7 @@ #include #include +#include static long riscv_sys_mmap(unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, @@ -16,6 +17,15 @@ static long riscv_sys_mmap(unsigned long addr, unsigned long len, if (unlikely(offset & (~PAGE_MASK >> page_shift_offset))) return -EINVAL; + /* + * If PROT_WRITE is specified then extend that to PROT_READ + * protection_map[VM_WRITE] is now going to select shadow stack encodings. + * So specifying PROT_WRITE actually should select protection_map [VM_WRITE | VM_READ] + * If user wants to create shadow stack then they should use `map_shadow_stack` syscall. + */ + if (unlikely((prot & PROT_WRITE) && !(prot & PROT_READ))) + prot |= PROT_READ; + return ksys_mmap_pgoff(addr, len, prot, flags, fd, offset >> (PAGE_SHIFT - page_shift_offset)); } diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 15b2eda4c364..9d6661638d0b 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -342,7 +342,7 @@ pgd_t early_pg_dir[PTRS_PER_PGD] __initdata __aligned(PAGE_SIZE); static const pgprot_t protection_map[16] = { [VM_NONE] = PAGE_NONE, [VM_READ] = PAGE_READ, - [VM_WRITE] = PAGE_COPY, + [VM_WRITE] = PAGE_SHADOWSTACK, [VM_WRITE | VM_READ] = PAGE_COPY, [VM_EXEC] = PAGE_EXEC, [VM_EXEC | VM_READ] = PAGE_READ_EXEC, From patchwork Mon Mar 10 14:52:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 872335 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2CBF2309B1 for ; Mon, 10 Mar 2025 14:52:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618375; cv=none; b=LW8fF/57jaI1PSxYz4QTt6DPvWzuzRqfV7b30dxcCRWPxmzI9ILavFUVLOb2qSPzph0agS0KOPqofDA7+WQ8q6YTHNgrTLJkPII4hlaoU5XfKTGYqyV9cTU1W+bQwgE5psdTsoHt1j31uylat7CAjVQfEC0feGWcodoN1kk6i8k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618375; c=relaxed/simple; bh=HOQqOSPO+MhBbccjb2UbKqhOT3MYkxspDNQyPTpGYhw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FXP34mmY3LhTlBNYXtuobmt2uWkXR6qGB/JK/1PrMxzUSY6BrvwaNZnii+bmf2hn4PsnzhCvQFKc5kbGX/rPvpV8B4MxQLOnHjGQzizKODudaAH4uMhLeVwDrVbYWKqT0ar7XmhL7sXNU2tQiFFrqcs+wbTEyPHmx1SBhzf7q1Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=Hx4U+qGs; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="Hx4U+qGs" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-22398e09e39so78269255ad.3 for ; Mon, 10 Mar 2025 07:52:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741618372; x=1742223172; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=WPde6NcIQ47rHbegQG8dPMP+orPth983zEAPX8ktkAY=; b=Hx4U+qGs9S6hqwXpS5iUSJGfoCj/H/Z2V37VGzS1jtYLjJ9Od9PdFoyeMKbfw8hB+A OylLH/zZLAYT7hAp2IKTnQfwYK/TU5Mg0N93bgKBl24PVn8Agn6YYZnpamFwYsLSXoTw +2d09hyxqQlZVx7gvxJAKZya1LORRFpS0Nl8WN9oQHIpJjGoRBPMpY3Mt1IaamowcCBu DdFkAfLXjr+9dikeulp7CLiDbkjs8yiWh+CK6SQjZoBzpDyHwxbohMqq+cwMK/158zJZ upRS1TC2lCXZd0ZYgl0ApPGe6FbmvTdHLDfhzlcM63pWopY5ykHE4RoJF1DH2YZjPQdj /wiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741618372; x=1742223172; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WPde6NcIQ47rHbegQG8dPMP+orPth983zEAPX8ktkAY=; b=eAg54+zYyqMiFuphesT5L7H1nuiGjP6BnVY2IVt7XJhNQ6wXRHKEhRrzp6ujtyKTiX Dd+ugfK0HxRkO/dQkJvvxNaq1PsKfYSvFP6tK0h3C7pfE1MdZYwLtF7xcPhNkjZBezZ3 FoL38IBadEY5Fl6wvSvqqNK4L8rgaCuFVnWKXYli4sqbo4ev9mAhiZf+PYdudf/KijqC dlPxPJd2Lj9xhSbQ9k4PQFWaD4cEykcANQpOnjSm1nSGIn1x84vPII7NXbrJyGZ/DuAL shRrCnXndjFMI7VAl+bB8xf3sV1m51cNmpduj/RgO33WVEqGQJDaYcnIA8j4g/nKxkip LNIw== X-Forwarded-Encrypted: i=1; AJvYcCWDpx+CeKnjNtREMWgBUBPyT/u53x91YhsXb78BiV0OSvLSJn3KBexkxPAEBdGG23ikArjXq9evXSacWCMldKg=@vger.kernel.org X-Gm-Message-State: AOJu0YzNwDkICmepPWQAyN2E5aIUzpADak3xgB7ba8E5x5OD1Zd1ondP XYHk+dfsX7xLlaUVZqKc9CH9IzRoZFgLOWZdW889GTz9oXKwTrANMTtGm7wZtK4= X-Gm-Gg: ASbGnctivdZeIgi8mT1DKVtVyDFF4HhCargBBNcA/zZAHPrtM1JVjgbhgYgP+gYhmvM VeqU9saSoBGluOpDKAtI1Hb0mUQ/17tfvf10vGSxeRuibPgVsV7jRM9Cm2N0I93GCxkEtxBus75 N2pJNi0prDyUM0pN28Bqo0CPXtYDPdbTbqmwdZ4mJGGeZFqCkbJEbK0WCMifblBh405erIWQ79d BB/+8+GstN7AF8Dwlpj+b8bYdSYlUOyc23gg+ps3a8KaNtOEjUbsc0/EosTunHcu14OTGkXa3Me k8w8knlk1/E+SyR3ejUM9VqhWOfKnI2l2NG3bmB82gVuuDKqVL3YGjk= X-Google-Smtp-Source: AGHT+IFqTxU+p9IhkI8RGdvHdyJEHoK+vlH5JWBOUOv0UhGLOT20CpZOV0dtGMVo/7iEBeBe/MTApw== X-Received: by 2002:a05:6a00:928b:b0:736:4d44:8b77 with SMTP id d2e1a72fcca58-736aaa1cf9fmr27006391b3a.8.1741618372105; Mon, 10 Mar 2025 07:52:52 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736d11d4600sm2890275b3a.116.2025.03.10.07.52.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Mar 2025 07:52:51 -0700 (PDT) From: Deepak Gupta Date: Mon, 10 Mar 2025 07:52:30 -0700 Subject: [PATCH v11 08/27] riscv mmu: teach pte_mkwrite to manufacture shadow stack PTEs Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250310-v5_user_cfi_series-v11-8-86b36cbfb910@rivosinc.com> References: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> In-Reply-To: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 pte_mkwrite creates PTEs with WRITE encodings for underlying arch. Underlying arch can have two types of writeable mappings. One that can be written using regular store instructions. Another one that can only be written using specialized store instructions (like shadow stack stores). pte_mkwrite can select write PTE encoding based on VMA range (i.e. VM_SHADOW_STACK) Signed-off-by: Deepak Gupta Reviewed-by: Alexandre Ghiti --- arch/riscv/include/asm/pgtable.h | 7 +++++++ arch/riscv/mm/pgtable.c | 17 +++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index ede43185ffdf..ccd2fa34afb8 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -416,6 +416,10 @@ static inline pte_t pte_wrprotect(pte_t pte) /* static inline pte_t pte_mkread(pte_t pte) */ +struct vm_area_struct; +pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma); +#define pte_mkwrite pte_mkwrite + static inline pte_t pte_mkwrite_novma(pte_t pte) { return __pte(pte_val(pte) | _PAGE_WRITE); @@ -749,6 +753,9 @@ static inline pmd_t pmd_mkyoung(pmd_t pmd) return pte_pmd(pte_mkyoung(pmd_pte(pmd))); } +pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma); +#define pmd_mkwrite pmd_mkwrite + static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) { return pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))); diff --git a/arch/riscv/mm/pgtable.c b/arch/riscv/mm/pgtable.c index 4ae67324f992..be5d38546bb3 100644 --- a/arch/riscv/mm/pgtable.c +++ b/arch/riscv/mm/pgtable.c @@ -155,3 +155,20 @@ pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, return pmd; } #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ + +pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma) +{ + if (vma->vm_flags & VM_SHADOW_STACK) + return pte_mkwrite_shstk(pte); + + return pte_mkwrite_novma(pte); +} + +pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma) +{ + if (vma->vm_flags & VM_SHADOW_STACK) + return pmd_mkwrite_shstk(pmd); + + return pmd_mkwrite_novma(pmd); +} + From patchwork Mon Mar 10 14:52:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 872334 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E776230D2B for ; Mon, 10 Mar 2025 14:52:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618379; cv=none; b=TiRbsAtLgDdUpCrMoCB6105GGHp9oqYmoSayqEEiOzMxAaqugSwrp9A8YWeNJfBLvBGcXos9yZMVXKv9+56Gqht5GtygHqvRWEBQlKbsqiN2mnJNmUI0gAAq4dLrS9T7UuqyBBNa0dMTpoPEB8PAo/dLQYCgumXaCN9CICKSlmo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618379; c=relaxed/simple; bh=n/OJIVv97sm5i0GJSBQDLTL5bF2hSZWy7j+gIWNrU0I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Z176QwSCPA2uIDzx5yhmeYGMf1adNxk9N6yhupoSg5UnLJEONow6Ve7SAh0T/4/pKsm+cPT8AmWRN6DJsIffLlOjqttxluq4NwuSV1pvfXZ4zSohin85WApNid+K2FsvSiNF7z7KZ6qDAaWK8PYIJQBSFwURGE0ht/+T5tbDKZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=pyUWQWKH; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="pyUWQWKH" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-224100e9a5cso80029375ad.2 for ; Mon, 10 Mar 2025 07:52:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741618377; x=1742223177; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hK7DlmuIRYzIsuvvXHgsbKnv3WN7JKJpEt1D7vAnJaQ=; b=pyUWQWKHtVELlxZsVva9Yh0OFLlmCHRDhPpwGxjr9CeIbmVmSNf2pLWiho+HKm+/V/ mocRtuWtCosANQXa+aQOsZeo+KkgFkilvu5aoFXqsb5bOtimfMr0hLb1unmKCzjdLEp3 4Y+aiStiCkV1ZCabRjvfUKRnYPpyyq76fBcojz1CPcnxXCKmNDmvdRKVhT1NEA2pYfZs L1hGHfYQ1teooBaokcTYPlE0Wc33DyKbDKD6pKJspSg06qziPeqaCohl+sSpxItYVG5I sb1s7NMN17PXj6bUVK04VzAzC/cq/rEOHgE71esd74WdeeBrm/DqIQzlMJitthd56d9U eC3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741618377; x=1742223177; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hK7DlmuIRYzIsuvvXHgsbKnv3WN7JKJpEt1D7vAnJaQ=; b=PwGauHyAoi99g2jZZa4RHB5YesrF/yj6ClgnbPupXQkfr667vzR+yWDOcgrYVIwPp3 +UZLs8eHmc4/gLNL/e/d+mHrfK1PNen+n48JR7ULV8km1x3G6CMzC2ZKCSfIxIjTruQf 806zkWJW/LBIrITHqEQizdm9LKhXNoeb03kdUo/RyiU2chhg/iB5gUc8qH64x1A+YjUv jC8z3OFbbw5mISNk2VfctCUK/3tpR2SZtfWpmuORYUf8nkdP2KMU7Be9VUhZjAu566h4 2DAriT/72fx/wtb2U8YvpPtY/T3qYGbIF1WUgD61KSXA9ejXr0r5B8/bRCCSbzCJVHGM hP8g== X-Forwarded-Encrypted: i=1; AJvYcCX+OnEjJgLRy/m222M9+CQVcYXileu6FAXxG14zX5KRJGQ8IUwcAbYXtHZEJYCuMr/S3codjd7dNbZkKjsVrCc=@vger.kernel.org X-Gm-Message-State: AOJu0Yw/KIFgz2kpbi9ohwQQm8wL6nBSUm0y/1RAi9TXS7keE4orR1B5 w08N8SfpAYVRMv8cmsrYPsX3GLHS7Z/m5OQiD1t4vwfrJW3WvoC9PQ51uOBVHwk= X-Gm-Gg: ASbGncs/fZ/x6p/WHmAkk4AlyZIlkTi3iKV5LW1SQdUl5lMClvKMUo/vwGtAajvw+TF 0NxxwpSfyjb1tP8sO5bcfYE8nkVherZjU0laRC9DmMjUcBG7pSD/nGSlxhkfJ6hxTLbffWgzogp 1x5B5e1svCoEV4rJJiPKSR9M0nq4PUbAOv8B8g7Oc2Ite2lmsYRku96E/YjpLnkVaudKWsrOwmZ o8A5Ok630QuL28XdJjWKqm3d5/Hyg1FL6VdqTXWGRrvO+kZdaGcYJNkWKtJVgwlExR2TZQvZIsT dAzyCBA9FBsogqpF2YVxPMZTZShbS2wEirxeN3kmnJa26oKkrYZQflI= X-Google-Smtp-Source: AGHT+IGqKWX94qO9AqEOI9XVMPr9YtNG73DineLHU1SUa0qmkdl6iHIBj3KU2DOsCD0Dz98oJGoQVg== X-Received: by 2002:a05:6a00:b86:b0:736:50c4:3e0f with SMTP id d2e1a72fcca58-736aaa373b8mr17095202b3a.10.1741618376979; Mon, 10 Mar 2025 07:52:56 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736d11d4600sm2890275b3a.116.2025.03.10.07.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Mar 2025 07:52:56 -0700 (PDT) From: Deepak Gupta Date: Mon, 10 Mar 2025 07:52:32 -0700 Subject: [PATCH v11 10/27] riscv/mm: Implement map_shadow_stack() syscall Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250310-v5_user_cfi_series-v11-10-86b36cbfb910@rivosinc.com> References: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> In-Reply-To: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 As discussed extensively in the changelog for the addition of this syscall on x86 ("x86/shstk: Introduce map_shadow_stack syscall") the existing mmap() and madvise() syscalls do not map entirely well onto the security requirements for shadow stack memory since they lead to windows where memory is allocated but not yet protected or stacks which are not properly and safely initialised. Instead a new syscall map_shadow_stack() has been defined which allocates and initialises a shadow stack page. This patch implements this syscall for riscv. riscv doesn't require token to be setup by kernel because user mode can do that by itself. However to provide compatibility and portability with other architectues, user mode can specify token set flag. Signed-off-by: Deepak Gupta --- arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/usercfi.c | 144 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 145 insertions(+) diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 8d186bfced45..3a861d320654 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -125,3 +125,4 @@ obj-$(CONFIG_ACPI) += acpi.o obj-$(CONFIG_ACPI_NUMA) += acpi_numa.o obj-$(CONFIG_GENERIC_CPU_VULNERABILITIES) += bugs.o +obj-$(CONFIG_RISCV_USER_CFI) += usercfi.o diff --git a/arch/riscv/kernel/usercfi.c b/arch/riscv/kernel/usercfi.c new file mode 100644 index 000000000000..24022809a7b5 --- /dev/null +++ b/arch/riscv/kernel/usercfi.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Rivos, Inc. + * Deepak Gupta + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SHSTK_ENTRY_SIZE sizeof(void *) + +/* + * Writes on shadow stack can either be `sspush` or `ssamoswap`. `sspush` can happen + * implicitly on current shadow stack pointed to by CSR_SSP. `ssamoswap` takes pointer to + * shadow stack. To keep it simple, we plan to use `ssamoswap` to perform writes on shadow + * stack. + */ +static noinline unsigned long amo_user_shstk(unsigned long *addr, unsigned long val) +{ + /* + * Never expect -1 on shadow stack. Expect return addresses and zero + */ + unsigned long swap = -1; + + __enable_user_access(); + asm goto( + ".option push\n" + ".option arch, +zicfiss\n" + "1: ssamoswap.d %[swap], %[val], %[addr]\n" + _ASM_EXTABLE(1b, %l[fault]) + RISCV_ACQUIRE_BARRIER + ".option pop\n" + : [swap] "=r" (swap), [addr] "+A" (*addr) + : [val] "r" (val) + : "memory" + : fault + ); + __disable_user_access(); + return swap; +fault: + __disable_user_access(); + return -1; +} + +/* + * Create a restore token on the shadow stack. A token is always XLEN wide + * and aligned to XLEN. + */ +static int create_rstor_token(unsigned long ssp, unsigned long *token_addr) +{ + unsigned long addr; + + /* Token must be aligned */ + if (!IS_ALIGNED(ssp, SHSTK_ENTRY_SIZE)) + return -EINVAL; + + /* On RISC-V we're constructing token to be function of address itself */ + addr = ssp - SHSTK_ENTRY_SIZE; + + if (amo_user_shstk((unsigned long __user *)addr, (unsigned long)ssp) == -1) + return -EFAULT; + + if (token_addr) + *token_addr = addr; + + return 0; +} + +static unsigned long allocate_shadow_stack(unsigned long addr, unsigned long size, + unsigned long token_offset, bool set_tok) +{ + int flags = MAP_ANONYMOUS | MAP_PRIVATE; + struct mm_struct *mm = current->mm; + unsigned long populate, tok_loc = 0; + + if (addr) + flags |= MAP_FIXED_NOREPLACE; + + mmap_write_lock(mm); + addr = do_mmap(NULL, addr, size, PROT_READ, flags, + VM_SHADOW_STACK | VM_WRITE, 0, &populate, NULL); + mmap_write_unlock(mm); + + if (!set_tok || IS_ERR_VALUE(addr)) + goto out; + + if (create_rstor_token(addr + token_offset, &tok_loc)) { + vm_munmap(addr, size); + return -EINVAL; + } + + addr = tok_loc; + +out: + return addr; +} + +SYSCALL_DEFINE3(map_shadow_stack, unsigned long, addr, unsigned long, size, unsigned int, flags) +{ + bool set_tok = flags & SHADOW_STACK_SET_TOKEN; + unsigned long aligned_size = 0; + + if (!cpu_supports_shadow_stack()) + return -EOPNOTSUPP; + + /* Anything other than set token should result in invalid param */ + if (flags & ~SHADOW_STACK_SET_TOKEN) + return -EINVAL; + + /* + * Unlike other architectures, on RISC-V, SSP pointer is held in CSR_SSP and is available + * CSR in all modes. CSR accesses are performed using 12bit index programmed in instruction + * itself. This provides static property on register programming and writes to CSR can't + * be unintentional from programmer's perspective. As long as programmer has guarded areas + * which perform writes to CSR_SSP properly, shadow stack pivoting is not possible. Since + * CSR_SSP is writeable by user mode, it itself can setup a shadow stack token subsequent + * to allocation. Although in order to provide portablity with other architecture (because + * `map_shadow_stack` is arch agnostic syscall), RISC-V will follow expectation of a token + * flag in flags and if provided in flags, setup a token at the base. + */ + + /* If there isn't space for a token */ + if (set_tok && size < SHSTK_ENTRY_SIZE) + return -ENOSPC; + + if (addr && (addr & (PAGE_SIZE - 1))) + return -EINVAL; + + aligned_size = PAGE_ALIGN(size); + if (aligned_size < size) + return -EOVERFLOW; + + return allocate_shadow_stack(addr, aligned_size, size, set_tok); +} From patchwork Mon Mar 10 14:52:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 872333 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BAA2233151 for ; Mon, 10 Mar 2025 14:53:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618384; cv=none; b=Z08XiEP+Ha31na9FlBtAi/XzBa9tC6LmXqqJkrIhWnk54g9m5IxfYV9+pSHDjH8bpJQ0xW83yOhCZEAcT+7PglPeIqX/TKOiuSVr6wzWfkmDNIwVhmM4tgDcqeUBY6AqQ5u6Mk/Hj+cIq3UsJ8/+19Yrs85NDHzPlkglmAYVtt4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618384; c=relaxed/simple; bh=6tij1ZY5YMYBXzl8yUkJ2kDZaNjjUiJRSlpStARzsww=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CXqns4xC7KfaHNHuObPygyb48BOSxv3264wAlR1pdol6wklYXe9boaByhFiRQBq7QK32kYhjv+4cP0KplQvSJUP07KEu5kCM33t8jStjYTOybCRKP3zOpdlmNRCfPUFLLAyOg/nEe7qhVBbKAWlNL5O3oGGrPMq6rl4XsBOl7qE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=PLfl5b5w; arc=none smtp.client-ip=209.85.214.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="PLfl5b5w" Received: by mail-pl1-f174.google.com with SMTP id d9443c01a7336-2254e0b4b79so11040455ad.2 for ; Mon, 10 Mar 2025 07:53:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741618382; x=1742223182; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Zfw9OtoVzzM7Z5oL2c+Ej/yDm51xyr1WNtqXJN3fx8s=; b=PLfl5b5wMQ8zWz3Jqeq8E3z1CJECjdkTEfwzmIPs7L+do8i6mjJqUmJUvZkxTwEqpx DGltGkP620pMRfEI14TY36ktd2LNKeqDY30oiCZblqYKrfmFv2JVBHJqk91FyUoDfymY RtrAE/uXspy9e3l0rshg5gCeUDRNfzA5Ls75k82CVrVmCpO4VbVuceBwyC3NJceNjOH2 8rdUopp4HgSyKFD4JjAXIRawlccILMo6f5ownl6QAdXBp0YrpTjo1lUpfOIYZBLJjNGW Hjw586MUsb2GAIlqD14PPWX3U43SxDUDupXN4P9i0TO58fwXMXoHyU1U/R0sSSThNK1X LHdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741618382; x=1742223182; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zfw9OtoVzzM7Z5oL2c+Ej/yDm51xyr1WNtqXJN3fx8s=; b=h2GGK6AxneZyBdz+XAhXNB750m0JzigL9Vg1atmEI5Znw2+wdP8+FPhWgCdO9zXbR8 MroUEUEgE+wt2pLamQLbiVuNCfGRsajPn8NaQjNkQ6VBvdSgXQHFCp3/Eo5UBwuM8Hty OJXRyNY90rdjDPZ+C89BNaK9bwMBF5kcW+GkqCqB24H6NkoIl41VYPHwvP8Uwu+gGOO1 Aapg7em3YvBp38VmrhxrAMJCGpi2Hvr97ZRIikygJPkc4BdFlEaejEsNt3nxrvK5cTtM LXLyFNXxw8s0mwNm1lmC10rwP31/PJVpHYFg9GFbTKIbaDCGZUAg+BCmO+Y0P/p852h7 AsOg== X-Forwarded-Encrypted: i=1; AJvYcCVjx9+zFPhPuqLTaGgI3rTbGvfmMw7jWrS9jk78uDdqHSKbKmBILNaUBqThYy+MqjqEWcrmxasKZea/S0fbRDo=@vger.kernel.org X-Gm-Message-State: AOJu0Yz4MOiArz6ZFjJmuSNLsV+QwXiSiSlDLfdvOWvWvVwPCTxpzqjA TKUQeccdTtdKl5Cl4dO2DxUHjKdcl7fdDpb5fYrWmdDPut0sXYKD1gbkNHt6fCw= X-Gm-Gg: ASbGncsPVofY0iuzhTozaIZvEr5v81U4n1Db8pcL4CbEvz8NxNKbrQ86fOqn3bOarqn zZ2DVTqCsFH95KxkKGcamC3GoqNc590HZa8K4yi4CowDgcJr8VHV8fRIYJ+m797O6qG0YxqKCW8 IzR4BaTtlQ2iw4mJ1FdC7Gf+CvGCtdJzfgsWO3FNj92howvqupIWX40veXDdQY2T9gviHB6gzqN ESAozVD2v94wWEl3rBqHf4t0NPW0Of1Q+bzOn0AYon+ZBtFMpKHsnvKA/aADe0eE78SFB2Burf1 sMD+XHaVBODbLRzYXQS3XPwpFu81AqT2uO0Kz+f1sp2HtBqGkKW13WumNtYGwW9rCg== X-Google-Smtp-Source: AGHT+IHCKzm+H1WuyN4ioLJbIhvG1jyYj+k1eB31ZxZlrJTUkTC6vhrDB22oVaHxl5JQ/hZbQyLd3A== X-Received: by 2002:a05:6a20:430a:b0:1f0:e893:409f with SMTP id adf61e73a8af0-1f544b180dbmr23325177637.23.1741618381901; Mon, 10 Mar 2025 07:53:01 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736d11d4600sm2890275b3a.116.2025.03.10.07.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Mar 2025 07:53:01 -0700 (PDT) From: Deepak Gupta Date: Mon, 10 Mar 2025 07:52:34 -0700 Subject: [PATCH v11 12/27] riscv: Implements arch agnostic shadow stack prctls Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250310-v5_user_cfi_series-v11-12-86b36cbfb910@rivosinc.com> References: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> In-Reply-To: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 Implement architecture agnostic prctls() interface for setting and getting shadow stack status. prctls implemented are PR_GET_SHADOW_STACK_STATUS, PR_SET_SHADOW_STACK_STATUS and PR_LOCK_SHADOW_STACK_STATUS. As part of PR_SET_SHADOW_STACK_STATUS/PR_GET_SHADOW_STACK_STATUS, only PR_SHADOW_STACK_ENABLE is implemented because RISCV allows each mode to write to their own shadow stack using `sspush` or `ssamoswap`. PR_LOCK_SHADOW_STACK_STATUS locks current configuration of shadow stack enabling. Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/usercfi.h | 18 ++++++- arch/riscv/kernel/process.c | 8 +++ arch/riscv/kernel/usercfi.c | 107 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 132 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/usercfi.h b/arch/riscv/include/asm/usercfi.h index 82d28ac98d76..c4dcd256f19a 100644 --- a/arch/riscv/include/asm/usercfi.h +++ b/arch/riscv/include/asm/usercfi.h @@ -7,6 +7,7 @@ #ifndef __ASSEMBLY__ #include +#include struct task_struct; struct kernel_clone_args; @@ -14,7 +15,8 @@ struct kernel_clone_args; #ifdef CONFIG_RISCV_USER_CFI struct cfi_status { unsigned long ubcfi_en : 1; /* Enable for backward cfi. */ - unsigned long rsvd : ((sizeof(unsigned long) * 8) - 1); + unsigned long ubcfi_locked : 1; + unsigned long rsvd : ((sizeof(unsigned long) * 8) - 2); unsigned long user_shdw_stk; /* Current user shadow stack pointer */ unsigned long shdw_stk_base; /* Base address of shadow stack */ unsigned long shdw_stk_size; /* size of shadow stack */ @@ -27,6 +29,12 @@ void set_shstk_base(struct task_struct *task, unsigned long shstk_addr, unsigned unsigned long get_shstk_base(struct task_struct *task, unsigned long *size); void set_active_shstk(struct task_struct *task, unsigned long shstk_addr); bool is_shstk_enabled(struct task_struct *task); +bool is_shstk_locked(struct task_struct *task); +bool is_shstk_allocated(struct task_struct *task); +void set_shstk_lock(struct task_struct *task); +void set_shstk_status(struct task_struct *task, bool enable); + +#define PR_SHADOW_STACK_SUPPORTED_STATUS_MASK (PR_SHADOW_STACK_ENABLE) #else @@ -42,6 +50,14 @@ bool is_shstk_enabled(struct task_struct *task); #define is_shstk_enabled(task) false +#define is_shstk_locked(task) false + +#define is_shstk_allocated(task) false + +#define set_shstk_lock(task) + +#define set_shstk_status(task, enable) + #endif /* CONFIG_RISCV_USER_CFI */ #endif /* __ASSEMBLY__ */ diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 99acb6342a37..cd11667593fe 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -153,6 +153,14 @@ void start_thread(struct pt_regs *regs, unsigned long pc, regs->epc = pc; regs->sp = sp; + /* + * clear shadow stack state on exec. + * libc will set it later via prctl. + */ + set_shstk_status(current, false); + set_shstk_base(current, 0, 0); + set_active_shstk(current, 0); + #ifdef CONFIG_64BIT regs->status &= ~SR_UXL; diff --git a/arch/riscv/kernel/usercfi.c b/arch/riscv/kernel/usercfi.c index 73cf87dab186..37d6fb8144e7 100644 --- a/arch/riscv/kernel/usercfi.c +++ b/arch/riscv/kernel/usercfi.c @@ -24,6 +24,16 @@ bool is_shstk_enabled(struct task_struct *task) return task->thread_info.user_cfi_state.ubcfi_en ? true : false; } +bool is_shstk_allocated(struct task_struct *task) +{ + return task->thread_info.user_cfi_state.shdw_stk_base ? true : false; +} + +bool is_shstk_locked(struct task_struct *task) +{ + return task->thread_info.user_cfi_state.ubcfi_locked ? true : false; +} + void set_shstk_base(struct task_struct *task, unsigned long shstk_addr, unsigned long size) { task->thread_info.user_cfi_state.shdw_stk_base = shstk_addr; @@ -42,6 +52,23 @@ void set_active_shstk(struct task_struct *task, unsigned long shstk_addr) task->thread_info.user_cfi_state.user_shdw_stk = shstk_addr; } +void set_shstk_status(struct task_struct *task, bool enable) +{ + task->thread_info.user_cfi_state.ubcfi_en = enable ? 1 : 0; + + if (enable) + task->thread.envcfg |= ENVCFG_SSE; + else + task->thread.envcfg &= ~ENVCFG_SSE; + + csr_write(CSR_ENVCFG, task->thread.envcfg); +} + +void set_shstk_lock(struct task_struct *task) +{ + task->thread_info.user_cfi_state.ubcfi_locked = 1; +} + /* * If size is 0, then to be compatible with regular stack we want it to be as big as * regular stack. Else PAGE_ALIGN it and return back @@ -262,3 +289,83 @@ void shstk_release(struct task_struct *tsk) vm_munmap(base, size); set_shstk_base(tsk, 0, 0); } + +int arch_get_shadow_stack_status(struct task_struct *t, unsigned long __user *status) +{ + unsigned long bcfi_status = 0; + + if (!cpu_supports_shadow_stack()) + return -EINVAL; + + /* this means shadow stack is enabled on the task */ + bcfi_status |= (is_shstk_enabled(t) ? PR_SHADOW_STACK_ENABLE : 0); + + return copy_to_user(status, &bcfi_status, sizeof(bcfi_status)) ? -EFAULT : 0; +} + +int arch_set_shadow_stack_status(struct task_struct *t, unsigned long status) +{ + unsigned long size = 0, addr = 0; + bool enable_shstk = false; + + if (!cpu_supports_shadow_stack()) + return -EINVAL; + + /* Reject unknown flags */ + if (status & ~PR_SHADOW_STACK_SUPPORTED_STATUS_MASK) + return -EINVAL; + + /* bcfi status is locked and further can't be modified by user */ + if (is_shstk_locked(t)) + return -EINVAL; + + enable_shstk = status & PR_SHADOW_STACK_ENABLE; + /* Request is to enable shadow stack and shadow stack is not enabled already */ + if (enable_shstk && !is_shstk_enabled(t)) { + /* shadow stack was allocated and enable request again + * no need to support such usecase and return EINVAL. + */ + if (is_shstk_allocated(t)) + return -EINVAL; + + size = calc_shstk_size(0); + addr = allocate_shadow_stack(0, size, 0, false); + if (IS_ERR_VALUE(addr)) + return -ENOMEM; + set_shstk_base(t, addr, size); + set_active_shstk(t, addr + size); + } + + /* + * If a request to disable shadow stack happens, let's go ahead and release it + * Although, if CLONE_VFORKed child did this, then in that case we will end up + * not releasing the shadow stack (because it might be needed in parent). Although + * we will disable it for VFORKed child. And if VFORKed child tries to enable again + * then in that case, it'll get entirely new shadow stack because following condition + * are true + * - shadow stack was not enabled for vforked child + * - shadow stack base was anyways pointing to 0 + * This shouldn't be a big issue because we want parent to have availability of shadow + * stack whenever VFORKed child releases resources via exit or exec but at the same + * time we want VFORKed child to break away and establish new shadow stack if it desires + * + */ + if (!enable_shstk) + shstk_release(t); + + set_shstk_status(t, enable_shstk); + return 0; +} + +int arch_lock_shadow_stack_status(struct task_struct *task, + unsigned long arg) +{ + /* If shtstk not supported or not enabled on task, nothing to lock here */ + if (!cpu_supports_shadow_stack() || + !is_shstk_enabled(task) || arg != 0) + return -EINVAL; + + set_shstk_lock(task); + + return 0; +} From patchwork Mon Mar 10 14:52:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 872332 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86F472343C1 for ; Mon, 10 Mar 2025 14:53:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618389; cv=none; b=WSSdVMeJO7s06n64fBfl8L1oOOrcV43m9XtVh4cqtOEVTv8yMWcjAsTD/EQ4AoDbuV8ubZ+V6PjRprsTXdf0OLcw2jTj/NX7OHPncnrMGwcl2hUDb5aGIRFOlXkupy2T/+/BoCe45SkKB9UwCeKIoZ9zPyOXdLapqNw70EWSmas= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618389; c=relaxed/simple; bh=mWDyYETp4wr+sZ2udIiiXn9veUStZJ0b+YrPzAFDVJE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QRnhk/Dg/JhATj8HRwlWvGXf8gH//UeFsmgDFtbtbXIzgXvUUNtOwKYY9J1o4oLu9JgP7fa2Cl8lVQ+N9YnfFA6H9O/9+1TaSNcJBlphiyvEtz+xQfyMqYM7/3JYY4AuP2qjngb/y4MeLOjiYwzbOAfT0R4nubQYtEu/0X1tz6k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=ruC45iPE; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="ruC45iPE" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-2239c066347so74044865ad.2 for ; Mon, 10 Mar 2025 07:53:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741618387; x=1742223187; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=M49HWf8gzr6wWBf1Qtr4VOivQAEEQjfyuWgORGOVTSw=; b=ruC45iPEggx6iINPgbVg/Jjk6tyrE36Kku7m4ofEcj0qNu+4jUkWMEzYe/sZKYzE0E gIV3hoyTmrg1sl0dKYyXjt73D29j0c3lnirnRbKaDag37wAlT9ORPeqHRQSKYq/UhkxZ pyLVDXddoxiaXA0HJKpWfCGJXWeAEp8d6dJ/c+qSmFbIdDIyqK8XYqtjO5EUt2vjh54x Kf3auTTaVrx54nLF5mPxAMqJs4yjR5A7bkcp2jU1hX3ISWhmQGxRIb0G7Ok9N7Wb8hpd b69AwO0wiyXkxv1eE/FKyYIT9Hhh682WhtD4dDY6B2M/XeKRy81Ye4Nm9od2nlhTaIIk Nd1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741618387; x=1742223187; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M49HWf8gzr6wWBf1Qtr4VOivQAEEQjfyuWgORGOVTSw=; b=i0SjB8nAa3M22nx1sKJNB5ac8bSUSNzqon1MvOegg2Ex2xBsEcv6eaD1SO9ukBC533 +sbftDeqMHt+6AAM0jCzHbF+ndpUdVIi7zyC46SX5TYzVdHL3Y69EJtSDCKGtHZqQ+g8 BAnAG7TQErc0n4IU3cL1wuMpiV5QATfw/j3Kl+FNDg3gq8Qk7AP6s69TXtBripSYxiZl dp21u7KnzcnjgCcjk/t4rzXFR23pJzgkUT5einMRzZJCMAzE/iGcYmL/3MmKU/0vr9nA fbs1NaTT7HJdtnjcpB4WpO9z35EPfGqJGkYZALiY/+P2k1klm0n9kl4VPM9ctlC0dHg3 qZVw== X-Forwarded-Encrypted: i=1; AJvYcCUxzDfL4gLT9GYPs9KB4P6QAsJ3J+saN+PuLCl4dnDvLets9D8K3UcLoj8UOdDt3SXPdqHLHfufXwolFxBK8iU=@vger.kernel.org X-Gm-Message-State: AOJu0Yz9QKrEUhuCFqFfmspc4jEYHSrotdjHkaW7vf0zF3mWXViqssf4 7ElVGY2Wf/Y6MKuJPkXeWAJ2DeAUXqAn/+NovmSOUXCjyLlY//GUeF97Ys4W8io= X-Gm-Gg: ASbGncv+xMm+DqNWyFN0RgDHjXeLrHWbf5L6UZ3qpq0y8i5lL/2V/csnB/DTHluecEU rSAn+hiIgzqBNUQXVRFG0ovX5ceJy3UwGm5KNYMLLcNocT2IS84vcQVMpkJizLT2R2XW0ZrGjgS wRx/nfqLMyZ2PwAo5IF4PORRZHoKkRGNAmH34aWWQE6ICB0J4IreKyE1+XL+J+rvaGrt6oMe4nW UK7X/UkRPfCX9ZYRDbFqiUt46oudX80zDb6MFMkyiX3HcskdjFgC7k7IkuV0ml7virjjjc+nYqg u5zr/0JQAAFducZpdPH/YDKGSd2WqLo3IEgBO9mMsZztYtCsbOn0SLA= X-Google-Smtp-Source: AGHT+IFsZxG1TWVrNQMrqkKpccFn2JJPQ/WSJPQEXgIDTpBCMBrYmD46kiCZqmMB33SVFrCrhoe36g== X-Received: by 2002:a05:6a20:2d2c:b0:1f5:8221:d68c with SMTP id adf61e73a8af0-1f58221fee5mr5284959637.3.1741618386923; Mon, 10 Mar 2025 07:53:06 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736d11d4600sm2890275b3a.116.2025.03.10.07.53.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Mar 2025 07:53:06 -0700 (PDT) From: Deepak Gupta Date: Mon, 10 Mar 2025 07:52:36 -0700 Subject: [PATCH v11 14/27] riscv/traps: Introduce software check exception Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250310-v5_user_cfi_series-v11-14-86b36cbfb910@rivosinc.com> References: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> In-Reply-To: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 zicfiss / zicfilp introduces a new exception to priv isa `software check exception` with cause code = 18. This patch implements software check exception. Additionally it implements a cfi violation handler which checks for code in xtval. If xtval=2, it means that sw check exception happened because of an indirect branch not landing on 4 byte aligned PC or not landing on `lpad` instruction or label value embedded in `lpad` not matching label value setup in `x7`. If xtval=3, it means that sw check exception happened because of mismatch between link register (x1 or x5) and top of shadow stack (on execution of `sspopchk`). In case of cfi violation, SIGSEGV is raised with code=SEGV_CPERR. SEGV_CPERR was introduced by x86 shadow stack patches. Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/asm-prototypes.h | 1 + arch/riscv/include/asm/entry-common.h | 2 ++ arch/riscv/kernel/entry.S | 3 +++ arch/riscv/kernel/traps.c | 43 +++++++++++++++++++++++++++++++++ 4 files changed, 49 insertions(+) diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/asm/asm-prototypes.h index cd627ec289f1..5a27cefd7805 100644 --- a/arch/riscv/include/asm/asm-prototypes.h +++ b/arch/riscv/include/asm/asm-prototypes.h @@ -51,6 +51,7 @@ DECLARE_DO_ERROR_INFO(do_trap_ecall_u); DECLARE_DO_ERROR_INFO(do_trap_ecall_s); DECLARE_DO_ERROR_INFO(do_trap_ecall_m); DECLARE_DO_ERROR_INFO(do_trap_break); +DECLARE_DO_ERROR_INFO(do_trap_software_check); asmlinkage void handle_bad_stack(struct pt_regs *regs); asmlinkage void do_page_fault(struct pt_regs *regs); diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h index b28ccc6cdeea..34ed149af5d1 100644 --- a/arch/riscv/include/asm/entry-common.h +++ b/arch/riscv/include/asm/entry-common.h @@ -40,4 +40,6 @@ static inline int handle_misaligned_store(struct pt_regs *regs) } #endif +bool handle_user_cfi_violation(struct pt_regs *regs); + #endif /* _ASM_RISCV_ENTRY_COMMON_H */ diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 00494b54ff4a..9c00cac3f6f2 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -472,6 +472,9 @@ SYM_DATA_START_LOCAL(excp_vect_table) RISCV_PTR do_page_fault /* load page fault */ RISCV_PTR do_trap_unknown RISCV_PTR do_page_fault /* store page fault */ + RISCV_PTR do_trap_unknown /* cause=16 */ + RISCV_PTR do_trap_unknown /* cause=17 */ + RISCV_PTR do_trap_software_check /* cause=18 is sw check exception */ SYM_DATA_END_LABEL(excp_vect_table, SYM_L_LOCAL, excp_vect_table_end) #ifndef CONFIG_MMU diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 8ff8e8b36524..3f7709f4595a 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -354,6 +354,49 @@ void do_trap_ecall_u(struct pt_regs *regs) } +#define CFI_TVAL_FCFI_CODE 2 +#define CFI_TVAL_BCFI_CODE 3 +/* handle cfi violations */ +bool handle_user_cfi_violation(struct pt_regs *regs) +{ + bool ret = false; + unsigned long tval = csr_read(CSR_TVAL); + + if ((tval == CFI_TVAL_FCFI_CODE && cpu_supports_indirect_br_lp_instr()) || + (tval == CFI_TVAL_BCFI_CODE && cpu_supports_shadow_stack())) { + do_trap_error(regs, SIGSEGV, SEGV_CPERR, regs->epc, + "Oops - control flow violation"); + ret = true; + } + + return ret; +} + +/* + * software check exception is defined with risc-v cfi spec. Software check + * exception is raised when:- + * a) An indirect branch doesn't land on 4 byte aligned PC or `lpad` + * instruction or `label` value programmed in `lpad` instr doesn't + * match with value setup in `x7`. reported code in `xtval` is 2. + * b) `sspopchk` instruction finds a mismatch between top of shadow stack (ssp) + * and x1/x5. reported code in `xtval` is 3. + */ +asmlinkage __visible __trap_section void do_trap_software_check(struct pt_regs *regs) +{ + if (user_mode(regs)) { + irqentry_enter_from_user_mode(regs); + + /* not a cfi violation, then merge into flow of unknown trap handler */ + if (!handle_user_cfi_violation(regs)) + do_trap_unknown(regs); + + irqentry_exit_to_user_mode(regs); + } else { + /* sw check exception coming from kernel is a bug in kernel */ + die(regs, "Kernel BUG"); + } +} + #ifdef CONFIG_MMU asmlinkage __visible noinstr void do_page_fault(struct pt_regs *regs) { From patchwork Mon Mar 10 14:52:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 872331 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B1CD2356D6 for ; Mon, 10 Mar 2025 14:53:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618394; cv=none; b=s13Wia3MJPKzsDDoSWQ9g72ivHae4sLOq7JYUxXl0L9n6u3YjfnIZ9BhTH8gcVDL2Aoup5uOa5Qk3fS6uHIn2pJmhMcjzXpl+o+fXDCYHcJ/VcC3w0A0pBjVyS/OTtFcz8NoxFFrD2KE2mPBuFRJ+dU+j4d4AdMoMbXVRCXlKTY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618394; c=relaxed/simple; bh=wI9o+6ZNrC0pPpw2dP6AWMAMeO7BYuPrKSYAS17pkaw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KYI0TaPBphF2peARZ9ECjon1yLsQvhhKk/8jQV1yYORS9zNRhF2p8aqeRDXZhHo3zOC7g/qOu5OKADLvB/Uk+nVQlj5G+e4nnDSUtkCtXd5YEQ1K1y52AMqfWgeeMriubYd9SPZua/6D3OtjLC3ZVwiEJ0XFvZhR55EjNJYSbaI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=ZuBV8IA3; arc=none smtp.client-ip=209.85.214.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="ZuBV8IA3" Received: by mail-pl1-f174.google.com with SMTP id d9443c01a7336-2239aa5da08so68485225ad.3 for ; Mon, 10 Mar 2025 07:53:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741618392; x=1742223192; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FZizf8oZeAex4CEwHeMnGWZudkjFQvNzoIsL7CfIy1g=; b=ZuBV8IA32Jr8hTGvCFE0IdZw+QQptGtu+T10SXZ006poHGETlGncEheOGF4ZmhtYaZ P3UIDdBjIHIQtTJ6ahTL9bCYo2Kbdjr8hfOF8cRyrDOsVbcidlTtooTk/W4XC45As3j2 ZRfqdPgxKQkTXVHp6R1ftseF1c77bXMkMw6jSDPeIS2lt8w3R2ixh8d1977M+7EFgPEt YwTCUwEu9BmEOwmNsusRicJl9F6hVBbeXrsUonC4X4qcuBfAevSr1/OZEGwj4UxI0HAY RHSHHxQya+TgXVEAb8Q0WDSjgreVFPTPLCNt3YSzEVieiV+1ZLpE/Qh2A6gwMr5O7HFS pIOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741618392; x=1742223192; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FZizf8oZeAex4CEwHeMnGWZudkjFQvNzoIsL7CfIy1g=; b=EdOcZ7iq5ALfAFsMfmxWRBMD5t3d/vaLBjJe+Gm5Z6q+ccwsbMtOIAwEqO9VHitJNr lyno237uZQy+A1E80wAb4XdzEG414pZL/1bdlom4UDP12ETzm05nG2uKuu/mygJbvxti n0Vt65EiPnmgsvwsUuuZjpvjDvqMD2+VcZoiTF6xU7p7H+vXd39j3Cr634rr4Fso1QLs cwPEk5LEQfb2SWqK6LKtZEVU481xk3J7EfGxTGMhjiE0rglORasfzChaJtu8f3lvZAQK gw1PtTfOGRbSVIXLqSY2bfeY/PNW9NJHogGUa5sPdX5HIQDHj4mPau//+8Kuxoc+hFKF Efvg== X-Forwarded-Encrypted: i=1; AJvYcCUDh1NywyqSk1LGhem8nov/dmRGCYM05NVowdMNbF16lq+4gGjTnOYrGbMAaWyXxCVM99KmXa6++uhDIfuweX8=@vger.kernel.org X-Gm-Message-State: AOJu0YzLHAm6UVJJ1tQWgvUty3cWLSv6V7A9YjJh3CHBchJJMd0n8cRq alElEAxn00JHV3Lv0TEzbCJ8BpAlBH3G+cvmmqytaoO9i9qoi/Mz0qZqdcAE8qA= X-Gm-Gg: ASbGncsc1VIwVuyNClPpGrRIsFAUdoLMLIHwVOY7pfAo8mRb8PZ0DuEYFQd6k5cu0jc Ze8xFasY1ewBONdD/XrB7cVttqmzJtZALhBCFgxSho6HhG6r0A4/9vVoaKiEqLWwDaXIWLGtRL7 gb0fq5WtVW/zkWLGcQfjoYY14pM/OAVzpokMSmPF43M0mi25fy7+PpWg2YOC9H1S/y/m1O5UalQ MQ0i0EpfI/DHEjknz95eyWQi/ieBiM06+SlG2bbljTWFExs2sbp5j6kXGSwusTirVAo4ZV8+TZA jH32Do1X5JTkaIAHev0irXKAXwYHar/IS43TaXyHC3OZDytrL+Zw4hs= X-Google-Smtp-Source: AGHT+IGtoWSwFQXp42Jt7uQ+iD9QmR3QbXX6mHvaYDmjRmHhCAWQmnMnksRJhwAUzL/h4lDxdU80yg== X-Received: by 2002:a05:6a21:4606:b0:1f5:7df9:f147 with SMTP id adf61e73a8af0-1f57df9f49dmr7383711637.40.1741618391807; Mon, 10 Mar 2025 07:53:11 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736d11d4600sm2890275b3a.116.2025.03.10.07.53.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Mar 2025 07:53:11 -0700 (PDT) From: Deepak Gupta Date: Mon, 10 Mar 2025 07:52:38 -0700 Subject: [PATCH v11 16/27] riscv/signal: save and restore of shadow stack for signal Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250310-v5_user_cfi_series-v11-16-86b36cbfb910@rivosinc.com> References: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> In-Reply-To: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta , Andy Chiu X-Mailer: b4 0.14.0 Save shadow stack pointer in sigcontext structure while delivering signal. Restore shadow stack pointer from sigcontext on sigreturn. As part of save operation, kernel uses `ssamoswap` to save snapshot of current shadow stack on shadow stack itself (can be called as a save token). During restore on sigreturn, kernel retrieves token from top of shadow stack and validates it. This allows that user mode can't arbitrary pivot to any shadow stack address without having a token and thus provide strong security assurance between signaly delivery and sigreturn window. Use ABI compatible way of saving/restoring shadow stack pointer into signal stack. This follows what Vector extension, where extra registers are placed in a form of extension header + extension body in the stack. The extension header indicates the size of the extra architectural states plus the size of header itself, and a magic identifier of the extension. Then, the extensions body contains the new architectural states in the form defined by uapi. Signed-off-by: Andy Chiu Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/usercfi.h | 10 ++++ arch/riscv/include/uapi/asm/ptrace.h | 4 ++ arch/riscv/include/uapi/asm/sigcontext.h | 1 + arch/riscv/kernel/signal.c | 80 ++++++++++++++++++++++++++++++++ arch/riscv/kernel/usercfi.c | 56 ++++++++++++++++++++++ 5 files changed, 151 insertions(+) diff --git a/arch/riscv/include/asm/usercfi.h b/arch/riscv/include/asm/usercfi.h index a8cec7c14d1d..361f59edbdef 100644 --- a/arch/riscv/include/asm/usercfi.h +++ b/arch/riscv/include/asm/usercfi.h @@ -8,6 +8,7 @@ #ifndef __ASSEMBLY__ #include #include +#include struct task_struct; struct kernel_clone_args; @@ -35,6 +36,9 @@ bool is_shstk_locked(struct task_struct *task); bool is_shstk_allocated(struct task_struct *task); void set_shstk_lock(struct task_struct *task); void set_shstk_status(struct task_struct *task, bool enable); +unsigned long get_active_shstk(struct task_struct *task); +int restore_user_shstk(struct task_struct *tsk, unsigned long shstk_ptr); +int save_user_shstk(struct task_struct *tsk, unsigned long *saved_shstk_ptr); bool is_indir_lp_enabled(struct task_struct *task); bool is_indir_lp_locked(struct task_struct *task); void set_indir_lp_status(struct task_struct *task, bool enable); @@ -72,6 +76,12 @@ void set_indir_lp_lock(struct task_struct *task); #define set_indir_lp_lock(task) +#define restore_user_shstk(tsk, shstk_ptr) -EINVAL + +#define save_user_shstk(tsk, saved_shstk_ptr) -EINVAL + +#define get_active_shstk(task) 0UL + #endif /* CONFIG_RISCV_USER_CFI */ #endif /* __ASSEMBLY__ */ diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h index a38268b19c3d..659ea3af5680 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -127,6 +127,10 @@ struct __riscv_v_regset_state { */ #define RISCV_MAX_VLENB (8192) +struct __sc_riscv_cfi_state { + unsigned long ss_ptr; /* shadow stack pointer */ +}; + #endif /* __ASSEMBLY__ */ #endif /* _UAPI_ASM_RISCV_PTRACE_H */ diff --git a/arch/riscv/include/uapi/asm/sigcontext.h b/arch/riscv/include/uapi/asm/sigcontext.h index cd4f175dc837..f37e4beffe03 100644 --- a/arch/riscv/include/uapi/asm/sigcontext.h +++ b/arch/riscv/include/uapi/asm/sigcontext.h @@ -10,6 +10,7 @@ /* The Magic number for signal context frame header. */ #define RISCV_V_MAGIC 0x53465457 +#define RISCV_ZICFISS_MAGIC 0x9487 #define END_MAGIC 0x0 /* The size of END signal context header. */ diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 80c70dccf09f..a7472a6fcdca 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -22,11 +22,13 @@ #include #include #include +#include unsigned long signal_minsigstksz __ro_after_init; extern u32 __user_rt_sigreturn[2]; static size_t riscv_v_sc_size __ro_after_init; +static size_t riscv_zicfiss_sc_size __ro_after_init; #define DEBUG_SIG 0 @@ -140,6 +142,62 @@ static long __restore_v_state(struct pt_regs *regs, void __user *sc_vec) return copy_from_user(current->thread.vstate.datap, datap, riscv_v_vsize); } +static long save_cfiss_state(struct pt_regs *regs, void __user *sc_cfi) +{ + struct __sc_riscv_cfi_state __user *state = sc_cfi; + unsigned long ss_ptr = 0; + long err = 0; + + if (!IS_ENABLED(CONFIG_RISCV_USER_CFI) || !is_shstk_enabled(current)) + return 0; + + /* + * Save a pointer to shadow stack itself on shadow stack as a form of token. + * A token on shadow gives following properties + * - Safe save and restore for shadow stack switching. Any save of shadow stack + * must have had saved a token on shadow stack. Similarly any restore of shadow + * stack must check the token before restore. Since writing to shadow stack with + * address of shadow stack itself is not easily allowed. A restore without a save + * is quite difficult for an attacker to perform. + * - A natural break. A token in shadow stack provides a natural break in shadow stack + * So a single linear range can be bucketed into different shadow stack segments. Any + * sspopchk will detect the condition and fault to kernel as sw check exception. + */ + err |= save_user_shstk(current, &ss_ptr); + err |= __put_user(ss_ptr, &state->ss_ptr); + if (unlikely(err)) + return -EFAULT; + + return riscv_zicfiss_sc_size; +} + +static long __restore_cfiss_state(struct pt_regs *regs, void __user *sc_cfi) +{ + struct __sc_riscv_cfi_state __user *state = sc_cfi; + unsigned long ss_ptr = 0; + long err; + + /* + * Restore shadow stack as a form of token stored on shadow stack itself as a safe + * way to restore. + * A token on shadow gives following properties + * - Safe save and restore for shadow stack switching. Any save of shadow stack + * must have had saved a token on shadow stack. Similarly any restore of shadow + * stack must check the token before restore. Since writing to shadow stack with + * address of shadow stack itself is not easily allowed. A restore without a save + * is quite difficult for an attacker to perform. + * - A natural break. A token in shadow stack provides a natural break in shadow stack + * So a single linear range can be bucketed into different shadow stack segments. + * sspopchk will detect the condition and fault to kernel as sw check exception. + */ + err = __copy_from_user(&ss_ptr, &state->ss_ptr, sizeof(unsigned long)); + + if (unlikely(err)) + return err; + + return restore_user_shstk(current, ss_ptr); +} + struct arch_ext_priv { __u32 magic; long (*save)(struct pt_regs *regs, void __user *sc_vec); @@ -150,6 +208,10 @@ struct arch_ext_priv arch_ext_list[] = { .magic = RISCV_V_MAGIC, .save = &save_v_state, }, + { + .magic = RISCV_ZICFISS_MAGIC, + .save = &save_cfiss_state, + }, }; const size_t nr_arch_exts = ARRAY_SIZE(arch_ext_list); @@ -202,6 +264,12 @@ static long restore_sigcontext(struct pt_regs *regs, err = __restore_v_state(regs, sc_ext_ptr); break; + case RISCV_ZICFISS_MAGIC: + if (!is_shstk_enabled(current) || size != riscv_zicfiss_sc_size) + return -EINVAL; + + err = __restore_cfiss_state(regs, sc_ext_ptr); + break; default: return -EINVAL; } @@ -222,6 +290,10 @@ static size_t get_rt_frame_size(bool cal_all) if (cal_all || riscv_v_vstate_query(task_pt_regs(current))) total_context_size += riscv_v_sc_size; } + + if (is_shstk_enabled(current)) + total_context_size += riscv_zicfiss_sc_size; + /* * Preserved a __riscv_ctx_hdr for END signal context header if an * extension uses __riscv_extra_ext_header @@ -365,6 +437,11 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, #ifdef CONFIG_MMU regs->ra = (unsigned long)VDSO_SYMBOL( current->mm->context.vdso, rt_sigreturn); + + /* if bcfi is enabled x1 (ra) and x5 (t0) must match. not sure if we need this? */ + if (is_shstk_enabled(current)) + regs->t0 = regs->ra; + #else /* * For the nommu case we don't have a VDSO. Instead we push two @@ -493,6 +570,9 @@ void __init init_rt_signal_env(void) { riscv_v_sc_size = sizeof(struct __riscv_ctx_hdr) + sizeof(struct __sc_riscv_v_state) + riscv_v_vsize; + + riscv_zicfiss_sc_size = sizeof(struct __riscv_ctx_hdr) + + sizeof(struct __sc_riscv_cfi_state); /* * Determine the stack space required for guaranteed signal delivery. * The signal_minsigstksz will be populated into the AT_MINSIGSTKSZ entry diff --git a/arch/riscv/kernel/usercfi.c b/arch/riscv/kernel/usercfi.c index 3a66f149a4ef..6e561256bfaf 100644 --- a/arch/riscv/kernel/usercfi.c +++ b/arch/riscv/kernel/usercfi.c @@ -52,6 +52,11 @@ void set_active_shstk(struct task_struct *task, unsigned long shstk_addr) task->thread_info.user_cfi_state.user_shdw_stk = shstk_addr; } +unsigned long get_active_shstk(struct task_struct *task) +{ + return task->thread_info.user_cfi_state.user_shdw_stk; +} + void set_shstk_status(struct task_struct *task, bool enable) { task->thread_info.user_cfi_state.ubcfi_en = enable ? 1 : 0; @@ -164,6 +169,57 @@ static int create_rstor_token(unsigned long ssp, unsigned long *token_addr) return 0; } +/* + * Save user shadow stack pointer on shadow stack itself and return pointer to saved location + * returns -EFAULT if operation was unsuccessful + */ +int save_user_shstk(struct task_struct *tsk, unsigned long *saved_shstk_ptr) +{ + unsigned long ss_ptr = 0; + unsigned long token_loc = 0; + int ret = 0; + + if (saved_shstk_ptr == NULL) + return -EINVAL; + + ss_ptr = get_active_shstk(tsk); + ret = create_rstor_token(ss_ptr, &token_loc); + + if (!ret) { + *saved_shstk_ptr = token_loc; + set_active_shstk(tsk, token_loc); + } + + return ret; +} + +/* + * Restores user shadow stack pointer from token on shadow stack for task `tsk` + * returns -EFAULT if operation was unsuccessful + */ +int restore_user_shstk(struct task_struct *tsk, unsigned long shstk_ptr) +{ + unsigned long token = 0; + + token = amo_user_shstk((unsigned long __user *)shstk_ptr, 0); + + if (token == -1) + return -EFAULT; + + /* invalid token, return EINVAL */ + if ((token - shstk_ptr) != SHSTK_ENTRY_SIZE) { + pr_info_ratelimited( + "%s[%d]: bad restore token in %s: pc=%p sp=%p, token=%p, shstk_ptr=%p\n", + tsk->comm, task_pid_nr(tsk), __func__, (void *)(task_pt_regs(tsk)->epc), + (void *)(task_pt_regs(tsk)->sp), (void *)token, (void *)shstk_ptr); + return -EINVAL; + } + + /* all checks passed, set active shstk and return success */ + set_active_shstk(tsk, token); + return 0; +} + static unsigned long allocate_shadow_stack(unsigned long addr, unsigned long size, unsigned long token_offset, bool set_tok) { From patchwork Mon Mar 10 14:52:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 872330 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3B27237718 for ; Mon, 10 Mar 2025 14:53:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618399; cv=none; b=Sq6iuhQoXKE4tk9JDZxn8LDqbuRS3tYCbkKeuECjewZJRdwOJpTN491BqAxO/jlAhQPn0bGtmV1l+7gVVZb66k+TE7ZKwXggRlVPt4xPxM78nlGLFonxNzzJQaNuMk6dKZHSM8pTBOJZJrXqLLLtOgolHkys13r9Iv3JqyahbHY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618399; c=relaxed/simple; bh=no//4s1hCd1n+ijW2BrzZfXeDu40oLpUpqqQfLr6u/M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hcPa7qAx4P5uL751qCOK6O5+S2PvKF0dvYCIHBAMY67g6Rqtkh1LrQdjiSzXeEdiBTvmB1Bj4jInIEwPvqFr6mBOQ0FoMJ19VQh0q9YLRYMUCbIUPkuezykTY08HIitmth/n1WKXxyhF7k4fKsyfbAJsLp9gfxI2XCjWjbZzgy4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=q7Y7ULmP; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="q7Y7ULmP" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-219f8263ae0so81545015ad.0 for ; Mon, 10 Mar 2025 07:53:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741618397; x=1742223197; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qihiC//CQppmEvCBgeNt37whYo0mSsmsLXBW9eHBYhI=; b=q7Y7ULmPK32MW3OtlYUCGdsP9cufm0C+WkOCAOrO7VD7tnMku/M7tZF2RS2+bbW3K9 GkoTZvR02Jh/6b87JS70oTo/ItSNFXe+crjkhM249Pl5E7YhnD+8kC/KTo0k5jx/y/cg 2plYyLCz3Pyz9sVY6idSrlB/Njx6XPgg8x9WsExcDSkWPC7s3wOlG7eOuJPVq8FFNNBP 3GZwb1B+fFpG+rkNJSvZ1of202xXfjd2JfWpsRiSbNCLth78bc6VB5vr3AtFoli9u15R yYsyuf8zADv/1hdAlXDnWKprDaQq3fuvJVaQ1/X5v8qAtANBk5tqonfO8shn5HiiTVuK NSjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741618397; x=1742223197; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qihiC//CQppmEvCBgeNt37whYo0mSsmsLXBW9eHBYhI=; b=TkWUhxsaufcWi/6QhE52ypAOUAha742zgS6N+h8kpWUNJHDXBB/B8smHwteD3PutNx CWOC1oQRL/KpArJoWwl2fVY3xdoiMLsdgSP7N2kGydJS6xpxnc2l+TpNoSEhAQg6SztM Eho0BHzqDDhvcOs9C9BrPEGj7kRupNHhFrD1iBV/c0DdQGMAjhWCMu/XWkUoo4Orlh/K FksLQdOwAhKsT/caFhl5L0AVaVftwHzfQqLD7NtUlOk56VCEU4tj+RBNdtK/AkCQEENX XWv95Y4AqRtwiCy6E5CFDoiAHlsa8eOvNh5hx+ZgVbkh6JPpmQV2OFz0GDffLSr9qfwp O1Sg== X-Forwarded-Encrypted: i=1; AJvYcCW+KnYnx4CuDFqpx0V6/1dIHEMyWj6xRZ6EG//FHtquEjMB41FRZhlqkOstGCs8CXhj28ECajEOS6biuNSZo0Y=@vger.kernel.org X-Gm-Message-State: AOJu0YxchgNluDuUgdj7y2zAym+PitZuuLEzUNpoWtaVYfIX7zulPptz yivy+S86SW/yrZa0XRKfuD5+1M+VI2PdmBtQlldo4+MMKlkz96HMjT4KomuIgJQ= X-Gm-Gg: ASbGncv7DRvM9DX/hXVbar7sszCqRuhNRNJLFWpT5ju2Es5/fyMvUT01LBj9U3ScPwn AkiO7AF5iIaXh4Y+i6zkZ6kJ0+8eQfNlTWBOFMSp1dY2fEfdhQu9lzGy6FJUNcc5KVLKp7PpzQX sHc5CghQaoX8a3eCAVaTvHthiA7JaraqRhrUtHqKFEDL/t9RtHNlxLrtdMhi5K15JpGuNrTN2QZ y0NtMWgRi+PeEogU96rHfFh0zI/t357+GkyBw7dGvAmjyggsb5SIEysvUMbZEfX5TQwmMVBQMU0 Dg7ATgiC2Ihv+JN7qFCNWZWlvqEmt8DTkAxwgUQCgXXZQOy4vAmvbm0= X-Google-Smtp-Source: AGHT+IHLu0RD5d4MddLFDjOWYpbnLGPGC73GF+e3WfGfDfnCowno5o+D7aYjLyREna2LMovQQemWaA== X-Received: by 2002:a05:6a00:c92:b0:736:8c0f:774f with SMTP id d2e1a72fcca58-736eb8a1ccbmr221171b3a.22.1741618396770; Mon, 10 Mar 2025 07:53:16 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736d11d4600sm2890275b3a.116.2025.03.10.07.53.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Mar 2025 07:53:16 -0700 (PDT) From: Deepak Gupta Date: Mon, 10 Mar 2025 07:52:40 -0700 Subject: [PATCH v11 18/27] riscv/ptrace: riscv cfi status and state via ptrace and in core files Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250310-v5_user_cfi_series-v11-18-86b36cbfb910@rivosinc.com> References: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> In-Reply-To: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 Expose a new register type NT_RISCV_USER_CFI for risc-v cfi status and state. Intentionally both landing pad and shadow stack status and state are rolled into cfi state. Creating two different NT_RISCV_USER_XXX would not be useful and wastage of a note type. Enabling or disabling of feature is not allowed via ptrace set interface. However setting `elp` state or setting shadow stack pointer are allowed via ptrace set interface. It is expected `gdb` might have use to fixup `elp` state or `shadow stack` pointer. Signed-off-by: Deepak Gupta --- arch/riscv/include/uapi/asm/ptrace.h | 18 ++++++++ arch/riscv/kernel/ptrace.c | 83 ++++++++++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 3 files changed, 102 insertions(+) diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h index 659ea3af5680..e6571fba8a8a 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -131,6 +131,24 @@ struct __sc_riscv_cfi_state { unsigned long ss_ptr; /* shadow stack pointer */ }; +struct __cfi_status { + /* indirect branch tracking state */ + __u64 lp_en : 1; + __u64 lp_lock : 1; + __u64 elp_state : 1; + + /* shadow stack status */ + __u64 shstk_en : 1; + __u64 shstk_lock : 1; + + __u64 rsvd : sizeof(__u64) - 5; +}; + +struct user_cfi_state { + struct __cfi_status cfi_status; + __u64 shstk_ptr; +}; + #endif /* __ASSEMBLY__ */ #endif /* _UAPI_ASM_RISCV_PTRACE_H */ diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index ea67e9fb7a58..df8b7c6ab671 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -19,6 +19,7 @@ #include #include #include +#include enum riscv_regset { REGSET_X, @@ -31,6 +32,9 @@ enum riscv_regset { #ifdef CONFIG_RISCV_ISA_SUPM REGSET_TAGGED_ADDR_CTRL, #endif +#ifdef CONFIG_RISCV_USER_CFI + REGSET_CFI, +#endif }; static int riscv_gpr_get(struct task_struct *target, @@ -184,6 +188,75 @@ static int tagged_addr_ctrl_set(struct task_struct *target, } #endif +#ifdef CONFIG_RISCV_USER_CFI +static int riscv_cfi_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + struct user_cfi_state user_cfi; + struct pt_regs *regs; + + regs = task_pt_regs(target); + + user_cfi.cfi_status.lp_en = is_indir_lp_enabled(target); + user_cfi.cfi_status.lp_lock = is_indir_lp_locked(target); + user_cfi.cfi_status.elp_state = (regs->status & SR_ELP); + + user_cfi.cfi_status.shstk_en = is_shstk_enabled(target); + user_cfi.cfi_status.shstk_lock = is_shstk_locked(target); + user_cfi.shstk_ptr = get_active_shstk(target); + + return membuf_write(&to, &user_cfi, sizeof(user_cfi)); +} + +/* + * Does it make sense to allowing enable / disable of cfi via ptrace? + * Not allowing enable / disable / locking control via ptrace for now. + * Setting shadow stack pointer is allowed. GDB might use it to unwind or + * some other fixup. Similarly gdb might want to suppress elp and may want + * to reset elp state. + */ +static int riscv_cfi_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + struct user_cfi_state user_cfi; + struct pt_regs *regs; + + regs = task_pt_regs(target); + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &user_cfi, 0, -1); + if (ret) + return ret; + + /* + * Not allowing enabling or locking shadow stack or landing pad + * There is no disabling of shadow stack or landing pad via ptrace + * rsvd field should be set to zero so that if those fields are needed in future + */ + if (user_cfi.cfi_status.lp_en || user_cfi.cfi_status.lp_lock || + user_cfi.cfi_status.shstk_en || user_cfi.cfi_status.shstk_lock || + !user_cfi.cfi_status.rsvd) + return -EINVAL; + + /* If lpad is enabled on target and ptrace requests to set / clear elp, do that */ + if (is_indir_lp_enabled(target)) { + if (user_cfi.cfi_status.elp_state) /* set elp state */ + regs->status |= SR_ELP; + else + regs->status &= ~SR_ELP; /* clear elp state */ + } + + /* If shadow stack enabled on target, set new shadow stack pointer */ + if (is_shstk_enabled(target)) + set_active_shstk(target, user_cfi.shstk_ptr); + + return 0; +} +#endif + static const struct user_regset riscv_user_regset[] = { [REGSET_X] = { .core_note_type = NT_PRSTATUS, @@ -224,6 +297,16 @@ static const struct user_regset riscv_user_regset[] = { .set = tagged_addr_ctrl_set, }, #endif +#ifdef CONFIG_RISCV_USER_CFI + [REGSET_CFI] = { + .core_note_type = NT_RISCV_USER_CFI, + .align = sizeof(__u64), + .n = sizeof(struct user_cfi_state) / sizeof(__u64), + .size = sizeof(__u64), + .regset_get = riscv_cfi_get, + .set = riscv_cfi_set, + }, +#endif }; static const struct user_regset_view riscv_user_native_view = { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index b44069d29cec..b9daed4ab780 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -452,6 +452,7 @@ typedef struct elf64_shdr { #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */ #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */ #define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (prctl()) */ +#define NT_RISCV_USER_CFI 0x903 /* RISC-V shadow stack state */ #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */ #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */ From patchwork Mon Mar 10 14:52:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 872329 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 233ED238D39 for ; Mon, 10 Mar 2025 14:53:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618403; cv=none; b=KWU9wbJ+SmwZlqQOv3wthDhhNBWSud1+3dHo4pA+J2fx9hHNvRfxr1rICSexQN63n4l9A1axZWYgkzeYelKUznOjC/LDIqYjQp2EHqT0LvGHGKbAR0WQdJ9rNB8JNUn6t/dqqrCvJzVYLMTXnmHsuZziC40mmcLf+GgfS7Z0gYs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618403; c=relaxed/simple; bh=lD6rgHPb/ib2WH9dder9ZLKtBlS2SotatDP0DK7YItE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pELTCWsOtXzBOL9pmjp3r1FLQqKolNuYFGNaXMw+Y/CnFqI/XgkkzTDk9UU5KMxXUiqxY/xIu+agmIoTgUWdw2fdpdae4GuKNPPr/2Hk/R1zFkAMS5pm4vcKkOiX44SiHkYeURoKgifv6VaAwKId2cgGrYQ+mcts2NqcCU5MAs0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=Ct+JB6P8; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="Ct+JB6P8" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-224191d92e4so73633075ad.3 for ; Mon, 10 Mar 2025 07:53:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741618402; x=1742223202; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=a5uI84SXblQRDID2BHNWhhHsRc7xVUDdoiei4kS9c/0=; b=Ct+JB6P8gBFhU2GL68I9x56icjkLjP62AapuT2jcDeENjphhxaGGU3o+qC8dvKrJ0g 2VfkE9773u7mT4/bPGU8BwIZlfR+Ynatelwu14iYwVM6exIiH6gjp+3B4XjVdJfL4EYs 4qC50m+e0mG7AbBt3fM2AWvnhDyCBIpD8l2BTMQceznIti+vPI3gt2Y8jENfIaqA2a9t YRel1XQSF1IYenBIUAg/xE4OMXKixw6zVwXIxoQBEQQPIM3e5Gk7KDzclPmCj/1bCMaG In0BU9boVSJlZ7ykEefPbMdFA3Qx0QxQ6esFxVSSS91DR0SnEDmlQDd66ojWVQcUwJ2q gKZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741618402; x=1742223202; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a5uI84SXblQRDID2BHNWhhHsRc7xVUDdoiei4kS9c/0=; b=MQNfxX9QL+tzUBbhk+mhprY1SARIRS5a+sLqJuBM02KbmU8B+lMrVQdByckZiv8CMf acAMUhEaNUyRE/ihS4YJFC0aVHfg7BM4r2BRyd9LGA8NeE2pqza9EFPyNcDnT8GmPsRZ 2s5CKrBu0ZRyh92Xn1SF+QfveK2y8i31m9l/eE6UYfvy46ToTjO372RGfukdtEM543tb QAMlhJC1Lq85cdOGyBodTEY7ZV/EQjMU9FbNe169gdIBmKeoL2N/5OrQzyDbif2tosf2 cwG6UvkUm7jubbzMwh7XCA1uvM66Vl0Po7inPwzB0kSSUvDGfWqqHwiL+SIiX8kRhMVh H8Yg== X-Forwarded-Encrypted: i=1; AJvYcCVCPJ5+ruzWWF7DhoFMXDHKbBSS1dI6GJptLDXyR56zVrSYFOGTdUisdkXMHLyHc2jno/B8JZ5buvGwbg1vSSE=@vger.kernel.org X-Gm-Message-State: AOJu0YyNZUVSaszCiKfMerl8yPEwU4XukW+FE+iM2CzHpCCUk8DsmkX5 ZX0vlt0S0m2diGQSpR+L6axHL/Vt5CopgKv9rVkU7T+FTkFKjg8uImFnFK72H3Q= X-Gm-Gg: ASbGncsFKDR325VaZ06YYK/wT4tjf0OYDLRWAJs23TrrMUtIdvjPxywSddWdhHN6/dF J9Anxi/KlP4aGxENZLPlEKdjN+ASasmaxPfZseYoG7REoj6dW0nR9jHPRkCAlU15oT73Wg+S1YU K6sfkoKGIeHi+ciFLQMiO0vG+uIVN2Q6B/7Q8bNjNB+y4iqrpxgbt6KFasX93SvGEIkc9x/h2bb OdPTxu1Dauc9E9FVUobLIP02ZIDa/w8c9zD5IyrRkDB9BBvwgZqReX4e1LSbcNs7owqSj8CJzP/ Gyh7wW0KQcJZruWNn5ah/qvmsgdGlXuryFWbHm+FbsxtsJP77mOrWcc= X-Google-Smtp-Source: AGHT+IFjDwjQ9fbG75ByIkC5Z62BpsOlmfgaoy0NDr7CGAoT4eOeNPAoaYep0Q4HRAItC/SdOQSQyA== X-Received: by 2002:a05:6a00:4b4a:b0:736:54c9:df2c with SMTP id d2e1a72fcca58-736aaab75e8mr18259867b3a.15.1741618401679; Mon, 10 Mar 2025 07:53:21 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736d11d4600sm2890275b3a.116.2025.03.10.07.53.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Mar 2025 07:53:21 -0700 (PDT) From: Deepak Gupta Date: Mon, 10 Mar 2025 07:52:42 -0700 Subject: [PATCH v11 20/27] riscv: Add Firmware Feature SBI extensions definitions Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250310-v5_user_cfi_series-v11-20-86b36cbfb910@rivosinc.com> References: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> In-Reply-To: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com X-Mailer: b4 0.14.0 From: Clément Léger Add necessary SBI definitions to use the FWFT extension. Signed-off-by: Clément Léger --- arch/riscv/include/asm/sbi.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 3d250824178b..23bfb254e3f4 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -35,6 +35,7 @@ enum sbi_ext_id { SBI_EXT_DBCN = 0x4442434E, SBI_EXT_STA = 0x535441, SBI_EXT_NACL = 0x4E41434C, + SBI_EXT_FWFT = 0x46574654, /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START = 0x08000000, @@ -401,6 +402,31 @@ enum sbi_ext_nacl_feature { #define SBI_NACL_SHMEM_SRET_X(__i) ((__riscv_xlen / 8) * (__i)) #define SBI_NACL_SHMEM_SRET_X_LAST 31 +/* SBI function IDs for FW feature extension */ +#define SBI_EXT_FWFT_SET 0x0 +#define SBI_EXT_FWFT_GET 0x1 + +enum sbi_fwft_feature_t { + SBI_FWFT_MISALIGNED_EXC_DELEG = 0x0, + SBI_FWFT_LANDING_PAD = 0x1, + SBI_FWFT_SHADOW_STACK = 0x2, + SBI_FWFT_DOUBLE_TRAP = 0x3, + SBI_FWFT_PTE_AD_HW_UPDATING = 0x4, + SBI_FWFT_LOCAL_RESERVED_START = 0x5, + SBI_FWFT_LOCAL_RESERVED_END = 0x3fffffff, + SBI_FWFT_LOCAL_PLATFORM_START = 0x40000000, + SBI_FWFT_LOCAL_PLATFORM_END = 0x7fffffff, + + SBI_FWFT_GLOBAL_RESERVED_START = 0x80000000, + SBI_FWFT_GLOBAL_RESERVED_END = 0xbfffffff, + SBI_FWFT_GLOBAL_PLATFORM_START = 0xc0000000, + SBI_FWFT_GLOBAL_PLATFORM_END = 0xffffffff, +}; + +#define SBI_FWFT_GLOBAL_FEATURE_BIT (1 << 31) +#define SBI_FWFT_PLATFORM_FEATURE_BIT (1 << 30) + +#define SBI_FWFT_SET_FLAG_LOCK (1 << 0) /* SBI spec version fields */ #define SBI_SPEC_VERSION_DEFAULT 0x1 From patchwork Mon Mar 10 14:52:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 872328 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B89722541D for ; Mon, 10 Mar 2025 14:53:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618409; cv=none; b=WNlMduhjSIoRWIsBW8I7Gtc6tpr5ggo8hbVZ1bxxdfxZfvtt3GhDmsarj5gCMEmveiQZEZlYGkiaDQhQqC4BFBRjZ1TL57FoP+X/GTOy2nA+U1+nErUf1Xh02wQ7kp4iuHf58sdYtnkePJ/DNoMaoSvXOKSu+b2aXt6gBaA5AF4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618409; c=relaxed/simple; bh=zWvCMjEUr0fm2YGOtkO5JQMRJ3MfHFejTQpY2YYRpeI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TqtZ8GacdZlgs5oVGUYnCutQlf5lWny/Faxr58xO+gycVnZj+YdUgFgoQ6Wd/ZDR/tlmvEiw0QeOADvyXkJ4zcJQJdePt7PlUkW5Y20DJs/NdJFZ3LLYv7oP3IOp1y3eEfGdnDEvh6rgG//peOSMtZTRVEktQk/xsgFIhfAcZBQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=02fXvqYm; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="02fXvqYm" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-2232aead377so13138525ad.0 for ; Mon, 10 Mar 2025 07:53:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741618406; x=1742223206; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=opxHamP1ejpgUrZttGLg4zwDHWHLF3xPs1/Qb/08WRM=; b=02fXvqYmI7IQzrMpZK7gWQgvRJrftC9vOY2QlY/CM8V2HigjhV+w/NhLxRTeEtYott S2q7kSjN72yJa5Ufr7WNsgAxBQaPRxaPtmQ14/lwF1on8E1MOrns3WfNwEZCQNFrYfxl GX52zg5xG6UIPsdCmuXWJna4/t0SmvTqPIp2e0KDF5gTKiAT1Amm+d7ScFnLCsHzXtGI FEyqvUmVtYaQI/Zb7K1ksG7qzmbIOSeCsvQqszo50mYTw1QzcKG9b/fXneMLRQWsQOnq bg32wUkKQoBy8zsP0AAuBeuiOmbpUWRyIMYciP3/LXXmnjAuZ1ZA/9PzQt0oY9ba4Agc 5BPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741618406; x=1742223206; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=opxHamP1ejpgUrZttGLg4zwDHWHLF3xPs1/Qb/08WRM=; b=IXjGbZS0mjgwzwUateiGta9nrGvguVZ6oabxmdqN0TYH4H6xl4qc6LRz9JBIXXPImT tPiUmx7iCKZxYzxvMOiThJmCXfJqdJDIP4xIWoU5G5iH86uQKZ3ufcDXXfDfgpvuBloP BqwRVS0bMU5n47W1tbEsLjSgh4kZ980fM+2Hw/8kSca8PuXn74ILIUrBHtKrsijhDLmZ Q+AuW6q9HFs1p5kfboErcL9AkVeiGMfGE0RhD5lUWxGb7SpfgrJQ8rhEG1CZiJTovVtH U5O3oG/79xb0QMvfIMCPN9aEuwVovOLx/0K+FUqHWKVfv65UYu4Gd917tlM2aw/j2AEE kOtQ== X-Forwarded-Encrypted: i=1; AJvYcCWRdytcA6dNFJINoyOTsYkkMn4vgEcPvHTeV5ZUtS/3/7LQHTkTP3GO+WwxcrVvdlzZ2TPv8/YhvcMJSMhLorY=@vger.kernel.org X-Gm-Message-State: AOJu0Yxdyjh/2ZLJKc7alNmy3jPXw7DuoOWNHqFXG4HnseTOcajFi2e2 RZVmbWpkajsS7VLsDdz7+/qbwkMcM4eJz/Z+xN6UoVyUvTmmMXVCD9qOmNzNWEY= X-Gm-Gg: ASbGncsqxcVCSHYkNAq3cyF2AIswpUIwWXXawstsTKCBG2JM63qZ434TQeZxTcEUV5f XAMjBq25AXTaZYk5krOqUZblFFnIO9n7PALFwiU29Xkp+gd16j4L/smQtoVNyMUaE4v1/1yG0NF bOKF+4vjlfWg5oFQZP8FoVFE1t9j6jCkt2b63Tt+LIxBs+xe6sGjFbaPGO0X/sKFs71DUfPzo0s sF8wCMQLCy+Ad88vWFKfcxrYY0+WnnuDSMK/h50/G/mRC+qUzMjBa9L1WfkCdnK5FQ1QwFI7xG6 zfVRNGdDPFgU6xGzuTvOh6ZR4NgimdOy/6vlcx5BIYh8gEcSAyO1qqg= X-Google-Smtp-Source: AGHT+IGghOp+j7sQ0Qt7sq7k8fXJkHLz3hwRxKC8iR81NfpyoYASRowQ1NRmeDSzKjKxRLkZDMtKZA== X-Received: by 2002:a62:fb06:0:b0:736:baa0:2acd with SMTP id d2e1a72fcca58-736baa02af4mr14991022b3a.20.1741618406530; Mon, 10 Mar 2025 07:53:26 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736d11d4600sm2890275b3a.116.2025.03.10.07.53.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Mar 2025 07:53:26 -0700 (PDT) From: Deepak Gupta Date: Mon, 10 Mar 2025 07:52:44 -0700 Subject: [PATCH v11 22/27] riscv: kernel command line option to opt out of user cfi Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250310-v5_user_cfi_series-v11-22-86b36cbfb910@rivosinc.com> References: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> In-Reply-To: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 This commit adds a kernel command line option using which user cfi can be disabled. Signed-off-by: Deepak Gupta --- arch/riscv/kernel/usercfi.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/riscv/kernel/usercfi.c b/arch/riscv/kernel/usercfi.c index 6e561256bfaf..be08e5bb6e62 100644 --- a/arch/riscv/kernel/usercfi.c +++ b/arch/riscv/kernel/usercfi.c @@ -17,6 +17,8 @@ #include #include +bool disable_riscv_usercfi; + #define SHSTK_ENTRY_SIZE sizeof(void *) bool is_shstk_enabled(struct task_struct *task) @@ -390,6 +392,9 @@ int arch_set_shadow_stack_status(struct task_struct *t, unsigned long status) unsigned long size = 0, addr = 0; bool enable_shstk = false; + if (disable_riscv_usercfi) + return 0; + if (!cpu_supports_shadow_stack()) return -EINVAL; @@ -469,6 +474,9 @@ int arch_set_indir_br_lp_status(struct task_struct *t, unsigned long status) { bool enable_indir_lp = false; + if (disable_riscv_usercfi) + return 0; + if (!cpu_supports_indirect_br_lp_instr()) return -EINVAL; @@ -501,3 +509,16 @@ int arch_lock_indir_br_lp_status(struct task_struct *task, return 0; } + +static int __init setup_global_riscv_enable(char *str) +{ + if (strcmp(str, "true") == 0) + disable_riscv_usercfi = true; + + pr_info("Setting riscv usercfi to be %s\n", + (disable_riscv_usercfi ? "disabled" : "enabled")); + + return 1; +} + +__setup("disable_riscv_usercfi=", setup_global_riscv_enable); From patchwork Mon Mar 10 14:52:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 872327 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD0E523E25D for ; Mon, 10 Mar 2025 14:53:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618414; cv=none; b=UrV0CEyEF4V6QUMlxlqiorKVrNIew989BsOiPhc0mcNDzAJZRnFKo7f4CvRc3r+QLTus5GbAvireVKOW8zM3xulqWoYHddM7FYqogP9eXE0ZmyiXlKeUwNuU1opUJ93ijXYWQqTunhosXa3m6SNb6DrLciwaXHnJ2HErJnFobs0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618414; c=relaxed/simple; bh=Eua84f2QnuJ0+u1eEfH6+3KRo1p7kHINzNbKNk8bPkI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YHN44KYPlD9Nk5NgrwVzT2daLvViWHfZ1jg3XgxOSwzgMyRBfwxpKaSCOhBHA4Cgq/XWxFtUs0yZVd70URl+NwqZn8txY4+5wZedZue+EgJigfJ5/iRWItYCh848bQinJeqB54TVK6Yz43Ck/UEJoTbSKkmC6rVZiGpiabWoazE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=O8fbsLvd; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="O8fbsLvd" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-223fd89d036so84683385ad.1 for ; Mon, 10 Mar 2025 07:53:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741618411; x=1742223211; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9LN1OOVFFK55bIQe9Bj7KSCICvDpdODqLxcVYOIQy28=; b=O8fbsLvdnD8UIpI0UlJYiIL1lmGzpKtFjWwms4QoY9YaH3g/9k1ytjjnEo0uM2m9Yy W2+Y6867Upup1zQj5IAU2dgH03j17eT/1zaY4BVmuJM23jmrrJXgehS3ICvbG7LfdfIZ QP2E02aEVi+J+ESa6fcPFwgqfT1ZxOVBUvlgBG8sImxddE4P/II57EuZQZcClr/HMaRD oSwMqUtUIZGhXodE0rBBd8Kx7q8fN3Z95Lo63cCYt1ivb9PhTmekIeiV6/dPI7mm1Uk7 12q7qlXE1j2tlsZ93G7j8IaJlk3TYZY8BGZDhnhxsag4zLwfdFjZDxV1TEZUwFAQzL9p YXig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741618411; x=1742223211; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9LN1OOVFFK55bIQe9Bj7KSCICvDpdODqLxcVYOIQy28=; b=obOGgwo0zgCMXKQDirKEQ6q/mp6JBWvaLJuHiVQczy9fHYVgvI6cr6eQP20oUBsoVT adaeYt/lfmwtWCvH1aPgIuemQCTpdJ08Fp7kmt3sIP3L+dEjvme1byGLQHM62H3HiPX5 gYFXyPTRPDiS96octJBJ/hG0Zk/VeaKRQ9odI/0WgOL7lwZCn//PbbmQiSniYyBgVXN6 iTobNhgg/TAWUlj4dxivENXXcSPegxftoVPr2t3HUzFyBl3XFw27SECEy3hIEvO0LDkW Esv/qQ+jSVHTwgJpPEEWJFgCNjNourc5NfBVos5LNkZl0DoT59Il3O4mxUD+JNaeIDhU Qdng== X-Forwarded-Encrypted: i=1; AJvYcCXQshXJUf68oJTSkE6iCaTTI8P81NaFj+CMeXbCAskY1oPQ/JO1yFbblHzA7xUWvaos4c4x9iK7OkmQgAj0Azk=@vger.kernel.org X-Gm-Message-State: AOJu0YxbgvQqgh+Z+clbsaVtxO1z9ZAG11uNraJvoKwUlsflTJNS7arX P0Od2xfwPzYQ8RYHsEFuIdIFmjDijLN/4iCERpMLu5YM3tKMPSDF7QgJV7lCWL4= X-Gm-Gg: ASbGncvFJqjQu1SszOGZ8d9vMVC9VlV4jm7tsMWte7bpG+7XnBfwuKYn9AzamMMG/bq IQUDYo9MEU7Dg8joRX2AtVXybWQ+pQN1ArBd2mtlRTlZlMM+ZanR40v++zEE4HpGGJmvBR0/ahu RewLb/Rgv8wJ0kJl3b+K7K+y+XdXPEEIqbqecJERg88CRdZ7Lso46WyzOxhp435bm6ib2CcnZpP wYrrzvertdqytJnmd9MD+HHy7NzjkzbRYykQzIvFUQJp1JE4Ya23OSv6ZSJn6OVs9nKjhHGTDiq H111gjBITKpHwdfFxTMD/LW8MuniPrCf5kg5eRxkJ5yvmBkUC3HV4Ws= X-Google-Smtp-Source: AGHT+IG9tC1WaMP/xC1ABIbEOt50ns/8+sJ1nYsKd4Gr0OatbIpLJiaEKJdeufsJkmLrEp7EYv+TbQ== X-Received: by 2002:a05:6a00:928b:b0:736:5dc6:a14b with SMTP id d2e1a72fcca58-736aaa1ace3mr21470128b3a.13.1741618411393; Mon, 10 Mar 2025 07:53:31 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736d11d4600sm2890275b3a.116.2025.03.10.07.53.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Mar 2025 07:53:31 -0700 (PDT) From: Deepak Gupta Date: Mon, 10 Mar 2025 07:52:46 -0700 Subject: [PATCH v11 24/27] riscv: create a config for shadow stack and landing pad instr support Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250310-v5_user_cfi_series-v11-24-86b36cbfb910@rivosinc.com> References: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> In-Reply-To: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 This patch creates a config for shadow stack support and landing pad instr support. Shadow stack support and landing instr support can be enabled by selecting `CONFIG_RISCV_USER_CFI`. Selecting `CONFIG_RISCV_USER_CFI` wires up path to enumerate CPU support and if cpu support exists, kernel will support cpu assisted user mode cfi. If CONFIG_RISCV_USER_CFI is selected, select `ARCH_USES_HIGH_VMA_FLAGS`, `ARCH_HAS_USER_SHADOW_STACK` and DYNAMIC_SIGFRAME for riscv. Signed-off-by: Deepak Gupta --- arch/riscv/Kconfig | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7612c52e9b1e..0a2e50f056e8 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -250,6 +250,26 @@ config ARCH_HAS_BROKEN_DWARF5 # https://github.com/llvm/llvm-project/commit/7ffabb61a5569444b5ac9322e22e5471cc5e4a77 depends on LD_IS_LLD && LLD_VERSION < 180000 +config RISCV_USER_CFI + def_bool y + bool "riscv userspace control flow integrity" + depends on 64BIT && $(cc-option,-mabi=lp64 -march=rv64ima_zicfiss) + depends on RISCV_ALTERNATIVE + select ARCH_HAS_USER_SHADOW_STACK + select ARCH_USES_HIGH_VMA_FLAGS + select DYNAMIC_SIGFRAME + help + Provides CPU assisted control flow integrity to userspace tasks. + Control flow integrity is provided by implementing shadow stack for + backward edge and indirect branch tracking for forward edge in program. + Shadow stack protection is a hardware feature that detects function + return address corruption. This helps mitigate ROP attacks. + Indirect branch tracking enforces that all indirect branches must land + on a landing pad instruction else CPU will fault. This mitigates against + JOP / COP attacks. Applications must be enabled to use it, and old user- + space does not get protection "for free". + default y + config ARCH_MMAP_RND_BITS_MIN default 18 if 64BIT default 8 From patchwork Mon Mar 10 14:52:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 872326 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1026E23F26B for ; Mon, 10 Mar 2025 14:53:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618419; cv=none; b=f/wHFiADvSR0o85b56JM/Hc8fu+VVt7a0lqD3vTB80f/BP+MmGmOezQXeiAE9x0TvjlEHq1I/dHsPzwmEhlwlGksjFnyOI4kiEbhmgwydWWWCPW/+6yJJuzmjEz4L+wor8hM+xsDSIsz96qPUhaWFV0ZNoWmRrDelBGW1Pswsek= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741618419; c=relaxed/simple; bh=o8EriA1inC7Heg917dIVYKG2AAC4jWIU3SL9yJoIqng=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=C7HSs8I5CywIhK96gsLwrAIT3MUSV3BSgnSU7QjVvoqnui427/I1CZUlb/J7W7/bxOzEWZQuCJRR1ClCeQ3rSZysoQsoFuVcvRdAZQUVrslfd6eTqQpRtYcVjtMIEOl3PlthKgd6JE3U/5Y9Eb9QsfBuaK2rlM0JnTn//pucY1E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=vqVfAmUI; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="vqVfAmUI" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-223378e2b0dso62392395ad.0 for ; Mon, 10 Mar 2025 07:53:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741618416; x=1742223216; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=tdDNQkSVTKtNTxsV0uSmAnlAiDQNW7ggaTdWphzDp8I=; b=vqVfAmUIeSLsKZpVUcenMx3iA0NsdIqkEXwKjudMTi5Lkcr9lENJgGj4GQf5lvwldD Nc6URQgtTlSfD3D8h113d4HKtz7eS1teZ461xB0UdVzm2b3UCmzL27mrnvOU+wGI790z iYccPjiiw1wFvG6PkBmI2h262oiMoq0bpJd3Pna4K//r8k4moOiFoadA3ph09j/8m0U6 JbgfCM7uENp44E+q3yfrHHPYtcC99iE3JXiiehim6uwj04JGSoC9TDCSLbrh8IpxT3A0 NWjEMCd/sws5mP6u64Wqdp/6SCvgzmE/xpTnuY24lNHXRzKrNaN1wShoQX9MrwbbNmON QYlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741618416; x=1742223216; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tdDNQkSVTKtNTxsV0uSmAnlAiDQNW7ggaTdWphzDp8I=; b=Tuglvx2zvINpZMRMvtAILSii/MXwVqfz5TlzBHU6wM6L95B/F2wkFHSnQzaSKpiSZ8 hJC2lSsTp6OAIeabwG8HJYLibtTZfpJuo6W2itmm5ZwNkWChvZNnXRIs/G5a0QMHzstP eN8DWOB4VXIP7Beqc7IUiRCCGf/xxjUaoZPOOlax3UtcU7Lv/M0FGX89M+pblhaPGcXn tYv8GphGPsTaMNJ0PXnvNXK412tmK/nrgo6s1gcVlHj2rT2OxTm6s7aomk5AxCNEG5zA 2RhQhNKYKc60J9Uq0pbiJpKYid/Yb6OHVtSJZF8TNymE+ia0aYWqMzpBGPq0v9NKAyY2 vi8Q== X-Forwarded-Encrypted: i=1; AJvYcCV3x2I+aA/zYrWF7KoIEgeYnnODqtqPjw2zAYCbSZMXp1SsLdt73GiCgL8cayrv6Ry8QsUEOYMAxaU7Ze81zEA=@vger.kernel.org X-Gm-Message-State: AOJu0YyznjS6xktYicP9wc4EGCBIWsXnMcZxOznQVbAC7aFxE5zqdq4w SALOOcIzZvK9ip0mbt0A/S3yNr6x45P/y0t9Pb+3322jq3NJd5P0alPMx+glznk= X-Gm-Gg: ASbGnctqo2gVtCGSWADJmlUOdxE+e16jW0aNTMsys03r9zPFapx3MJsSlAsp1potg6u vsCyNGhRBsqzqicLrXFdoEMKN0pjAIOmqWK8teaRwsLyJsIbONIdt00hIPzuEtkQMHdftcNQVke jl2emr79DbsW/OYxXrdRBd6f62yHK4OU+AX58uy9EywHuHYgWEnMEk5e8RM6ODQz74BqeyD5eBz 9g9RlHik81/fQY81iM5MTVwneVM7XTViNW+zSboIvJKwx6Qhq5hGqV7cgZ+ImVouQm/UoLs1OR2 ejJ9ysZqKaxhUnjuHYBF6UoyLnR6s5W4fIgBX4PkZ4DjS/9X0mmd2DA= X-Google-Smtp-Source: AGHT+IFaFODVJO35zmAo4CgY/g0ssVNrnGer/dAkzpFZFHLuf8O1kgqUgyNRnEx4GJyvPtN1uJ38Mg== X-Received: by 2002:a05:6a21:4606:b0:1f5:7df9:f147 with SMTP id adf61e73a8af0-1f57df9f49dmr7386102637.40.1741618416216; Mon, 10 Mar 2025 07:53:36 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736d11d4600sm2890275b3a.116.2025.03.10.07.53.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Mar 2025 07:53:35 -0700 (PDT) From: Deepak Gupta Date: Mon, 10 Mar 2025 07:52:48 -0700 Subject: [PATCH v11 26/27] riscv: Documentation for shadow stack on riscv Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250310-v5_user_cfi_series-v11-26-86b36cbfb910@rivosinc.com> References: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> In-Reply-To: <20250310-v5_user_cfi_series-v11-0-86b36cbfb910@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 Adding documentation on shadow stack for user mode on riscv and kernel interfaces exposed so that user tasks can enable it. Signed-off-by: Deepak Gupta --- Documentation/arch/riscv/index.rst | 1 + Documentation/arch/riscv/zicfiss.rst | 176 +++++++++++++++++++++++++++++++++++ 2 files changed, 177 insertions(+) diff --git a/Documentation/arch/riscv/index.rst b/Documentation/arch/riscv/index.rst index be7237b69682..e240eb0ceb70 100644 --- a/Documentation/arch/riscv/index.rst +++ b/Documentation/arch/riscv/index.rst @@ -15,6 +15,7 @@ RISC-V architecture vector cmodx zicfilp + zicfiss features diff --git a/Documentation/arch/riscv/zicfiss.rst b/Documentation/arch/riscv/zicfiss.rst new file mode 100644 index 000000000000..5ba389f15b3f --- /dev/null +++ b/Documentation/arch/riscv/zicfiss.rst @@ -0,0 +1,176 @@ +.. SPDX-License-Identifier: GPL-2.0 + +:Author: Deepak Gupta +:Date: 12 January 2024 + +========================================================= +Shadow stack to protect function returns on RISC-V Linux +========================================================= + +This document briefly describes the interface provided to userspace by Linux +to enable shadow stack for user mode applications on RISV-V + +1. Feature Overview +-------------------- + +Memory corruption issues usually result in to crashes, however when in hands of +an adversary and if used creatively can result into variety security issues. + +One of those security issues can be code re-use attacks on program where +adversary can use corrupt return addresses present on stack and chain them +together to perform return oriented programming (ROP) and thus compromising +control flow integrity (CFI) of the program. + +Return addresses live on stack and thus in read-write memory and thus are +susceptible to corruption and allows an adversary to reach any program counter +(PC) in address space. On RISC-V ``zicfiss`` extension provides an alternate +stack termed as shadow stack on which return addresses can be safely placed in +prolog of the function and retrieved in epilog. ``zicfiss`` extension makes +following changes: + +- PTE encodings for shadow stack virtual memory + An earlier reserved encoding in first stage translation i.e. + PTE.R=0, PTE.W=1, PTE.X=0 becomes PTE encoding for shadow stack pages. + +- ``sspush x1/x5`` instruction pushes (stores) ``x1/x5`` to shadow stack. + +- ``sspopchk x1/x5`` instruction pops (loads) from shadow stack and compares + with ``x1/x5`` and if un-equal, CPU raises ``software check exception`` with + ``*tval = 3`` + +Compiler toolchain makes sure that function prologue have ``sspush x1/x5`` to +save return address on shadow stack in addition to regular stack. Similarly +function epilogs have ``ld x5, offset(x2)`` followed by ``sspopchk x5`` to +ensure that popped value from regular stack matches with popped value from +shadow stack. + +2. Shadow stack protections and linux memory manager +----------------------------------------------------- + +As mentioned earlier, shadow stack get new page table encodings and thus have +some special properties assigned to them and instructions that operate on them +as below: + +- Regular stores to shadow stack memory raises access store faults. This way + shadow stack memory is protected from stray inadvertant writes. + +- Regular loads to shadow stack memory are allowed. This allows stack trace + utilities or backtrace functions to read true callstack (not tampered). + +- Only shadow stack instructions can generate shadow stack load or shadow stack + store. + +- Shadow stack load / shadow stack store on read-only memory raises AMO/store + page fault. Thus both ``sspush x1/x5`` and ``sspopchk x1/x5`` will raise AMO/ + store page fault. This simplies COW handling in kernel During fork, kernel + can convert shadow stack pages into read-only memory (as it does for regular + read-write memory) and as soon as subsequent ``sspush`` or ``sspopchk`` in + userspace is encountered, then kernel can perform COW. + +- Shadow stack load / shadow stack store on read-write, read-write-execute + memory raises an access fault. This is a fatal condition because shadow stack + should never be operating on read-write, read-write-execute memory. + +3. ELF and psABI +----------------- + +Toolchain sets up :c:macro:`GNU_PROPERTY_RISCV_FEATURE_1_BCFI` for property +:c:macro:`GNU_PROPERTY_RISCV_FEATURE_1_AND` in notes section of the object file. + +4. Linux enabling +------------------ + +User space programs can have multiple shared objects loaded in its address space +and it's a difficult task to make sure all the dependencies have been compiled +with support of shadow stack. Thus it's left to dynamic loader to enable +shadow stack for the program. + +5. prctl() enabling +-------------------- + +:c:macro:`PR_SET_SHADOW_STACK_STATUS` / :c:macro:`PR_GET_SHADOW_STACK_STATUS` / +:c:macro:`PR_LOCK_SHADOW_STACK_STATUS` are three prctls added to manage shadow +stack enabling for tasks. prctls are arch agnostic and returns -EINVAL on other +arches. + +* prctl(PR_SET_SHADOW_STACK_STATUS, unsigned long arg) + +If arg1 :c:macro:`PR_SHADOW_STACK_ENABLE` and if CPU supports ``zicfiss`` then +kernel will enable shadow stack for the task. Dynamic loader can issue this +:c:macro:`prctl` once it has determined that all the objects loaded in address +space have support for shadow stack. Additionally if there is a +:c:macro:`dlopen` to an object which wasn't compiled with ``zicfiss``, dynamic +loader can issue this prctl with arg1 set to 0 (i.e. +:c:macro:`PR_SHADOW_STACK_ENABLE` being clear) + +* prctl(PR_GET_SHADOW_STACK_STATUS, unsigned long *arg) + +Returns current status of indirect branch tracking. If enabled it'll return +:c:macro:`PR_SHADOW_STACK_ENABLE`. + +* prctl(PR_LOCK_SHADOW_STACK_STATUS, unsigned long arg) + +Locks current status of shadow stack enabling on the task. User space may want +to run with strict security posture and wouldn't want loading of objects +without ``zicfiss`` support in it and thus would want to disallow disabling of +shadow stack on current task. In that case user space can use this prctl to +lock current settings. + +5. violations related to returns with shadow stack enabled +----------------------------------------------------------- + +Pertaining to shadow stack, CPU raises software check exception in following +condition: + +- On execution of ``sspopchk x1/x5``, ``x1/x5`` didn't match top of shadow + stack. If mismatch happens then cpu does ``*tval = 3`` and raise software + check exception. + +Linux kernel will treat this as :c:macro:`SIGSEV`` with code = +:c:macro:`SEGV_CPERR` and follow normal course of signal delivery. + +6. Shadow stack tokens +----------------------- +Regular stores on shadow stacks are not allowed and thus can't be tampered +with via arbitrary stray writes due to bugs. Method of pivoting / switching to +shadow stack is simply writing to csr ``CSR_SSP`` changes active shadow stack. +This can be problematic because usually value to be written to ``CSR_SSP`` will +be loaded somewhere in writeable memory and thus allows an adversary to +corruption bug in software to pivot to an any address in shadow stack range. +Shadow stack tokens can help mitigate this problem by making sure that: + +- When software is switching away from a shadow stack, shadow stack pointer + should be saved on shadow stack itself and call it ``shadow stack token`` + +- When software is switching to a shadow stack, it should read the + ``shadow stack token`` from shadow stack pointer and verify that + ``shadow stack token`` itself is pointer to shadow stack itself. + +- Once the token verification is done, software can perform the write to + ``CSR_SSP`` to switch shadow stack. + +Here software can be user mode task runtime itself which is managing various +contexts as part of single thread. Software can be kernel as well when kernel +has to deliver a signal to user task and must save shadow stack pointer. Kernel +can perform similar procedure by saving a token on user shadow stack itself. +This way whenever :c:macro:`sigreturn` happens, kernel can read the token and +verify the token and then switch to shadow stack. Using this mechanism, kernel +helps user task so that any corruption issue in user task is not exploited by +adversary by arbitrarily using :c:macro:`sigreturn`. Adversary will have to +make sure that there is a ``shadow stack token`` in addition to invoking +:c:macro:`sigreturn` + +7. Signal shadow stack +----------------------- +Following structure has been added to sigcontext for RISC-V:: + + struct __sc_riscv_cfi_state { + unsigned long ss_ptr; + }; + +As part of signal delivery, shadow stack token is saved on current shadow stack +itself and updated pointer is saved away in :c:macro:`ss_ptr` field in +:c:macro:`__sc_riscv_cfi_state` under :c:macro:`sigcontext`. Existing shadow +stack allocation is used for signal delivery. During :c:macro:`sigreturn`, +kernel will obtain :c:macro:`ss_ptr` from :c:macro:`sigcontext` and verify the +saved token on shadow stack itself and switch shadow stack.