From patchwork Tue Mar 11 19:44:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 872669 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2072.outbound.protection.outlook.com [40.107.94.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50F0C264638; Tue, 11 Mar 2025 19:45:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.72 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741722337; cv=fail; b=he3Trj5bQsDTysE92riqxRz08C5YUCjBoqhhx6QpJP/i5lOAOEqnbuCaR25dAJLxzRU1c+WRGJVfM+h04f5vP283/wSujDgak+4tuuBscexZYaB8X/QjRb/FA2oRmKYRKKjrBWKHg+KucH098RZBnRYq2iobaTfBxwlhIMj0zpA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741722337; c=relaxed/simple; bh=xWBSgKXfCZJspqtK8RXUTQ64g0V0TrCaPdQGOyyV6wU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RT21rSclW13IkMfoZyjb6Ma/lt7WGs5r8fQSpE/W3y0VS6jHyDq2X9KY41cOgBDdJn4lrks1GcCqjZEEtTuT4Sd9HSKG2v8aSIclIwAbNej/t2ysEr237i8/MszIXdMt/4gywbhhvZqNJc4hMqUHWxtjRHvaOvHXUEYSEekBVxk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=FsP4jUgD; arc=fail smtp.client-ip=40.107.94.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="FsP4jUgD" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=vcVBYG6Swkoegq5oOj9zhjmOMGs/yiokTuLiYwBnKfTnSOwy9FCuQdgZAnsKBH3OCSV/24r6DcVoA84/PWE9v93CkMADVDRH3+mCwPAecB3LaOpmaA8EQ02Ji8c9Ku+kUYWb88GcLvWJihU8piGbgB3T2e3NLx1AcJ1iDb55tZRqInL1ndXbCnjv02I4xo7ppQaTVZ82JiufW+bkPp2oACgKS4qkHxp82RoXgoa94rzKScikypKcTLI51V4Sokqglk1859nGhDw1/l/LsyDxDhg67k8Wap5JKpKruvbQap5vZRmqYTq337Slm8o9Viqg7s8so5rSdpD/6zbjxQQDsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=9u0SFMN96KsPXoxMU/7TYYEUCxKd75WWRmS+1LzAEAM=; b=UsP0K7bSmXvs+mLQGC5oVUJale5doOmruRpdeQOWCl4UOsYUj/Wq3aL06acZEW9Yv++xJ8897iwGd1TAMOMwvIw/xMRWpypoFodaatvpiHUepPkIvWJ2OWuov9+SjSLkXE3mGiD5yDlc5B66mbcmpgbw0C9xEhfaP6fxwx35NdvVqqG5S9FVsBe2+obmezCzBXgwJd5ttER/QsF3LpFXT1q4URUAmHaQ3kjCHhpujW0S7qlNitb/7H26wWImMZwWxXnlyH/RB7b5SYBMRlfGNpPEti+mpEHE2eOcnO/6EI7sv3dXPPVjX/k4aT0+iDNdx9wpbRh+QnABpUW0Z6/OIA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9u0SFMN96KsPXoxMU/7TYYEUCxKd75WWRmS+1LzAEAM=; b=FsP4jUgDxYCPNEFe0/F7AuoKnrR/3ZFJCou9i42k6L3U3dhHM2f3uiuMA9M65zJ0IhAJLgSlicEhpOzoDghhQVRVRRUt2cSY2mBXiQnBQEIumifbDKBx5RblDTVmCG0C9kor9nho6pv4Za6xhMDrY5G2GTJ7lJsGsW2rP+X/rqMcEjE9cEllely892WeLypl8BrsKCwZAkAKBjbSWxSA1RG6KzOpqouZppUNbK4db4YcAi0G6XQMP9ppMx06sYfj0YFL/WY217MN1fnhUKn8s8vNLyTgd6aGsiMJzb3icolNGuJjhyM4mRf6Bw6RerYtvJXTrWwVID3pS/h5Hd8tmQ== Received: from BY5PR17CA0065.namprd17.prod.outlook.com (2603:10b6:a03:167::42) by CH3PR12MB8233.namprd12.prod.outlook.com (2603:10b6:610:129::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8511.27; Tue, 11 Mar 2025 19:45:28 +0000 Received: from SJ1PEPF00001CE1.namprd05.prod.outlook.com (2603:10b6:a03:167:cafe::9a) by BY5PR17CA0065.outlook.office365.com (2603:10b6:a03:167::42) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8511.27 via Frontend Transport; Tue, 11 Mar 2025 19:45:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SJ1PEPF00001CE1.mail.protection.outlook.com (10.167.242.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8534.20 via Frontend Transport; Tue, 11 Mar 2025 19:45:27 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 11 Mar 2025 12:45:12 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Tue, 11 Mar 2025 12:45:11 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Tue, 11 Mar 2025 12:45:10 -0700 From: Nicolin Chen To: CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 03/14] iommufd: Abstract an iommufd_eventq from iommufd_fault Date: Tue, 11 Mar 2025 12:44:21 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE1:EE_|CH3PR12MB8233:EE_ X-MS-Office365-Filtering-Correlation-Id: 4983cc9b-86d0-4b3a-7c0e-08dd60d54649 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700013|1800799024|376014|7416014; X-Microsoft-Antispam-Message-Info: LzSPTqydposMEJpIBgli4fEBKFgCO0leESzjkT/7/o3PMJJCfB1wnGoWp8lDpMP5iwRjv93xK73BeGt+OF3W4t6vvhsiC/Dwj3OfeOxqfCIncgHzBTIEPmjOtDrwF6wg8mi3YVtpd/Fdvf0UlCneKMP6IWi68qSpTMRbxnJB1wb1q77RyZkOQBQXEe0lP21Gyel0JNqnqN/Avg4O2VP9zi+BL87zoKoJ/4UMsOl8DAEqhYko+35gjq5xv4rcrkVxCmxi+7XczC112sQmyPpEnu+IQFfgRBkQk9pNp8HVmZRpvL9Zkwxes6rynNgqZlyqvPsAOCbTH1DjDOGRODdOa1BrNhOe7aR2ZfPwEQTfLa0xaZBzzHpWf3/nfsGgpoQKzGww0VOQ7PjgvsrSQ5IjtVoALohiQQm45WXJOd6nigFpCRjcOBppiVIRfy+Hriag1cKG4zlP2qLC/4zjB+8YY9UR3yUjHwnG3+lDos5f5K5UQxsM4aLzZI4AMsRVHm87eBCOLMX0Bc5KA4hc9Q1zyvjPnlTGDHm6ldp7bYRXfLymXV6lF48Vn/X+2t7+riJJ8J0rkWHhx93fXzULP+ekCFLSc6Du0WGdir87LBRy94p1Ike7aXAY/7NL0O01j4Fql8uY5AfUq+t3zkNS9VO4LV4UR33vVFRi1GYCPQ0JeNO+aKiUPIHUcX91q5D43fioqvKhNCi0RgsnEZHnZnV9fvxZtHk/GJZY4ZhYlpZCi79WRTkqJFtblyaxCE4oipsa0cqW5X//XvSVTloh20LDvsRnenEjL0xCQ+C78NoxpvK2ot/cfYv0VDYrGqNaNFEMWW+ubv54EGC/hf6Vx+k/NDecRkB+5Q8UTEBBwr/9KvbkWBalW5LuOQ9LATkvEPYo2RM+huRoY5KXRv3G4wO8jmNROemUmu/OjtpY9rcjmKL37EKd9F26Wm3NCeuZq/C6QQFtYlenkKenIIyxBO6C5F86ukLHkIgtmTPFpUZtgrvsCz1H4MMSFwLusClZEQDsdtbAH6jCju0tgQRkbxhHRPFszhzaBtv08seSXixWKPUtNXsvIod02kE+sjJtcG64wWx9tsU/unzmc3oMJUCS5dKSJrEeCKKnGAG43BQo8Jn9xJHkGExxCNPCmfJihRQWbX7fOdkqxNgJR3IzJ77h8qqEiyXR3Kb7zk752NKFnxntvOdwI97KwpFB1HYUCIIZZ4EteD1MS2o0qiq6YBIyzjmYHeY1O5o4Um/3vjDQd6JtJVCqYxRQLR0rIS/y4r70w7Hw+fueRoPg98f4Zn3lC+k7vOV2aM6aWf74AkLpOhLVNj9Vig7eHfAW3b8GXmg88y64bJfzz/ZODVjtlPuQa+BQML7GJNPTEdlXTOqASn6inViWOGGembIWpWUmo1KMrGDDv99jOnSp7iG6QYAi2TfpSg7oXwvOgEN3UTsfynoxFsTNrd6++p2yjY8E24/XvZ3RWtKqfi+y98AGCq0O63IpSzvd/FZ4qiD5pOgzgCM= X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(7416014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Mar 2025 19:45:27.9531 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4983cc9b-86d0-4b3a-7c0e-08dd60d54649 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8233 The fault object was designed exclusively for hwpt's IO page faults (PRI). But its queue implementation can be reused for other purposes too, such as hardware IRQ and event injections to user space. Meanwhile, a fault object holds a list of faults. So it's more accurate to call it a "fault queue". Combining the reusing idea above, abstract a new iommufd_eventq as a common structure embedded into struct iommufd_fault, similar to hwpt_paging holding a common hwpt. Add a common iommufd_eventq_ops and iommufd_eventq_init to prepare for an IOMMUFD_OBJ_VEVENTQ (vIOMMU Event Queue). Reviewed-by: Lu Baolu Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/iommufd_private.h | 28 ++++-- drivers/iommu/iommufd/fault.c | 111 +++++++++++++----------- drivers/iommu/iommufd/hw_pagetable.c | 6 +- 3 files changed, 82 insertions(+), 63 deletions(-) diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h index 1c58f5fe17b4..44fb30af10b0 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -454,20 +454,13 @@ void iopt_remove_access(struct io_pagetable *iopt, u32 iopt_access_list_id); void iommufd_access_destroy_object(struct iommufd_object *obj); -/* - * An iommufd_fault object represents an interface to deliver I/O page faults - * to the user space. These objects are created/destroyed by the user space and - * associated with hardware page table objects during page-table allocation. - */ -struct iommufd_fault { +struct iommufd_eventq { struct iommufd_object obj; struct iommufd_ctx *ictx; struct file *filep; spinlock_t lock; /* protects the deliver list */ struct list_head deliver; - struct mutex mutex; /* serializes response flows */ - struct xarray response; struct wait_queue_head wait_queue; }; @@ -480,12 +473,29 @@ struct iommufd_attach_handle { /* Convert an iommu attach handle to iommufd handle. */ #define to_iommufd_handle(hdl) container_of(hdl, struct iommufd_attach_handle, handle) +/* + * An iommufd_fault object represents an interface to deliver I/O page faults + * to the user space. These objects are created/destroyed by the user space and + * associated with hardware page table objects during page-table allocation. + */ +struct iommufd_fault { + struct iommufd_eventq common; + struct mutex mutex; /* serializes response flows */ + struct xarray response; +}; + +static inline struct iommufd_fault * +eventq_to_fault(struct iommufd_eventq *eventq) +{ + return container_of(eventq, struct iommufd_fault, common); +} + static inline struct iommufd_fault * iommufd_get_fault(struct iommufd_ucmd *ucmd, u32 id) { return container_of(iommufd_get_object(ucmd->ictx, id, IOMMUFD_OBJ_FAULT), - struct iommufd_fault, obj); + struct iommufd_fault, common.obj); } int iommufd_fault_alloc(struct iommufd_ucmd *ucmd); diff --git a/drivers/iommu/iommufd/fault.c b/drivers/iommu/iommufd/fault.c index 5d8de98732b6..f8e60e5879d1 100644 --- a/drivers/iommu/iommufd/fault.c +++ b/drivers/iommu/iommufd/fault.c @@ -17,6 +17,8 @@ #include "../iommu-priv.h" #include "iommufd_private.h" +/* IOMMUFD_OBJ_FAULT Functions */ + int iommufd_fault_iopf_enable(struct iommufd_device *idev) { struct device *dev = idev->dev; @@ -73,13 +75,13 @@ void iommufd_auto_response_faults(struct iommufd_hw_pagetable *hwpt, INIT_LIST_HEAD(&free_list); mutex_lock(&fault->mutex); - spin_lock(&fault->lock); - list_for_each_entry_safe(group, next, &fault->deliver, node) { + spin_lock(&fault->common.lock); + list_for_each_entry_safe(group, next, &fault->common.deliver, node) { if (group->attach_handle != &handle->handle) continue; list_move(&group->node, &free_list); } - spin_unlock(&fault->lock); + spin_unlock(&fault->common.lock); list_for_each_entry_safe(group, next, &free_list, node) { list_del(&group->node); @@ -99,7 +101,9 @@ void iommufd_auto_response_faults(struct iommufd_hw_pagetable *hwpt, void iommufd_fault_destroy(struct iommufd_object *obj) { - struct iommufd_fault *fault = container_of(obj, struct iommufd_fault, obj); + struct iommufd_eventq *eventq = + container_of(obj, struct iommufd_eventq, obj); + struct iommufd_fault *fault = eventq_to_fault(eventq); struct iopf_group *group, *next; unsigned long index; @@ -109,7 +113,7 @@ void iommufd_fault_destroy(struct iommufd_object *obj) * accessing this pointer. Therefore, acquiring the mutex here * is unnecessary. */ - list_for_each_entry_safe(group, next, &fault->deliver, node) { + list_for_each_entry_safe(group, next, &fault->common.deliver, node) { list_del(&group->node); iopf_group_response(group, IOMMU_PAGE_RESP_INVALID); iopf_free_group(group); @@ -142,15 +146,15 @@ static void iommufd_compose_fault_message(struct iommu_fault *fault, static struct iopf_group * iommufd_fault_deliver_fetch(struct iommufd_fault *fault) { - struct list_head *list = &fault->deliver; + struct list_head *list = &fault->common.deliver; struct iopf_group *group = NULL; - spin_lock(&fault->lock); + spin_lock(&fault->common.lock); if (!list_empty(list)) { group = list_first_entry(list, struct iopf_group, node); list_del(&group->node); } - spin_unlock(&fault->lock); + spin_unlock(&fault->common.lock); return group; } @@ -158,16 +162,17 @@ iommufd_fault_deliver_fetch(struct iommufd_fault *fault) static void iommufd_fault_deliver_restore(struct iommufd_fault *fault, struct iopf_group *group) { - spin_lock(&fault->lock); - list_add(&group->node, &fault->deliver); - spin_unlock(&fault->lock); + spin_lock(&fault->common.lock); + list_add(&group->node, &fault->common.deliver); + spin_unlock(&fault->common.lock); } static ssize_t iommufd_fault_fops_read(struct file *filep, char __user *buf, size_t count, loff_t *ppos) { size_t fault_size = sizeof(struct iommu_hwpt_pgfault); - struct iommufd_fault *fault = filep->private_data; + struct iommufd_eventq *eventq = filep->private_data; + struct iommufd_fault *fault = eventq_to_fault(eventq); struct iommu_hwpt_pgfault data = {}; struct iommufd_device *idev; struct iopf_group *group; @@ -216,7 +221,8 @@ static ssize_t iommufd_fault_fops_write(struct file *filep, const char __user *b size_t count, loff_t *ppos) { size_t response_size = sizeof(struct iommu_hwpt_page_response); - struct iommufd_fault *fault = filep->private_data; + struct iommufd_eventq *eventq = filep->private_data; + struct iommufd_fault *fault = eventq_to_fault(eventq); struct iommu_hwpt_page_response response; struct iopf_group *group; size_t done = 0; @@ -256,59 +262,61 @@ static ssize_t iommufd_fault_fops_write(struct file *filep, const char __user *b return done == 0 ? rc : done; } -static __poll_t iommufd_fault_fops_poll(struct file *filep, - struct poll_table_struct *wait) +/* Common Event Queue Functions */ + +static __poll_t iommufd_eventq_fops_poll(struct file *filep, + struct poll_table_struct *wait) { - struct iommufd_fault *fault = filep->private_data; + struct iommufd_eventq *eventq = filep->private_data; __poll_t pollflags = EPOLLOUT; - poll_wait(filep, &fault->wait_queue, wait); - spin_lock(&fault->lock); - if (!list_empty(&fault->deliver)) + poll_wait(filep, &eventq->wait_queue, wait); + spin_lock(&eventq->lock); + if (!list_empty(&eventq->deliver)) pollflags |= EPOLLIN | EPOLLRDNORM; - spin_unlock(&fault->lock); + spin_unlock(&eventq->lock); return pollflags; } -static int iommufd_fault_fops_release(struct inode *inode, struct file *filep) +static int iommufd_eventq_fops_release(struct inode *inode, struct file *filep) { - struct iommufd_fault *fault = filep->private_data; + struct iommufd_eventq *eventq = filep->private_data; - refcount_dec(&fault->obj.users); - iommufd_ctx_put(fault->ictx); + refcount_dec(&eventq->obj.users); + iommufd_ctx_put(eventq->ictx); return 0; } -#define INIT_FAULT_FOPS(read_op, write_op) \ +#define INIT_EVENTQ_FOPS(read_op, write_op) \ ((const struct file_operations){ \ .owner = THIS_MODULE, \ .open = nonseekable_open, \ .read = read_op, \ .write = write_op, \ - .poll = iommufd_fault_fops_poll, \ - .release = iommufd_fault_fops_release, \ + .poll = iommufd_eventq_fops_poll, \ + .release = iommufd_eventq_fops_release, \ }) -static int iommufd_fault_init(struct iommufd_fault *fault, char *name, - struct iommufd_ctx *ictx, - const struct file_operations *fops) +static int iommufd_eventq_init(struct iommufd_eventq *eventq, char *name, + struct iommufd_ctx *ictx, + const struct file_operations *fops) { struct file *filep; int fdno; - spin_lock_init(&fault->lock); - INIT_LIST_HEAD(&fault->deliver); - init_waitqueue_head(&fault->wait_queue); + spin_lock_init(&eventq->lock); + INIT_LIST_HEAD(&eventq->deliver); + init_waitqueue_head(&eventq->wait_queue); - filep = anon_inode_getfile(name, fops, fault, O_RDWR); + filep = anon_inode_getfile(name, fops, eventq, O_RDWR); if (IS_ERR(filep)) return PTR_ERR(filep); - fault->ictx = ictx; - iommufd_ctx_get(fault->ictx); - fault->filep = filep; - refcount_inc(&fault->obj.users); + eventq->ictx = ictx; + iommufd_ctx_get(eventq->ictx); + eventq->filep = filep; + refcount_inc(&eventq->obj.users); fdno = get_unused_fd_flags(O_CLOEXEC); if (fdno < 0) @@ -317,7 +325,7 @@ static int iommufd_fault_init(struct iommufd_fault *fault, char *name, } static const struct file_operations iommufd_fault_fops = - INIT_FAULT_FOPS(iommufd_fault_fops_read, iommufd_fault_fops_write); + INIT_EVENTQ_FOPS(iommufd_fault_fops_read, iommufd_fault_fops_write); int iommufd_fault_alloc(struct iommufd_ucmd *ucmd) { @@ -329,36 +337,37 @@ int iommufd_fault_alloc(struct iommufd_ucmd *ucmd) if (cmd->flags) return -EOPNOTSUPP; - fault = iommufd_object_alloc(ucmd->ictx, fault, IOMMUFD_OBJ_FAULT); + fault = __iommufd_object_alloc(ucmd->ictx, fault, IOMMUFD_OBJ_FAULT, + common.obj); if (IS_ERR(fault)) return PTR_ERR(fault); xa_init_flags(&fault->response, XA_FLAGS_ALLOC1); mutex_init(&fault->mutex); - fdno = iommufd_fault_init(fault, "[iommufd-pgfault]", ucmd->ictx, - &iommufd_fault_fops); + fdno = iommufd_eventq_init(&fault->common, "[iommufd-pgfault]", + ucmd->ictx, &iommufd_fault_fops); if (fdno < 0) { rc = fdno; goto out_abort; } - cmd->out_fault_id = fault->obj.id; + cmd->out_fault_id = fault->common.obj.id; cmd->out_fault_fd = fdno; rc = iommufd_ucmd_respond(ucmd, sizeof(*cmd)); if (rc) goto out_put_fdno; - iommufd_object_finalize(ucmd->ictx, &fault->obj); + iommufd_object_finalize(ucmd->ictx, &fault->common.obj); - fd_install(fdno, fault->filep); + fd_install(fdno, fault->common.filep); return 0; out_put_fdno: put_unused_fd(fdno); - fput(fault->filep); + fput(fault->common.filep); out_abort: - iommufd_object_abort_and_destroy(ucmd->ictx, &fault->obj); + iommufd_object_abort_and_destroy(ucmd->ictx, &fault->common.obj); return rc; } @@ -371,11 +380,11 @@ int iommufd_fault_iopf_handler(struct iopf_group *group) hwpt = group->attach_handle->domain->iommufd_hwpt; fault = hwpt->fault; - spin_lock(&fault->lock); - list_add_tail(&group->node, &fault->deliver); - spin_unlock(&fault->lock); + spin_lock(&fault->common.lock); + list_add_tail(&group->node, &fault->common.deliver); + spin_unlock(&fault->common.lock); - wake_up_interruptible(&fault->wait_queue); + wake_up_interruptible(&fault->common.wait_queue); return 0; } diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/hw_pagetable.c index 268315b1d8bc..ee40235f9285 100644 --- a/drivers/iommu/iommufd/hw_pagetable.c +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -14,7 +14,7 @@ static void __iommufd_hwpt_destroy(struct iommufd_hw_pagetable *hwpt) iommu_domain_free(hwpt->domain); if (hwpt->fault) - refcount_dec(&hwpt->fault->obj.users); + refcount_dec(&hwpt->fault->common.obj.users); } void iommufd_hwpt_paging_destroy(struct iommufd_object *obj) @@ -412,8 +412,8 @@ int iommufd_hwpt_alloc(struct iommufd_ucmd *ucmd) } hwpt->fault = fault; hwpt->domain->iopf_handler = iommufd_fault_iopf_handler; - refcount_inc(&fault->obj.users); - iommufd_put_object(ucmd->ictx, &fault->obj); + refcount_inc(&fault->common.obj.users); + iommufd_put_object(ucmd->ictx, &fault->common.obj); } hwpt->domain->iommufd_hwpt = hwpt; From patchwork Tue Mar 11 19:44:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 872668 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2045.outbound.protection.outlook.com [40.107.244.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36E3422173D; Tue, 11 Mar 2025 19:45:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.45 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741722338; cv=fail; b=VlMDkpkNwSlZEtSSbhO1WaRG3aT/HVSbUFzTOO8I4w3JW7L3XiV5LqoiIrXxMtVWLjlvB3fZseUPJ1UGjJromrqxqE/pMqLhaNp7dBzTepnX5B3Tjl4IX5iUaNxQDT9tcPhs3rd4sQ8aW9orD2XTg/kUw4uYXaNVplCfDj8ZTqQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741722338; c=relaxed/simple; bh=ruU3l6LO3gcvQMJ/McVT7Z4wcUdf7zVyHJ18oFpZPsk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fP3TgVeUYepU9NV5zalJYooIMdvbQthPN8or3u/SLX3isp83VtZYHzaHj1WILuD72spzOhcZ/ttkWUBUDvFbkZj5+H8/d/xNt06V3D8VmZhM+mdL7nhFtfH3MQt3h5ZXGgarl8X10Ns9tnYSiuaQ1dD3W4dep1yiJgiWr05B9Ow= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=sqN/YLg0; arc=fail smtp.client-ip=40.107.244.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="sqN/YLg0" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=CW1DPKC4IrtP1Fl5K74P5acnDuWt8q2KFTJgXWonXIpmQyNUoTb2FPwnLqi67goOvKIFSysUFqkn/GuKZC1osBDson0lSDy9Q4SsV4N55kdsAEKCcN7iKkIPGaNkANcG7I2ANAu4epYjid3gc5I3KYeIP4W4A1JcTJ0/WcZKLtINldi4CQsr/Pc0fsqJO0MmI2H/0bI2BIAtQgh+ZNrPrNQzX50otCCwcLtiAfBk5VkHrrHRfjldiByBPhVp1Ee2BQLTP05pshS24jWM2h13ILRgOCFgXub7NR8aU8UxDxqf4OCI9u+7viZtvKEcg/ASB58FsTL8TBM3JmErwvUJyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=TkfPylT5fZJ84edFbny4xMpZcPqfkqgdYNkiG7L9kJQ=; b=m69wDljCyS18jEj352rRpShrT9YHf+2trKijV25Fcn4ErQ/u1uvlLeAncpru7DmxllfpijpgFVP1mauOzecF5x19bRfQNbqq+YqmCfoIuSfRORg28MQXABhaLXBrJ6mO99Xj78VGk3hD/M8+OYrr3djDDjrV8HH5MAlyHyN06h6noGvTNiTUIrC/DOjQA0E8s1/jeCMQY8P5kfBCmKCa3VH5x7UYaJEpke8InCCuGfUiyIcgmbYz339aT5/kJrHKhi6FruRBiAy8OsWT6jRJIW2oqxB/gln+Jx0f/MPXDRRnZcH206P2ubZkjKmIK7Tk3V2wCOAli5+iyBJw+FsYfw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TkfPylT5fZJ84edFbny4xMpZcPqfkqgdYNkiG7L9kJQ=; b=sqN/YLg082hno6GztghRru2vtoxR6c4PH0MTAueEekDU8MgzYJTuEjEJ/gnUspqxPnNO30Y1im4k6WwAx/tFbZ6eziOk0sMZPiIH3ydx5Seunu+E0tpEnktTKT3FVfaPSuYm1vu0Dt7NOGDK0v6Q9CCnSdynDRRjWs0aAIQ3Ujd/cCp51fVlifHCpMG+ZzOfSgbCgwAt3sUzlBVq5UM+YEprJAxLUaD00eKYRiTVprF1Rpen0qkkexotz7yqAMdq6gBTM7HmFgY5BCO/5yBGyCtgjlcX0KePBSOWx67Jb/mYbo3wKn6Oe7YooRMh9p8XZ0L9CuKtfegIWfpmT9XmSw== Received: from MN0PR05CA0013.namprd05.prod.outlook.com (2603:10b6:208:52c::7) by IA0PR12MB8280.namprd12.prod.outlook.com (2603:10b6:208:3df::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8511.27; Tue, 11 Mar 2025 19:45:28 +0000 Received: from BN1PEPF0000468D.namprd05.prod.outlook.com (2603:10b6:208:52c:cafe::c3) by MN0PR05CA0013.outlook.office365.com (2603:10b6:208:52c::7) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8534.23 via Frontend Transport; Tue, 11 Mar 2025 19:45:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by BN1PEPF0000468D.mail.protection.outlook.com (10.167.243.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8534.20 via Frontend Transport; Tue, 11 Mar 2025 19:45:28 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 11 Mar 2025 12:45:16 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Tue, 11 Mar 2025 12:45:15 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Tue, 11 Mar 2025 12:45:14 -0700 From: Nicolin Chen To: CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 05/14] iommufd: Add IOMMUFD_OBJ_VEVENTQ and IOMMUFD_CMD_VEVENTQ_ALLOC Date: Tue, 11 Mar 2025 12:44:23 -0700 Message-ID: <21acf0751dd5c93846935ee06f93b9c65eff5e04.1741719725.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468D:EE_|IA0PR12MB8280:EE_ X-MS-Office365-Filtering-Correlation-Id: 39887016-e9b7-401b-7524-08dd60d5467d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|7416014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: J0vlzv8fvMUGRFj1INMOoVhAjn60MsiNPFx3hM2uqpfylGmPOQr4ZRcuAOFji0/Z4wiMpuJxVhzYkiQflvi5FMa8ushSsoFVHS2hmFsWiccIyMk29h1rnyihGuFH6I6u2+ItmTwAyk4ZHwJ5+ZhFCyQUskKQ7Q4ahDKgu7uCA1LN3Yb4vp37+dKiRaYZymQLKjctC/5mdTFJVnwYC9nLfPCcytBUwp+4eB/ibCEN1yi3IEThaqsuv84UNHM4PWy23Ex2lj8PZO9nu1B3L58DNRrklpccSpKHdu940fDXZbIvmI0+XsNAiAc5KhNtvBzWPTmOQ1kSd/2ZH6XNGxpG7Sm/uW2j8gNAYgtY7fAq8RTLGV41NgrcHV1pHpRWY9CBCfJxZBlAyEoEcLA7W3XQBVpWHkUM/qzW1fV8plgCjU9uZDCo+OHTtOrgFpEPl2d66WN8ra7yhZkntR+2KAhTag5JmLgEw84wIai4dtlXjIugqaFq1+nfRXc8uikjBdJdTDQqGJADhqdnoMCPm1+uZ0u1cw/SqRduS4cmCrM1vnjYBv7WkxifmQoMZbPXKY6nYItgSaVKZ/L2+F4/1GTu9V33ytpywRnFkL4elCmPV2mKRcxSF7GaOdB8CdBC0pc3th9T4wIfTU7WE5Fw0bSKR7Wxsqfm/Wl/f+f/3T+caHlkiGPV8qQL9IkR5NXvf03XjAOIQ72zx5DVToycMX1iNSpisaRxpfL/1Z+Y+tOkOLOND7q5yTKqIp7e+Fohx1W9wC1MRvCX3Up8wtkvC+eHS9vIARLKYStZyHsM2ytfyhuAtYI/JI0VrOOu/cQqybaPtEpzvbBEyMQ7f1cMkZUOpyJYOS1axmyuVtk5BT/CSDYffEyN+VvMpPy9sRIhRs3B0BOwpfJ3hr1WL6tawJ8J7EX/IeY/4fBEcxGDicU6bkUi9Sas1K+wwwklKmFrdDjMVw7JYfCdxvzeuJugwSgqnrieeTKJG7jKXhhvr8dGYovbX0pfhnbcZL8/8L7mGDZCSNzpc0/DsXEb6jVOrQlLndgbVDkasg678CkHf2h2MFoPap1czOiw/C4flfcjcgr9vtn7NhsNLyNGv3DDLY2UORWS+04qzFdko5oM6zjVeTQRik3nsT7FkoyXjFTR2hBSzZxsgXNfsffjP26Eh4osA8p2tSj9BNzrtsa+I/P3BOJ5aq+66fVxFQ55/jMDb4dhSUri4IpQzj5FeV4O6FyQOql7qLU0yXtyeq7lV4gr4ZZhWddN+0DZTWUMv/C9GUKD8/3pZX5eOAsbzjrehYRrSoLOYE6konnAXTDVfots1Ass5oMOpYxwt3mtxtdrGeVELTTGHBElTfjhzbs442mcGN8XC7b4nRRaLIFWtLFeBECf1Lv5F8mmFMlLuEhbTKwn9dTvKq1D/rNGBWJ2dasMq6km19gX0KJNzMxtw8uL8nBZAOxFRUVbHV92NMp0hDQhCuTYczVi6fFsTyMnGRwl9EjaxhE5/q8fmepVWMGofHM= X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(7416014)(36860700013)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Mar 2025 19:45:28.1531 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39887016-e9b7-401b-7524-08dd60d5467d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8280 Introduce a new IOMMUFD_OBJ_VEVENTQ object for vIOMMU Event Queue that provides user space (VMM) another FD to read the vIOMMU Events. Allow a vIOMMU object to allocate vEVENTQs, with a condition that each vIOMMU can only have one single vEVENTQ per type. Add iommufd_veventq_alloc() with iommufd_veventq_ops for the new ioctl. Reviewed-by: Lu Baolu Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/iommufd_private.h | 82 ++++++++++ include/linux/iommufd.h | 3 + include/uapi/linux/iommufd.h | 82 ++++++++++ drivers/iommu/iommufd/eventq.c | 209 +++++++++++++++++++++++- drivers/iommu/iommufd/main.c | 7 + drivers/iommu/iommufd/viommu.c | 2 + 6 files changed, 384 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h index 44fb30af10b0..8cda9c4672eb 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -507,6 +507,74 @@ void iommufd_fault_iopf_disable(struct iommufd_device *idev); void iommufd_auto_response_faults(struct iommufd_hw_pagetable *hwpt, struct iommufd_attach_handle *handle); +/* An iommufd_vevent represents a vIOMMU event in an iommufd_veventq */ +struct iommufd_vevent { + struct iommufd_vevent_header header; + struct list_head node; /* for iommufd_eventq::deliver */ + ssize_t data_len; + u64 event_data[] __counted_by(data_len); +}; + +#define vevent_for_lost_events_header(vevent) \ + (vevent->header.flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS) + +/* + * An iommufd_veventq object represents an interface to deliver vIOMMU events to + * the user space. It is created/destroyed by the user space and associated with + * a vIOMMU object during the allocations. + */ +struct iommufd_veventq { + struct iommufd_eventq common; + struct iommufd_viommu *viommu; + struct list_head node; /* for iommufd_viommu::veventqs */ + struct iommufd_vevent lost_events_header; + + unsigned int type; + unsigned int depth; + + /* Use common.lock for protection */ + u32 num_events; + u32 sequence; +}; + +static inline struct iommufd_veventq * +eventq_to_veventq(struct iommufd_eventq *eventq) +{ + return container_of(eventq, struct iommufd_veventq, common); +} + +static inline struct iommufd_veventq * +iommufd_get_veventq(struct iommufd_ucmd *ucmd, u32 id) +{ + return container_of(iommufd_get_object(ucmd->ictx, id, + IOMMUFD_OBJ_VEVENTQ), + struct iommufd_veventq, common.obj); +} + +int iommufd_veventq_alloc(struct iommufd_ucmd *ucmd); +void iommufd_veventq_destroy(struct iommufd_object *obj); +void iommufd_veventq_abort(struct iommufd_object *obj); + +static inline void iommufd_vevent_handler(struct iommufd_veventq *veventq, + struct iommufd_vevent *vevent) +{ + struct iommufd_eventq *eventq = &veventq->common; + + lockdep_assert_held(&eventq->lock); + + /* + * Remove the lost_events_header and add the new node at the same time. + * Note the new node can be lost_events_header, for a sequence update. + */ + if (list_is_last(&veventq->lost_events_header.node, &eventq->deliver)) + list_del(&veventq->lost_events_header.node); + list_add_tail(&vevent->node, &eventq->deliver); + vevent->header.sequence = veventq->sequence; + veventq->sequence = (veventq->sequence + 1) & INT_MAX; + + wake_up_interruptible(&eventq->wait_queue); +} + static inline struct iommufd_viommu * iommufd_get_viommu(struct iommufd_ucmd *ucmd, u32 id) { @@ -515,6 +583,20 @@ iommufd_get_viommu(struct iommufd_ucmd *ucmd, u32 id) struct iommufd_viommu, obj); } +static inline struct iommufd_veventq * +iommufd_viommu_find_veventq(struct iommufd_viommu *viommu, u32 type) +{ + struct iommufd_veventq *veventq, *next; + + lockdep_assert_held(&viommu->veventqs_rwsem); + + list_for_each_entry_safe(veventq, next, &viommu->veventqs, node) { + if (veventq->type == type) + return veventq; + } + return NULL; +} + int iommufd_viommu_alloc_ioctl(struct iommufd_ucmd *ucmd); void iommufd_viommu_destroy(struct iommufd_object *obj); int iommufd_vdevice_alloc_ioctl(struct iommufd_ucmd *ucmd); diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index 11110c749200..8948b1836940 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -34,6 +34,7 @@ enum iommufd_object_type { IOMMUFD_OBJ_FAULT, IOMMUFD_OBJ_VIOMMU, IOMMUFD_OBJ_VDEVICE, + IOMMUFD_OBJ_VEVENTQ, #ifdef CONFIG_IOMMUFD_TEST IOMMUFD_OBJ_SELFTEST, #endif @@ -93,6 +94,8 @@ struct iommufd_viommu { const struct iommufd_viommu_ops *ops; struct xarray vdevs; + struct list_head veventqs; + struct rw_semaphore veventqs_rwsem; unsigned int type; }; diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 78747b24bd0f..2ade4839880d 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -55,6 +55,7 @@ enum { IOMMUFD_CMD_VIOMMU_ALLOC = 0x90, IOMMUFD_CMD_VDEVICE_ALLOC = 0x91, IOMMUFD_CMD_IOAS_CHANGE_PROCESS = 0x92, + IOMMUFD_CMD_VEVENTQ_ALLOC = 0x93, }; /** @@ -1014,4 +1015,85 @@ struct iommu_ioas_change_process { #define IOMMU_IOAS_CHANGE_PROCESS \ _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_CHANGE_PROCESS) +/** + * enum iommu_veventq_flag - flag for struct iommufd_vevent_header + * @IOMMU_VEVENTQ_FLAG_OVERFLOW: vEVENTQ has lost vEVENTs + */ +enum iommu_veventq_flag { + IOMMU_VEVENTQ_FLAG_LOST_EVENTS = (1U << 0), +}; + +/** + * struct iommufd_vevent_header - Virtual Event Header for a vEVENTQ Status + * @flags: Combination of enum iommu_veventq_flag + * @sequence: The sequence index of a vEVENT in the vEVENTQ, with a range of + * [0, INT_MAX] where the following index of INT_MAX is 0 + * + * Each iommufd_vevent_header reports a sequence index of the following vEVENT: + * ------------------------------------------------------------------------- + * | header0 {sequence=0} | data0 | header1 {sequence=1} | data1 |...| dataN | + * ------------------------------------------------------------------------- + * And this sequence index is expected to be monotonic to the sequence index of + * the previous vEVENT. If two adjacent sequence indexes has a delta larger than + * 1, it means that delta - 1 number of vEVENTs has lost, e.g. two lost vEVENTs: + * ------------------------------------------------------------------------- + * | ... | header3 {sequence=3} | data3 | header6 {sequence=6} | data6 | ... | + * ------------------------------------------------------------------------- + * If a vEVENT lost at the tail of the vEVENTQ and there is no following vEVENT + * providing the next sequence index, an IOMMU_VEVENTQ_FLAG_LOST_EVENTS header + * would be added to the tail, and no data would follow this header: + * --------------------------------------------------------------------------- + * |..| header3 {sequence=3} | data3 | header4 {flags=LOST_EVENTS, sequence=4} | + * --------------------------------------------------------------------------- + */ +struct iommufd_vevent_header { + __u32 flags; + __u32 sequence; +}; + +/** + * enum iommu_veventq_type - Virtual Event Queue Type + * @IOMMU_VEVENTQ_TYPE_DEFAULT: Reserved for future use + */ +enum iommu_veventq_type { + IOMMU_VEVENTQ_TYPE_DEFAULT = 0, +}; + +/** + * struct iommu_veventq_alloc - ioctl(IOMMU_VEVENTQ_ALLOC) + * @size: sizeof(struct iommu_veventq_alloc) + * @flags: Must be 0 + * @viommu: virtual IOMMU ID to associate the vEVENTQ with + * @type: Type of the vEVENTQ. Must be defined in enum iommu_veventq_type + * @veventq_depth: Maximum number of events in the vEVENTQ + * @out_veventq_id: The ID of the new vEVENTQ + * @out_veventq_fd: The fd of the new vEVENTQ. User space must close the + * successfully returned fd after using it + * @__reserved: Must be 0 + * + * Explicitly allocate a virtual event queue interface for a vIOMMU. A vIOMMU + * can have multiple FDs for different types, but is confined to one per @type. + * User space should open the @out_veventq_fd to read vEVENTs out of a vEVENTQ, + * if there are vEVENTs available. A vEVENTQ will lose events due to overflow, + * if the number of the vEVENTs hits @veventq_depth. + * + * Each vEVENT in a vEVENTQ encloses a struct iommufd_vevent_header followed by + * a type-specific data structure, in a normal case: + * ------------------------------------------------------------- + * || header0 | data0 | header1 | data1 | ... | headerN | dataN || + * ------------------------------------------------------------- + * unless a tailing IOMMU_VEVENTQ_FLAG_LOST_EVENTS header is logged (refer to + * struct iommufd_vevent_header). + */ +struct iommu_veventq_alloc { + __u32 size; + __u32 flags; + __u32 viommu_id; + __u32 type; + __u32 veventq_depth; + __u32 out_veventq_id; + __u32 out_veventq_fd; + __u32 __reserved; +}; +#define IOMMU_VEVENTQ_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VEVENTQ_ALLOC) #endif diff --git a/drivers/iommu/iommufd/eventq.c b/drivers/iommu/iommufd/eventq.c index f8e60e5879d1..4c43ace8c725 100644 --- a/drivers/iommu/iommufd/eventq.c +++ b/drivers/iommu/iommufd/eventq.c @@ -262,13 +262,148 @@ static ssize_t iommufd_fault_fops_write(struct file *filep, const char __user *b return done == 0 ? rc : done; } +/* IOMMUFD_OBJ_VEVENTQ Functions */ + +void iommufd_veventq_abort(struct iommufd_object *obj) +{ + struct iommufd_eventq *eventq = + container_of(obj, struct iommufd_eventq, obj); + struct iommufd_veventq *veventq = eventq_to_veventq(eventq); + struct iommufd_viommu *viommu = veventq->viommu; + struct iommufd_vevent *cur, *next; + + lockdep_assert_held_write(&viommu->veventqs_rwsem); + + list_for_each_entry_safe(cur, next, &eventq->deliver, node) { + list_del(&cur->node); + if (cur != &veventq->lost_events_header) + kfree(cur); + } + + refcount_dec(&viommu->obj.users); + list_del(&veventq->node); +} + +void iommufd_veventq_destroy(struct iommufd_object *obj) +{ + struct iommufd_veventq *veventq = eventq_to_veventq( + container_of(obj, struct iommufd_eventq, obj)); + + down_write(&veventq->viommu->veventqs_rwsem); + iommufd_veventq_abort(obj); + up_write(&veventq->viommu->veventqs_rwsem); +} + +static struct iommufd_vevent * +iommufd_veventq_deliver_fetch(struct iommufd_veventq *veventq) +{ + struct iommufd_eventq *eventq = &veventq->common; + struct list_head *list = &eventq->deliver; + struct iommufd_vevent *vevent = NULL; + + spin_lock(&eventq->lock); + if (!list_empty(list)) { + struct iommufd_vevent *next; + + next = list_first_entry(list, struct iommufd_vevent, node); + /* Make a copy of the lost_events_header for copy_to_user */ + if (next == &veventq->lost_events_header) { + vevent = kzalloc(sizeof(*vevent), GFP_ATOMIC); + if (!vevent) + goto out_unlock; + } + list_del(&next->node); + if (vevent) + memcpy(vevent, next, sizeof(*vevent)); + else + vevent = next; + } +out_unlock: + spin_unlock(&eventq->lock); + return vevent; +} + +static void iommufd_veventq_deliver_restore(struct iommufd_veventq *veventq, + struct iommufd_vevent *vevent) +{ + struct iommufd_eventq *eventq = &veventq->common; + struct list_head *list = &eventq->deliver; + + spin_lock(&eventq->lock); + if (vevent_for_lost_events_header(vevent)) { + /* Remove the copy of the lost_events_header */ + kfree(vevent); + vevent = NULL; + /* An empty list needs the lost_events_header back */ + if (list_empty(list)) + vevent = &veventq->lost_events_header; + } + if (vevent) + list_add(&vevent->node, list); + spin_unlock(&eventq->lock); +} + +static ssize_t iommufd_veventq_fops_read(struct file *filep, char __user *buf, + size_t count, loff_t *ppos) +{ + struct iommufd_eventq *eventq = filep->private_data; + struct iommufd_veventq *veventq = eventq_to_veventq(eventq); + struct iommufd_vevent_header *hdr; + struct iommufd_vevent *cur; + size_t done = 0; + int rc = 0; + + if (*ppos) + return -ESPIPE; + + while ((cur = iommufd_veventq_deliver_fetch(veventq))) { + /* Validate the remaining bytes against the header size */ + if (done >= count || sizeof(*hdr) > count - done) { + iommufd_veventq_deliver_restore(veventq, cur); + break; + } + hdr = &cur->header; + + /* If being a normal vEVENT, validate against the full size */ + if (!vevent_for_lost_events_header(cur) && + sizeof(hdr) + cur->data_len > count - done) { + iommufd_veventq_deliver_restore(veventq, cur); + break; + } + + if (copy_to_user(buf + done, hdr, sizeof(*hdr))) { + iommufd_veventq_deliver_restore(veventq, cur); + rc = -EFAULT; + break; + } + done += sizeof(*hdr); + + if (cur->data_len && + copy_to_user(buf + done, cur->event_data, cur->data_len)) { + iommufd_veventq_deliver_restore(veventq, cur); + rc = -EFAULT; + break; + } + spin_lock(&eventq->lock); + veventq->num_events--; + spin_unlock(&eventq->lock); + done += cur->data_len; + kfree(cur); + } + + return done == 0 ? rc : done; +} + /* Common Event Queue Functions */ static __poll_t iommufd_eventq_fops_poll(struct file *filep, struct poll_table_struct *wait) { struct iommufd_eventq *eventq = filep->private_data; - __poll_t pollflags = EPOLLOUT; + __poll_t pollflags = 0; + + if (eventq->obj.type == IOMMUFD_OBJ_FAULT) + pollflags |= EPOLLOUT; poll_wait(filep, &eventq->wait_queue, wait); spin_lock(&eventq->lock); @@ -388,3 +523,75 @@ int iommufd_fault_iopf_handler(struct iopf_group *group) return 0; } + +static const struct file_operations iommufd_veventq_fops = + INIT_EVENTQ_FOPS(iommufd_veventq_fops_read, NULL); + +int iommufd_veventq_alloc(struct iommufd_ucmd *ucmd) +{ + struct iommu_veventq_alloc *cmd = ucmd->cmd; + struct iommufd_veventq *veventq; + struct iommufd_viommu *viommu; + int fdno; + int rc; + + if (cmd->flags || cmd->__reserved || + cmd->type == IOMMU_VEVENTQ_TYPE_DEFAULT) + return -EOPNOTSUPP; + if (!cmd->veventq_depth) + return -EINVAL; + + viommu = iommufd_get_viommu(ucmd, cmd->viommu_id); + if (IS_ERR(viommu)) + return PTR_ERR(viommu); + + down_write(&viommu->veventqs_rwsem); + + if (iommufd_viommu_find_veventq(viommu, cmd->type)) { + rc = -EEXIST; + goto out_unlock_veventqs; + } + + veventq = __iommufd_object_alloc(ucmd->ictx, veventq, + IOMMUFD_OBJ_VEVENTQ, common.obj); + if (IS_ERR(veventq)) { + rc = PTR_ERR(veventq); + goto out_unlock_veventqs; + } + + veventq->type = cmd->type; + veventq->viommu = viommu; + refcount_inc(&viommu->obj.users); + veventq->depth = cmd->veventq_depth; + list_add_tail(&veventq->node, &viommu->veventqs); + veventq->lost_events_header.header.flags = + IOMMU_VEVENTQ_FLAG_LOST_EVENTS; + + fdno = iommufd_eventq_init(&veventq->common, "[iommufd-viommu-event]", + ucmd->ictx, &iommufd_veventq_fops); + if (fdno < 0) { + rc = fdno; + goto out_abort; + } + + cmd->out_veventq_id = veventq->common.obj.id; + cmd->out_veventq_fd = fdno; + + rc = iommufd_ucmd_respond(ucmd, sizeof(*cmd)); + if (rc) + goto out_put_fdno; + + iommufd_object_finalize(ucmd->ictx, &veventq->common.obj); + fd_install(fdno, veventq->common.filep); + goto out_unlock_veventqs; + +out_put_fdno: + put_unused_fd(fdno); + fput(veventq->common.filep); +out_abort: + iommufd_object_abort_and_destroy(ucmd->ictx, &veventq->common.obj); +out_unlock_veventqs: + up_write(&viommu->veventqs_rwsem); + iommufd_put_object(ucmd->ictx, &viommu->obj); + return rc; +} diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index b6fa9fd11bc1..3df468f64e7d 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -317,6 +317,7 @@ union ucmd_buffer { struct iommu_ioas_unmap unmap; struct iommu_option option; struct iommu_vdevice_alloc vdev; + struct iommu_veventq_alloc veventq; struct iommu_vfio_ioas vfio_ioas; struct iommu_viommu_alloc viommu; #ifdef CONFIG_IOMMUFD_TEST @@ -372,6 +373,8 @@ static const struct iommufd_ioctl_op iommufd_ioctl_ops[] = { IOCTL_OP(IOMMU_OPTION, iommufd_option, struct iommu_option, val64), IOCTL_OP(IOMMU_VDEVICE_ALLOC, iommufd_vdevice_alloc_ioctl, struct iommu_vdevice_alloc, virt_id), + IOCTL_OP(IOMMU_VEVENTQ_ALLOC, iommufd_veventq_alloc, + struct iommu_veventq_alloc, out_veventq_fd), IOCTL_OP(IOMMU_VFIO_IOAS, iommufd_vfio_ioas, struct iommu_vfio_ioas, __reserved), IOCTL_OP(IOMMU_VIOMMU_ALLOC, iommufd_viommu_alloc_ioctl, @@ -514,6 +517,10 @@ static const struct iommufd_object_ops iommufd_object_ops[] = { [IOMMUFD_OBJ_VDEVICE] = { .destroy = iommufd_vdevice_destroy, }, + [IOMMUFD_OBJ_VEVENTQ] = { + .destroy = iommufd_veventq_destroy, + .abort = iommufd_veventq_abort, + }, [IOMMUFD_OBJ_VIOMMU] = { .destroy = iommufd_viommu_destroy, }, diff --git a/drivers/iommu/iommufd/viommu.c b/drivers/iommu/iommufd/viommu.c index 69b88e8c7c26..01df2b985f02 100644 --- a/drivers/iommu/iommufd/viommu.c +++ b/drivers/iommu/iommufd/viommu.c @@ -59,6 +59,8 @@ int iommufd_viommu_alloc_ioctl(struct iommufd_ucmd *ucmd) viommu->ictx = ucmd->ictx; viommu->hwpt = hwpt_paging; refcount_inc(&viommu->hwpt->common.obj.users); + INIT_LIST_HEAD(&viommu->veventqs); + init_rwsem(&viommu->veventqs_rwsem); /* * It is the most likely case that a physical IOMMU is unpluggable. A * pluggable IOMMU instance (if exists) is responsible for refcounting From patchwork Tue Mar 11 19:44:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 872667 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2086.outbound.protection.outlook.com [40.107.220.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED7C5264A71; Tue, 11 Mar 2025 19:45:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.220.86 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741722339; cv=fail; b=GE2gXL1YBWwiG9RfQHIOvddGcvdHMBDz7HpD1dIzNEEUOP5XQKe2U9zw67MPy+WqtGMLJHpXNyLD9I80YkRhcoRS3QQbw2VXCecrN1sjD6kb020wfmBjVKX1NgFXafD0oj4jvMx20KkJUjW2nq5b4/OMR3giAQG4UvdW2b5dSfE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741722339; c=relaxed/simple; bh=iecy4fIFlsJi6mG0vyn2Kzx2uCT5cKHBhUEZhmYTA0Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rfEzQXOaXm9j1WLneNco7spdS4aWt5tXGHIvbbPD1PbVHUqh1ZUESbeE1HG2QOEK1yCXdBTvwid2ODOmbOzLmrJ/7NR+k5NL04zCBkI6hvMjhSfi0vsJAWcUSfY2gKosa20DhFDXp1Jk7fJZoYy/cCLWwqlMQ48T8PpiGFT3gCA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=i0spDSxi; arc=fail smtp.client-ip=40.107.220.86 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="i0spDSxi" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=PHk4Xy4aHB3YKgG/kK7O/k5DlzZQpdiC9lpM9ODSaGdfr5RIQMgr67PEAlWut1YtOKtjGij2FxrnPjITOxlSPAliree1RORkCH+fTD6zi80eHbXVhW+IobJyIEiLQTP0pKT08FWz3cz1E4HilZNExzoj6Dr/MxRCIyCEW5fb+1xxFeMv/hyYkuu7qHyFHUC2I77eeyCb6aX8G97kDQz75uW4zIFJCpLKElUzz3OltcDJ+NXomWLn3S0kYxlWPANyYwafh+DulDwrNMUO6bqmJXJWI5jIBm6MO5sgxn7kOEpnR031kIEuB7epbZxv0nSQOCSdLgzkmns0T+rE7XrXNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=WvhDhdq8BqMWYZAy8VZpGH4FR6q5dbcFBgzSx7Z7lc0=; b=YoVGecYLJbdBz9BxiAjCHVOd3SCbRerCEkTfch+ZjVPIBSrbqb97tID1Nf9C0JfVBhrkWhdmo+TTrxpmbxLWxB327GBkYBrqQIoVTqlyizuOCEX0+VundfMQipuU1Hj9KI1P2rbm+0LjHKUoTJHg85eL6JqPHufB50M9ShBH3lcRcU+K+zs4Q+rEFJEL4FA/1724jIg7kcsuLm8LIbBdGKmNhzFvyhsn57qLu0aTGwOIQ4KgmN4OR7KTFsHvr3LTj3+lewNjVBL7vSZWDJkx+AcW8Ty6rB7tRsx9xim34qpkCZIko5PXhcMmonievqqc0MrS5mCNZLKYQg3T/FsZNQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=WvhDhdq8BqMWYZAy8VZpGH4FR6q5dbcFBgzSx7Z7lc0=; b=i0spDSxiWCffECqLyhhhTP6V3tfvMMSpBcaBbHXwcu0bFBfXiCaievqOxdxEpXiDmf2lnWnq0XjybbMVvjuTUgyP4LOWdSjdn3+VYddQmNBAXkM5veFs/GTA7VcGxjvpgstS899OPqv4p4WPRp+4rvCI95JlqIEhlpQ1+BjQYhwdbsnymQ81DXKxA+LPztJf+BK9KpUXwkAEbJrxZTX3g0K7STFEiFxthN+Kdg+w45vojmgcvcZP47qxgxcHLsknHXMWhAjXvi70qBB7eF1henGacQOnCbnm/vutnche/ZDcDXeRLfmY5R/AwCRCoHUgVT7MnK9+NtuelhLqFVV3+A== Received: from BN1PR10CA0002.namprd10.prod.outlook.com (2603:10b6:408:e0::7) by DM4PR12MB6448.namprd12.prod.outlook.com (2603:10b6:8:8a::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8511.27; Tue, 11 Mar 2025 19:45:30 +0000 Received: from BN1PEPF00004687.namprd05.prod.outlook.com (2603:10b6:408:e0:cafe::b7) by BN1PR10CA0002.outlook.office365.com (2603:10b6:408:e0::7) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8534.21 via Frontend Transport; Tue, 11 Mar 2025 19:45:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by BN1PEPF00004687.mail.protection.outlook.com (10.167.243.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8534.20 via Frontend Transport; Tue, 11 Mar 2025 19:45:29 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 11 Mar 2025 12:45:18 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Tue, 11 Mar 2025 12:45:17 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Tue, 11 Mar 2025 12:45:16 -0700 From: Nicolin Chen To: CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 06/14] iommufd/viommu: Add iommufd_viommu_get_vdev_id helper Date: Tue, 11 Mar 2025 12:44:24 -0700 Message-ID: <18b8e8bc1b8104d43b205d21602c036fd0804e56.1741719725.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004687:EE_|DM4PR12MB6448:EE_ X-MS-Office365-Filtering-Correlation-Id: cfa852be-075a-4dbb-ab9c-08dd60d54724 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: wRfPtIoLaNdvqHlFt9C3OJkTJqqk2qM5+a5Uf1UPVwe79z35JfxL6uyJW9j0XlYcYAn64iSlsP0VZ2gl3GcejaS0BcHSSniG7muaCXxaie5aC5fJp2F1SbIhoTEaqboj/y0ERAuqR+KmMze0cAQgh9VtJIpZEKZV2D70jZrAYV8jgrpL+y4i5wrC+Qf15gYKXV9ZZxQtbbu+NGu9ofi9rBYd2aAppKfbrmYztBGTEuVCTUNVZ3nlUpcDBMB9AfI4lm9Fdg+i/Ie1yff4j4d1AYQr9wogCQ8MkObaj9omZDWVKg28K3IUqqTk7K1g/N+sty94I085Pgimc2gPoLhZmXw9/la4DLykQOHysoy6BEIw8O/oqYLC0jKZEP1pVT40Ip7Dc7aBQ+Tu6cL89mNjswsBICY5oQmhjK9BeIwIJ/h0pPS8CU6f9M/ymKPpB2lxb6cLD28V+lgbG4ud4BmlP2T8Kacpx57lg7MR5iucEdmJr1gfAWvhNHCUoeHgaOACWSG7SBmRpirIIa76wGD3J2inXjKLR0hrFFUNHEC+Zb5ui/3Ca1A9NsxyenHxjw7U78nMRM+UPCn+IJArMGwFIiDcas/lqZD5zGSyAI3gVaEM6EN2X6BkS3xW/e0YkytqCbyK6dAWAcqrQmv/43h3prJFE8O9iyb9jLmJw8Dc45dIyzIgw/4A9lRyjgvrzWsBGEGNfm8lzEzMyGupk3yGxICLhpljDf94uRwls1VA1mKx2E5qwHmntbNFXGtM852ghac1XWdEU6kSC6QijIDIS2IFtr8Cys15z+9YUlbdfTRm8BSTMEKEOyVgmx+0Rocvcjrn5oNID/TpClEyvDZpljVH5i/HvA0PKv8ERfERAjwz7GM90AVgJzy+NamrrYxQKhyQQVnpqMYXqzqiPdATxQWMI/fjSeZNZ1WakdHKvptzQxJATHr+zXsnhibXRkMETzuN+oA5tfyTs1Lc532Gz8gt+tn13nxITH/uIaTVTeSg97qZKzPyvzIaauBBCbqxSpjWTQ/QdOMU4i4qfneerl1WYhJZNLKLNmeee4K2lnBWYZFsYTyoiBgU8MFnC4EbATM3SMggcMe3jq8uah5/f90y22AYuL9N1zlPwvuSjd7TtS6JfxO0StjQP01N1qb82zg9Xm5wSwArtSKVnM34VpyvVrtFpUKfefVQ5glEO1vOXrCjybRGAe6QdxBODDry46F2qz0Zq+d0fcyj7R9TjcYMfDEg0RXuCR/HOmfAm2qau1pPgy8QLU9cicU4fzMlT5jiATsAiwuuPhvh0MIiUTcY5Aje1zJ7hedAvZM9qkZwC/xBzV9WuMOj/GjfEeoFZslaQ0apFxocYv6OzVaz6/kNiIMZst78vK0hyiev1ovaMEWQYAIgAmG/Dt831uFLuqsYfh1cQlEFCV4S/xHEqnF72TyGYXJHP4zXampS0Kqb9ypqmP2Jqo/bVmM4VR6zNYfRntZ+gtNKgwc445uE7dSEjX2TfKCXLQGdXQC9wZ0= X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014)(7416014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Mar 2025 19:45:29.2489 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cfa852be-075a-4dbb-ab9c-08dd60d54724 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004687.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6448 This is a reverse search v.s. iommufd_viommu_find_dev, as drivers may want to convert a struct device pointer (physical) to its virtual device ID for an event injection to the user space VM. Again, this avoids exposing more core structures to the drivers, than the iommufd_viommu alone. Reviewed-by: Lu Baolu Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- include/linux/iommufd.h | 9 +++++++++ drivers/iommu/iommufd/driver.c | 24 ++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index 8948b1836940..05cb393aff0a 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -190,6 +190,8 @@ struct iommufd_object *_iommufd_object_alloc(struct iommufd_ctx *ictx, enum iommufd_object_type type); struct device *iommufd_viommu_find_dev(struct iommufd_viommu *viommu, unsigned long vdev_id); +int iommufd_viommu_get_vdev_id(struct iommufd_viommu *viommu, + struct device *dev, unsigned long *vdev_id); #else /* !CONFIG_IOMMUFD_DRIVER_CORE */ static inline struct iommufd_object * _iommufd_object_alloc(struct iommufd_ctx *ictx, size_t size, @@ -203,6 +205,13 @@ iommufd_viommu_find_dev(struct iommufd_viommu *viommu, unsigned long vdev_id) { return NULL; } + +static inline int iommufd_viommu_get_vdev_id(struct iommufd_viommu *viommu, + struct device *dev, + unsigned long *vdev_id) +{ + return -ENOENT; +} #endif /* CONFIG_IOMMUFD_DRIVER_CORE */ /* diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 2d98b04ff1cb..f132b98fb899 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -49,5 +49,29 @@ struct device *iommufd_viommu_find_dev(struct iommufd_viommu *viommu, } EXPORT_SYMBOL_NS_GPL(iommufd_viommu_find_dev, "IOMMUFD"); +/* Return -ENOENT if device is not associated to the vIOMMU */ +int iommufd_viommu_get_vdev_id(struct iommufd_viommu *viommu, + struct device *dev, unsigned long *vdev_id) +{ + struct iommufd_vdevice *vdev; + unsigned long index; + int rc = -ENOENT; + + if (WARN_ON_ONCE(!vdev_id)) + return -EINVAL; + + xa_lock(&viommu->vdevs); + xa_for_each(&viommu->vdevs, index, vdev) { + if (vdev->dev == dev) { + *vdev_id = vdev->id; + rc = 0; + break; + } + } + xa_unlock(&viommu->vdevs); + return rc; +} +EXPORT_SYMBOL_NS_GPL(iommufd_viommu_get_vdev_id, "IOMMUFD"); + MODULE_DESCRIPTION("iommufd code shared with builtin modules"); MODULE_LICENSE("GPL"); From patchwork Tue Mar 11 19:44:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 872666 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2040.outbound.protection.outlook.com [40.107.93.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3553826462C; Tue, 11 Mar 2025 19:45:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.93.40 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741722340; cv=fail; b=XDzGcURQIuS6hMAYM+/UTytleCBnvTLZeFrpcSF7uMNfYmf+Yw24tDPqkkgKdz1r14FkCDwFPeEKiQfXT2rMEYrwQb8eCzJJ8Ta1Ezd6d55/sfx/egRLb3KHlOVI8JA6QgKAwOCzY3nMNkdaXeXE//lm/9Pw1paRqxmvB2/6Ys0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741722340; c=relaxed/simple; bh=RbmqYB3ouXEt01BYZKTJXPb8OVGmtcC88trq8l19SJw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bKie8HgRuTuplyLFut4l1J9yJ6O3TBGWORPfKZkH5+bFgPEv7C3eYK7hKA4ThKYnxNP5UKqNhfTSFQBTZY7xNql8wJFrZhDhA7EOStrkxh13Qnh0nXA6l2gUODf93l0gFL0jdIkovYw8GIlEECPl0NkOj+wOLVjyph7ejJ8W3hg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=SvwT2WZe; arc=fail smtp.client-ip=40.107.93.40 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="SvwT2WZe" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=FYFo9LfwYbjPWQn1JBUJfqaZkyhGKQsqNFo6Ciel5iC5PM/yLRjNW+UNN3ZDgaVoXcSWSfajq1MQp8wN3YQsQ6DGTqT69wHjNoCM0qUF7jZiu+oS5Nx218jRVvBVJAHKBm02wD2IERGzR+pkSozapBDaZmGTT2lhVlAyy832RR02odXq1XT/S+DKRLX12IV6f2lrXAxOYSiR2dOq6fbuetrg+mYUNNCvR6ewVW65it8nG2vDYqtPxJDkt3r7+OvBmPRgLD5MiVXSmNCciBHahUWbvayFwbVA7HabzPPTLf+hkFvdubPEtTQSaMjYUWo9kQb1VJbo5fHBc+V/ZkCMqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=H23MZTa9PfhxhiEvruW5o79lf9Zye7dvmLXJYsQIxuw=; b=vbNRznMwqdEhhZbynq/urZQyABvRK3C2WPxFYzw62rUOYr+EG+j+F2a2nk3Sz9zNuiO/lnggLFFsQnD1rLMY+qvKOqCvc79XRG775isHeQjR12a0qaboAwBh4Td8rkk7sU/lfmxk3Tw2DulSGTQ6nX9iETTILRqsVqw/MEAPm9RUbE+rHN47YbOKEm/OwKkhRe9JNdnPIv136M0Iqds2Qc/A4Ly1TsyFC4H8g6qsi+vTTtgBzQBVfaj+q1ozNDLNKvMYLNFo1/n5ClRQ9tYjpX683UYZ6ss7Vph0fXa+PRSttH3IAVFPMtfY3Rr1Ef4a2N7QJrMydjxqgJsJ6ThldA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=H23MZTa9PfhxhiEvruW5o79lf9Zye7dvmLXJYsQIxuw=; b=SvwT2WZebqX7O0lZ6YmgbdolWIzf625gVNkGHez6Ew/F+DkzGDeXMnfUnCv0CCEaXtvAPr4PvruX+CRltEMrcViMvmtNZEo8JEscx3jQl+uIy1c9YQXeFJQwsIi0WNL8BRKWIcJZWSyVRw2WPB8nJNFUWESI+EAy2dcykV2awpdghbCcH2a1hsEJXRUgTTBPVt2zt4GsBiUAFipNmiHw0IR+TSdgRKERJiniQPcB8plI4pV2GxkB4bhJCMlwgRmDkUCj3d5vLgEi8lMyfbyN7c5AvcTR21ixELWZozr74XbPLnYg5xfCnG+nCgTOVGtwcbDRYNlAgOppVHiw3GfHWA== Received: from BN1PR10CA0008.namprd10.prod.outlook.com (2603:10b6:408:e0::13) by LV8PR12MB9082.namprd12.prod.outlook.com (2603:10b6:408:180::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8511.27; Tue, 11 Mar 2025 19:45:33 +0000 Received: from BN1PEPF00004687.namprd05.prod.outlook.com (2603:10b6:408:e0:cafe::cd) by BN1PR10CA0008.outlook.office365.com (2603:10b6:408:e0::13) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8511.26 via Frontend Transport; Tue, 11 Mar 2025 19:45:33 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by BN1PEPF00004687.mail.protection.outlook.com (10.167.243.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8534.20 via Frontend Transport; Tue, 11 Mar 2025 19:45:33 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 11 Mar 2025 12:45:23 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Tue, 11 Mar 2025 12:45:23 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Tue, 11 Mar 2025 12:45:21 -0700 From: Nicolin Chen To: CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 09/14] iommufd/selftest: Add IOMMU_TEST_OP_TRIGGER_VEVENT for vEVENTQ coverage Date: Tue, 11 Mar 2025 12:44:27 -0700 Message-ID: <1ea874d20e56d65e7cfd6e0e8e01bd3dbd038761.1741719725.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004687:EE_|LV8PR12MB9082:EE_ X-MS-Office365-Filtering-Correlation-Id: baab3fae-4118-406a-90a4-08dd60d54971 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: 0yzFdU27NVVlxnl3hkNV6SpA5xNAHTjjCwBoCpXujbvTINulfwDIW6PpW2pN1lZ0Uk2aMYaXSo8uGLxSL/MMVZ6qPyBZNaE+sm2nSozgusJXcg7SEnKzHjeq6PlVqRBj7NE7RQvAk3Hc6rFvdnI8x52UJ7AMlkQgryBrbpxpDXHmfBeVIYTUyzV2M9I9kfa8qyZppG7zKUjhgS+I8egNpEyDsq6iw+Avdr0yoDCFKSivoSyt2U08+a4daIHZs2yM5ow9aOeDz8y7MQa6uHwpH8SgDW6LqN5Biz/S1EGBr7OD5LbA3g/BVAC7Z0OrN3Uv7w8xwWJlc22zt+8sRgvUW2fJdDfsN/Us9w0KCBXU8zEDS+SywSkgAW8JQ8Sk9oToezHAClI1s3zpPt04P0XgzJcQ7eCRQaxJxH80uCl3358OcrcJmoB2c/TwVX66YbY0XQIo/YPTBjSyDHGz9KuQYn2y+RpQGKtACS2+rh8aUp1F6PbEvrNui5qDd7FXsG16zQx9XNSOcTebyCl2iUnyAVzEo3bfpAva0+OJFzKAsNH5bEpa7Vg0WsuvNNjj5tFFgG4t5AKREKjOqPsLezwtSsGAL6YPEjGOmRE3XFH+9ReqyL1jaNCYaMyPpvNyPgidOhQpYU82RydZxE7P641GGQhlwsE/HBOiGybFDg+tqOXoyBxfgtQZ4l4s8387sa2APA7ldRvZ+CccQ2AJbXWWgJ6lyTfh31AD0uvnPzbmc680rPf1KFq5bNfLXU6GCpIETpVWPF4ZWYYnfyXZQdhwf4MBSO/1YQSk5ZhiOmJelsgz7ouABBTv60dHNQbHVkw6F5uUuKa1pFi3TuDX0kfdFvp7inOrfjXButj5TxbAVPWxoo6UGmMM/Yk1BZ3sc8jJq0s2dN64VQmy/3v/nuuTpo+Qf+w2E7TrgUGctz2Jn+pAk3bnm6q3y60Mhar1ADk4xLYFhwm7rv84XkKofdLRN8wzP77+JxjUa3phitBciEdDoEcwJr62ammkd5Gf8Tuk/6cWhKbzC5cvI7d9pka01pAmCQof/dopgU8VtkdQcJvMyHJ+sphiPXdrx+49zm3RSm5reQTHOs3tU5iPZ+X71RDcwu7wMG7v7DRW23LPtk7H6sJvbP+iluf3bW/4K197d938E58Pnf+b49mmbA0Rt9iH2AXflT4AR7Z3Cj8TVRinRdvML4dJtsuS1qMpIMcgQ7ISO+zr3a+ZMLOcY/OwVyXnh0lpSNy26NbaASpUKVcYKsN3Ccu12u8+JHviFNolhcNc23EbUFvnZNpSXyq33v0DYXqGfUbltsK9UZSxxSU4aw6URLWKnY1w5T7bGsOeIuOOMj0EnxHQDSmsasX+OO+6WyqTEWkXDF6WhWY+Ht/6033IItw543qgU1MH0hsVkPicxiwb25bWN6z+Zj/qYlc92AAMLdpIQyaw+y445Z/g8d51hgQ7R0trfzw6uqVFLD2J55Nd7wNk3gQi1cx8qOTnZ+y2kuzEpAQXlSeVxPo= X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014)(7416014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Mar 2025 19:45:33.1083 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: baab3fae-4118-406a-90a4-08dd60d54971 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004687.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9082 The handler will get vDEVICE object from the given mdev and convert it to its per-vIOMMU virtual ID to mimic a real IOMMU driver. Reviewed-by: Kevin Tian Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/iommufd_test.h | 10 ++++++++++ drivers/iommu/iommufd/selftest.c | 30 ++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/drivers/iommu/iommufd/iommufd_test.h b/drivers/iommu/iommufd/iommufd_test.h index a6b7a163f636..87e9165cea27 100644 --- a/drivers/iommu/iommufd/iommufd_test.h +++ b/drivers/iommu/iommufd/iommufd_test.h @@ -24,6 +24,7 @@ enum { IOMMU_TEST_OP_MD_CHECK_IOTLB, IOMMU_TEST_OP_TRIGGER_IOPF, IOMMU_TEST_OP_DEV_CHECK_CACHE, + IOMMU_TEST_OP_TRIGGER_VEVENT, }; enum { @@ -145,6 +146,9 @@ struct iommu_test_cmd { __u32 id; __u32 cache; } check_dev_cache; + struct { + __u32 dev_id; + } trigger_vevent; }; __u32 last; }; @@ -212,4 +216,10 @@ struct iommu_viommu_invalidate_selftest { __u32 cache_id; }; +#define IOMMU_VEVENTQ_TYPE_SELFTEST 0xbeefbeef + +struct iommu_viommu_event_selftest { + __u32 virt_id; +}; + #endif diff --git a/drivers/iommu/iommufd/selftest.c b/drivers/iommu/iommufd/selftest.c index ba84bacbce2e..d55dde28e9bc 100644 --- a/drivers/iommu/iommufd/selftest.c +++ b/drivers/iommu/iommufd/selftest.c @@ -1621,6 +1621,34 @@ static int iommufd_test_trigger_iopf(struct iommufd_ucmd *ucmd, return 0; } +static int iommufd_test_trigger_vevent(struct iommufd_ucmd *ucmd, + struct iommu_test_cmd *cmd) +{ + struct iommu_viommu_event_selftest test = {}; + struct iommufd_device *idev; + struct mock_dev *mdev; + int rc = -ENOENT; + + idev = iommufd_get_device(ucmd, cmd->trigger_vevent.dev_id); + if (IS_ERR(idev)) + return PTR_ERR(idev); + mdev = to_mock_dev(idev->dev); + + down_read(&mdev->viommu_rwsem); + if (!mdev->viommu || !mdev->vdev_id) + goto out_unlock; + + test.virt_id = mdev->vdev_id; + rc = iommufd_viommu_report_event(&mdev->viommu->core, + IOMMU_VEVENTQ_TYPE_SELFTEST, &test, + sizeof(test)); +out_unlock: + up_read(&mdev->viommu_rwsem); + iommufd_put_object(ucmd->ictx, &idev->obj); + + return rc; +} + void iommufd_selftest_destroy(struct iommufd_object *obj) { struct selftest_obj *sobj = to_selftest_obj(obj); @@ -1702,6 +1730,8 @@ int iommufd_test(struct iommufd_ucmd *ucmd) cmd->dirty.flags); case IOMMU_TEST_OP_TRIGGER_IOPF: return iommufd_test_trigger_iopf(ucmd, cmd); + case IOMMU_TEST_OP_TRIGGER_VEVENT: + return iommufd_test_trigger_vevent(ucmd, cmd); default: return -EOPNOTSUPP; } From patchwork Tue Mar 11 19:44:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 872665 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2062.outbound.protection.outlook.com [40.107.237.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5F1C266189; Tue, 11 Mar 2025 19:45:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.237.62 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741722346; cv=fail; b=UgZg9Oqu5oRbIIMXB+kSLzzByVqosUC0k9VitXTKOngK1v+OZGjAxX6YWX0giTyByBx3w7jHrN87ObsuhhFt0jOuoPC6tvu9yHAR96g4dd4FILP8UfBUm6hBe6A6emvmmky0Z2mqVNvdU+l8rVBXuFSIEC6w2p6Kij5/g0GzSH8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741722346; c=relaxed/simple; bh=2Q+la1Vr7KdS12V/vYxQZgWA60+Htge+0ih7MtG1OTc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ztvl+/CRkMThQ/aq61IZF9rg1wfsECswcrO7HcXomGGehqaUKr/iLzHaA2WxkfXRgQnWww8rCf0VswkMLGrHxmlsHkQ5mnTGR6gh9+vTpmS1A+cEumgW+gUFLMSbHG/vh+JHZL9L4VtcBDxhnrUr2qBTmrmoQd62y/XKhkCP1d8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Hn3Q/jZu; arc=fail smtp.client-ip=40.107.237.62 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Hn3Q/jZu" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=RTBodu9NVz/xQwOwX0lUf9pXaC53VFx26+UqJyHZ74tDaMZCDzCuEp8BSyhcIb9y4iiHlqBVp451j5uxfZ7YAuwqIz6aGWdBCNJF2c0TDVd0VH0tcKJxZfM5U0HgvoJr4Itl3njE/FPTLgABdmHfwHrX9TdnaOBGw4F3xtYeF+chsrSk4/liGBxl8KNPWNl7/NzGtfEqdNXGmldnYffkeXqWU+gnycsRfo4EtAZOspSoLdanBDhOCyljBgXUj/1qrkBeI8RtCK5TvkhlY5a5HBn+9LNMrSeCaia3E5rXrekhHW4BkgPAexL4CiGrC1mvZ/CgzRcUfYgO0Rd9nfJr7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6NYHNYHk4Eskt64jA06hjjLb7nD8fIqO7zbe3QJ7OYY=; b=LZsl85bFQ3r9Q/imJ8/5A2q2VLnmVDpwiy0H/f3EKg+MpdYUbHCdJ2S5Rfs2HlLPIHhsNbF3M4Mb6vRE7PvANq7d2D+agtRJrYeE5+LbRk7nYh+GjnCeOlHex6cJMWBAS2nDg0BtHat6vrPJCIWfYuNuy+E/hhnicJ9PDjJS+GPXu0yjfvcA8el9jLzWaAIy01Ii1DzqaPZ/ZR4ZEZEYydrTggAsqBBrqpG5Ez/bMuYb6S9j+c921tFVf5eAqhKWYZZVwrenbSLTl2NwvTzc+d9QdoM6xQDBtS8yCueBPNyb59/O6p9JiVO09JhWnPE3FTVZHNK1O02zyArsw9QBig== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6NYHNYHk4Eskt64jA06hjjLb7nD8fIqO7zbe3QJ7OYY=; b=Hn3Q/jZuDaA1K31d4hZSzfAIYCv2k/7/wFNt983PeRJEm9UO0K67CGTpX/OLMUrBsNd/WwPIIoOuJ4bb6kBEkgXfz7Ck0R45lQT3u6o9FYyY0gP8zwLOHuQoiHg4ZTfvb5gRD7vxcLM1u+oBFtOCCaRRCFG3AU8LpfnbwXr01kIp6jL4m/J3LTrtrDTjQiYYN9L0YLvgY7rMw/QuZtLSpdADOYURcVEevZrKXtftPeJBfaTDJJ+AXCJJlmJUbCJ4/qUvB05sso86cUg2gO4gg0ME6kMNL8TSDd0fQOIp7DEp7tr/YvUHN6xs6X6VVeHJW+kLB0UlejnO0jfrEiM53w== Received: from BY5PR16CA0030.namprd16.prod.outlook.com (2603:10b6:a03:1a0::43) by CH3PR12MB8969.namprd12.prod.outlook.com (2603:10b6:610:17c::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8511.27; Tue, 11 Mar 2025 19:45:38 +0000 Received: from SJ1PEPF00001CDE.namprd05.prod.outlook.com (2603:10b6:a03:1a0:cafe::36) by BY5PR16CA0030.outlook.office365.com (2603:10b6:a03:1a0::43) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8511.24 via Frontend Transport; Tue, 11 Mar 2025 19:45:38 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SJ1PEPF00001CDE.mail.protection.outlook.com (10.167.242.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8534.20 via Frontend Transport; Tue, 11 Mar 2025 19:45:38 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 11 Mar 2025 12:45:27 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Tue, 11 Mar 2025 12:45:26 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Tue, 11 Mar 2025 12:45:25 -0700 From: Nicolin Chen To: CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 11/14] Documentation: userspace-api: iommufd: Update FAULT and VEVENTQ Date: Tue, 11 Mar 2025 12:44:29 -0700 Message-ID: <09829fbc218872d242323d8834da4bec187ce6f4.1741719725.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CDE:EE_|CH3PR12MB8969:EE_ X-MS-Office365-Filtering-Correlation-Id: 47318468-a7f4-442b-d12d-08dd60d54c5c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: q5YSd3frGtciYp9a+Zuq6TiZtlNwJCk393pel8deh/3OlPEePbPGD95HmrXAzpgp1egqmdEZwJY/waUMEoR1rZeBUZCP98x8SHVQnwAuJUGJY2XhTqzu3ECi3K6lY5GeFlf6sj6MgsyoXaunxvQBSWF2kryYPkq2qJanSQ4IcHphHNHk5eujqYos10l8UNr2Il1lMpegMxlCNQIPVaja5CHW0lVA2JVbUc8QA/iWycf2BOxgFzu8xfNnWA3BHU5SRc290Dulkv8mi5RSfEDjTvqNzngsjTCszj2CsPbye5GtivLh/y74/zFJLOfdmrD9pnfQruWfUHJ72PZASawsdJy+oaDfFMNhkniLZTSQVkcroWSKUdycSPnIKmUcQ283OfpugK/aibixG/UKZFuBI7LoU4lgrHgY1zUMQh00vOdKmHao7OEC7+S7aeGr+j0HfHdi4Ia8TEfIjw6++u/LXMD3ABfw3Ya5cWmv2q8TXxSP40O2OpKjpLC55Z5pUmBnR1rKrB2X0o6jZhBTM7VEKydHIp3bMHVex0VEFT4o1BTJ6qeoWshY2m3NY6OL9DVZhSbBbF/PTqjivGytnT8y4/nM3Ncip7EVkjagelxXUOfRAhQmDczqS3pmstc/+hWSo1aK5+KEcsyMLNWwZH03fw9CpNd9bamPLG4uMfM2NuuQ0sNBf2Tm0j3GyGuI8ysSSR1XeC+r2wkQaOiOCDY9Q7MPnBMScsLTQ8RTNjZYCec7lggXzE2iyn3WwZJMfgesPqNZTd/imPuzepmpsBvkE3BQf0wYv3SBqKaLYft6Zs5QbCgc0kTHNR0y2h8FU9SY0lHuu9F2LVXfK5Td7c8l+uhmhuh9Fu1V4R4wSi67MVbo/zs4z8rio8GifdkDiC2ZUQmOORWvI5hPE65wlVkzZHc4tUxx9GHKGCy9VqnjrAGj4kJYhNQgBUlRg0kio2xlXL0AK8a0YcxdjDi8ei1tufCs6j5xqrz1UJ3OkSiNIhQdX3MoXLJrn8HC7hgzU0eLyKHVVN99VvFv3wvO5M3FrToyF8aq4RvRays+MGsaxbGFbDNZ8cpFh+c5nEs9VPPGqgPro42y6iOz7GlxjEZF0bZwYRydBqFx8UjjbFYNKofFpkivlxWLmkA2JYUkSliqNaPFyEiijet+pDrr4ZdLhQaKF6GlB2SyIGpM1A0UBGDoQM/ljpkOW0lyaEaR3aJl6TyeXLon3ffr569sgq6nEK8ykbmYrKNgdS2qBVMMAs8v2ou9zLGEo/nTdTqes6+ViGZV8m7GwqeO6DuzhC4RGfS3L4Cs06D49tCrlRP/hwA4A7mThEGZRXZztuXs8Wk1/K+xgM5q9CMJqDXGTpoY40ohdktvoISeadVFKjehhrQfmAWQYeh2pY99CAnfkS+FvKcUCLgJSXdrWUL7YcfLw8EWdy801fiaWDD3Lp/cSuQ8IapbJnZAs4VzFzYpgv95KJUcB4niTFEVMFPHCfFOs1Af2QN3/UQt+uym5wohq+8= X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014)(7416014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Mar 2025 19:45:38.1149 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 47318468-a7f4-442b-d12d-08dd60d54c5c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CDE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8969 With the introduction of the new objects, update the doc to reflect that. Reviewed-by: Lu Baolu Reviewed-by: Kevin Tian Reviewed-by: Bagas Sanjaya Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- Documentation/userspace-api/iommufd.rst | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/userspace-api/iommufd.rst b/Documentation/userspace-api/iommufd.rst index 70289d6815d2..b0df15865dec 100644 --- a/Documentation/userspace-api/iommufd.rst +++ b/Documentation/userspace-api/iommufd.rst @@ -63,6 +63,13 @@ Following IOMMUFD objects are exposed to userspace: space usually has mappings from guest-level I/O virtual addresses to guest- level physical addresses. +- IOMMUFD_FAULT, representing a software queue for an HWPT reporting IO page + faults using the IOMMU HW's PRI (Page Request Interface). This queue object + provides user space an FD to poll the page fault events and also to respond + to those events. A FAULT object must be created first to get a fault_id that + could be then used to allocate a fault-enabled HWPT via the IOMMU_HWPT_ALLOC + command by setting the IOMMU_HWPT_FAULT_ID_VALID bit in its flags field. + - IOMMUFD_OBJ_VIOMMU, representing a slice of the physical IOMMU instance, passed to or shared with a VM. It may be some HW-accelerated virtualization features and some SW resources used by the VM. For examples: @@ -109,6 +116,14 @@ Following IOMMUFD objects are exposed to userspace: vIOMMU, which is a separate ioctl call from attaching the same device to an HWPT_PAGING that the vIOMMU holds. +- IOMMUFD_OBJ_VEVENTQ, representing a software queue for a vIOMMU to report its + events such as translation faults occurred to a nested stage-1 (excluding I/O + page faults that should go through IOMMUFD_OBJ_FAULT) and HW-specific events. + This queue object provides user space an FD to poll/read the vIOMMU events. A + vIOMMU object must be created first to get its viommu_id, which could be then + used to allocate a vEVENTQ. Each vIOMMU can support multiple types of vEVENTS, + but is confined to one vEVENTQ per vEVENTQ type. + All user-visible objects are destroyed via the IOMMU_DESTROY uAPI. The diagrams below show relationships between user-visible objects and kernel @@ -251,8 +266,10 @@ User visible objects are backed by following datastructures: - iommufd_device for IOMMUFD_OBJ_DEVICE. - iommufd_hwpt_paging for IOMMUFD_OBJ_HWPT_PAGING. - iommufd_hwpt_nested for IOMMUFD_OBJ_HWPT_NESTED. +- iommufd_fault for IOMMUFD_OBJ_FAULT. - iommufd_viommu for IOMMUFD_OBJ_VIOMMU. - iommufd_vdevice for IOMMUFD_OBJ_VDEVICE. +- iommufd_veventq for IOMMUFD_OBJ_VEVENTQ. Several terminologies when looking at these datastructures: From patchwork Tue Mar 11 19:44:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 872664 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2063.outbound.protection.outlook.com [40.107.95.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1E0626658E; Tue, 11 Mar 2025 19:45:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.95.63 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741722354; cv=fail; b=uTMDgzZ3cU8rRPq8prQA0/1v4lDWDtwunaAbTGk9bgLypwSkg9J4DUgAqLAUtH1XorirKwFf71oG+KYCSAszTGC90A8+wZ3sXZU9s7+1G5QQHmPIbcqFk/YFTDrZXuvUTS4AqYS3yngzp/ivbL5UB7gTvnyaXimf3kWmvprpRmY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741722354; c=relaxed/simple; bh=xI8xWRHnOfI9codLmeqhcs41jhFYzFCoSa1pEsa1jfw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Np/zOuDk2LoCq4cy5eoRFrNnJ5aehzHke8MJn755xFIHNL02o530m3m6DztZDQhxPxYD/mk0VK7wTdkaqhQgdt5Hzphc3dtg4EuvwJoWHwK6623Dnq6oxQXGmPATSjkQVNFAEcSwGHpSudH7EBgz0cYBCIl9+E3HSSRJhw51Cd8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=iPERSWnQ; arc=fail smtp.client-ip=40.107.95.63 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="iPERSWnQ" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=s+4Ybv4KizyKZCgv5iPCax09bDxiH0Vjeex2SEG5too5ohSxRXQzbJdTzZ3MTT8BQnZNCH6nVQJB5mlYkoxX47CojLu1V50WdelGE52BqdFqzkoOG6v8mIMWUxbnhe5k340/3IC5mv42MgKaLFyFr2gaxX2x12/LaYZjoysYEGGXw6WgsQoCt0iW7jnDOH0kBdmxViPFtKH3vaQSTt/112VtLzSWixP+GM3mPH3Ty0i4vxquV4nJNdO4A6aF9s9iJqVZd7gJBfAQvKvUpfpZK/nBkh7Fvv0oyirFEyP1fLxBzBpBg9UokopyFqs+pvlCbp1bnaLAsb4Tuqp0YPXm7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=NxiS32odSr0DkjElkJMQNekMxcZtMgE+1qiaDaWeSuk=; b=mpJyfd5GaiLn6gvdn5zd4G/I5pQ2kU9PYQyupM+AguJuh9+kwWIrNzXRgfaIebcvkDVFAJOKnAtU7RLb+CaP6AL4YNuPaR4t1/REpHCMReqQfygS3kaieQjCG0nbLi+s2RUTHQOJMYlECgbXblJQNSA6g3gSwhM75QNNr/8OVyDw/5VZbSiB6Di78hGj/joPbudfBbI4xhmUrSedphKl0LQNCVp7Y0CGfIGEEmDYhLEsc4IXoAiS0UnUQA8IWf2padIA2KsGv33fJH6Ta5CXo7HKVhqUTyO0OJwnF46fG8DwAdUtGSFVdq8KEpqRb0iw/emhHqb5BBy0L37MIBHRJg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NxiS32odSr0DkjElkJMQNekMxcZtMgE+1qiaDaWeSuk=; b=iPERSWnQVMw8+/U8r3R920GfdFhruNFucznZGwSEoV6M4HZ7r67cRNT9YsWr87h1Or+JYcivz/FsNhcRMh/AUWx8deAYwlkKCvIzDGVQ++YJLYsIlNJfA2jykFdR8YfpJ5zqfGmZnaz45U+YXfPiISvrZpsEb6OLcMbfoqHFWsGB0EVDP0J6Gv1dckEOrSkigneN93B6kAajRhpOXcMrdWV5UdruJuuBf+uWuMnxio6H3Jcb1vvdRH6C+r9V1yq8Gb10BMS7tbIuTJYmZgJk1to9+blAfqmZ3XXHiIdQ2DinSHoxCamJsFzRbTdI+92U/FrEfccZm0T1GYBYYDXtwA== Received: from SJ0PR13CA0124.namprd13.prod.outlook.com (2603:10b6:a03:2c6::9) by LV2PR12MB5800.namprd12.prod.outlook.com (2603:10b6:408:178::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8511.27; Tue, 11 Mar 2025 19:45:43 +0000 Received: from SJ1PEPF00001CDD.namprd05.prod.outlook.com (2603:10b6:a03:2c6:cafe::84) by SJ0PR13CA0124.outlook.office365.com (2603:10b6:a03:2c6::9) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8534.18 via Frontend Transport; Tue, 11 Mar 2025 19:45:42 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SJ1PEPF00001CDD.mail.protection.outlook.com (10.167.242.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8534.20 via Frontend Transport; Tue, 11 Mar 2025 19:45:42 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 11 Mar 2025 12:45:30 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Tue, 11 Mar 2025 12:45:30 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Tue, 11 Mar 2025 12:45:28 -0700 From: Nicolin Chen To: CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 13/14] iommu/arm-smmu-v3: Report events that belong to devices attached to vIOMMU Date: Tue, 11 Mar 2025 12:44:31 -0700 Message-ID: <5cf6719682fdfdabffdb08374cdf31ad2466d75a.1741719725.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CDD:EE_|LV2PR12MB5800:EE_ X-MS-Office365-Filtering-Correlation-Id: 8e45fcd9-ed4a-4156-ec5f-08dd60d54edc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|7416014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: GffSZLlkOoi7G5wNC4brBcZqRJVhTUix0y8rrmR3Vq2zStur7fvmFNQ3WFqqRc6vEk21V2v2yksXw9iG6Xsn49gLQ/fW/Y40lwELC5xcHIWQsJMmGmuOw8F7lnUBq6qcS9ghHnZ0IB8cUtbGLS549dh6zIt4VUJKisugv8+IuYs2WLs9VW2htutxORFbqVTkSO/RccquCpdzcYixxRRBffP523Ex/J9kmy6SXGAIkgPpS9REltDUEUPFGDXLGpRqsvJ9a9wPTzhrVm2xsFNFg0+Ih6qOLT3RvLvzaHcTl/VsUSxMHHN4ds3NXjU9/BlhX3gM60pJvakFBwRTwWo6SmpJVM1Xx+jiLGQ08XS6Qjm23E0q8/6kjddteGU21SFX21NHKNE/CVgaOhaodB5xSpfIzZOrJ612WDUGjh9iIshXq0MywRNffzNJlhgGSqNFGmV+/rmJL3ZKtfxEXzKiUID6sid/oon9iCufesg+4qOYooqD2rzoFiPNuce5yCyhtLig7rOATdUudojtNnHRYZVvj1IALGUZenvPGKhN0j5shrTfVOV4PB2uLywSCgZLPrrDXspSugzne1NVX3vD0Y4F2lIr85VslFAE00p+fw+coDOr3RCI5I3LARZTQNcrZTSo1npRwghwxHs6F9/lKNPdQCqPVpgKB5fCpFXyouQp3E6HVfOdw0vNmex67Zr7YqxksYeI9Jb3F7tfwwN1EvfKCJVbBV/gSur5saIfKEvKROL7foYtjqDSL0HLPr97Q/bjFa8DKiNLYciDC34q83TChNmg1YLVT/iUvomajrmaONHBty3V78NFXVWgoX3ObNGdIH5sygGaF7q/QBJK/2SPyRU02PpN2+WaX+SIHOYKu0R61o8Gyy8fmX4+7J55igvkTiQmD8qGOa57E+bK5YfUd3up1tfyFUUHTN8MxUmJ2gH6ty9x1V6c/4QLQ9Cz3UUAXJ2xG3UC/+6K69KmcWcWb14Yk7NkpjMzUtB/unRBKRhWerP89b7M9nSH92xfjy7XGXIilFIqMxS7uSkxeixAZnj4dHi9iGLBqlDbEoc/wTz1Po6ulwR4p8B9EDYqmq3X7Qp6oUGySGiNl60E7ZPy7Z6t1jF94BcrBt3z03WKtavXCt+BrhkBLf5DRfw3aMxMNEsazQqP/DAhYIef8b59xkenxOH772kBQaWNtujEk73ZbHw9K5X1udHMlQSBWpQ840fpJNcbfZmzSmJGU+911og4wO8bO2hNJPA8bkhLCTsHE/zLTf9EDUMUYzCWJxYwQYfNlbnveJT+HBFgL2VHREUKsuvAUe9DdsN43YngM+p3G3Jt81U0S9Cbtv7S9u41a0Ii1c+4dUlZwsuhBOmSLikqZG0qanVxe83G4Usa7MudgaDP6WdRn/ykC0HA6u89QXO5BWp6vXSAyQiY7tm0Z7i5BBsIuoY+3+aoaLLkqYk96Xt1vZGKKMH93fPz6n1/AH1soxmMTOHP+hP3qU57fQ2EfRzz3erhuZve3F4= X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(7416014)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Mar 2025 19:45:42.3724 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8e45fcd9-ed4a-4156-ec5f-08dd60d54edc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CDD.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5800 Aside from the IOPF framework, iommufd provides an additional pathway to report hardware events, via the vEVENTQ of vIOMMU infrastructure. Define an iommu_vevent_arm_smmuv3 uAPI structure, and report stage-1 events in the threaded IRQ handler. Also, add another four event record types that can be forwarded to a VM. Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Reviewed-by: Pranjal Shrivastava Acked-by: Will Deacon Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 +++ include/uapi/linux/iommufd.h | 23 ++++++++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 17 ++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 58 +++++++++++-------- 4 files changed, 80 insertions(+), 25 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 557b300a3a0f..df06076a1698 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1066,6 +1066,7 @@ int arm_smmu_attach_prepare_vmaster(struct arm_smmu_attach_state *state, struct arm_smmu_nested_domain *nested_domain); void arm_smmu_attach_commit_vmaster(struct arm_smmu_attach_state *state); void arm_smmu_master_clear_vmaster(struct arm_smmu_master *master); +int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaster, u64 *evt); #else #define arm_smmu_hw_info NULL #define arm_vsmmu_alloc NULL @@ -1086,6 +1087,12 @@ static inline void arm_smmu_master_clear_vmaster(struct arm_smmu_master *master) { } + +static inline int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaster, + u64 *evt) +{ + return -EOPNOTSUPP; +} #endif /* CONFIG_ARM_SMMU_V3_IOMMUFD */ #endif /* _ARM_SMMU_V3_H */ diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 2ade4839880d..5fc7e27804b7 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -1054,9 +1054,32 @@ struct iommufd_vevent_header { /** * enum iommu_veventq_type - Virtual Event Queue Type * @IOMMU_VEVENTQ_TYPE_DEFAULT: Reserved for future use + * @IOMMU_VEVENTQ_TYPE_ARM_SMMUV3: ARM SMMUv3 Virtual Event Queue */ enum iommu_veventq_type { IOMMU_VEVENTQ_TYPE_DEFAULT = 0, + IOMMU_VEVENTQ_TYPE_ARM_SMMUV3 = 1, +}; + +/** + * struct iommu_vevent_arm_smmuv3 - ARM SMMUv3 Virtual Event + * (IOMMU_VEVENTQ_TYPE_ARM_SMMUV3) + * @evt: 256-bit ARM SMMUv3 Event record, little-endian. + * Reported event records: (Refer to "7.3 Event records" in SMMUv3 HW Spec) + * - 0x04 C_BAD_STE + * - 0x06 F_STREAM_DISABLED + * - 0x08 C_BAD_SUBSTREAMID + * - 0x0a C_BAD_CD + * - 0x10 F_TRANSLATION + * - 0x11 F_ADDR_SIZE + * - 0x12 F_ACCESS + * - 0x13 F_PERMISSION + * + * StreamID field reports a virtual device ID. To receive a virtual event for a + * device, a vDEVICE must be allocated via IOMMU_VDEVICE_ALLOC. + */ +struct iommu_vevent_arm_smmuv3 { + __aligned_le64 evt[4]; }; /** diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index dfc80e1a8e2e..65adfed56969 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -433,4 +433,21 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, return &vsmmu->core; } +int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaster, u64 *evt) +{ + struct iommu_vevent_arm_smmuv3 vevt; + int i; + + lockdep_assert_held(&vmaster->vsmmu->smmu->streams_mutex); + + vevt.evt[0] = cpu_to_le64((evt[0] & ~EVTQ_0_SID) | + FIELD_PREP(EVTQ_0_SID, vmaster->vsid)); + for (i = 1; i < EVTQ_ENT_DWORDS; i++) + vevt.evt[i] = cpu_to_le64(evt[i]); + + return iommufd_viommu_report_event(&vmaster->vsmmu->core, + IOMMU_VEVENTQ_TYPE_ARM_SMMUV3, &vevt, + sizeof(vevt)); +} + MODULE_IMPORT_NS("IOMMUFD"); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 964d2cf27d3d..5fa817a8f5f1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1813,8 +1813,8 @@ static void arm_smmu_decode_event(struct arm_smmu_device *smmu, u64 *raw, mutex_unlock(&smmu->streams_mutex); } -static int arm_smmu_handle_event(struct arm_smmu_device *smmu, - struct arm_smmu_event *event) +static int arm_smmu_handle_event(struct arm_smmu_device *smmu, u64 *evt, + struct arm_smmu_event *event) { int ret = 0; u32 perm = 0; @@ -1823,6 +1823,10 @@ static int arm_smmu_handle_event(struct arm_smmu_device *smmu, struct iommu_fault *flt = &fault_evt.fault; switch (event->id) { + case EVT_ID_BAD_STE_CONFIG: + case EVT_ID_STREAM_DISABLED_FAULT: + case EVT_ID_BAD_SUBSTREAMID_CONFIG: + case EVT_ID_BAD_CD_CONFIG: case EVT_ID_TRANSLATION_FAULT: case EVT_ID_ADDR_SIZE_FAULT: case EVT_ID_ACCESS_FAULT: @@ -1832,31 +1836,30 @@ static int arm_smmu_handle_event(struct arm_smmu_device *smmu, return -EOPNOTSUPP; } - if (!event->stall) - return -EOPNOTSUPP; - - if (event->read) - perm |= IOMMU_FAULT_PERM_READ; - else - perm |= IOMMU_FAULT_PERM_WRITE; + if (event->stall) { + if (event->read) + perm |= IOMMU_FAULT_PERM_READ; + else + perm |= IOMMU_FAULT_PERM_WRITE; - if (event->instruction) - perm |= IOMMU_FAULT_PERM_EXEC; + if (event->instruction) + perm |= IOMMU_FAULT_PERM_EXEC; - if (event->privileged) - perm |= IOMMU_FAULT_PERM_PRIV; + if (event->privileged) + perm |= IOMMU_FAULT_PERM_PRIV; - flt->type = IOMMU_FAULT_PAGE_REQ; - flt->prm = (struct iommu_fault_page_request) { - .flags = IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE, - .grpid = event->stag, - .perm = perm, - .addr = event->iova, - }; + flt->type = IOMMU_FAULT_PAGE_REQ; + flt->prm = (struct iommu_fault_page_request){ + .flags = IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE, + .grpid = event->stag, + .perm = perm, + .addr = event->iova, + }; - if (event->ssv) { - flt->prm.flags |= IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; - flt->prm.pasid = event->ssid; + if (event->ssv) { + flt->prm.flags |= IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; + flt->prm.pasid = event->ssid; + } } mutex_lock(&smmu->streams_mutex); @@ -1866,7 +1869,12 @@ static int arm_smmu_handle_event(struct arm_smmu_device *smmu, goto out_unlock; } - ret = iommu_report_device_fault(master->dev, &fault_evt); + if (event->stall) + ret = iommu_report_device_fault(master->dev, &fault_evt); + else if (master->vmaster && !event->s2) + ret = arm_vmaster_report_event(master->vmaster, evt); + else + ret = -EOPNOTSUPP; /* Unhandled events should be pinned */ out_unlock: mutex_unlock(&smmu->streams_mutex); return ret; @@ -1944,7 +1952,7 @@ static irqreturn_t arm_smmu_evtq_thread(int irq, void *dev) do { while (!queue_remove_raw(q, evt)) { arm_smmu_decode_event(smmu, evt, &event); - if (arm_smmu_handle_event(smmu, &event)) + if (arm_smmu_handle_event(smmu, evt, &event)) arm_smmu_dump_event(smmu, evt, &event, &rs); put_device(event.dev);