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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec366a699sm76334805e9.38.2025.04.05.09.13.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:13:26 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v4 01/16] target/riscv: Remove AccelCPUClass::cpu_class_init need Date: Sat, 5 Apr 2025 18:13:05 +0200 Message-ID: <20250405161320.76854-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Expose riscv_tcg_ops symbol, then directly set it as CPUClass::tcg_ops in TYPE_RISCV_CPU's class_init(), using CONFIG_TCG #ifdef'ry. No need for the AccelCPUClass::cpu_class_init() handler anymore. Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/tcg/tcg-cpu.h | 2 ++ target/riscv/cpu.c | 3 +++ target/riscv/tcg/tcg-cpu.c | 16 +--------------- 3 files changed, 6 insertions(+), 15 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h index ce94253fe42..a23716a5acf 100644 --- a/target/riscv/tcg/tcg-cpu.h +++ b/target/riscv/tcg/tcg-cpu.h @@ -26,6 +26,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp); bool riscv_cpu_tcg_compatible(RISCVCPU *cpu); +extern const TCGCPUOps riscv_tcg_ops; + struct DisasContext; struct RISCVCPUConfig; typedef struct RISCVDecoder { diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ad534cee51f..2b830b33178 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3054,6 +3054,9 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data) cc->get_arch_id = riscv_get_arch_id; #endif cc->gdb_arch_name = riscv_gdb_arch_name; +#ifdef CONFIG_TCG + cc->tcg_ops = &riscv_tcg_ops; +#endif /* CONFIG_TCG */ device_class_set_props(dc, riscv_cpu_properties); } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 5d0429b4d00..6a87367f239 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -139,7 +139,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, env->excp_uw2 = data[2]; } -static const TCGCPUOps riscv_tcg_ops = { +const TCGCPUOps riscv_tcg_ops = { .initialize = riscv_translate_init, .translate_code = riscv_translate_code, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, @@ -1524,24 +1524,10 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs) } } -static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) -{ - /* - * All cpus use the same set of operations. - */ - cc->tcg_ops = &riscv_tcg_ops; -} - -static void riscv_tcg_cpu_class_init(CPUClass *cc) -{ - cc->init_accel_cpu = riscv_tcg_cpu_init_ops; -} - static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) { AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); - acc->cpu_class_init = riscv_tcg_cpu_class_init; acc->cpu_instance_init = riscv_tcg_cpu_instance_init; acc->cpu_target_realize = riscv_tcg_cpu_realize; } From patchwork Sat Apr 5 16:13:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 878413 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp4288489wrs; Sat, 5 Apr 2025 09:14:06 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVViyeBF524BOIxrNu5al7FwGFgSHjBCTjhYlrdTNwPQsQMSc+ITDD2mWdeqAg199ru45/1Zg==@linaro.org X-Google-Smtp-Source: AGHT+IGYAJwVQLzMPiXjvu2OZY8hklBXmSyED6NkeVPdfUdg/eNehuc8lFOBGC2ZUr4xM7JObUt6 X-Received: by 2002:a05:622a:1349:b0:477:548:849e with SMTP id d75a77b69052e-47925958054mr80921671cf.15.1743869645929; Sat, 05 Apr 2025 09:14:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743869645; cv=none; d=google.com; s=arc-20240605; b=EUvSHWzid3TnhkLAuNBdroBJrarpPj3LGAF5vDjpxsjFHZFSzWg2XOeinW+/fh3sc8 zpow2jL4EA6VXK73YOe2yF+ZnE/GN7L+tSwwCXGpF6wY2aTDY2Gnyvfx/uX4yGJf5gXy 8qiXvf7DGwk3PvvIsDVLpXci5zWm85cypKBjNhFL4mnkd+D5bqGSUUjn4sNTEZ8aL2aP FIHS9DFXJndeZNSdgEqQmpVA+enTHO6jJg7zq/6mFEaEyukOyBI/ZvmuNmLoc9jfXtQp Mf/tjrLxqvYbPV1d4oCzQgUO1ccomtRNowCRdrDECK2xEzT3AS8eXc1bWnum/AZAxqED LiFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SfypuBuFqBrJN/RG4a0oTJgQCsI2EHmEmRAR6WvMt9k=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=FbZ6iF6aOHwYeu+sKTRwKdtAnG1dERUMJgY2CeRjWrasE4kS0hMzSZfWYWimL/NMDT REb6y4LYfQ7DQkhFyCCy+TLA14JJXS3gpaQHrVgr2ZGX7ItmI/7Siowx/rVPAOAZ3yYE vn//+HYVSBbNJy0+wCrC2em/x7h+6fpAvciqCzeeUETOTUr81UrmiSMuLl3SubU0j+YY SL7tfOEd6Q8XJ8daMIUcayaCAZoUYdw3z5413iEoagMm0ON0sAaL3oEaCZfOsXZ5eDh5 +ulOW0rbN9tAmFOaT3vroCpJ7KeeV2+w+hSgsR722DhMLjpVdnZFdOQrOdAVv8YLBzV4 A9PA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="vxLHTfg/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39d75335591sm1134461f8f.1.2025.04.05.09.13.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:13:31 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v4 02/16] target/i386: Remove AccelCPUClass::cpu_class_init need Date: Sat, 5 Apr 2025 18:13:06 +0200 Message-ID: <20250405161320.76854-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Expose x86_tcg_ops symbol, then directly set it as CPUClass::tcg_ops in TYPE_X86_CPU's class_init(), using CONFIG_TCG #ifdef'ry. No need for the AccelCPUClass::cpu_class_init() handler anymore. Signed-off-by: Philippe Mathieu-Daudé --- target/i386/tcg/tcg-cpu.h | 4 ++++ target/i386/cpu.c | 4 ++++ target/i386/tcg/tcg-cpu.c | 14 +------------- 3 files changed, 9 insertions(+), 13 deletions(-) diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h index 7580f8afb4f..85bcd61678f 100644 --- a/target/i386/tcg/tcg-cpu.h +++ b/target/i386/tcg/tcg-cpu.h @@ -19,6 +19,8 @@ #ifndef TCG_CPU_H #define TCG_CPU_H +#include "cpu.h" + #define XSAVE_FCW_FSW_OFFSET 0x000 #define XSAVE_FTW_FOP_OFFSET 0x004 #define XSAVE_CWD_RIP_OFFSET 0x008 @@ -76,6 +78,8 @@ QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != XSAVE_ZMM_HI256_OFF QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != XSAVE_HI16_ZMM_OFFSET); QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != XSAVE_PKRU_OFFSET); +extern const TCGCPUOps x86_tcg_ops; + bool tcg_cpu_realizefn(CPUState *cs, Error **errp); int x86_mmu_index_pl(CPUX86State *env, unsigned pl); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d930ebd262e..31487f4b282 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -43,6 +43,7 @@ #include "hw/boards.h" #include "hw/i386/sgx-epc.h" #endif +#include "tcg/tcg-cpu.h" #include "disas/capstone.h" #include "cpu-internal.h" @@ -8903,6 +8904,9 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) #ifndef CONFIG_USER_ONLY cc->sysemu_ops = &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ +#ifdef CONFIG_TCG + cc->tcg_ops = &x86_tcg_ops; +#endif /* CONFIG_TCG */ cc->gdb_arch_name = x86_gdb_arch_name; #ifdef TARGET_X86_64 diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 35b17f2b183..27c163d17e2 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -124,7 +124,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "accel/tcg/cpu-ops.h" -static const TCGCPUOps x86_tcg_ops = { +const TCGCPUOps x86_tcg_ops = { .initialize = tcg_x86_init, .translate_code = x86_translate_code, .synchronize_from_tb = x86_cpu_synchronize_from_tb, @@ -148,17 +148,6 @@ static const TCGCPUOps x86_tcg_ops = { #endif /* !CONFIG_USER_ONLY */ }; -static void x86_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) -{ - /* for x86, all cpus use the same set of operations */ - cc->tcg_ops = &x86_tcg_ops; -} - -static void x86_tcg_cpu_class_init(CPUClass *cc) -{ - cc->init_accel_cpu = x86_tcg_cpu_init_ops; -} - static void x86_tcg_cpu_xsave_init(void) { #define XO(bit, field) \ @@ -207,7 +196,6 @@ static void x86_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) acc->cpu_target_realize = tcg_cpu_realizefn; #endif /* CONFIG_USER_ONLY */ - acc->cpu_class_init = x86_tcg_cpu_class_init; acc->cpu_instance_init = x86_tcg_cpu_instance_init; } static const TypeInfo x86_tcg_cpu_accel_type_info = { From patchwork Sat Apr 5 16:13:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 878421 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp4289042wrs; Sat, 5 Apr 2025 09:15:34 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVRinPkY38Yd+IHJ1BO6B4ymsTIEOhwSfTok9wyo1+uroTPhx4qHamD0YmuVWoKwNkNZDBrFw==@linaro.org X-Google-Smtp-Source: AGHT+IG5LDFjgf8v1atgFfwTOKI+if7zP/PpYkI9oy9h3Dk1iLGy1dOQ0BzHbvAsp2Y74J+dESYL X-Received: by 2002:a05:620a:404d:b0:7c5:4be5:b0b1 with SMTP id af79cd13be357-7c775abf4demr834073785a.35.1743869734262; Sat, 05 Apr 2025 09:15:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743869734; cv=none; d=google.com; s=arc-20240605; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec1794e94sm81620965e9.31.2025.04.05.09.13.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:13:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v4 03/16] accel: Remove AccelCPUClass::cpu_class_init() callback Date: Sat, 5 Apr 2025 18:13:07 +0200 Message-ID: <20250405161320.76854-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org No more target defines the AccelCPUClass::cpu_class_init() callback anymore, remove it. Signed-off-by: Philippe Mathieu-Daudé --- include/accel/accel-cpu-target.h | 1 - accel/accel-target.c | 3 --- 2 files changed, 4 deletions(-) diff --git a/include/accel/accel-cpu-target.h b/include/accel/accel-cpu-target.h index 37dde7fae3e..e983fa1dac3 100644 --- a/include/accel/accel-cpu-target.h +++ b/include/accel/accel-cpu-target.h @@ -33,7 +33,6 @@ typedef struct AccelCPUClass { ObjectClass parent_class; /*< public >*/ - void (*cpu_class_init)(CPUClass *cc); void (*cpu_instance_init)(CPUState *cpu); bool (*cpu_target_realize)(CPUState *cpu, Error **errp); } AccelCPUClass; diff --git a/accel/accel-target.c b/accel/accel-target.c index 33a539b4cbb..a45a7317758 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -74,9 +74,6 @@ static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque) * TCGCPUOps depending on the CPU type. */ cc->accel_cpu = accel_cpu; - if (accel_cpu->cpu_class_init) { - accel_cpu->cpu_class_init(cc); - } if (cc->init_accel_cpu) { cc->init_accel_cpu(accel_cpu, cc); } From patchwork Sat Apr 5 16:13:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 878428 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp4289613wrs; Sat, 5 Apr 2025 09:16:55 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVBGqiaBcRTP2EW4t028jHRlVu21+70J8oKrnkFnKIkrKAbLZg3u7+r+NukLgrOpGeePpgL0Q==@linaro.org X-Google-Smtp-Source: AGHT+IE0cOLzFup1onPlhN47XuP8KwXZTUoTqqs7Gy3PWjRNi9uctv8l+/bdQr6RjNTqnuih3kVz X-Received: by 2002:ac8:5d0e:0:b0:478:f736:f545 with SMTP id d75a77b69052e-479310e380dmr43883301cf.51.1743869815146; Sat, 05 Apr 2025 09:16:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743869815; cv=none; d=google.com; s=arc-20240605; b=bK34kZ/pQyN3YpfEeJsKLeEXTfBFb528lGtq72/kt+9aCp6NXEUVrAAvS4S1xSOjYk pkVYCdFYGwGwVfzNN0V89eqVm4cfCJSzMuh2g6AagZFC8WkyJiwZu9CfP7oalcwknj6v SmEQK5uiDllAJZZRpYfGcbFAlyZUAqkCIiYsGOOfhdOgVGcPYNeZmdok0jMEZf0YWO2z uneVBklSVIODRZ/LEdcr1UC7H66zCBbte6X7m1eFx5hQf7YI3bNspB5qxsDhIGGLKZHj 3ORluBUh62+Gy8K5xruj9SYdU3AqjEAulE2S2e62Ap/5u3GnuvYlgGRIRHmEazgwS5uL sewg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=U3DRTmhLmbjPLSrOpbcOACaj65qViLoVjxZHvJ/pQ1o=; fh=GWiEQuVbyl+3s5YahDKEhuRdrEmSORXTAolRbYVHkiY=; b=jdjSmfPQPl3nSPW7NQUBIcrGguTRAZMqNlTGUTKK8+yOD6zIQ+aDkh6FYuGjpgGurC bEfaej0zG6EFuYy+vq2U8x0kW3XnctuU3gcChwTidmeyWWVEpAxeGE4YqPk4MjOSmmHT B/qdZJTv0tBmv3ulgyvWN8Z7+jsVtuq1OFILLbQiXfV+ol0tAyoN0B20sgZHy2oJ6J6c 71LyaYebOVEWNuFXDmklr5YdWosu57ZrEPGlRgZ7HI2IajwWBSn3uZyyx+qdwP/r6I+H O00TqA8kS2P921vcuA7+Zgmds5Vu4h13hR9STw4p2llNEH7mzLgO1UVSTUbL6ppNYo4F MDyw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZYgR3Dsc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c3009644dsm7164710f8f.6.2025.04.05.09.13.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:13:40 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Brian Cain , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.1 v4 04/16] target/hexagon: Add memory order definition Date: Sat, 5 Apr 2025 18:13:08 +0200 Message-ID: <20250405161320.76854-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Brian Cain Signed-off-by: Brian Cain Message-ID: <20250404025203.335025-7-brian.cain@oss.qualcomm.com> Signed-off-by: Philippe Mathieu-Daudé --- target/hexagon/cpu-param.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 635d509e743..22bffa78816 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -25,4 +25,9 @@ #define TARGET_INSN_START_EXTRA_WORDS 0 +/* + * Hexagon processors have a strong memory model. + */ +#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL) + #endif From patchwork Sat Apr 5 16:13:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 878415 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp4288620wrs; Sat, 5 Apr 2025 09:14:26 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWeI5gOXHlSM8IR5BtQLKzgxtPm4sBZ5BJ+uuRl6crkA9/jTaC/XbIlS5lC2SeYVV+cdo9MBQ==@linaro.org X-Google-Smtp-Source: AGHT+IF+squcxilvu9CVC9pWMGs9UgWBHjaf9EqQz3nM3J7YzxgXQhBm3DOmJe7iJGQjvtQlx5F/ X-Received: by 2002:a05:6214:2a8c:b0:6ea:d033:2853 with SMTP id 6a1803df08f44-6f0584ea122mr105613666d6.16.1743869666263; Sat, 05 Apr 2025 09:14:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743869666; cv=none; d=google.com; s=arc-20240605; b=jNkOWB+7CR5x8lzG2yd/v/QSU6IAgyO9GNwaIozvtUCEagYUTa3d1sP8jGol/ZZEjL BY724zk354thVzXFTPSHmwbOn4E8pXre/lrhG5FsnFni5E+twlRY7CIJUqEx9M11gb/q rgMxVXK+9asMPjS/kFn8JTgJpuej1NIH8aJoPM9lAvYibNV940UOSiTHXiZxUUhBSbXT xQsQwVw5wSYZGdVLOcGBymau7dJW+ffb3d8cV4MA/rIwIr+Lpf1OJ1wgavdwLE8b2KFx mF68ZG3Z910gUAA7g0STDpN8B7c1AOlFVqNmIgveahXJHqfjF0eOAWK07NNCuykn6oNB iXDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=22lxwaDoEwngFmE/+xTqkjd0CAM2fFfU6hC2em0g/bA=; fh=ylnw7U4KxGWi5H7QdoxjmFHf/0LKSGXnbXb+iD8gkqQ=; b=VajgmqAMUVTSPaHeG++DIbSGDR4wkNvVXyenWdEwHPwxCgPWipdP8BtOZaN3vtIYeZ hnCCNBISprQBSNJbgX6LIpUtT68mY42GVnZtIJbwDslLPwMfpDLZ2zwa9jc3YHwhxX4b Gg345uRFW/vNn+6ltw7hd1USTzDyPu3XcUQL3KMCkvL/Ba+fNw5xqLDINorSw/Qv2loT Wu5o0aEFaOMN7xQ1TZ4+I9OSrOozJQzT0cMACxfQ/zej1PO/9qk7oQB32JJuJRnfQSKZ RmS9OWBtP4hBx+akuY8wgCiRzCK8s/Xx+IPMRmNFOoKgAWegHR7/Zut/DHvdhg1e2iws NUwQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nOmVKJ4z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec364ec90sm76948075e9.27.2025.04.05.09.13.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:13:44 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Anton Johansson , Pierrick Bouvier Subject: [PATCH-for-10.1 v4 05/16] tcg: Always define TCG_GUEST_DEFAULT_MO Date: Sat, 5 Apr 2025 18:13:09 +0200 Message-ID: <20250405161320.76854-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled frontends, otherwise we use a default value of TCG_MO_ALL. In order to simplify, require the definition for all targets, defining it for hexagon, m68k, rx, sh4 and tricore. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/m68k/cpu-param.h | 3 +++ target/rx/cpu-param.h | 3 +++ target/sh4/cpu-param.h | 3 +++ target/tricore/cpu-param.h | 3 +++ accel/tcg/translate-all.c | 4 ---- 5 files changed, 12 insertions(+), 4 deletions(-) diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 256a2b5f8b2..10a8d74bfa9 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -19,4 +19,7 @@ #define TARGET_INSN_START_EXTRA_WORDS 1 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index 84934f3bcaf..fe39a77ca38 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -26,4 +26,7 @@ #define TARGET_INSN_START_EXTRA_WORDS 0 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index f328715ee86..acdf2397495 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -18,4 +18,7 @@ #define TARGET_INSN_START_EXTRA_WORDS 1 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index eb33a67c419..45fde756b6a 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -14,4 +14,7 @@ #define TARGET_INSN_START_EXTRA_WORDS 0 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c5590eb6955..7467255f6e4 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -353,11 +353,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS; #endif tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS; -#ifdef TCG_GUEST_DEFAULT_MO tcg_ctx->guest_mo = TCG_GUEST_DEFAULT_MO; -#else - tcg_ctx->guest_mo = TCG_MO_ALL; -#endif restart_translate: trace_translate_block(tb, pc, tb->tc.ptr); From patchwork Sat Apr 5 16:13:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 878417 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp4288748wrs; Sat, 5 Apr 2025 09:14:48 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW1hlBcYRfxAsToY8ewGDna3eXct6FRT+wRqtflIB06oRQYSvflzNoAZS+Hz7In2Vce5NjJyA==@linaro.org X-Google-Smtp-Source: AGHT+IGLRF1T3fZYEsJkNoFnm5EFD+81KBfcEga+H5Kie85bBQQ+OfrUABaCzwWsGQxn0ZWGTqdU X-Received: by 2002:a05:6214:768:b0:6e1:715f:cdf5 with SMTP id 6a1803df08f44-6eff55c6312mr94584426d6.15.1743869688660; Sat, 05 Apr 2025 09:14:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743869688; cv=none; d=google.com; s=arc-20240605; b=ZS0oYn4qq+27jLDfUFy8dMxPwAeJnTH4+p8XflqBzA/f8r8vi/uwHWLkFMZvtyBVMT 1mM3J2wzRtqmqdRVV5tp/Et1LLWKk8r8Y7YIbAcE/xVRGDxO8EFBO4bV9hpq0AtqQLPJ 0b8XrLCn+JTPC70KE8JjASJHNOVeNrPWFeRw+7SDo2hLqsJ5xMHEZjLTOg9+rH8HmiC5 UeZqDe9/saqq/46Z5bzOFxhyWOuXlkp0haru85hJy32LkO6F2ZToXYX2q1II1gEN6VTU u08DSkA3NT5fiG5ggDonYkAfICjAArC5LyltxmLv3yHvKgkbJutOGqxLEGNPZrxrb+8c gfiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=VUBhKNJ33VGc0tAXVv72Kq3hUC0BPxTHmotqIBCHglo=; fh=ylnw7U4KxGWi5H7QdoxjmFHf/0LKSGXnbXb+iD8gkqQ=; b=ambnGI8Mr0F2iJnFkUNh9YImolIA9hFSdwVUdaynlklkzZj05DD0fEAZyuzbGmn7Wk FxxdMGRwBI5CxmoFAIUHMmM9aPonAVt/UCyf9CAY2RFsceCsNrRPVaW9Xu6xgl5r1Dj5 OjcNjmF0tLOIpBtlUC5wLbSB1QKK8AWIlPLPX+lE/POQxeWQA87Vs9IMtesoRc5M8ROJ DHY6l1fD4VMUAtScD8wqxtAD12+PrQE8WTnlDDMKKwzOBdmKt4p4YSFRSFfg/0fG8go2 MvRbX0V+QsYnBHEKmf7EEmP2Cn23k+a2uA8GR7lW65od0wuWkL1emuSeLm+BMHay1SKy X29Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DantRVHw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301a67b7sm7124528f8f.25.2025.04.05.09.13.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:13:49 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Anton Johansson , Pierrick Bouvier Subject: [PATCH-for-10.1 v4 06/16] tcg: Simplify tcg_req_mo() macro Date: Sat, 5 Apr 2025 18:13:10 +0200 Message-ID: <20250405161320.76854-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that TCG_GUEST_DEFAULT_MO is always defined, simplify the tcg_req_mo() macro. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/internal-target.h | 9 +-------- accel/tcg/tcg-all.c | 3 --- 2 files changed, 1 insertion(+), 11 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 05abaeb8e0e..1a46a7c87dc 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -52,17 +52,10 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); * memory ordering vs the host memory ordering. A non-zero * result indicates that some barrier is required. * - * If TCG_GUEST_DEFAULT_MO is not defined, assume that the - * guest requires strict ordering. - * * This is a macro so that it's constant even without optimization. */ -#ifdef TCG_GUEST_DEFAULT_MO -# define tcg_req_mo(type) \ +#define tcg_req_mo(type) \ ((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) -#else -# define tcg_req_mo(type) ((type) & ~TCG_TARGET_DEFAULT_MO) -#endif /** * cpu_req_mo: diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 7a5b810b88c..a5a1fd6a11e 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -77,9 +77,6 @@ static bool default_mttcg_enabled(void) return false; } #ifdef TARGET_SUPPORTS_MTTCG -# ifndef TCG_GUEST_DEFAULT_MO -# error "TARGET_SUPPORTS_MTTCG without TCG_GUEST_DEFAULT_MO" -# endif return true; #else return false; From patchwork Sat Apr 5 16:13:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 878420 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp4288927wrs; Sat, 5 Apr 2025 09:15:15 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWF/QvnFfRgeLXcnTkG5nV9x8MgvArSFioc2uXm+LzISgUZ+gq/vj5oVziFouVo8tOvE4Olfw==@linaro.org X-Google-Smtp-Source: AGHT+IGjQpQHG9enw3bFma1W8cQiI8igfG3iqvc5dhXkS16n/sNoJAlOmat3MhHYGVQmkeNIwaRp X-Received: by 2002:a05:6214:2401:b0:6e6:6964:ca77 with SMTP id 6a1803df08f44-6f064aef844mr107368766d6.28.1743869715722; Sat, 05 Apr 2025 09:15:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743869715; cv=none; d=google.com; s=arc-20240605; b=Bug+JcFM3tSF4Ie54KdlPzQbpTh3YmYuWTSPW564zaZSf3WtlhqEOQOL+Qc0Ezk2Xo fM3gnPaIOuLVA3zj1SKcX7cL0WIxHYslvjpxccPksoY/UItW/oEWtQu9eAAYP4RTgZt9 KdW4h2ebiWdAsA5ki8ker3rze8nhUBZzzZI809S4sVtZRMBIQw3HNT/Tuv9hqBjSeCZ2 NQl7W1IPr4Ov0M4ljlqw+JAquZU142mOlf+CT7mq6aWIqwQ83i5eob0uIDuBIuXCGScf qQGze9WsQu2/0kP4Xfo8wX32jfE1Ll152SD9/3UCDGqWRTqTicU85p6DAZuMy3w3VtmW qSAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=l6oG33dd0c008198OrmG4EKmpqvfjOdVYAYzlzpnP7o=; fh=ylnw7U4KxGWi5H7QdoxjmFHf/0LKSGXnbXb+iD8gkqQ=; b=U40GepP7c+F1OJvOlkhTyWLJ83YGLsZ/UR1mJoEKy7Ddd7vEOzB/ygPpOhgvN5PB6q iQ0wiVn/mA/s0khruLLcqSwcZtTT3NKdowkwcu8FEdOU8Ex8UU/DAC9aEiT1irF4jZVK tJDuKupDfjbcH+VMaKbquw1I6ONryrXSUVeCTwOh/+qE9C14uB1rjBwzECv2cbw6+aIq Z5BVzKiHVSNM1GaJi4qct8YNNRqhWRNcC3pvxbvvS5KNoPRwsRUGy5OoCSk8WmLKVm1R wofbkuZKK3QcLZx3ZlW56Fk3Dqt3fJA8fa0qWva0lz6tBovCXP8IUhZIPCCpK5E+C52H 0iiw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A7NKQvz+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec342827fsm78018465e9.6.2025.04.05.09.13.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:13:54 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Anton Johansson , Pierrick Bouvier Subject: [PATCH-for-10.1 v4 07/16] tcg: Define guest_default_memory_order in TCGCPUOps Date: Sat, 5 Apr 2025 18:13:11 +0200 Message-ID: <20250405161320.76854-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add the TCGCPUOps::guest_default_memory_order field and have each target initialize it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/accel/tcg/cpu-ops.h | 8 ++++++++ target/alpha/cpu.c | 2 ++ target/arm/cpu.c | 2 ++ target/arm/tcg/cpu-v7m.c | 2 ++ target/avr/cpu.c | 1 + target/hexagon/cpu.c | 1 + target/hppa/cpu.c | 2 ++ target/i386/tcg/tcg-cpu.c | 2 ++ target/loongarch/cpu.c | 2 ++ target/m68k/cpu.c | 2 ++ target/microblaze/cpu.c | 2 ++ target/mips/cpu.c | 2 ++ target/openrisc/cpu.c | 2 ++ target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 2 ++ target/rx/cpu.c | 2 ++ target/s390x/cpu.c | 2 ++ target/sh4/cpu.c | 2 ++ target/sparc/cpu.c | 2 ++ target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 2 ++ 21 files changed, 44 insertions(+) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 106a0688da8..a4932fc5d7c 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -16,8 +16,16 @@ #include "exec/memop.h" #include "exec/mmu-access-type.h" #include "exec/vaddr.h" +#include "tcg/tcg-mo.h" struct TCGCPUOps { + + /** + * @guest_default_memory_order: default barrier that is required + * for the guest memory ordering. + */ + TCGBar guest_default_memory_order; + /** * @initialize: Initialize TCG state * diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 99d839a2792..6f931117a25 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -235,6 +235,8 @@ static const struct SysemuCPUOps alpha_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps alpha_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = alpha_translate_init, .translate_code = alpha_translate_code, .synchronize_from_tb = alpha_cpu_synchronize_from_tb, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c9e043bc9b5..3f20e258fd0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2671,6 +2671,8 @@ static const struct SysemuCPUOps arm_sysemu_ops = { #ifdef CONFIG_TCG static const TCGCPUOps arm_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = arm_translate_init, .translate_code = arm_translate_code, .synchronize_from_tb = arm_cpu_synchronize_from_tb, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 1a913faa50f..4553fe9de07 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -232,6 +232,8 @@ static void cortex_m55_initfn(Object *obj) } static const TCGCPUOps arm_v7m_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = arm_translate_init, .translate_code = arm_translate_code, .synchronize_from_tb = arm_cpu_synchronize_from_tb, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index feb73e722b3..67918684faf 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -224,6 +224,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps avr_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, .initialize = avr_cpu_tcg_init, .translate_code = avr_cpu_translate_code, .synchronize_from_tb = avr_cpu_synchronize_from_tb, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index ad1f303fbcf..b12e0dccd09 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -325,6 +325,7 @@ static void hexagon_cpu_init(Object *obj) #include "accel/tcg/cpu-ops.h" static const TCGCPUOps hexagon_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, .initialize = hexagon_translate_init, .translate_code = hexagon_translate_code, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 51bff0c5d62..ac4560febea 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -253,6 +253,8 @@ static const struct SysemuCPUOps hppa_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps hppa_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = hppa_translate_init, .translate_code = hppa_translate_code, .synchronize_from_tb = hppa_cpu_synchronize_from_tb, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 27c163d17e2..e58084b12f6 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -125,6 +125,8 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "accel/tcg/cpu-ops.h" const TCGCPUOps x86_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = tcg_x86_init, .translate_code = x86_translate_code, .synchronize_from_tb = x86_cpu_synchronize_from_tb, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 4cc8e02f70b..ee74509a664 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -864,6 +864,8 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) #include "accel/tcg/cpu-ops.h" static const TCGCPUOps loongarch_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = loongarch_translate_init, .translate_code = loongarch_translate_code, .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 4409d8941ce..bfde9b85948 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -589,6 +589,8 @@ static const struct SysemuCPUOps m68k_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps m68k_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = m68k_tcg_init, .translate_code = m68k_translate_code, .restore_state_to_opc = m68k_restore_state_to_opc, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index d10ae0702ad..e46863574c6 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -427,6 +427,8 @@ static const struct SysemuCPUOps mb_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps mb_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = mb_tcg_init, .translate_code = mb_translate_code, .synchronize_from_tb = mb_cpu_synchronize_from_tb, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 269d3d69bd5..860ec398229 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -550,6 +550,8 @@ static const Property mips_cpu_properties[] = { #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" static const TCGCPUOps mips_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = mips_tcg_init, .translate_code = mips_translate_code, .synchronize_from_tb = mips_cpu_synchronize_from_tb, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index dc55594a7de..e62c698a407 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -243,6 +243,8 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps openrisc_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = openrisc_translate_init, .translate_code = openrisc_translate_code, .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 740d8b92c0b..57565c9a2f2 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7478,6 +7478,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps ppc_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, .initialize = ppc_translate_init, .translate_code = ppc_translate_code, .restore_state_to_opc = ppc_restore_state_to_opc, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 6a87367f239..832a5172ee9 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -140,6 +140,8 @@ static void riscv_restore_state_to_opc(CPUState *cs, } const TCGCPUOps riscv_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = riscv_translate_init, .translate_code = riscv_translate_code, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index e14d9cbef93..d7eac551fd4 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -204,6 +204,8 @@ static const struct SysemuCPUOps rx_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps rx_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = rx_translate_init, .translate_code = rx_translate_code, .synchronize_from_tb = rx_cpu_synchronize_from_tb, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d15b1943e0e..f232d82fa34 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -345,6 +345,8 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, } static const TCGCPUOps s390_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = s390x_translate_init, .translate_code = s390x_translate_code, .restore_state_to_opc = s390x_restore_state_to_opc, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index df093988cb1..29f4be7ba9c 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -262,6 +262,8 @@ static const struct SysemuCPUOps sh4_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps superh_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = sh4_translate_init, .translate_code = sh4_translate_code, .synchronize_from_tb = superh_cpu_synchronize_from_tb, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index af3cec43e78..ef04efcb183 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1001,6 +1001,8 @@ static const struct SysemuCPUOps sparc_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps sparc_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = sparc_tcg_init, .translate_code = sparc_translate_code, .synchronize_from_tb = sparc_cpu_synchronize_from_tb, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 833a93d37af..3bf399335ac 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -172,6 +172,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps tricore_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, .initialize = tricore_tcg_init, .translate_code = tricore_translate_code, .synchronize_from_tb = tricore_cpu_synchronize_from_tb, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 51f9ee9e89a..23471064957 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -232,6 +232,8 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps xtensa_tcg_ops = { + .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .initialize = xtensa_translate_init, .translate_code = xtensa_translate_code, .debug_excp_handler = xtensa_breakpoint_handler, From patchwork Sat Apr 5 16:13:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 878414 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec1692ba4sm79368045e9.16.2025.04.05.09.13.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:13:58 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v4 08/16] tcg: Remove use of TCG_GUEST_DEFAULT_MO in tb_gen_code() Date: Sat, 5 Apr 2025 18:13:12 +0200 Message-ID: <20250405161320.76854-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use TCGCPUOps::guest_default_memory_order to set TCGContext::guest_mo. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/translate-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 7467255f6e4..c007b9a1902 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -353,7 +353,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS; #endif tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS; - tcg_ctx->guest_mo = TCG_GUEST_DEFAULT_MO; + tcg_ctx->guest_mo = cpu->cc->tcg_ops->guest_default_memory_order; restart_translate: trace_translate_block(tb, pc, tb->tc.ptr); From patchwork Sat Apr 5 16:13:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 878419 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp4288813wrs; Sat, 5 Apr 2025 09:14:58 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUID/98v7xCrhhrQ+d9uEyvfzCzyusexmnOgfCuLYVpKYfieFapOgZgVPq+OvsukqXgvGb7wg==@linaro.org X-Google-Smtp-Source: AGHT+IG1GN3HimRmyrK7nuQkVWgi6cKI4xfsmEt05pS2URTJyY5Vic7eNBg9rpg7mtWE7+G+C1/h X-Received: by 2002:ac8:5716:0:b0:476:8612:f01d with SMTP id d75a77b69052e-47931113e22mr44728001cf.48.1743869698629; Sat, 05 Apr 2025 09:14:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743869698; cv=none; d=google.com; s=arc-20240605; b=VzR4XSkXPUchV78Ufzu4zTvi1/BHtWV4n/jSTYTy86ZRD9i+tX6a69r3RM2pofm5Dx YjfH02gX5K0Bpn1WFcxddlJTmqBfgrjyvhcBOFDNgOFrrGK6eLaulkKWMENnz+DN1Uve D9Uv6JlBH3V4NpxXEoLyyzA1uD6OWJufzhLMS2bhf0gRDwqkwprodnaura4LXJ//OMZ9 yLux0MKjFkf2Azq2+aIlnzvV+iiUYwBxKVctPQU2jwy1m6h2TbQEQ7Hwso/3XVPQ6na8 Ngqccjf1pUcZSeVM5jRxD0/4EUSA2t4Es/Kpl1tHRGBwOLuNBGh8Ayd0FlznsEy4bWl6 UC6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rcpj2tcbvjBZshPtyS3/CSwa5AEapPfd25KE2HwFvNA=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=iLAzcVGq27zw28H4tyOpZmJuDFQEbWUfycYicUt+pDRsmKMUO1G5BdOCCZrDYER3z1 EPMK7/Ppv6uzETw0/R05uzJ1v+IztjD+GlHFYpT6L2XpWYiiimgYz3EpLtyCSw6MwoY+ yN8CZxRycADIEuuQOaMVeSnwaKghshkQN4J64cjj5cjcFsKus+Nga3sOUwU2o74nXYod aiB13JACsCYO9+I70db1CdC2xa/TOWln1s/xp/jHRjpZYgdIibnFKCKCLCHKuleN81rD GpYmEploILHqN06Eatqe0ypTbGr64oIVhNvgDcBuTGb4BuSOY0Ud/UJvK3A6sS4S1P/0 MiCw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BK4NVrKO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ea97904b7sm92433845e9.1.2025.04.05.09.14.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:14:03 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v4 09/16] tcg: Propagate CPUState argument to cpu_req_mo() Date: Sat, 5 Apr 2025 18:13:13 +0200 Message-ID: <20250405161320.76854-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In preparation of having tcg_req_mo() access CPUState in the next commit, pass it to cpu_req_mo(), its single caller. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/internal-target.h | 3 ++- accel/tcg/cputlb.c | 20 ++++++++++---------- accel/tcg/user-exec.c | 20 ++++++++++---------- 3 files changed, 22 insertions(+), 21 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 1a46a7c87dc..23aac39b572 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -59,12 +59,13 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); /** * cpu_req_mo: + * @cpu: CPUState * @type: TCGBar * * If tcg_req_mo indicates a barrier for @type is required * for the guest memory model, issue a host memory barrier. */ -#define cpu_req_mo(type) \ +#define cpu_req_mo(cpu, type) \ do { \ if (tcg_req_mo(type)) { \ smp_mb(); \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 2cafd38d2af..35b1ff03a51 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2324,7 +2324,7 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, MMULookupLocals l; bool crosspage; - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage = mmu_lookup(cpu, addr, oi, ra, access_type, &l); tcg_debug_assert(!crosspage); @@ -2339,7 +2339,7 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uint16_t ret; uint8_t a, b; - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage = mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_2(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, ra); @@ -2363,7 +2363,7 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, bool crosspage; uint32_t ret; - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage = mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_4(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, ra); @@ -2384,7 +2384,7 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, bool crosspage; uint64_t ret; - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage = mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_8(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, ra); @@ -2407,7 +2407,7 @@ static Int128 do_ld16_mmu(CPUState *cpu, vaddr addr, Int128 ret; int first; - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_LOAD, &l); if (likely(!crosspage)) { if (unlikely(l.page[0].flags & TLB_MMIO)) { @@ -2735,7 +2735,7 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, uint8_t val, MMULookupLocals l; bool crosspage; - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); tcg_debug_assert(!crosspage); @@ -2749,7 +2749,7 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr, uint16_t val, bool crosspage; uint8_t a, b; - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_2(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2771,7 +2771,7 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr, uint32_t val, MMULookupLocals l; bool crosspage; - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_4(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2792,7 +2792,7 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr, uint64_t val, MMULookupLocals l; bool crosspage; - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_8(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2815,7 +2815,7 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, Int128 val, uint64_t a, b; int first; - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { if (unlikely(l.page[0].flags & TLB_MMIO)) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 1b878ead7a7..3f4d6824460 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1061,7 +1061,7 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, void *haddr; uint8_t ret; - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr = cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, access_type); ret = ldub_p(haddr); clear_helper_retaddr(); @@ -1075,7 +1075,7 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uint16_t ret; MemOp mop = get_memop(oi); - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr = cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret = load_atom_2(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1093,7 +1093,7 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uint32_t ret; MemOp mop = get_memop(oi); - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr = cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret = load_atom_4(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1111,7 +1111,7 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uint64_t ret; MemOp mop = get_memop(oi); - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr = cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret = load_atom_8(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1130,7 +1130,7 @@ static Int128 do_ld16_mmu(CPUState *cpu, abi_ptr addr, MemOp mop = get_memop(oi); tcg_debug_assert((mop & MO_SIZE) == MO_128); - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr = cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_LOAD); ret = load_atom_16(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1146,7 +1146,7 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, uint8_t val, { void *haddr; - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr = cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, MMU_DATA_STORE); stb_p(haddr, val); clear_helper_retaddr(); @@ -1158,7 +1158,7 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr, uint16_t val, void *haddr; MemOp mop = get_memop(oi); - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr = cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); if (mop & MO_BSWAP) { @@ -1174,7 +1174,7 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr, uint32_t val, void *haddr; MemOp mop = get_memop(oi); - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr = cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); if (mop & MO_BSWAP) { @@ -1190,7 +1190,7 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr, uint64_t val, void *haddr; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec34be2ffsm76593335e9.22.2025.04.05.09.14.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:14:07 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v4 10/16] tcg: Have tcg_req_mo() use TCGCPUOps::guest_default_memory_order Date: Sat, 5 Apr 2025 18:13:14 +0200 Message-ID: <20250405161320.76854-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In order to use TCG with multiple targets, replace the compile time use of TCG_GUEST_DEFAULT_MO by a runtime access to TCGCPUOps::guest_default_memory_order via CPUState. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/internal-target.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 23aac39b572..f5a3fd7e402 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -46,16 +46,15 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); /** * tcg_req_mo: + * @guest_mo: Guest default memory order * @type: TCGBar * * Filter @type to the barrier that is required for the guest * memory ordering vs the host memory ordering. A non-zero * result indicates that some barrier is required. - * - * This is a macro so that it's constant even without optimization. */ -#define tcg_req_mo(type) \ - ((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) +#define tcg_req_mo(guest_mo, type) \ + ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) /** * cpu_req_mo: @@ -67,7 +66,7 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); */ #define cpu_req_mo(cpu, type) \ do { \ - if (tcg_req_mo(type)) { \ + if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \ smp_mb(); \ } \ } while (0) From patchwork Sat Apr 5 16:13:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 878427 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp4289558wrs; Sat, 5 Apr 2025 09:16:46 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVkNsnj5ynm77SHm+1OVRTxCZh0TQVucHlYT7xb76iHBbxpPKwczcvBvkWB9yJfCH9ozFbA8Q==@linaro.org X-Google-Smtp-Source: AGHT+IE8nMIhsp0FxbtPtiEmMrRakgjrvy/6jla8+OJayG44tdJqKqvjuBFeEQwdelROWbFH3MU6 X-Received: by 2002:a05:620a:1a94:b0:7c5:4b91:6a44 with SMTP id af79cd13be357-7c775a1023dmr763634285a.19.1743869806406; Sat, 05 Apr 2025 09:16:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743869806; cv=none; d=google.com; s=arc-20240605; b=lEFtoA/o3VPUY9ogyxZTcbDL3AOCsaCq1y53eCeZcxzi/Cw8loeGueO2PvmwdmSdpV FKwvZDsn9iLCw5Q68TlVmRV//kEjJ98pxqu8GON26j0Gb35sHicK37Y8p2xm1yHwpJJl YjntEYkaExD9ivN583StjlPZFladXc9GsrfMmRXML36YKAwkxOaAPpy+JcGdoGITSASL xG/14qIdZwBpAQ1Zh68MOUVNC//L5Wkif06DY2dHXcyi2PpX2PaIiqvIN2bp8JDHNmzs BpWW5J20jSxr9QIb3JZPHRvnjzJzEJCIUA8lW8pGsVPNMs0qL5kGTRQm9ZHnSQZt0PzZ SxAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jbeIlrtLd2jXBN6pnVLjy0Ez8TgEHAsNX4HbXOjA0NA=; fh=ylnw7U4KxGWi5H7QdoxjmFHf/0LKSGXnbXb+iD8gkqQ=; b=Azo1kWguQmLJZnBAn6BQx7gGujnzbyKuR8MwtR6ZfUF/qXZHTfYS1U030VaZnFtccD tHt/9lWqdm4++X3i+FZbsQ+itryh6IdkAj5FaVP+WKXUL6qpxaSIQE4QaSN7wf0jIzzO AHEXCvtX1Nd2eHclxEMNRCgsihGvBUMSJv0DdkX2Jgz9OOQ8Q2fWbE7xGNnN/z7WwMQB 1CuwwThdXEViMwLnFWYV3MwqxEVwIhtxWUuWPVBvKxpReIsvbNMSmOmyfcZu7B5omtRt OXr9Y73I/ll8AeV1iiQ9tLND1UkKxLOzS8znnl36GLPoXX/F78B88eBD/plNnX91gMgv /wEQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TStlkklc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c3020d938sm7329692f8f.65.2025.04.05.09.14.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:14:12 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Anton Johansson , Pierrick Bouvier Subject: [PATCH-for-10.1 v4 11/16] tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally Date: Sat, 5 Apr 2025 18:13:15 +0200 Message-ID: <20250405161320.76854-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org By directly using TCGCPUOps::guest_default_memory_order, we don't need the TCG_GUEST_DEFAULT_MO definition anymore. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- docs/devel/multi-thread-tcg.rst | 4 ++-- include/exec/poison.h | 1 - target/alpha/cpu-param.h | 3 --- target/arm/cpu-param.h | 3 --- target/avr/cpu-param.h | 2 -- target/hexagon/cpu-param.h | 5 ----- target/hppa/cpu-param.h | 8 -------- target/i386/cpu-param.h | 3 --- target/loongarch/cpu-param.h | 2 -- target/m68k/cpu-param.h | 3 --- target/microblaze/cpu-param.h | 3 --- target/mips/cpu-param.h | 2 -- target/openrisc/cpu-param.h | 2 -- target/ppc/cpu-param.h | 2 -- target/riscv/cpu-param.h | 2 -- target/rx/cpu-param.h | 3 --- target/s390x/cpu-param.h | 6 ------ target/sh4/cpu-param.h | 3 --- target/sparc/cpu-param.h | 23 ----------------------- target/tricore/cpu-param.h | 3 --- target/xtensa/cpu-param.h | 3 --- target/alpha/cpu.c | 3 ++- target/arm/cpu.c | 3 ++- target/arm/tcg/cpu-v7m.c | 3 ++- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 5 ++++- target/hppa/cpu.c | 8 +++++++- target/i386/tcg/tcg-cpu.c | 5 ++++- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 3 ++- target/microblaze/cpu.c | 3 ++- target/mips/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- target/rx/cpu.c | 3 ++- target/s390x/cpu.c | 6 +++++- target/sh4/cpu.c | 3 ++- target/sparc/cpu.c | 23 ++++++++++++++++++++++- target/tricore/cpu.c | 3 ++- target/xtensa/cpu.c | 3 ++- 41 files changed, 68 insertions(+), 104 deletions(-) diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.rst index b0f473961dd..14a2a9dc7b5 100644 --- a/docs/devel/multi-thread-tcg.rst +++ b/docs/devel/multi-thread-tcg.rst @@ -28,8 +28,8 @@ vCPU Scheduling We introduce a new running mode where each vCPU will run on its own user-space thread. This is enabled by default for all FE/BE combinations where the host memory model is able to accommodate the -guest (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO is zero) and the -guest has had the required work done to support this safely +guest (TCGCPUOps::guest_default_memory_order & ~TCG_TARGET_DEFAULT_MO is zero) +and the guest has had the required work done to support this safely (TARGET_SUPPORTS_MTTCG). System emulation will fall back to the original round robin approach diff --git a/include/exec/poison.h b/include/exec/poison.h index a09e0c12631..0f336cdc618 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -37,7 +37,6 @@ #pragma GCC poison TARGET_NAME #pragma GCC poison TARGET_SUPPORTS_MTTCG #pragma GCC poison TARGET_BIG_ENDIAN -#pragma GCC poison TCG_GUEST_DEFAULT_MO #pragma GCC poison TARGET_HAS_PRECISE_SMC #pragma GCC poison TARGET_LONG_BITS diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index dd44feb1793..a799f42db31 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -26,7 +26,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 0 -/* Alpha processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 2cee4be6938..5c5bc8a009e 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -44,7 +44,4 @@ */ #define TARGET_INSN_START_EXTRA_WORDS 2 -/* ARM processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 9d37848d97d..f74bfc25804 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -27,6 +27,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 0 -#define TCG_GUEST_DEFAULT_MO 0 - #endif diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 22bffa78816..635d509e743 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -25,9 +25,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 0 -/* - * Hexagon processors have a strong memory model. - */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL) - #endif diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index 68ed84e84af..9bf7ac76d0c 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -21,12 +21,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 2 -/* PA-RISC 1.x processors have a strong memory model. */ -/* - * ??? While we do not yet implement PA-RISC 2.0, those processors have - * a weak memory model, but with TLB bits that force ordering on a per-page - * basis. It's probably easier to fall back to a strong memory model. - */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index 0c8efce8619..ebb844bcc83 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -24,7 +24,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 1 -/* The x86 has a strong memory model with some store-after-load re-ordering */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) - #endif diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index dbe414bb35a..58cc45a377e 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -15,6 +15,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 0 -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 10a8d74bfa9..256a2b5f8b2 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -19,7 +19,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 1 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 5d55e0e3c4a..e0a37945136 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -29,7 +29,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 1 -/* MicroBlaze is always in-order. */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 99ca8d1684c..58f450827f7 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -22,6 +22,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 2 -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h index 7ea0ecb55a6..b4f57bbe692 100644 --- a/target/openrisc/cpu-param.h +++ b/target/openrisc/cpu-param.h @@ -14,6 +14,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 1 -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index d0651d2ac89..e4ed9080ee9 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -39,6 +39,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 0 -#define TCG_GUEST_DEFAULT_MO 0 - #endif diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index ff4ba81965a..cfdc67c258c 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -34,6 +34,4 @@ * - M mode HLV/HLVX/HSV 0b111 */ -#define TCG_GUEST_DEFAULT_MO 0 - #endif diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index fe39a77ca38..84934f3bcaf 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -26,7 +26,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 0 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index a8a4377f4ff..abfae3bedfb 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -14,10 +14,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 2 -/* - * The z/Architecture has a strong memory model with some - * store-after-load re-ordering. - */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) - #endif diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index acdf2397495..f328715ee86 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -18,7 +18,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 1 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index 62d47b804bb..45eea9d6bac 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -23,27 +23,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 1 -/* - * From Oracle SPARC Architecture 2015: - * - * Compatibility notes: The PSO memory model described in SPARC V8 and - * SPARC V9 compatibility architecture specifications was never implemented - * in a SPARC V9 implementation and is not included in the Oracle SPARC - * Architecture specification. - * - * The RMO memory model described in the SPARC V9 specification was - * implemented in some non-Sun SPARC V9 implementations, but is not - * directly supported in Oracle SPARC Architecture 2015 implementations. - * - * Therefore always use TSO in QEMU. - * - * D.5 Specification of Partial Store Order (PSO) - * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. - * - * D.6 Specification of Total Store Order (TSO) - * ... PSO with the additional requirement that all [stores] are followed - * by an implied MEMBAR #StoreStore. - */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) - #endif diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index 45fde756b6a..eb33a67c419 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -14,7 +14,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 0 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index e7cb747aaae..7a0c22c9005 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -18,7 +18,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 0 -/* Xtensa processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 6f931117a25..eeaf3a81c1a 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -235,7 +235,8 @@ static const struct SysemuCPUOps alpha_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps alpha_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + /* Alpha processors have a weak memory model */ + .guest_default_memory_order = 0, .initialize = alpha_translate_init, .translate_code = alpha_translate_code, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3f20e258fd0..3e9760b5518 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2671,7 +2671,8 @@ static const struct SysemuCPUOps arm_sysemu_ops = { #ifdef CONFIG_TCG static const TCGCPUOps arm_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + /* ARM processors have a weak memory model */ + .guest_default_memory_order = 0, .initialize = arm_translate_init, .translate_code = arm_translate_code, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 4553fe9de07..89d4e4b4a2f 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -232,7 +232,8 @@ static void cortex_m55_initfn(Object *obj) } static const TCGCPUOps arm_v7m_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + /* ARM processors have a weak memory model */ + .guest_default_memory_order = 0, .initialize = arm_translate_init, .translate_code = arm_translate_code, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 67918684faf..8f79cf4c08b 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -224,7 +224,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps avr_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order = 0, .initialize = avr_cpu_tcg_init, .translate_code = avr_cpu_translate_code, .synchronize_from_tb = avr_cpu_synchronize_from_tb, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index b12e0dccd09..e54f10c2294 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -325,7 +325,10 @@ static void hexagon_cpu_init(Object *obj) #include "accel/tcg/cpu-ops.h" static const TCGCPUOps hexagon_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + /* + * Hexagon processors have a strong memory model. + */ + .guest_default_memory_order = TCG_MO_ALL, .initialize = hexagon_translate_init, .translate_code = hexagon_translate_code, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index ac4560febea..dfbd9330565 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -253,7 +253,13 @@ static const struct SysemuCPUOps hppa_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps hppa_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + /* PA-RISC 1.x processors have a strong memory model. */ + /* + * ??? While we do not yet implement PA-RISC 2.0, those processors have + * a weak memory model, but with TLB bits that force ordering on a per-page + * basis. It's probably easier to fall back to a strong memory model. + */ + .guest_default_memory_order = TCG_MO_ALL, .initialize = hppa_translate_init, .translate_code = hppa_translate_code, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index e58084b12f6..5295fcea5c3 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -125,7 +125,10 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "accel/tcg/cpu-ops.h" const TCGCPUOps x86_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + /* + * The x86 has a strong memory model with some store-after-load re-ordering + */ + .guest_default_memory_order = TCG_MO_ALL & ~TCG_MO_ST_LD, .initialize = tcg_x86_init, .translate_code = x86_translate_code, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ee74509a664..f5b8ef29ab0 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -864,7 +864,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) #include "accel/tcg/cpu-ops.h" static const TCGCPUOps loongarch_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order = 0, .initialize = loongarch_translate_init, .translate_code = loongarch_translate_code, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index bfde9b85948..b2d8c8f1dea 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -589,7 +589,8 @@ static const struct SysemuCPUOps m68k_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps m68k_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order = TCG_MO_ALL, .initialize = m68k_tcg_init, .translate_code = m68k_translate_code, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index e46863574c6..4efba0dddb2 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -427,7 +427,8 @@ static const struct SysemuCPUOps mb_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps mb_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + /* MicroBlaze is always in-order. */ + .guest_default_memory_order = TCG_MO_ALL, .initialize = mb_tcg_init, .translate_code = mb_translate_code, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 860ec398229..010773405a8 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -550,7 +550,7 @@ static const Property mips_cpu_properties[] = { #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" static const TCGCPUOps mips_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order = 0, .initialize = mips_tcg_init, .translate_code = mips_translate_code, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index e62c698a407..87fe779042c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -243,7 +243,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps openrisc_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order = 0, .initialize = openrisc_translate_init, .translate_code = openrisc_translate_code, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 57565c9a2f2..8300fa5777e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7478,7 +7478,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps ppc_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order = 0, .initialize = ppc_translate_init, .translate_code = ppc_translate_code, .restore_state_to_opc = ppc_restore_state_to_opc, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 832a5172ee9..e146c76e6aa 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -140,7 +140,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, } const TCGCPUOps riscv_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order = 0, .initialize = riscv_translate_init, .translate_code = riscv_translate_code, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index d7eac551fd4..f073fe8fc98 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -204,7 +204,8 @@ static const struct SysemuCPUOps rx_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps rx_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order = TCG_MO_ALL, .initialize = rx_translate_init, .translate_code = rx_translate_code, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index f232d82fa34..1e101b5afeb 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -345,7 +345,11 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, } static const TCGCPUOps s390_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + /* + * The z/Architecture has a strong memory model with some + * store-after-load re-ordering. + */ + .guest_default_memory_order = TCG_MO_ALL & ~TCG_MO_ST_LD, .initialize = s390x_translate_init, .translate_code = s390x_translate_code, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 29f4be7ba9c..7a05301c6ff 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -262,7 +262,8 @@ static const struct SysemuCPUOps sh4_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps superh_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order = TCG_MO_ALL, .initialize = sh4_translate_init, .translate_code = sh4_translate_code, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ef04efcb183..56d9417ae3f 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1001,7 +1001,28 @@ static const struct SysemuCPUOps sparc_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps sparc_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + /* + * From Oracle SPARC Architecture 2015: + * + * Compatibility notes: The PSO memory model described in SPARC V8 and + * SPARC V9 compatibility architecture specifications was never + * implemented in a SPARC V9 implementation and is not included in the + * Oracle SPARC Architecture specification. + * + * The RMO memory model described in the SPARC V9 specification was + * implemented in some non-Sun SPARC V9 implementations, but is not + * directly supported in Oracle SPARC Architecture 2015 implementations. + * + * Therefore always use TSO in QEMU. + * + * D.5 Specification of Partial Store Order (PSO) + * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. + * + * D.6 Specification of Total Store Order (TSO) + * ... PSO with the additional requirement that all [stores] are followed + * by an implied MEMBAR #StoreStore. + */ + .guest_default_memory_order = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST, .initialize = sparc_tcg_init, .translate_code = sparc_translate_code, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 3bf399335ac..c68954b4096 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -172,7 +172,8 @@ static const struct SysemuCPUOps tricore_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps tricore_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order = TCG_MO_ALL, .initialize = tricore_tcg_init, .translate_code = tricore_translate_code, .synchronize_from_tb = tricore_cpu_synchronize_from_tb, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 23471064957..2cbf4e30108 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -232,7 +232,8 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps xtensa_tcg_ops = { - .guest_default_memory_order = TCG_GUEST_DEFAULT_MO, + /* Xtensa processors have a weak memory model */ + .guest_default_memory_order = 0, .initialize = xtensa_translate_init, .translate_code = xtensa_translate_code, From patchwork Sat Apr 5 16:13:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 878422 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp4289045wrs; Sat, 5 Apr 2025 09:15:35 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWHbN2V3rbmWGfXcT1uXgTsPqhvT+/JYMRFOXDlbXsSsHbU2biSPr/7oOr1WsEvx5UciCFlAA==@linaro.org X-Google-Smtp-Source: AGHT+IF64I1OpDUBNMq47q9CTJugGd7YJkxip/gX5haB208zjreQiotNKgBS3sr7QssJwJknKtJk X-Received: by 2002:ad4:5c8d:0:b0:6d8:8d16:7cec with SMTP id 6a1803df08f44-6f01e7ce87cmr123897216d6.37.1743869734927; Sat, 05 Apr 2025 09:15:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743869734; cv=none; d=google.com; s=arc-20240605; b=ivqOWo1u1hRRKGCfESOp/0hzz7pT1FFBZhijjpHLwvFsmmwcj+OLvGW8WUFC0fhUoL 3bmXC9rKRRyqEfSl4mpioGqntfN5XgCvP7czHLOxads42z4GojvMHC+5kiqmNBAxBPz+ wZlzVuzssl0SA7UWAzAd5kIBItDrDPMOSuqHhsshLdjTDxO4nts5HVFlwmnlcc5Ib5KQ 8iTXiTMLf2FcgIbjyICGojoryVPfLeGzl+oLb1J3hvMOUeWMbpjpR+NMLSbyig9gDEUX e9afzSigWPUgYYHFbHnKUtZa13XgV4QDx8BLQzzQZ1/Wx3gTnWeJYyeL9g20bddw4Xle QMLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=FyHyqUVPAmJjyMO6Sr/Bf3FWzhnRIjw+jQa7gHGhFEQ=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=BGv2FQ3clCBdbId26UyEnnQZTFtW/CHhBK/hPTsJK4FBbPlwpNTHklpTGB/+jqwEF3 +EG9NOot5yb1+4OQEk/wF26qURDmTDt13iIaB9CCRd/YA46zLXibHiwl80Jr6m15+s2z sKquVHwbva44jtjtHHgDLpAMnHclIMf0IysH3FgWimI5Q+GoSoVLjcfq3CEnxnpJnVl9 sH5gOcpPNV6WH9/WOeJXwpSREcUpFk3asGLSdWbzLkwkq+oOHqkdhs6FwUXS3O0/ntQ+ TzIBWVPuxSrCuQ8dmJgvEx+uE7G95yYd/JP4+EPQpyYKoeppsYk0i72VICP1+aiLQJf7 yGLA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OK49d9lX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec364ec90sm76959905e9.27.2025.04.05.09.14.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:14:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v4 12/16] tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h' Date: Sat, 5 Apr 2025 18:13:16 +0200 Message-ID: <20250405161320.76854-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/backend-ldst.h | 41 +++++++++++++++++++++++++++++++++++++ accel/tcg/internal-target.h | 28 ------------------------- accel/tcg/cputlb.c | 1 + accel/tcg/user-exec.c | 1 + 4 files changed, 43 insertions(+), 28 deletions(-) create mode 100644 accel/tcg/backend-ldst.h diff --git a/accel/tcg/backend-ldst.h b/accel/tcg/backend-ldst.h new file mode 100644 index 00000000000..9c3a407a5af --- /dev/null +++ b/accel/tcg/backend-ldst.h @@ -0,0 +1,41 @@ +/* + * Internal memory barrier helpers for QEMU (target agnostic) + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ACCEL_TCG_BACKEND_LDST_H +#define ACCEL_TCG_BACKEND_LDST_H + +#include "tcg-target-mo.h" + +/** + * tcg_req_mo: + * @guest_mo: Guest default memory order + * @type: TCGBar + * + * Filter @type to the barrier that is required for the guest + * memory ordering vs the host memory ordering. A non-zero + * result indicates that some barrier is required. + */ +#define tcg_req_mo(guest_mo, type) \ + ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) + +/** + * cpu_req_mo: + * @cpu: CPUState + * @type: TCGBar + * + * If tcg_req_mo indicates a barrier for @type is required + * for the guest memory model, issue a host memory barrier. + */ +#define cpu_req_mo(cpu, type) \ + do { \ + if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \ + smp_mb(); \ + } \ + } while (0) + +#endif diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index f5a3fd7e402..9a9cef31406 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -13,7 +13,6 @@ #include "exec/exec-all.h" #include "exec/translation-block.h" #include "tb-internal.h" -#include "tcg-target-mo.h" #include "exec/mmap-lock.h" /* @@ -44,31 +43,4 @@ void page_table_config_init(void); G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); #endif /* CONFIG_USER_ONLY */ -/** - * tcg_req_mo: - * @guest_mo: Guest default memory order - * @type: TCGBar - * - * Filter @type to the barrier that is required for the guest - * memory ordering vs the host memory ordering. A non-zero - * result indicates that some barrier is required. - */ -#define tcg_req_mo(guest_mo, type) \ - ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) - -/** - * cpu_req_mo: - * @cpu: CPUState - * @type: TCGBar - * - * If tcg_req_mo indicates a barrier for @type is required - * for the guest memory model, issue a host memory barrier. - */ -#define cpu_req_mo(cpu, type) \ - do { \ - if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \ - smp_mb(); \ - } \ - } while (0) - #endif /* ACCEL_TCG_INTERNAL_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 35b1ff03a51..d9fb68d7198 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -48,6 +48,7 @@ #include "qemu/plugin-memory.h" #endif #include "tcg/tcg-ldst.h" +#include "backend-ldst.h" /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 3f4d6824460..5eef8e7f186 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -37,6 +37,7 @@ #include "qemu/int128.h" #include "trace.h" #include "tcg/tcg-ldst.h" +#include "backend-ldst.h" #include "internal-common.h" #include "internal-target.h" #include "tb-internal.h" From patchwork Sat Apr 5 16:13:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 878424 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp4289104wrs; Sat, 5 Apr 2025 09:15:42 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVPGeMznhKnJLk527dFARnomyI7pW7xrQI+aSjWr9TSSg3n+Q2JZ7WHI0xIOkkRdVu//EbS5A==@linaro.org X-Google-Smtp-Source: AGHT+IFIPLXZQuS7WVqnCzHHDFaYv3nI2Y/HBZ+BAC1B0dTXjybDTiurO9Yd+ENr45SVqBa33RKq X-Received: by 2002:ac8:574e:0:b0:476:60a1:3115 with SMTP id d75a77b69052e-479249a7bbcmr123647971cf.33.1743869742502; Sat, 05 Apr 2025 09:15:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743869742; cv=none; d=google.com; s=arc-20240605; b=kDdJ4txSGnGeWa/FUshJko79r2CG74pAkZbKaqGJObGLYzZgBpdkSSMxl4b53t1Gq3 dyp1N1LRLo4s1Y87ABVYuNeAvKEhQkpe+YWO6QkJQLXj/YaAV65Nrirthby3KjdGeCWn 0DXGTZAAHtKJv2aOp6y6aN8wxZ9dOY6TdXRC1bDAe7huDG4OtkVaCwXcj5qMiJ7fnJ4o FkFf9laxzjC9TR+TTZsuRI0Euz5ZmJiudvV5KkxBZrWvol5r9dAqOTqpH862il1Fh+Xj hfUdbtPIqdTApUHgkE3OQxKtoHui2J5Dl8fOsn1tUYy8XaUzGmFePIMXLbQk1aoM1jEM eMxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=G/LTVfYsOIJ5re5/xeDsdKiBrQeXn6HocLb4nBW7R3Q=; fh=ewablq11zO+WL7X4n3MMOCnLV8HxPJyS9XF5ZM+AHaM=; b=QvfmvCGV8AaqGYj8L+uPODWrBaoU0f+mGQPg/Rox+f0sxTAxgQeRlySdvCfP5HEAtH fjmg4bs2nKOFU/+Aqz6IJ1izYhbCrZfTaXyGuRc+jhfzHNpOjW/uMA5A6+JyQtPSD1mi OY8DO8JHzRGXxygjPfvSPMOsm5AbgvFd+CniQNUjxxAcyIZZWWVrtUOeLh0VvjOuDKV6 JLSn/SEiMfty12LyCy/bzoYoQd1SpoMqv2hqp0UrtL4W1bRzbyDz6fBVCXps45Xg5gn7 fj/zz61+wSeqIAOW3vhONSnhknxIyUJFYgtW9vsQHVcilnWfqCjyOuxqb6gu2h26ZzDU H8nA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="gqf/1rff"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec17b3572sm80270355e9.39.2025.04.05.09.14.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:14:22 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH-for-10.1 v4 13/16] tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h' Date: Sat, 5 Apr 2025 18:13:17 +0200 Message-ID: <20250405161320.76854-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org qemu_tcg_mttcg_enabled() is specific to 1/ TCG and 2/ system emulation. Move the prototype declaration to "system/tcg.h", reducing 'mttcg_enabled' variable scope. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 9 --------- include/system/tcg.h | 8 ++++++++ accel/tcg/tcg-all.c | 16 ++++++++++++++-- target/riscv/tcg/tcg-cpu.c | 1 + tcg/region.c | 4 +++- 5 files changed, 26 insertions(+), 12 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 10b6b25b344..c8d6abff19a 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -594,15 +594,6 @@ extern CPUTailQ cpus_queue; extern __thread CPUState *current_cpu; -/** - * qemu_tcg_mttcg_enabled: - * Check whether we are running MultiThread TCG or not. - * - * Returns: %true if we are in MTTCG mode %false otherwise. - */ -extern bool mttcg_enabled; -#define qemu_tcg_mttcg_enabled() (mttcg_enabled) - /** * cpu_paging_enabled: * @cpu: The CPU whose state is to be inspected. diff --git a/include/system/tcg.h b/include/system/tcg.h index 73229648c63..7622dcea302 100644 --- a/include/system/tcg.h +++ b/include/system/tcg.h @@ -17,4 +17,12 @@ extern bool tcg_allowed; #define tcg_enabled() 0 #endif +/** + * qemu_tcg_mttcg_enabled: + * Check whether we are running MultiThread TCG or not. + * + * Returns: %true if we are in MTTCG mode %false otherwise. + */ +bool qemu_tcg_mttcg_enabled(void); + #endif diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index a5a1fd6a11e..b8874430d30 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -38,6 +38,7 @@ #include "hw/qdev-core.h" #else #include "hw/boards.h" +#include "system/tcg.h" #endif #include "internal-common.h" #include "cpu-param.h" @@ -58,6 +59,17 @@ typedef struct TCGState TCGState; DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE, TYPE_TCG_ACCEL) +#ifndef CONFIG_USER_ONLY + +static bool mttcg_enabled; + +bool qemu_tcg_mttcg_enabled(void) +{ + return mttcg_enabled; +} + +#endif /* !CONFIG_USER_ONLY */ + /* * We default to false if we know other options have been enabled * which are currently incompatible with MTTCG. Otherwise when each @@ -97,7 +109,6 @@ static void tcg_accel_instance_init(Object *obj) #endif } -bool mttcg_enabled; bool one_insn_per_tb; static int tcg_init_machine(MachineState *ms) @@ -107,10 +118,11 @@ static int tcg_init_machine(MachineState *ms) unsigned max_cpus = 1; #else unsigned max_cpus = ms->smp.max_cpus; + + mttcg_enabled = s->mttcg_enabled; #endif tcg_allowed = true; - mttcg_enabled = s->mttcg_enabled; page_init(); tb_htable_init(); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e146c76e6aa..44fdf6c4cf1 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -36,6 +36,7 @@ #include "tcg/tcg.h" #ifndef CONFIG_USER_ONLY #include "hw/boards.h" +#include "system/tcg.h" #endif /* Hash that stores user set extensions */ diff --git a/tcg/region.c b/tcg/region.c index 478ec051c4b..56d2e988719 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -34,7 +34,9 @@ #include "exec/translation-block.h" #include "tcg-internal.h" #include "host/cpuinfo.h" - +#ifndef CONFIG_USER_ONLY +#include "system/tcg.h" +#endif /* * Local source-level compatibility with Unix. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec1630de9sm79905905e9.1.2025.04.05.09.14.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:14:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Anton Johansson Subject: [PATCH-for-10.1 v4 14/16] tcg: Convert TCGState::mttcg_enabled to TriState Date: Sat, 5 Apr 2025 18:13:18 +0200 Message-ID: <20250405161320.76854-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use the OnOffAuto type as 3-state. Since the TCGState instance is zero-initialized, the mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO). In tcg_init_machine(), if mttcg_enabled is still AUTO, set a default value (effectively inlining the default_mttcg_enabled() method content). In the tcg_get_thread() getter, consider AUTO / OFF states as "single", otherwise ON is "multi". Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/tcg-all.c | 60 ++++++++++++++++++++++----------------------- 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index b8874430d30..15d4e9232ae 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -32,6 +32,7 @@ #include "qemu/error-report.h" #include "qemu/accel.h" #include "qemu/atomic.h" +#include "qapi/qapi-types-common.h" #include "qapi/qapi-builtin-visit.h" #include "qemu/units.h" #if defined(CONFIG_USER_ONLY) @@ -47,7 +48,7 @@ struct TCGState { AccelState parent_obj; - bool mttcg_enabled; + OnOffAuto mttcg_enabled; bool one_insn_per_tb; int splitwx_enabled; unsigned long tb_size; @@ -70,37 +71,10 @@ bool qemu_tcg_mttcg_enabled(void) #endif /* !CONFIG_USER_ONLY */ -/* - * We default to false if we know other options have been enabled - * which are currently incompatible with MTTCG. Otherwise when each - * guest (target) has been updated to support: - * - atomic instructions - * - memory ordering primitives (barriers) - * they can set the appropriate CONFIG flags in ${target}-softmmu.mak - * - * Once a guest architecture has been converted to the new primitives - * there is one remaining limitation to check: - * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host) - */ - -static bool default_mttcg_enabled(void) -{ - if (icount_enabled()) { - return false; - } -#ifdef TARGET_SUPPORTS_MTTCG - return true; -#else - return false; -#endif -} - static void tcg_accel_instance_init(Object *obj) { TCGState *s = TCG_STATE(obj); - s->mttcg_enabled = default_mttcg_enabled(); - /* If debugging enabled, default "auto on", otherwise off. */ #if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY) s->splitwx_enabled = -1; @@ -118,7 +92,31 @@ static int tcg_init_machine(MachineState *ms) unsigned max_cpus = 1; #else unsigned max_cpus = ms->smp.max_cpus; +#ifdef TARGET_SUPPORTS_MTTCG + bool mttcg_supported = true; +#else + bool mttcg_supported = false; +#endif + if (s->mttcg_enabled == ON_OFF_AUTO_AUTO) { + /* + * We default to false if we know other options have been enabled + * which are currently incompatible with MTTCG. Otherwise when each + * guest (target) has been updated to support: + * - atomic instructions + * - memory ordering primitives (barriers) + * they can set the appropriate CONFIG flags in ${target}-softmmu.mak + * + * Once a guest architecture has been converted to the new primitives + * there is one remaining limitation to check: + * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host) + */ + if (icount_enabled()) { + s->mttcg_enabled = ON_OFF_AUTO_OFF; + } else { + s->mttcg_enabled = mttcg_supported; + } + } mttcg_enabled = s->mttcg_enabled; #endif @@ -147,7 +145,7 @@ static char *tcg_get_thread(Object *obj, Error **errp) { TCGState *s = TCG_STATE(obj); - return g_strdup(s->mttcg_enabled ? "multi" : "single"); + return g_strdup(s->mttcg_enabled == ON_OFF_AUTO_ON ? "multi" : "single"); } static void tcg_set_thread(Object *obj, const char *value, Error **errp) @@ -162,10 +160,10 @@ static void tcg_set_thread(Object *obj, const char *value, Error **errp) warn_report("Guest not yet converted to MTTCG - " "you may get unexpected results"); #endif - s->mttcg_enabled = true; + s->mttcg_enabled = ON_OFF_AUTO_ON; } } else if (strcmp(value, "single") == 0) { - s->mttcg_enabled = false; + s->mttcg_enabled = ON_OFF_AUTO_OFF; } else { error_setg(errp, "Invalid 'thread' setting %s", value); } From patchwork Sat Apr 5 16:13:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 878423 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp4289090wrs; Sat, 5 Apr 2025 09:15:41 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUL47IXHfRqMQM25aA7BnMo/jMjtIZzWNQJP2gr2Fo92YOoTtSZit5zIs0JN+IIUZV9748RlQ==@linaro.org X-Google-Smtp-Source: AGHT+IEyUS79TM5bnKrW3R0EhubD9WIQdm8U57SLM0tRx8wKfYwy6uGzWtCvieMq/wVn1CN7j6sm X-Received: by 2002:ad4:5ec8:0:b0:6e2:49eb:fb7 with SMTP id 6a1803df08f44-6ef0be4f62dmr141844796d6.3.1743869740869; Sat, 05 Apr 2025 09:15:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743869740; cv=none; d=google.com; s=arc-20240605; b=amIQUCJLpdu+0+yJkBQJQ0aTrWEh4IJ+abqTdreM3kLJj/XPbUahR0rI6BI/LUbGWr 3g/r/RffCA0lwS2xlxwSABplijuZUl3pdXQfgSVaDzEdN4+jlXg1NMoa1qlf7m5zY77G 6Ux4dRVbe+Bi1jg+412DciojLUKWazm3L8s4+Hp0FZ+vlzBq0f7CMkb2gS9sHJVsj9qH Ia3U4cBx88onHQJf7mx3ZjKjgcu66BKjoHCTd4+RuCOK0f+YJOUajZ9i6semYO8tKuF4 oyWA5PMsWDo8vTJWqakgAdXuke7ISqsnZOWC7k4i4c4uPqwZjGVWHpWp4qMOJvp+sKAw GIOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fLiC832/142ITmF1Yvgl6ilLfBOuUrOH271pHrSjNR0=; fh=ZXDWg7hKG7Hj19AbRuutTLw+Zvn/B9RsGUUw/YagpFI=; b=NUDyhnwmFBWZ6BGZhTrQr1DkzhidBSSW0IF0MtDgOEHqCLTMSZHkQUWmcOUh8izqIO lNiiPIeeZ+ENuNYajgkkC7T9PIHxnRpfZNszhupP3y42yM1vONazyt/yqf1urLUUJm0+ WvYVuqkeIo76cKdKPbl7mgs4OTk0wFzbhOzqjQthcGuzU8n1EX3enKia6LPtuoPdaer2 S5pUQKdyit59byKByFnh4V0hi2PPQSIO00DYZQP9MvVoJo4GQme4Pr4JFEBAR6tqAXlp 9w6SmrlTAfJCTZxGN4REk8A7nlhamRaeo0Vb375V0cBEd6W3Z49zaZdfibFVLoOApu9k mIaw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="cOWh/9oi"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec1794efesm80953835e9.28.2025.04.05.09.14.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:14:33 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v4 15/16] tcg: Factor mttcg_init() out Date: Sat, 5 Apr 2025 18:13:19 +0200 Message-ID: <20250405161320.76854-16-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Keep MTTCG initialization code out of tcg_init_machine(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/tcg-all.c | 50 +++++++++++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 22 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 15d4e9232ae..267830658ca 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -69,29 +69,8 @@ bool qemu_tcg_mttcg_enabled(void) return mttcg_enabled; } -#endif /* !CONFIG_USER_ONLY */ - -static void tcg_accel_instance_init(Object *obj) +static void mttcg_init(TCGState *s) { - TCGState *s = TCG_STATE(obj); - - /* If debugging enabled, default "auto on", otherwise off. */ -#if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY) - s->splitwx_enabled = -1; -#else - s->splitwx_enabled = 0; -#endif -} - -bool one_insn_per_tb; - -static int tcg_init_machine(MachineState *ms) -{ - TCGState *s = TCG_STATE(current_accel()); -#ifdef CONFIG_USER_ONLY - unsigned max_cpus = 1; -#else - unsigned max_cpus = ms->smp.max_cpus; #ifdef TARGET_SUPPORTS_MTTCG bool mttcg_supported = true; #else @@ -118,6 +97,33 @@ static int tcg_init_machine(MachineState *ms) } } mttcg_enabled = s->mttcg_enabled; +} + +#endif /* !CONFIG_USER_ONLY */ + +static void tcg_accel_instance_init(Object *obj) +{ + TCGState *s = TCG_STATE(obj); + + /* If debugging enabled, default "auto on", otherwise off. */ +#if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY) + s->splitwx_enabled = -1; +#else + s->splitwx_enabled = 0; +#endif +} + +bool one_insn_per_tb; + +static int tcg_init_machine(MachineState *ms) +{ + TCGState *s = TCG_STATE(current_accel()); +#ifdef CONFIG_USER_ONLY + unsigned max_cpus = 1; +#else + unsigned max_cpus = ms->smp.max_cpus; + + mttcg_init(s); #endif tcg_allowed = true; From patchwork Sat Apr 5 16:13:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 878425 Delivered-To: patch@linaro.org Received: by 2002:a5d:6dae:0:b0:38f:210b:807b with SMTP id u14csp4289136wrs; Sat, 5 Apr 2025 09:15:46 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUVSOB2QUaBpxUE1nyC3zR+1u496QuKgEbHgPX0LE2VdezlPyLeNmsVmXnZyHfOoDxkE1dQOQ==@linaro.org X-Google-Smtp-Source: AGHT+IHa9uEe6tM5Vsc3vtkCcRe4hF2iiSlIYkEDyWNQJ9iivgPtxOBbSfFN7t99X3YQ6zAfpmrA X-Received: by 2002:a05:620a:c53:b0:7c5:55be:7bff with SMTP id af79cd13be357-7c775ad8921mr1024896985a.43.1743869745872; Sat, 05 Apr 2025 09:15:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1743869745; cv=none; d=google.com; s=arc-20240605; b=YZh9tOeJjwmnLgrnxJIgpfRXkFAIxvcKKlRetAeNSWsUNcXIV5/jrn/jL/AGR5rhvs 950gqwdakPHSP5hjwDPPNhuQONZl0zYcjMfH+aTQfBBu6NO45JvpouWCt9GvCiIhdVzc v7Rf91+9KNS1WMwisJRb+Fs1CexbDkBqgty9zylOp1B6USJgAqiy0TE9UcNz+9hS6vU3 s0U29H9M3+YJ3Mj/ohkh2B+jhJqBB7UcNZKacDupwMDkjXuCBYRU8q7c6g1oY+ElOesG IyqMKVcjm0rJxnCW2Wtd3B9Gr8k5ToBpK7/CCspfKAlvFU89xVcxKX24zwMyaCZPqI1C yiWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Za9SN5SGg/6VR8rTeUlc4Qwr/9ZnskfD9hV5+cRNuTY=; fh=ylnw7U4KxGWi5H7QdoxjmFHf/0LKSGXnbXb+iD8gkqQ=; b=GRuQnGNAVQ6/KYahJsl05UtexRCfSdnH3AHcHrfNP8EM4Ov0KeCowlLjgyOR8d09xa 2cgJLaDNcZedaE7uzj59gI5MyfsbLqUUO01Mym++Gj5dkKle8y71OdIBqqvQLSW1RrAY qOcqs10t9CD60R0WlCvAlQidlL7eDAl+fzQp+ThTWSr+8j4t6RjnPG1L5BTx2u8EgjG5 Kh+zFYsn9crn3m31pBJInYSL87zP2i00AH2S3GAvE40eK/W5YXDersM7sIJc8GdQu9Ct 5be2nuQ6hdHDYDOsCfvejHt0YWzJ8LpDjI50HO9TCoSp3pSeew0IlCgrc87HkbNXrLK0 qazA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vG5fW6aF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec1795243sm81002725e9.32.2025.04.05.09.14.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:14:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Anton Johansson , Pierrick Bouvier Subject: [PATCH-for-10.1 v4 16/16] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field Date: Sat, 5 Apr 2025 18:13:20 +0200 Message-ID: <20250405161320.76854-17-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition, have each target set the 'mttcg_supported' field in the TCGCPUOps structure. Since so far we only emulate one target architecture at a time, tcg_init_machine() gets whether MTTCG is supported via the current CPU class (CPU_RESOLVING_TYPE). Since TARGET_SUPPORTS_MTTCG isn't available anymore, instead of emiting a warning when the 'thread' property is set in tcg_set_thread(), emit it in tcg_init_machine() where it is consumed. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- docs/devel/multi-thread-tcg.rst | 2 +- configs/targets/aarch64-softmmu.mak | 1 - configs/targets/alpha-softmmu.mak | 1 - configs/targets/arm-softmmu.mak | 1 - configs/targets/hppa-softmmu.mak | 1 - configs/targets/i386-softmmu.mak | 1 - configs/targets/loongarch64-softmmu.mak | 1 - configs/targets/microblaze-softmmu.mak | 1 - configs/targets/microblazeel-softmmu.mak | 1 - configs/targets/mips-softmmu.mak | 1 - configs/targets/mipsel-softmmu.mak | 1 - configs/targets/or1k-softmmu.mak | 1 - configs/targets/ppc64-softmmu.mak | 1 - configs/targets/riscv32-softmmu.mak | 1 - configs/targets/riscv64-softmmu.mak | 1 - configs/targets/s390x-softmmu.mak | 1 - configs/targets/sparc-softmmu.mak | 1 - configs/targets/sparc64-softmmu.mak | 1 - configs/targets/x86_64-softmmu.mak | 1 - configs/targets/xtensa-softmmu.mak | 1 - configs/targets/xtensaeb-softmmu.mak | 1 - include/accel/tcg/cpu-ops.h | 8 ++++++++ include/exec/poison.h | 1 - accel/tcg/tcg-all.c | 17 ++++++++--------- target/alpha/cpu.c | 1 + target/arm/cpu.c | 1 + target/arm/tcg/cpu-v7m.c | 1 + target/avr/cpu.c | 1 + target/hexagon/cpu.c | 1 + target/hppa/cpu.c | 1 + target/i386/tcg/tcg-cpu.c | 1 + target/loongarch/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 1 + target/rx/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + 44 files changed, 37 insertions(+), 31 deletions(-) diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.rst index 14a2a9dc7b5..da9a1530c9f 100644 --- a/docs/devel/multi-thread-tcg.rst +++ b/docs/devel/multi-thread-tcg.rst @@ -30,7 +30,7 @@ user-space thread. This is enabled by default for all FE/BE combinations where the host memory model is able to accommodate the guest (TCGCPUOps::guest_default_memory_order & ~TCG_TARGET_DEFAULT_MO is zero) and the guest has had the required work done to support this safely -(TARGET_SUPPORTS_MTTCG). +(TCGCPUOps::mttcg_supported). System emulation will fall back to the original round robin approach if: diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak index 82cb72cb83d..5dfeb35af90 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml # needed by boot.c diff --git a/configs/targets/alpha-softmmu.mak b/configs/targets/alpha-softmmu.mak index 89f3517aca0..5275076e50d 100644 --- a/configs/targets/alpha-softmmu.mak +++ b/configs/targets/alpha-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=alpha -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=64 diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.mak index afc64f5927b..6a5a8eda949 100644 --- a/configs/targets/arm-softmmu.mak +++ b/configs/targets/arm-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=arm -TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml # needed by boot.c TARGET_NEED_FDT=y diff --git a/configs/targets/hppa-softmmu.mak b/configs/targets/hppa-softmmu.mak index 63ca74ed5e6..ea331107a08 100644 --- a/configs/targets/hppa-softmmu.mak +++ b/configs/targets/hppa-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=hppa TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=64 diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmmu.mak index 5dd89217560..e9d89e8ab41 100644 --- a/configs/targets/i386-softmmu.mak +++ b/configs/targets/i386-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=i386 -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_KVM_HAVE_RESET_PARKED_VCPU=y TARGET_XML_FILES= gdb-xml/i386-32bit.xml diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak index 351341132f6..fc44c54233d 100644 --- a/configs/targets/loongarch64-softmmu.mak +++ b/configs/targets/loongarch64-softmmu.mak @@ -1,7 +1,6 @@ TARGET_ARCH=loongarch64 TARGET_BASE_ARCH=loongarch TARGET_KVM_HAVE_GUEST_DEBUG=y -TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-lasx.xml # all boards require libfdt TARGET_NEED_FDT=y diff --git a/configs/targets/microblaze-softmmu.mak b/configs/targets/microblaze-softmmu.mak index 99a33ed44a8..23457d0ae65 100644 --- a/configs/targets/microblaze-softmmu.mak +++ b/configs/targets/microblaze-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=microblaze TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y # needed by boot.c TARGET_NEED_FDT=y TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml diff --git a/configs/targets/microblazeel-softmmu.mak b/configs/targets/microblazeel-softmmu.mak index 52cdeae1a28..c82c509623d 100644 --- a/configs/targets/microblazeel-softmmu.mak +++ b/configs/targets/microblazeel-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=microblaze -TARGET_SUPPORTS_MTTCG=y # needed by boot.c TARGET_NEED_FDT=y TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml diff --git a/configs/targets/mips-softmmu.mak b/configs/targets/mips-softmmu.mak index b62a0882499..c9588066b8d 100644 --- a/configs/targets/mips-softmmu.mak +++ b/configs/targets/mips-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=mips TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=32 diff --git a/configs/targets/mipsel-softmmu.mak b/configs/targets/mipsel-softmmu.mak index 620ec681785..90e09bdc3e5 100644 --- a/configs/targets/mipsel-softmmu.mak +++ b/configs/targets/mipsel-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=mips -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=32 diff --git a/configs/targets/or1k-softmmu.mak b/configs/targets/or1k-softmmu.mak index adfddb1a8ac..0e47d9878b0 100644 --- a/configs/targets/or1k-softmmu.mak +++ b/configs/targets/or1k-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=openrisc -TARGET_SUPPORTS_MTTCG=y TARGET_BIG_ENDIAN=y # needed by boot.c and all boards TARGET_NEED_FDT=y diff --git a/configs/targets/ppc64-softmmu.mak b/configs/targets/ppc64-softmmu.mak index 7cee0e97f43..74572864b36 100644 --- a/configs/targets/ppc64-softmmu.mak +++ b/configs/targets/ppc64-softmmu.mak @@ -1,7 +1,6 @@ TARGET_ARCH=ppc64 TARGET_BASE_ARCH=ppc TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/power64-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml gdb-xml/power-vsx.xml # all boards require libfdt diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-softmmu.mak index c828066ce6b..db55275b868 100644 --- a/configs/targets/riscv32-softmmu.mak +++ b/configs/targets/riscv32-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=riscv32 TARGET_BASE_ARCH=riscv -TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c TARGET_NEED_FDT=y diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak index 09f613d24a0..2bdd4a62cd2 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c diff --git a/configs/targets/s390x-softmmu.mak b/configs/targets/s390x-softmmu.mak index 5242ebe7c2e..76dd5de6584 100644 --- a/configs/targets/s390x-softmmu.mak +++ b/configs/targets/s390x-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=s390x TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml TARGET_LONG_BITS=64 diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak index 78c2e25bd13..57801faf1fc 100644 --- a/configs/targets/sparc-softmmu.mak +++ b/configs/targets/sparc-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=sparc TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=32 diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak index f7bab97a002..2504e31ae33 100644 --- a/configs/targets/sparc64-softmmu.mak +++ b/configs/targets/sparc64-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=sparc64 TARGET_BASE_ARCH=sparc TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=64 diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-softmmu.mak index 1ceefde1313..5619b2bc686 100644 --- a/configs/targets/x86_64-softmmu.mak +++ b/configs/targets/x86_64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=x86_64 TARGET_BASE_ARCH=i386 -TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y TARGET_KVM_HAVE_RESET_PARKED_VCPU=y TARGET_XML_FILES= gdb-xml/i386-64bit.xml diff --git a/configs/targets/xtensa-softmmu.mak b/configs/targets/xtensa-softmmu.mak index 65845df4ffa..2a9797338a6 100644 --- a/configs/targets/xtensa-softmmu.mak +++ b/configs/targets/xtensa-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=xtensa -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=32 diff --git a/configs/targets/xtensaeb-softmmu.mak b/configs/targets/xtensaeb-softmmu.mak index f1f789d6971..5204729af8b 100644 --- a/configs/targets/xtensaeb-softmmu.mak +++ b/configs/targets/xtensaeb-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=xtensa TARGET_BIG_ENDIAN=y -TARGET_SUPPORTS_MTTCG=y TARGET_LONG_BITS=32 diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index a4932fc5d7c..0e4352513d1 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -19,6 +19,14 @@ #include "tcg/tcg-mo.h" struct TCGCPUOps { + /** + * mttcg_supported: multi-threaded TCG is supported + * + * Target (TCG frontend) supports: + * - atomic instructions + * - memory ordering primitives (barriers) + */ + bool mttcg_supported; /** * @guest_default_memory_order: default barrier that is required diff --git a/include/exec/poison.h b/include/exec/poison.h index 0f336cdc618..413dfd16f24 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -35,7 +35,6 @@ #pragma GCC poison TARGET_HAS_BFLT #pragma GCC poison TARGET_NAME -#pragma GCC poison TARGET_SUPPORTS_MTTCG #pragma GCC poison TARGET_BIG_ENDIAN #pragma GCC poison TARGET_HAS_PRECISE_SMC diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 267830658ca..bf27c5c0fb3 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -41,8 +41,10 @@ #include "hw/boards.h" #include "system/tcg.h" #endif +#include "accel/tcg/cpu-ops.h" #include "internal-common.h" #include "cpu-param.h" +#include "cpu.h" struct TCGState { @@ -71,11 +73,8 @@ bool qemu_tcg_mttcg_enabled(void) static void mttcg_init(TCGState *s) { -#ifdef TARGET_SUPPORTS_MTTCG - bool mttcg_supported = true; -#else - bool mttcg_supported = false; -#endif + CPUClass *cc = CPU_CLASS(object_class_by_name(CPU_RESOLVING_TYPE)); + bool mttcg_supported = cc->tcg_ops->mttcg_supported; if (s->mttcg_enabled == ON_OFF_AUTO_AUTO) { /* @@ -96,6 +95,10 @@ static void mttcg_init(TCGState *s) s->mttcg_enabled = mttcg_supported; } } + if (s->mttcg_enabled == ON_OFF_AUTO_ON && !mttcg_supported) { + warn_report("Guest not yet converted to MTTCG - " + "you may get unexpected results"); + } mttcg_enabled = s->mttcg_enabled; } @@ -162,10 +165,6 @@ static void tcg_set_thread(Object *obj, const char *value, Error **errp) if (icount_enabled()) { error_setg(errp, "No MTTCG when icount is enabled"); } else { -#ifndef TARGET_SUPPORTS_MTTCG - warn_report("Guest not yet converted to MTTCG - " - "you may get unexpected results"); -#endif s->mttcg_enabled = ON_OFF_AUTO_ON; } } else if (strcmp(value, "single") == 0) { diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index eeaf3a81c1a..35fb145d27f 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -237,6 +237,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = { static const TCGCPUOps alpha_tcg_ops = { /* Alpha processors have a weak memory model */ .guest_default_memory_order = 0, + .mttcg_supported = true, .initialize = alpha_translate_init, .translate_code = alpha_translate_code, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3e9760b5518..377791c84dd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2671,6 +2671,7 @@ static const struct SysemuCPUOps arm_sysemu_ops = { #ifdef CONFIG_TCG static const TCGCPUOps arm_tcg_ops = { + .mttcg_supported = true, /* ARM processors have a weak memory model */ .guest_default_memory_order = 0, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 89d4e4b4a2f..f71560aa43b 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -234,6 +234,7 @@ static void cortex_m55_initfn(Object *obj) static const TCGCPUOps arm_v7m_tcg_ops = { /* ARM processors have a weak memory model */ .guest_default_memory_order = 0, + .mttcg_supported = true, .initialize = arm_translate_init, .translate_code = arm_translate_code, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 8f79cf4c08b..84f3b839c9b 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -225,6 +225,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = { static const TCGCPUOps avr_tcg_ops = { .guest_default_memory_order = 0, + .mttcg_supported = false, .initialize = avr_cpu_tcg_init, .translate_code = avr_cpu_translate_code, .synchronize_from_tb = avr_cpu_synchronize_from_tb, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index e54f10c2294..2de6911f5aa 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -329,6 +329,7 @@ static const TCGCPUOps hexagon_tcg_ops = { * Hexagon processors have a strong memory model. */ .guest_default_memory_order = TCG_MO_ALL, + .mttcg_supported = false, .initialize = hexagon_translate_init, .translate_code = hexagon_translate_code, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index dfbd9330565..10e18c945ef 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -260,6 +260,7 @@ static const TCGCPUOps hppa_tcg_ops = { * basis. It's probably easier to fall back to a strong memory model. */ .guest_default_memory_order = TCG_MO_ALL, + .mttcg_supported = true, .initialize = hppa_translate_init, .translate_code = hppa_translate_code, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 5295fcea5c3..c00a94fd582 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -125,6 +125,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "accel/tcg/cpu-ops.h" const TCGCPUOps x86_tcg_ops = { + .mttcg_supported = true, /* * The x86 has a strong memory model with some store-after-load re-ordering */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index f5b8ef29ab0..fe9462b3b7e 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -865,6 +865,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) static const TCGCPUOps loongarch_tcg_ops = { .guest_default_memory_order = 0, + .mttcg_supported = true, .initialize = loongarch_translate_init, .translate_code = loongarch_translate_code, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index b2d8c8f1dea..99adc5eb910 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -591,6 +591,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = { static const TCGCPUOps m68k_tcg_ops = { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, + .mttcg_supported = false, .initialize = m68k_tcg_init, .translate_code = m68k_translate_code, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 4efba0dddb2..edfb05758b3 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -429,6 +429,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = { static const TCGCPUOps mb_tcg_ops = { /* MicroBlaze is always in-order. */ .guest_default_memory_order = TCG_MO_ALL, + .mttcg_supported = true, .initialize = mb_tcg_init, .translate_code = mb_translate_code, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 010773405a8..77bdb6db887 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -550,6 +550,7 @@ static const Property mips_cpu_properties[] = { #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" static const TCGCPUOps mips_tcg_ops = { + .mttcg_supported = TARGET_LONG_BITS == 32, .guest_default_memory_order = 0, .initialize = mips_tcg_init, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 87fe779042c..6601e0c0666 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -244,6 +244,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { static const TCGCPUOps openrisc_tcg_ops = { .guest_default_memory_order = 0, + .mttcg_supported = true, .initialize = openrisc_translate_init, .translate_code = openrisc_translate_code, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 8300fa5777e..f95c731c97f 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7478,6 +7478,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = { #include "accel/tcg/cpu-ops.h" static const TCGCPUOps ppc_tcg_ops = { + .mttcg_supported = TARGET_LONG_BITS == 64, .guest_default_memory_order = 0, .initialize = ppc_translate_init, .translate_code = ppc_translate_code, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 44fdf6c4cf1..426145c3b9f 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -141,6 +141,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, } const TCGCPUOps riscv_tcg_ops = { + .mttcg_supported = true, .guest_default_memory_order = 0, .initialize = riscv_translate_init, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index f073fe8fc98..0a7a2b55b5a 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -206,6 +206,7 @@ static const struct SysemuCPUOps rx_sysemu_ops = { static const TCGCPUOps rx_tcg_ops = { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, + .mttcg_supported = false, .initialize = rx_translate_init, .translate_code = rx_translate_code, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 1e101b5afeb..41cccc1e692 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -345,6 +345,7 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, } static const TCGCPUOps s390_tcg_ops = { + .mttcg_supported = true, /* * The z/Architecture has a strong memory model with some * store-after-load re-ordering. diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 7a05301c6ff..861fdd47f76 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -264,6 +264,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = { static const TCGCPUOps superh_tcg_ops = { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, + .mttcg_supported = false, .initialize = sh4_translate_init, .translate_code = sh4_translate_code, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 56d9417ae3f..f7d231c6f8b 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1023,6 +1023,7 @@ static const TCGCPUOps sparc_tcg_ops = { * by an implied MEMBAR #StoreStore. */ .guest_default_memory_order = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST, + .mttcg_supported = true, .initialize = sparc_tcg_init, .translate_code = sparc_translate_code, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index c68954b4096..a4f93e7d910 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -174,6 +174,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = { static const TCGCPUOps tricore_tcg_ops = { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order = TCG_MO_ALL, + .mttcg_supported = false, .initialize = tricore_tcg_init, .translate_code = tricore_translate_code, .synchronize_from_tb = tricore_cpu_synchronize_from_tb, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 2cbf4e30108..971e67ad978 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -234,6 +234,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { static const TCGCPUOps xtensa_tcg_ops = { /* Xtensa processors have a weak memory model */ .guest_default_memory_order = 0, + .mttcg_supported = true, .initialize = xtensa_translate_init, .translate_code = xtensa_translate_code,