From patchwork Wed Apr 9 06:56:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "zhenglifeng \(A\)" X-Patchwork-Id: 879782 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB751213245; Wed, 9 Apr 2025 06:57:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.191 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744181831; cv=none; b=YWqSgNBY2ULqXBVGlSmT62YYcI7ce7WgxaWrZzj1ILZPNUSuraE9/0EfBbj9UNb7G2zhH0dh04GvECwawuiPGiwzB99xhzgDcLWmKbNZgBmC10gBdDwwNiQJ4AlgIcUTIhExyWSSAkILJMG146h5inb4zI9WH0rPYSvYSzFFVPc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744181831; c=relaxed/simple; bh=nDNvcGa9mb12hyB1y6PAopbo3bvof6x9tkNdInKpOU8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZLSop/UMTcKIMC9Ime9PbdfMzv8cEG37gwIfeEI/SbwWJlMzF+TwXMy9WYl+a+LIJuq9lY98gN/+gvbBtY/BPav7T/atF4cHsFiCDvgo1vZxF9t/3ueeNgPPDiYVTWcpwyfxC4tafVe/vuFakBUfMrb79e1HC5EuaxVznQpe0Jg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.191 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.17]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4ZXYXT0w8Dz26gwd; Wed, 9 Apr 2025 14:52:09 +0800 (CST) Received: from kwepemh100008.china.huawei.com (unknown [7.202.181.93]) by mail.maildlp.com (Postfix) with ESMTPS id 024681A0188; Wed, 9 Apr 2025 14:57:06 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by kwepemh100008.china.huawei.com (7.202.181.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 9 Apr 2025 14:57:05 +0800 From: Lifeng Zheng To: , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v6 1/8] ACPI: CPPC: Add IS_OPTIONAL_CPC_REG macro to judge if a cpc_reg is optional Date: Wed, 9 Apr 2025 14:56:56 +0800 Message-ID: <20250409065703.1461867-2-zhenglifeng1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250409065703.1461867-1-zhenglifeng1@huawei.com> References: <20250409065703.1461867-1-zhenglifeng1@huawei.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To kwepemh100008.china.huawei.com (7.202.181.93) In ACPI 6.5, s8.4.6.1 _CPC (Continuous Performance Control), whether each of the per-cpu cpc_regs[] is mendatory or optional is defined. Since the CPC_SUPPORTED() check is only for optional cpc field, another macro to check if the field is optional is needed. Reviewed-by: Pierre Gondois Signed-off-by: Lifeng Zheng --- drivers/acpi/cppc_acpi.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index f193e713825a..39f019e265da 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -129,6 +129,20 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr); #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \ !!(cpc)->cpc_entry.int_value : \ !IS_NULL_REG(&(cpc)->cpc_entry.reg)) + +/* + * Each bit indicates the optionality of the register in per-cpu + * cpc_regs[] with the corresponding index. 0 means mandatory and 1 + * means optional. + */ +#define REG_OPTIONAL (0x1FC7D0) + +/* + * Use the index of the register in per-cpu cpc_regs[] to check if + * it's an optional one. + */ +#define IS_OPTIONAL_CPC_REG(reg_idx) (REG_OPTIONAL & (1U << (reg_idx))) + /* * Arbitrary Retries in case the remote processor is slow to respond * to PCC commands. Keeping it high enough to cover emulators where From patchwork Wed Apr 9 06:56:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "zhenglifeng \(A\)" X-Patchwork-Id: 879781 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FB2621324E; Wed, 9 Apr 2025 06:57:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744181832; cv=none; b=PRe2tA24hJeXUcjR4rBf3JaQrUkUtcz6U6mI8ZdqnmG3WTTpOSZmjqwZsI/Iiri9Cjjr9AD2F3IBTyP1aHjkHZJekkgi4F1tTDi2x9tzD0FjjYjby8xnoeZhbEC6YMEPjXXTEwO1Eydw/2PafL4F+bI/MLjDzgGv28sl8up4pTw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744181832; c=relaxed/simple; bh=azfOtZ+FisifIFITjBNrySyBCSvJfsqNadjetFy/v8I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kGX5Fi9KcH1eEVeA3TT3yhLR2yAepVS/nIZ6bnCVip6AcstnnCLfPU6MoI7wnC07FA0mdFMqTriO63EWU6FrIWecB5ELETPRtHn7drD3iNcXPo0mKurpQexZPpy2OhbXtKca2FYSz8fGjXu8lt/jcBjXAyb5UnYOS8JmskpOGAA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.162.254]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4ZXYYs3prqz69Zw; Wed, 9 Apr 2025 14:53:21 +0800 (CST) Received: from kwepemh100008.china.huawei.com (unknown [7.202.181.93]) by mail.maildlp.com (Postfix) with ESMTPS id 9335D180471; Wed, 9 Apr 2025 14:57:06 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by kwepemh100008.china.huawei.com (7.202.181.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 9 Apr 2025 14:57:05 +0800 From: Lifeng Zheng To: , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v6 2/8] ACPI: CPPC: Optimize cppc_get_perf() Date: Wed, 9 Apr 2025 14:56:57 +0800 Message-ID: <20250409065703.1461867-3-zhenglifeng1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250409065703.1461867-1-zhenglifeng1@huawei.com> References: <20250409065703.1461867-1-zhenglifeng1@huawei.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To kwepemh100008.china.huawei.com (7.202.181.93) Optimize cppc_get_perf() with three changes: 1. Change the error kind to "no such device" when pcc_ss_id < 0, as other register value getting functions. 2. Add a check to verify if the register is supported to be read before using it. The logic is: (1) If the register is of the integer type, check whether the register is optional and its value is 0. If yes, the register is not supported. (2) If the register is of other types, a null one is not supported. 3. Return the result of cpc_read() instead of 0. Reviewed-by: Pierre Gondois Signed-off-by: Lifeng Zheng --- drivers/acpi/cppc_acpi.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 39f019e265da..2f789d3b3cad 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1201,20 +1201,29 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) reg = &cpc_desc->cpc_regs[reg_idx]; + if (reg->type == ACPI_TYPE_INTEGER ? + (IS_OPTIONAL_CPC_REG(reg_idx) && !reg->cpc_entry.int_value) : + IS_NULL_REG(®->cpc_entry.reg)) { + pr_debug("CPC register is not supported\n"); + return -EOPNOTSUPP; + } + if (CPC_IN_PCC(reg)) { int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); struct cppc_pcc_data *pcc_ss_data = NULL; - int ret = 0; + int ret; - if (pcc_ss_id < 0) - return -EIO; + if (pcc_ss_id < 0) { + pr_debug("Invalid pcc_ss_id\n"); + return -ENODEV; + } pcc_ss_data = pcc_data[pcc_ss_id]; down_write(&pcc_ss_data->pcc_lock); if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) - cpc_read(cpunum, reg, perf); + ret = cpc_read(cpunum, reg, perf); else ret = -EIO; @@ -1223,9 +1232,7 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) return ret; } - cpc_read(cpunum, reg, perf); - - return 0; + return cpc_read(cpunum, reg, perf); } /** From patchwork Wed Apr 9 06:56:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "zhenglifeng \(A\)" X-Patchwork-Id: 879779 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98F5A2135AD; Wed, 9 Apr 2025 06:57:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744181834; cv=none; b=pgYjxzutolWZOKsdY14hq5IZa6sPF+M79eoDa5cMrrbzUYVWX/HFvzQDFLjIfgTme49pA3MJYRrrevpxnzvRTrTVg/JajfD9fSM0v4kBGk7pGHLQOPist+boRotTIHLD1d14W+kuHF3WOZ+It9wln7MFrZbHDRxZIE4+iLswciA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744181834; c=relaxed/simple; bh=PEccsy/K24DS0RhM/KB6pU2VAZ1yxVdt8mZtrEpb5Uo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=r36i0/U1fQDCfnCTmcXmNIxjc2vUvnlLxUh/OQG2/SWIAz/UdukWP7t7piP/k5i8E/syFtNatVRPuw9PpGAlVVhmgxKDfJ0cAksRjQd2BZePQq/A+9yBrVsl8maVd/7p/Xv1BL8NBM4jN4iXdpcsqdwf8/lFW5u5AaHnYg7KLwc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.194]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4ZXYdQ3YXYz13LVx; Wed, 9 Apr 2025 14:56:26 +0800 (CST) Received: from kwepemh100008.china.huawei.com (unknown [7.202.181.93]) by mail.maildlp.com (Postfix) with ESMTPS id 2F88A1401E0; Wed, 9 Apr 2025 14:57:07 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by kwepemh100008.china.huawei.com (7.202.181.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 9 Apr 2025 14:57:06 +0800 From: Lifeng Zheng To: , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v6 3/8] ACPI: CPPC: Rename cppc_get_perf() to cppc_get_reg_val() Date: Wed, 9 Apr 2025 14:56:58 +0800 Message-ID: <20250409065703.1461867-4-zhenglifeng1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250409065703.1461867-1-zhenglifeng1@huawei.com> References: <20250409065703.1461867-1-zhenglifeng1@huawei.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To kwepemh100008.china.huawei.com (7.202.181.93) Rename cppc_get_perf() to cppc_get_reg_val() as a generic function to read cppc registers. Reviewed-by: Pierre Gondois Signed-off-by: Lifeng Zheng --- drivers/acpi/cppc_acpi.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 2f789d3b3cad..9e26f115e1a9 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1189,13 +1189,13 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) return ret_val; } -static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) +static int cppc_get_reg_val(int cpu, enum cppc_regs reg_idx, u64 *val) { - struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); struct cpc_register_resource *reg; if (!cpc_desc) { - pr_debug("No CPC descriptor for CPU:%d\n", cpunum); + pr_debug("No CPC descriptor for CPU:%d\n", cpu); return -ENODEV; } @@ -1209,7 +1209,7 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) } if (CPC_IN_PCC(reg)) { - int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); struct cppc_pcc_data *pcc_ss_data = NULL; int ret; @@ -1223,7 +1223,7 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) down_write(&pcc_ss_data->pcc_lock); if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) - ret = cpc_read(cpunum, reg, perf); + ret = cpc_read(cpu, reg, val); else ret = -EIO; @@ -1232,7 +1232,7 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) return ret; } - return cpc_read(cpunum, reg, perf); + return cpc_read(cpu, reg, val); } /** @@ -1244,7 +1244,7 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) */ int cppc_get_desired_perf(int cpunum, u64 *desired_perf) { - return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf); + return cppc_get_reg_val(cpunum, DESIRED_PERF, desired_perf); } EXPORT_SYMBOL_GPL(cppc_get_desired_perf); @@ -1257,7 +1257,7 @@ EXPORT_SYMBOL_GPL(cppc_get_desired_perf); */ int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) { - return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf); + return cppc_get_reg_val(cpunum, NOMINAL_PERF, nominal_perf); } /** @@ -1269,7 +1269,7 @@ int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) */ int cppc_get_highest_perf(int cpunum, u64 *highest_perf) { - return cppc_get_perf(cpunum, HIGHEST_PERF, highest_perf); + return cppc_get_reg_val(cpunum, HIGHEST_PERF, highest_perf); } EXPORT_SYMBOL_GPL(cppc_get_highest_perf); @@ -1282,7 +1282,7 @@ EXPORT_SYMBOL_GPL(cppc_get_highest_perf); */ int cppc_get_epp_perf(int cpunum, u64 *epp_perf) { - return cppc_get_perf(cpunum, ENERGY_PERF, epp_perf); + return cppc_get_reg_val(cpunum, ENERGY_PERF, epp_perf); } EXPORT_SYMBOL_GPL(cppc_get_epp_perf); From patchwork Wed Apr 9 06:56:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "zhenglifeng \(A\)" X-Patchwork-Id: 879377 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FB8621325F; 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dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.252]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4ZXYYt5DbDz69Y1; Wed, 9 Apr 2025 14:53:22 +0800 (CST) Received: from kwepemh100008.china.huawei.com (unknown [7.202.181.93]) by mail.maildlp.com (Postfix) with ESMTPS id C6134180B4A; Wed, 9 Apr 2025 14:57:07 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by kwepemh100008.china.huawei.com (7.202.181.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 9 Apr 2025 14:57:07 +0800 From: Lifeng Zheng To: , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v6 4/8] ACPI: CPPC: Extract cppc_get_reg_val_in_pcc() Date: Wed, 9 Apr 2025 14:56:59 +0800 Message-ID: <20250409065703.1461867-5-zhenglifeng1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250409065703.1461867-1-zhenglifeng1@huawei.com> References: <20250409065703.1461867-1-zhenglifeng1@huawei.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To kwepemh100008.china.huawei.com (7.202.181.93) Extract the operations if register is in pcc out from cppc_get_reg_val() as cppc_get_reg_val_in_pcc(). Reviewed-by: Pierre Gondois Signed-off-by: Lifeng Zheng --- drivers/acpi/cppc_acpi.c | 50 ++++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 23 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 9e26f115e1a9..d844d0715761 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1189,6 +1189,31 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) return ret_val; } +static int cppc_get_reg_val_in_pcc(int cpu, struct cpc_register_resource *reg, u64 *val) +{ + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret; + + if (pcc_ss_id < 0) { + pr_debug("Invalid pcc_ss_id\n"); + return -ENODEV; + } + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + + if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) + ret = cpc_read(cpu, reg, val); + else + ret = -EIO; + + up_write(&pcc_ss_data->pcc_lock); + + return ret; +} + static int cppc_get_reg_val(int cpu, enum cppc_regs reg_idx, u64 *val) { struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); @@ -1208,29 +1233,8 @@ static int cppc_get_reg_val(int cpu, enum cppc_regs reg_idx, u64 *val) return -EOPNOTSUPP; } - if (CPC_IN_PCC(reg)) { - int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); - struct cppc_pcc_data *pcc_ss_data = NULL; - int ret; - - if (pcc_ss_id < 0) { - pr_debug("Invalid pcc_ss_id\n"); - return -ENODEV; - } - - pcc_ss_data = pcc_data[pcc_ss_id]; - - down_write(&pcc_ss_data->pcc_lock); - - if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) - ret = cpc_read(cpu, reg, val); - else - ret = -EIO; - - up_write(&pcc_ss_data->pcc_lock); - - return ret; - } + if (CPC_IN_PCC(reg)) + return cppc_get_reg_val_in_pcc(cpu, reg, val); return cpc_read(cpu, reg, val); } From patchwork Wed Apr 9 06:57:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "zhenglifeng \(A\)" X-Patchwork-Id: 879375 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 821DF21ABAD; Wed, 9 Apr 2025 06:57:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.255 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744181838; cv=none; b=nmPYzQ55JE9OtfjESW2oT187ByOQIOPGEdoo1bMTKLTLwynpQXnNchIRGfOiwqE99DLBFaO1icppA7o4NxkHd3H3eXOyqAxJVV/sPFBmQ2b/qD7MWXCNNdOBq8mciQ0PjPbA8bZtjCpjuVxiCmmF82cvwnrcHuoKCqpvmh2/qhI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744181838; c=relaxed/simple; bh=FwzhynTwPOtOs9JX2lAa6bb/8rafXzd93ZgaE96lIIk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=E2lnt42MS9xgQZpCzdDOKobKGDBIX7g1EpXw/1W2Affa22z0oyG5+42Y/b1R3AxYt2XnX5MZiNhRH+5ufr5SxdBLUBJ5iS9luHOrBUIQni4nwa0kMDu6ay1/JSg4yFvO0rv6iNcW3pItFQufvqh+4sS6rKeRuADU9HIKkRf23no= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.255 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.162.254]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4ZXYdR5dZ4z1cyT0; Wed, 9 Apr 2025 14:56:27 +0800 (CST) Received: from kwepemh100008.china.huawei.com (unknown [7.202.181.93]) by mail.maildlp.com (Postfix) with ESMTPS id 59634180471; Wed, 9 Apr 2025 14:57:08 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by kwepemh100008.china.huawei.com (7.202.181.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 9 Apr 2025 14:57:07 +0800 From: Lifeng Zheng To: , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v6 5/8] ACPI: CPPC: Add cppc_set_reg_val() Date: Wed, 9 Apr 2025 14:57:00 +0800 Message-ID: <20250409065703.1461867-6-zhenglifeng1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250409065703.1461867-1-zhenglifeng1@huawei.com> References: <20250409065703.1461867-1-zhenglifeng1@huawei.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To kwepemh100008.china.huawei.com (7.202.181.93) Add cppc_set_reg_val() as a generic function for setting cppc registers value, with this features: 1. Check register. If a register is writeable, it must be a buffer and can not be null. 2. Extract the operations if register is in pcc out as cppc_set_reg_val_in_pcc(). This function can be used to reduce some existing code duplication. Reviewed-by: Pierre Gondois Signed-off-by: Lifeng Zheng --- drivers/acpi/cppc_acpi.c | 49 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index d844d0715761..cd584ce2634a 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1239,6 +1239,55 @@ static int cppc_get_reg_val(int cpu, enum cppc_regs reg_idx, u64 *val) return cpc_read(cpu, reg, val); } +static int cppc_set_reg_val_in_pcc(int cpu, struct cpc_register_resource *reg, u64 val) +{ + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret; + + if (pcc_ss_id < 0) { + pr_debug("Invalid pcc_ss_id\n"); + return -ENODEV; + } + + ret = cpc_write(cpu, reg, val); + if (ret) + return ret; + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + /* after writing CPC, transfer the ownership of PCC to platform */ + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); + up_write(&pcc_ss_data->pcc_lock); + + return ret; +} + +static int cppc_set_reg_val(int cpu, enum cppc_regs reg_idx, u64 val) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cpc_register_resource *reg; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -ENODEV; + } + + reg = &cpc_desc->cpc_regs[reg_idx]; + + /* if a register is writeable, it must be a buffer and not null */ + if ((reg->type != ACPI_TYPE_BUFFER) || IS_NULL_REG(®->cpc_entry.reg)) { + pr_debug("CPC register is not supported\n"); + return -EOPNOTSUPP; + } + + if (CPC_IN_PCC(reg)) + return cppc_set_reg_val_in_pcc(cpu, reg, val); + + return cpc_write(cpu, reg, val); +} + /** * cppc_get_desired_perf - Get the desired performance register value. * @cpunum: CPU from which to get desired performance. From patchwork Wed Apr 9 06:57:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "zhenglifeng \(A\)" X-Patchwork-Id: 879780 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AC6A1DE4E7; Wed, 9 Apr 2025 06:57:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744181833; cv=none; b=szYbY5UUcIzeRlb0xW4vHiv7NyuBdMrfKRGGL/TcL2tmzotz4AWD5asnjGcPF8+9TPcyI4ohzontKp1pS4B57+12UJHLxGcNDl2tlUdMIRtViFfNhlwdwDO/Y4SXzojIhZEiiAKmJxz+GzBOrVeGcSnshFDKr+/vZ1nTs5boP8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744181833; c=relaxed/simple; bh=+Z6G2PstoRtd0w7Niiq4BBzc5uh5N1e83GE8Bj9Rp00=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Q3apW6pPE9qaecdqDWeHFJzc0DD1oaHohUDhKIo74v5wDTkRwpyJJLDCHBjn5tbTWEsPi9abeyU/saCd9OhGc7dG3pCmO2GQGWhHPb8XROhq2fL1qEhv+BIQtWi7fDhM0I9k5ebsgWYhmWFK8xBG6QYH3HC1TBQI2QSiH8qp8C8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.162.254]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4ZXYdS23gcz13LX7; Wed, 9 Apr 2025 14:56:28 +0800 (CST) Received: from kwepemh100008.china.huawei.com (unknown [7.202.181.93]) by mail.maildlp.com (Postfix) with ESMTPS id F3B50180471; Wed, 9 Apr 2025 14:57:08 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by kwepemh100008.china.huawei.com (7.202.181.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 9 Apr 2025 14:57:08 +0800 From: Lifeng Zheng To: , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v6 6/8] ACPI: CPPC: Refactor register value get and set ABIs Date: Wed, 9 Apr 2025 14:57:01 +0800 Message-ID: <20250409065703.1461867-7-zhenglifeng1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250409065703.1461867-1-zhenglifeng1@huawei.com> References: <20250409065703.1461867-1-zhenglifeng1@huawei.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To kwepemh100008.china.huawei.com (7.202.181.93) Refactor register value get and set ABIs by using cppc_get_reg_val(), cppc_set_reg_val() and CPPC_REG_VAL_READ(). Reviewed-by: Pierre Gondois Signed-off-by: Lifeng Zheng --- drivers/acpi/cppc_acpi.c | 111 +++------------------------------------ 1 file changed, 7 insertions(+), 104 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index cd584ce2634a..ab492c89b0d8 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1615,44 +1615,14 @@ EXPORT_SYMBOL_GPL(cppc_set_epp_perf); */ int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps) { - struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); - struct cpc_register_resource *auto_sel_reg; - u64 auto_sel; - - if (!cpc_desc) { - pr_debug("No CPC descriptor for CPU:%d\n", cpunum); - return -ENODEV; - } - - auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; - - if (!CPC_SUPPORTED(auto_sel_reg)) - pr_warn_once("Autonomous mode is not unsupported!\n"); - - if (CPC_IN_PCC(auto_sel_reg)) { - int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); - struct cppc_pcc_data *pcc_ss_data = NULL; - int ret = 0; - - if (pcc_ss_id < 0) - return -ENODEV; - - pcc_ss_data = pcc_data[pcc_ss_id]; - - down_write(&pcc_ss_data->pcc_lock); - - if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) { - cpc_read(cpunum, auto_sel_reg, &auto_sel); - perf_caps->auto_sel = (bool)auto_sel; - } else { - ret = -EIO; - } - - up_write(&pcc_ss_data->pcc_lock); + u64 auto_sel; + int ret; + ret = cppc_get_reg_val(cpunum, AUTO_SEL_ENABLE, &auto_sel); + if (ret) return ret; - } + perf_caps->auto_sel = (bool)auto_sel; return 0; } EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps); @@ -1664,43 +1634,7 @@ EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps); */ int cppc_set_auto_sel(int cpu, bool enable) { - int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); - struct cpc_register_resource *auto_sel_reg; - struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); - struct cppc_pcc_data *pcc_ss_data = NULL; - int ret = -EINVAL; - - if (!cpc_desc) { - pr_debug("No CPC descriptor for CPU:%d\n", cpu); - return -ENODEV; - } - - auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; - - if (CPC_IN_PCC(auto_sel_reg)) { - if (pcc_ss_id < 0) { - pr_debug("Invalid pcc_ss_id\n"); - return -ENODEV; - } - - if (CPC_SUPPORTED(auto_sel_reg)) { - ret = cpc_write(cpu, auto_sel_reg, enable); - if (ret) - return ret; - } - - pcc_ss_data = pcc_data[pcc_ss_id]; - - down_write(&pcc_ss_data->pcc_lock); - /* after writing CPC, transfer the ownership of PCC to platform */ - ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); - up_write(&pcc_ss_data->pcc_lock); - } else { - ret = -ENOTSUPP; - pr_debug("_CPC in PCC is not supported\n"); - } - - return ret; + return cppc_set_reg_val(cpu, AUTO_SEL_ENABLE, enable); } EXPORT_SYMBOL_GPL(cppc_set_auto_sel); @@ -1714,38 +1648,7 @@ EXPORT_SYMBOL_GPL(cppc_set_auto_sel); */ int cppc_set_enable(int cpu, bool enable) { - int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); - struct cpc_register_resource *enable_reg; - struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); - struct cppc_pcc_data *pcc_ss_data = NULL; - int ret = -EINVAL; - - if (!cpc_desc) { - pr_debug("No CPC descriptor for CPU:%d\n", cpu); - return -EINVAL; - } - - enable_reg = &cpc_desc->cpc_regs[ENABLE]; - - if (CPC_IN_PCC(enable_reg)) { - - if (pcc_ss_id < 0) - return -EIO; - - ret = cpc_write(cpu, enable_reg, enable); - if (ret) - return ret; - - pcc_ss_data = pcc_data[pcc_ss_id]; - - down_write(&pcc_ss_data->pcc_lock); - /* after writing CPC, transfer the ownership of PCC to platfrom */ - ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); - up_write(&pcc_ss_data->pcc_lock); - return ret; - } - - return cpc_write(cpu, enable_reg, enable); + return cppc_set_reg_val(cpu, ENABLE, enable); } EXPORT_SYMBOL_GPL(cppc_set_enable); From patchwork Wed Apr 9 06:57:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "zhenglifeng \(A\)" X-Patchwork-Id: 879778 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A23652144C0; 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dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.252]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4ZXYdS6nPQz1d18W; Wed, 9 Apr 2025 14:56:28 +0800 (CST) Received: from kwepemh100008.china.huawei.com (unknown [7.202.181.93]) by mail.maildlp.com (Postfix) with ESMTPS id 84420180B4A; Wed, 9 Apr 2025 14:57:09 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by kwepemh100008.china.huawei.com (7.202.181.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 9 Apr 2025 14:57:08 +0800 From: Lifeng Zheng To: , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v6 7/8] ACPI: CPPC: Modify cppc_get_auto_sel_caps() to cppc_get_auto_sel() Date: Wed, 9 Apr 2025 14:57:02 +0800 Message-ID: <20250409065703.1461867-8-zhenglifeng1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250409065703.1461867-1-zhenglifeng1@huawei.com> References: <20250409065703.1461867-1-zhenglifeng1@huawei.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To kwepemh100008.china.huawei.com (7.202.181.93) Modify cppc_get_auto_sel_caps() to cppc_get_auto_sel(). Using a cppc_perf_caps to carry the value is unnecessary. Reviewed-by: Pierre Gondois Signed-off-by: Lifeng Zheng --- drivers/acpi/cppc_acpi.c | 15 ++++++++------- drivers/cpufreq/amd-pstate.c | 3 ++- include/acpi/cppc_acpi.h | 6 +++--- 3 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index ab492c89b0d8..ef2394c074e3 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1609,23 +1609,24 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable) EXPORT_SYMBOL_GPL(cppc_set_epp_perf); /** - * cppc_get_auto_sel_caps - Read autonomous selection register. - * @cpunum : CPU from which to read register. - * @perf_caps : struct where autonomous selection register value is updated. + * cppc_get_auto_sel() - Read autonomous selection register. + * @cpu: CPU from which to read register. + * @enable: Return address. */ -int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps) +int cppc_get_auto_sel(int cpu, bool *enable) { u64 auto_sel; int ret; - ret = cppc_get_reg_val(cpunum, AUTO_SEL_ENABLE, &auto_sel); + ret = cppc_get_reg_val(cpu, AUTO_SEL_ENABLE, &auto_sel); if (ret) return ret; - perf_caps->auto_sel = (bool)auto_sel; + *enable = (bool)auto_sel; + return 0; } -EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps); +EXPORT_SYMBOL_GPL(cppc_get_auto_sel); /** * cppc_set_auto_sel - Write autonomous selection register. diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 6789eed1bb5b..9cd54d8630cd 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -417,6 +417,7 @@ static int shmem_init_perf(struct amd_cpudata *cpudata) struct cppc_perf_caps cppc_perf; union perf_cached perf = READ_ONCE(cpudata->perf); u64 numerator; + bool auto_sel; int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); if (ret) @@ -438,7 +439,7 @@ static int shmem_init_perf(struct amd_cpudata *cpudata) if (cppc_state == AMD_PSTATE_ACTIVE) return 0; - ret = cppc_get_auto_sel_caps(cpudata->cpu, &cppc_perf); + ret = cppc_get_auto_sel(cpudata->cpu, &auto_sel); if (ret) { pr_warn("failed to get auto_sel, ret: %d\n", ret); return 0; diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 62d368bcd9ec..31767c65be20 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -159,7 +159,7 @@ extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val); extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val); extern int cppc_get_epp_perf(int cpunum, u64 *epp_perf); extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable); -extern int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps); +extern int cppc_get_auto_sel(int cpu, bool *enable); extern int cppc_set_auto_sel(int cpu, bool enable); extern int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf); extern int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator); @@ -229,11 +229,11 @@ static inline int cppc_get_epp_perf(int cpunum, u64 *epp_perf) { return -EOPNOTSUPP; } -static inline int cppc_set_auto_sel(int cpu, bool enable) +static inline int cppc_get_auto_sel(int cpu, bool *enable) { return -EOPNOTSUPP; } -static inline int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps) +static inline int cppc_set_auto_sel(int cpu, bool enable) { return -EOPNOTSUPP; } From patchwork Wed Apr 9 06:57:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "zhenglifeng \(A\)" X-Patchwork-Id: 879376 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19BE921480A; Wed, 9 Apr 2025 06:57:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744181834; cv=none; b=QfNEubkLVB41tmjZygrdUf9Q3yXj16sSLd4T1XG5Ogu2tmxMb+q2cOsUBF5GjvjnsGJXq8aIlcAW0r+h69p6s/01uJK66UcC5V2ROqeF1DpKXTf1pJJsrWmWZnsArGVtnoDu09wOkH1qjhVYxutVLTGsHKP2j8F+PmCoOef6Kd0= ARC-Message-Signature: i=1; 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Wed, 9 Apr 2025 14:57:10 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by kwepemh100008.china.huawei.com (7.202.181.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 9 Apr 2025 14:57:09 +0800 From: Lifeng Zheng To: , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v6 8/8] ACPI: CPPC: Add three functions related to autonomous selection Date: Wed, 9 Apr 2025 14:57:03 +0800 Message-ID: <20250409065703.1461867-9-zhenglifeng1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250409065703.1461867-1-zhenglifeng1@huawei.com> References: <20250409065703.1461867-1-zhenglifeng1@huawei.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To kwepemh100008.china.huawei.com (7.202.181.93) cppc_set_epp - write energy performance preference register value, based on ACPI 6.5, s8.4.6.1.7 cppc_get_auto_act_window - read autonomous activity window register value, based on ACPI 6.5, s8.4.6.1.6 cppc_set_auto_act_window - write autonomous activity window register value, based on ACPI 6.5, s8.4.6.1.6 Reviewed-by: Pierre Gondois Signed-off-by: Lifeng Zheng --- drivers/acpi/cppc_acpi.c | 80 ++++++++++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 24 ++++++++++++ 2 files changed, 104 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index ef2394c074e3..3d5eace44af5 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1608,6 +1608,86 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable) } EXPORT_SYMBOL_GPL(cppc_set_epp_perf); +/** + * cppc_set_epp() - Write the EPP register. + * @cpu: CPU on which to write register. + * @epp_val: Value to write to the EPP register. + */ +int cppc_set_epp(int cpu, u64 epp_val) +{ + if (epp_val > CPPC_ENERGY_PERF_MAX) + return -EINVAL; + + return cppc_set_reg_val(cpu, ENERGY_PERF, epp_val); +} +EXPORT_SYMBOL_GPL(cppc_set_epp); + +/** + * cppc_get_auto_act_window() - Read autonomous activity window register. + * @cpu: CPU from which to read register. + * @auto_act_window: Return address. + * + * According to ACPI 6.5, s8.4.6.1.6, the value read from the autonomous + * activity window register consists of two parts: a 7 bits value indicate + * significand and a 3 bits value indicate exponent. + */ +int cppc_get_auto_act_window(int cpu, u64 *auto_act_window) +{ + unsigned int exp; + u64 val, sig; + int ret; + + ret = cppc_get_reg_val(cpu, AUTO_ACT_WINDOW, &val); + if (ret) + return ret; + + sig = val & CPPC_AUTO_ACT_WINDOW_MAX_SIG; + exp = (val >> CPPC_AUTO_ACT_WINDOW_SIG_BIT_SIZE) & CPPC_AUTO_ACT_WINDOW_MAX_EXP; + *auto_act_window = sig * int_pow(10, exp); + + return 0; +} +EXPORT_SYMBOL_GPL(cppc_get_auto_act_window); + +/** + * cppc_set_auto_act_window() - Write autonomous activity window register. + * @cpu: CPU on which to write register. + * @auto_act_window: usec value to write to the autonomous activity window register. + * + * According to ACPI 6.5, s8.4.6.1.6, the value to write to the autonomous + * activity window register consists of two parts: a 7 bits value indicate + * significand and a 3 bits value indicate exponent. + */ +int cppc_set_auto_act_window(int cpu, u64 auto_act_window) +{ + /* The max value to stroe is 1270000000 */ + u64 max_val = CPPC_AUTO_ACT_WINDOW_MAX_SIG * int_pow(10, CPPC_AUTO_ACT_WINDOW_MAX_EXP); + int exp = 0; + u64 val; + + if (auto_act_window > max_val) + return -EINVAL; + + /* + * The max significand is 127, when auto_act_window is larger than + * 129, discard the precision of the last digit and increase the + * exponent by 1. + */ + while (auto_act_window > CPPC_AUTO_ACT_WINDOW_SIG_CARRY_THRESH) { + auto_act_window /= 10; + exp += 1; + } + + /* For 128 and 129, cut it to 127. */ + if (auto_act_window > CPPC_AUTO_ACT_WINDOW_MAX_SIG) + auto_act_window = CPPC_AUTO_ACT_WINDOW_MAX_SIG; + + val = (exp << CPPC_AUTO_ACT_WINDOW_SIG_BIT_SIZE) + auto_act_window; + + return cppc_set_reg_val(cpu, AUTO_ACT_WINDOW, val); +} +EXPORT_SYMBOL_GPL(cppc_set_auto_act_window); + /** * cppc_get_auto_sel() - Read autonomous selection register. * @cpu: CPU from which to read register. diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 31767c65be20..325e9543e08f 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -32,6 +32,15 @@ #define CMD_READ 0 #define CMD_WRITE 1 +#define CPPC_AUTO_ACT_WINDOW_SIG_BIT_SIZE (7) +#define CPPC_AUTO_ACT_WINDOW_EXP_BIT_SIZE (3) +#define CPPC_AUTO_ACT_WINDOW_MAX_SIG ((1 << CPPC_AUTO_ACT_WINDOW_SIG_BIT_SIZE) - 1) +#define CPPC_AUTO_ACT_WINDOW_MAX_EXP ((1 << CPPC_AUTO_ACT_WINDOW_EXP_BIT_SIZE) - 1) +/* CPPC_AUTO_ACT_WINDOW_MAX_SIG is 127, so 128 and 129 will decay to 127 when writing */ +#define CPPC_AUTO_ACT_WINDOW_SIG_CARRY_THRESH 129 + +#define CPPC_ENERGY_PERF_MAX (0xFF) + /* Each register has the folowing format. */ struct cpc_reg { u8 descriptor; @@ -159,6 +168,9 @@ extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val); extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val); extern int cppc_get_epp_perf(int cpunum, u64 *epp_perf); extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable); +extern int cppc_set_epp(int cpu, u64 epp_val); +extern int cppc_get_auto_act_window(int cpu, u64 *auto_act_window); +extern int cppc_set_auto_act_window(int cpu, u64 auto_act_window); extern int cppc_get_auto_sel(int cpu, bool *enable); extern int cppc_set_auto_sel(int cpu, bool enable); extern int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf); @@ -229,6 +241,18 @@ static inline int cppc_get_epp_perf(int cpunum, u64 *epp_perf) { return -EOPNOTSUPP; } +static inline int cppc_set_epp(int cpu, u64 epp_val) +{ + return -EOPNOTSUPP; +} +static inline int cppc_get_auto_act_window(int cpu, u64 *auto_act_window) +{ + return -EOPNOTSUPP; +} +static inline int cppc_set_auto_act_window(int cpu, u64 auto_act_window) +{ + return -EOPNOTSUPP; +} static inline int cppc_get_auto_sel(int cpu, bool *enable) { return -EOPNOTSUPP;