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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4206fasm3280221f8f.2.2025.04.18.10.29.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Apr 2025 10:29:14 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v3 01/14] qapi: Rename TargetInfo structure as BinaryTargetInfo Date: Fri, 18 Apr 2025 19:28:55 +0200 Message-ID: <20250418172908.25147-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250418172908.25147-1-philmd@linaro.org> References: <20250418172908.25147-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The QAPI-generated 'TargetInfo' structure name is only used in a single file. We want to heavily use another structure similarly named. Rename the QAPI one, since structure names are not part of the public API. Suggested-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- qapi/machine.json | 12 ++++++------ hw/core/machine-qmp-cmds.c | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/qapi/machine.json b/qapi/machine.json index a6b8795b09e..3246212f048 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -275,15 +275,15 @@ { 'command': 'query-current-machine', 'returns': 'CurrentMachineParams' } ## -# @TargetInfo: +# @BinaryTargetInfo: # -# Information describing the QEMU target. +# Information describing the QEMU binary target. # -# @arch: the target architecture +# @arch: the binary target architecture # # Since: 1.2 ## -{ 'struct': 'TargetInfo', +{ 'struct': 'BinaryTargetInfo', 'data': { 'arch': 'SysEmuTarget' } } ## @@ -291,11 +291,11 @@ # # Return information about the target for this QEMU # -# Returns: TargetInfo +# Returns: BinaryTargetInfo # # Since: 1.2 ## -{ 'command': 'query-target', 'returns': 'TargetInfo' } +{ 'command': 'query-target', 'returns': 'BinaryTargetInfo' } ## # @UuidInfo: diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c index 3130c5cd456..408994b67d7 100644 --- a/hw/core/machine-qmp-cmds.c +++ b/hw/core/machine-qmp-cmds.c @@ -132,9 +132,9 @@ CurrentMachineParams *qmp_query_current_machine(Error **errp) return params; } -TargetInfo *qmp_query_target(Error **errp) +BinaryTargetInfo *qmp_query_target(Error **errp) { - TargetInfo *info = g_malloc0(sizeof(*info)); + BinaryTargetInfo *info = g_malloc0(sizeof(*info)); info->arch = qapi_enum_parse(&SysEmuTarget_lookup, target_name(), -1, &error_abort); From patchwork Fri Apr 18 17:28:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882326 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp916243wrs; Fri, 18 Apr 2025 10:29:49 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXEur9hhwFN8eBYdzemxJBmnh8CbI4jMdM9LU4GKwO4uLG3JmEj9+BXHE9fuT6p2iC0XFw9JQ==@linaro.org X-Google-Smtp-Source: AGHT+IEJE2c0MspqxbwHASgWmAtL76zhxHtsC/Q+OFcZmV0isQ06GtyHyA0gXEbVJ85hgtQFpbYq X-Received: by 2002:a05:620a:bc8:b0:7c9:1335:633e with SMTP id af79cd13be357-7c927f6b658mr531684285a.1.1744997389099; Fri, 18 Apr 2025 10:29:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1744997389; cv=none; d=google.com; s=arc-20240605; b=dPRiol1usFzxmZwBW0bu13BiOX+PwxLfh5fOlNhuCzthbiqVah6oYZPCZ+wfdcyXoI 9Q6tpQjaubCfjzFSaYxOSTJ5Y5TfGlG1jiJqm/VlMyweO9ESvpF0uZDOmDGdcIrNqjOs UMo1ayzlSOk+Bk/oqKPmkRph1zJxfetat9SLW7Sq3P0qAUvxlxcevR20SEdmkh6SggYP RVpdTGPcF+UZGuYx2usj6A/TgYEEWtyNYlPEumhLjFDIU4jl7/I4pCLgXPGSo07hwWt6 Gmv39z3q20mgcQ60w/Wfu51blMHEWnKw/FmKcAyx3IyutEMDQhOOKY5CdRl0khAEgoeE oawQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=eHO81WMTDdR6HpW0S2Vp1ELnicrpI5yyRuKdwopAMDM=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=akme6L2aZklgdIBKPO+l05KqPS/8uIOnesN6Cpa7CTolya2782AJNPtDVQXPa998I7 aHvTuwAqwwRIK4Op68pB8q4VIiwvAwrxDJK1aDQIjSfaLdQX1Zn3JAQqJPiDKzPAIhNr tFkSgy+8K20J772fvX5lT8h6ZiQhboYYd0Ql8LMgI5DzjWrG0MVmBzrm4Dhm9c2UjUmg taWpTZFgmFrQ5JTJlzDqvD0V8oUbSwIFw0vUncFU3p4YesYcHGDV8x9nui80oyngHxPF oGUEDCSorO7oSfTEM8/W/SgF/7TC4u/HRuGkvgoKcx9Ao4EfO+cqDQzkQcwHvgGjklEs +fSg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mqtAv8UX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4332f8sm3275516f8f.40.2025.04.18.10.29.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Apr 2025 10:29:18 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v3 02/14] qemu: Convert target_name() to TargetInfo API Date: Fri, 18 Apr 2025 19:28:56 +0200 Message-ID: <20250418172908.25147-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250418172908.25147-1-philmd@linaro.org> References: <20250418172908.25147-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have target_name() be a target-agnostic method, dispatching to a per-target TargetInfo singleton structure. By default a stub singleton is used. No logical change expected. Inspired-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- meson.build | 3 +++ include/hw/core/cpu.h | 2 -- include/qemu/target_info-impl.h | 23 +++++++++++++++++++++++ include/qemu/target_info.h | 19 +++++++++++++++++++ cpu-target.c | 5 ----- hw/core/machine-qmp-cmds.c | 1 + plugins/loader.c | 2 +- system/vl.c | 2 +- target_info-stub.c | 19 +++++++++++++++++++ target_info.c | 16 ++++++++++++++++ 10 files changed, 83 insertions(+), 9 deletions(-) create mode 100644 include/qemu/target_info-impl.h create mode 100644 include/qemu/target_info.h create mode 100644 target_info-stub.c create mode 100644 target_info.c diff --git a/meson.build b/meson.build index bcb9d39a387..49a050a28a3 100644 --- a/meson.build +++ b/meson.build @@ -3807,6 +3807,9 @@ endif common_ss.add(pagevary) specific_ss.add(files('page-target.c', 'page-vary-target.c')) +common_ss.add(files('target_info.c')) +specific_ss.add(files('target_info-stub.c')) + subdir('backends') subdir('disas') subdir('migration') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5b645df59f5..9d9448341d1 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1115,8 +1115,6 @@ bool cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); void cpu_exec_reset_hold(CPUState *cpu); -const char *target_name(void); - #ifdef COMPILING_PER_TARGET extern const VMStateDescription vmstate_cpu_common; diff --git a/include/qemu/target_info-impl.h b/include/qemu/target_info-impl.h new file mode 100644 index 00000000000..11b92796b28 --- /dev/null +++ b/include/qemu/target_info-impl.h @@ -0,0 +1,23 @@ +/* + * QEMU binary/target API ... + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef QEMU_TARGET_INFO_IMPL_H +#define QEMU_TARGET_INFO_IMPL_H + +#include "qemu/target_info.h" + +typedef struct TargetInfo { + + /* runtime equivalent of TARGET_NAME definition */ + const char *const target_name; + +} TargetInfo; + +const TargetInfo *target_info(void); + +#endif diff --git a/include/qemu/target_info.h b/include/qemu/target_info.h new file mode 100644 index 00000000000..3f6cbbbd300 --- /dev/null +++ b/include/qemu/target_info.h @@ -0,0 +1,19 @@ +/* + * QEMU binary/target API + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef QEMU_TARGET_INFO_H +#define QEMU_TARGET_INFO_H + +/** + * target_name: + * + * Returns: Canonical target name (i.e. "i386"). + */ +const char *target_name(void); + +#endif diff --git a/cpu-target.c b/cpu-target.c index c99d208a7c4..3f82d3ea444 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -165,8 +165,3 @@ bool target_words_bigendian(void) { return TARGET_BIG_ENDIAN; } - -const char *target_name(void) -{ - return TARGET_NAME; -} diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c index 408994b67d7..b317aec234f 100644 --- a/hw/core/machine-qmp-cmds.c +++ b/hw/core/machine-qmp-cmds.c @@ -19,6 +19,7 @@ #include "qapi/qobject-input-visitor.h" #include "qapi/type-helpers.h" #include "qemu/uuid.h" +#include "qemu/target_info.h" #include "qom/qom-qobject.h" #include "system/hostmem.h" #include "system/hw_accel.h" diff --git a/plugins/loader.c b/plugins/loader.c index 7523d554f03..36a4e88d4db 100644 --- a/plugins/loader.c +++ b/plugins/loader.c @@ -29,7 +29,7 @@ #include "qemu/xxhash.h" #include "qemu/plugin.h" #include "qemu/memalign.h" -#include "hw/core/cpu.h" +#include "qemu/target_info.h" #include "exec/tb-flush.h" #include "plugin.h" diff --git a/system/vl.c b/system/vl.c index c17945c4939..d8a0fe713c9 100644 --- a/system/vl.c +++ b/system/vl.c @@ -40,6 +40,7 @@ #include "qemu/help_option.h" #include "qemu/hw-version.h" #include "qemu/uuid.h" +#include "qemu/target_info.h" #include "system/reset.h" #include "system/runstate.h" #include "system/runstate-action.h" @@ -79,7 +80,6 @@ #include "hw/block/block.h" #include "hw/i386/x86.h" #include "hw/i386/pc.h" -#include "hw/core/cpu.h" #include "migration/cpr.h" #include "migration/misc.h" #include "migration/snapshot.h" diff --git a/target_info-stub.c b/target_info-stub.c new file mode 100644 index 00000000000..f15972c5b22 --- /dev/null +++ b/target_info-stub.c @@ -0,0 +1,19 @@ +/* + * QEMU target info stubs + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target_info-impl.h" + +static const TargetInfo target_info_stub = { + .target_name = TARGET_NAME, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_stub; +} diff --git a/target_info.c b/target_info.c new file mode 100644 index 00000000000..48c4a413326 --- /dev/null +++ b/target_info.c @@ -0,0 +1,16 @@ +/* + * QEMU binary/target helpers + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target_info-impl.h" +#include "qemu/target_info.h" + +const char *target_name(void) +{ + return target_info()->target_name; +} From patchwork Fri Apr 18 17:28:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882330 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp916708wrs; Fri, 18 Apr 2025 10:31:01 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWBLvAiSX5Z0cZ8DO9lz0iMAORbiTBo7KfEUE80qTCJ/2NNgT6QNTG74ZrgvOjDD23p97vAuw==@linaro.org X-Google-Smtp-Source: AGHT+IHYXqH9KN9GrRkqwxr4AfzRrtBnJvnOqMSPoVUkFYhCldzVLq1j4+Kmqt7FAGAoRTIEmsp/ X-Received: by 2002:a05:620a:244e:b0:7c7:5afb:5878 with SMTP id af79cd13be357-7c927fb6558mr541669585a.25.1744997461328; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4a4d67sm3338940f8f.94.2025.04.18.10.29.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Apr 2025 10:29:23 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v3 03/14] system/vl: Filter machine list available for a particular target binary Date: Fri, 18 Apr 2025 19:28:57 +0200 Message-ID: <20250418172908.25147-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250418172908.25147-1-philmd@linaro.org> References: <20250418172908.25147-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Binaries can register a QOM type to filter their machines by filling their TargetInfo::machine_typename field. This can be used by example by main() -> machine_help_func() to filter the machines list. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- meson.build | 1 + include/qemu/target_info-impl.h | 3 +++ include/qemu/target_info.h | 8 ++++++++ system/vl.c | 3 ++- target_info-qom.c | 15 +++++++++++++++ target_info-stub.c | 2 ++ target_info.c | 5 +++++ 7 files changed, 36 insertions(+), 1 deletion(-) create mode 100644 target_info-qom.c diff --git a/meson.build b/meson.build index 49a050a28a3..168b07b5887 100644 --- a/meson.build +++ b/meson.build @@ -3808,6 +3808,7 @@ common_ss.add(pagevary) specific_ss.add(files('page-target.c', 'page-vary-target.c')) common_ss.add(files('target_info.c')) +system_ss.add(files('target_info-qom.c')) specific_ss.add(files('target_info-stub.c')) subdir('backends') diff --git a/include/qemu/target_info-impl.h b/include/qemu/target_info-impl.h index 11b92796b28..e3344278a92 100644 --- a/include/qemu/target_info-impl.h +++ b/include/qemu/target_info-impl.h @@ -16,6 +16,9 @@ typedef struct TargetInfo { /* runtime equivalent of TARGET_NAME definition */ const char *const target_name; + /* QOM typename machines for this binary must implement */ + const char *const machine_typename; + } TargetInfo; const TargetInfo *target_info(void); diff --git a/include/qemu/target_info.h b/include/qemu/target_info.h index 3f6cbbbd300..c67b97d66f3 100644 --- a/include/qemu/target_info.h +++ b/include/qemu/target_info.h @@ -16,4 +16,12 @@ */ const char *target_name(void); +/** + * target_machine_typename: + * + * Returns: Name of the QOM interface implemented by machines + * usable on this target binary. + */ +const char *target_machine_typename(void); + #endif diff --git a/system/vl.c b/system/vl.c index d8a0fe713c9..8fb18f82e20 100644 --- a/system/vl.c +++ b/system/vl.c @@ -27,6 +27,7 @@ #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/module.h" +#include "qemu/target_info.h" #include "exec/cpu-common.h" #include "exec/page-vary.h" #include "hw/qdev-properties.h" @@ -1564,7 +1565,7 @@ static void machine_help_func(const QDict *qdict) GSList *el; const char *type = qdict_get_try_str(qdict, "type"); - machines = object_class_get_list(TYPE_MACHINE, false); + machines = object_class_get_list(target_machine_typename(), false); if (type) { ObjectClass *machine_class = OBJECT_CLASS(find_machine(type, machines)); if (machine_class) { diff --git a/target_info-qom.c b/target_info-qom.c new file mode 100644 index 00000000000..a6fd8f1d5a3 --- /dev/null +++ b/target_info-qom.c @@ -0,0 +1,15 @@ +/* + * QEMU binary/target API (QOM types) + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qom/object.h" + +static const TypeInfo target_info_types[] = { +}; + +DEFINE_TYPES(target_info_types) diff --git a/target_info-stub.c b/target_info-stub.c index f15972c5b22..14e6d5e68d2 100644 --- a/target_info-stub.c +++ b/target_info-stub.c @@ -8,9 +8,11 @@ #include "qemu/osdep.h" #include "qemu/target_info-impl.h" +#include "hw/boards.h" static const TargetInfo target_info_stub = { .target_name = TARGET_NAME, + .machine_typename = TYPE_MACHINE, }; const TargetInfo *target_info(void) diff --git a/target_info.c b/target_info.c index 48c4a413326..1de4334ecc5 100644 --- a/target_info.c +++ b/target_info.c @@ -14,3 +14,8 @@ const char *target_name(void) { return target_info()->target_name; } + +const char *target_machine_typename(void) +{ + return target_info()->machine_typename; +} From patchwork Fri Apr 18 17:28:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882328 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp916530wrs; Fri, 18 Apr 2025 10:30:34 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVWJKBXQoZo5TbXY3brokPO3FZIqpCae/FVPSpcoSCNuv5NDlb3V48YtR8kV7mf6SAH84i0HA==@linaro.org X-Google-Smtp-Source: AGHT+IEe5PKi/Ren+LozsflKlhGmyQiKLAisk1XYAKhf6Tyt3ilPVa1Us1K067LzFZLRrWgepHzP X-Received: by 2002:a05:6214:2584:b0:6e5:a0fc:f65d with SMTP id 6a1803df08f44-6f2c26f41ddmr71164906d6.10.1744997434675; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d6e0364sm28822525e9.38.2025.04.18.10.29.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Apr 2025 10:29:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v3 04/14] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces Date: Fri, 18 Apr 2025 19:28:58 +0200 Message-ID: <20250418172908.25147-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250418172908.25147-1-philmd@linaro.org> References: <20250418172908.25147-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Define the TYPE_TARGET_ARM_MACHINE and TYPE_TARGET_AARCH64_MACHINE QOM interface names to allow machines to implement them. Register these interfaces in common code in target_info-qom.c used by all binaries because QOM interfaces must be registered before being checked (see next commit with the 'none' machine). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/hw/arm/machines-qom.h | 18 ++++++++++++++++++ target_info-qom.c | 9 +++++++++ 2 files changed, 27 insertions(+) create mode 100644 include/hw/arm/machines-qom.h diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h new file mode 100644 index 00000000000..a17225f5f92 --- /dev/null +++ b/include/hw/arm/machines-qom.h @@ -0,0 +1,18 @@ +/* + * QOM type definitions for ARM / Aarch64 machines + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_MACHINES_QOM_H +#define HW_ARM_MACHINES_QOM_H + +#define TYPE_TARGET_ARM_MACHINE \ + "target-info-arm-machine" + +#define TYPE_TARGET_AARCH64_MACHINE \ + "target-info-aarch64-machine" + +#endif diff --git a/target_info-qom.c b/target_info-qom.c index a6fd8f1d5a3..7fd58d24818 100644 --- a/target_info-qom.c +++ b/target_info-qom.c @@ -8,8 +8,17 @@ #include "qemu/osdep.h" #include "qom/object.h" +#include "hw/arm/machines-qom.h" static const TypeInfo target_info_types[] = { + { + .name = TYPE_TARGET_ARM_MACHINE, + .parent = TYPE_INTERFACE, + }, + { + .name = TYPE_TARGET_AARCH64_MACHINE, + .parent = TYPE_INTERFACE, + }, }; DEFINE_TYPES(target_info_types) From patchwork Fri Apr 18 17:28:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882336 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp918253wrs; Fri, 18 Apr 2025 10:35:05 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWyVCtBvUC3q2Lrt8PPmj0OLq32sEc772onutz1c3wKq+tkwi+AYfESwlrPkiLVsydWVKIPzQ==@linaro.org X-Google-Smtp-Source: AGHT+IHD6VlkmtQ2hIjRs8qXdH4UpWIilBgHq24Vy1CSDOvlCe8JPp47kmaukxRzLct3peaWYmVa X-Received: by 2002:a05:622a:388:b0:476:b02d:2b4a with SMTP id d75a77b69052e-47aec3ecad1mr66858811cf.27.1744997705165; Fri, 18 Apr 2025 10:35:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1744997705; cv=none; d=google.com; s=arc-20240605; b=kmyRfQdxqRcqgwbSxh8ISsWTimgkIT2OhEw3HOz00H9sAJ9xmwF7tyNvSzNUPlYzvu gkiq9T0Yfu0L6H+JtDKdQ8TT26pRVKg0+nhNrdCD2+vmVBgbNFwsXPqbpsMfhe3SQ30Y qav8ZtHveHa2m7I5pITQMsaSSehhiG4wf08sXkvlqKVLpiUqgg4raVOukarpk24zq71z zYtB+DB8N+SzZ2a/2IQmlhCNOhxupJ9amMcrc1DujphlzQBNVNH3mlxtrKhneiD0uyZt 49XS41TGpysdCbS3kSFfzTnHMcsOU39WGxBbhaBd0Pzgpulfv4/sMD/l+iJTJYWYp5mP Oq3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0t/uXKNyhujXRRINXuzOy18EBWQDT1SxjDNFS8yAx2w=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=C9bdxBwRfftu7OUW8oDBaPp63WhQztIxpVgtl8chr5uRg2QhZj81chqEwNpH8RNfi7 Sj9ghSHEf8rRpM1nRoQR82TnDMJK7ojlmRTCVsQxeAs12I2nIBJnEhxHrpeuD0wf8r0v aNaRPFzCLOhQRuSTN7bd4BKJfXYH/+Wey7/NsHIO86Fg+a5bI9gmZ0sJVSqpOXAraU7q 3Sv2Nmual7319KlTsRs1FiRKaRnySoo2GEWiTEEpvFuzGy82Ti5OExxm0vt+YeUleMhR wHzAbbCER4riTKDol+8DwlERnK9PtLwJq/fSv7tSOvtrshnhNX2ulhQTHVD3XHzyh8fA 8M6w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=No4NEv1I; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d5aced5sm29098395e9.16.2025.04.18.10.29.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Apr 2025 10:29:32 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v3 05/14] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine Date: Fri, 18 Apr 2025 19:28:59 +0200 Message-ID: <20250418172908.25147-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250418172908.25147-1-philmd@linaro.org> References: <20250418172908.25147-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When we'll start to use target_machine_typename() to filter machines for the ARM/Aarch64 binaries, the 'none' machine will be filtered out. Register the proper interfaces to keep it available. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/core/null-machine.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c index 1ccaf652eb4..dd56d7cb7e5 100644 --- a/hw/core/null-machine.c +++ b/hw/core/null-machine.c @@ -16,6 +16,7 @@ #include "hw/boards.h" #include "system/address-spaces.h" #include "hw/core/cpu.h" +#include "hw/arm/machines-qom.h" static void machine_none_init(MachineState *mch) { @@ -62,6 +63,11 @@ static const TypeInfo null_machine_types[] = { .name = MACHINE_TYPE_NAME("none"), .parent = TYPE_MACHINE, .class_init = null_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; From patchwork Fri Apr 18 17:29:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882329 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp916528wrs; Fri, 18 Apr 2025 10:30:34 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWiXDNaVa6gqmY7wz8JpteZiXiDGd+OZXcC4IWdwt0TQv6/hIV7WXen5CUMMTbAN60lrQNjjw==@linaro.org X-Google-Smtp-Source: AGHT+IGzmP1gzhTjPKk9VAM6ZraK1byLQXJZbfzFK+Uh3rsoocbXZ9ff1lPVUNeKKH3bmaYXCCuJ X-Received: by 2002:ad4:5ba2:0:b0:6e6:683c:1e32 with SMTP id 6a1803df08f44-6f2c45155camr79282976d6.8.1744997434451; Fri, 18 Apr 2025 10:30:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1744997434; cv=none; d=google.com; s=arc-20240605; b=X9VtN0lVkTSYa3TjgkQF46DjCoM8okUi7cEBobVAAJAG4jBgJRVr59u3sE+X9ZiTFi 0sdT3sISUP5UbeotDH7mvVv79znkHmLafskv6Df/khgD0ma0mkA3Y9TWC7GAIVm+fwpZ YlgtOKrnW1lIhaLJ426pLnIOj6InarmFlGqW/kP4Nks4liIRoLhuadySgBQjk+ppv3f1 EX/fsOOcg6bsOvYETLoE1k9mhtwhodnDbZu++Eu53ZMzvf3TJl47itt8opmohVuRhnml CxRrd00Qr92NWYZh9Q2NM4VIBtWwhDo9howxpZ9/hiJfptfdQjMkKD7kIYuuq/HEYk64 jKMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wt4qKJ0+qbDFtV5JdYISjNhnPLXIq7IfaAn6j0T22LM=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=AXBdXgXqweLdSF5uonUoGh9D89wUkrysANFwh6+T0xH7Rgm1fxG6E+j4d4E7ICOkek 5qqc4MRRa2zIjgejmiR6xelaB84vIPGS6423tgJDoMOHcLtiJxtH/FIOhG3LBWhjmFVw 15/99/j7Z8yqwvpvre30micLuAyHvFuc1xFSGC4iFD3da0QWchFYiG11zQIhyVaUDUQO ruetCjVO7avhA0V1FHWbFMo/22qhXk5+1AX6MFHCVVf12AlLj7B+9/m1aFJxSl9jvgQS XiJUGLPJlPZqlfzvZpamzPiJzmvs3s/YQSJuPnpzRoLB9BxJxkT16xCc7i2OhGYeXggy YW0g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PQjdQNTv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d5bbd7fsm29288815e9.21.2025.04.18.10.29.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Apr 2025 10:29:37 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v3 06/14] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Date: Fri, 18 Apr 2025 19:29:00 +0200 Message-ID: <20250418172908.25147-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250418172908.25147-1-philmd@linaro.org> References: <20250418172908.25147-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since the qemu-system-aarch64 binary is able to run all machines indistinctly, simply register the TYPE_TARGET_AARCH64_MACHINE interface for all existing machines under the hw/arm/ directory. Very few machines are restricted to the qemu-system-aarch64 binary: $ git grep TARGET_AARCH64 hw/arm/meson.build hw/arm/meson.build:31:arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c')) hw/arm/meson.build:50:arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c')) $ git grep -W AARCH64 hw/arm/Kconfig hw/arm/Kconfig=185=config SBSA_REF hw/arm/Kconfig-186- bool hw/arm/Kconfig-187- default y hw/arm/Kconfig:188: depends on TCG && AARCH64 -- hw/arm/Kconfig=413=config XLNX_ZYNQMP_ARM hw/arm/Kconfig-414- bool hw/arm/Kconfig-415- default y if PIXMAN hw/arm/Kconfig:416: depends on TCG && AARCH64 -- hw/arm/Kconfig=435=config XLNX_VERSAL hw/arm/Kconfig-436- bool hw/arm/Kconfig-437- default y hw/arm/Kconfig:438: depends on TCG && AARCH64 -- hw/arm/Kconfig=475=config NPCM8XX hw/arm/Kconfig-476- bool hw/arm/Kconfig-477- default y hw/arm/Kconfig:478: depends on TCG && AARCH64 -- hw/arm/Kconfig=605=config FSL_IMX8MP_EVK hw/arm/Kconfig-606- bool hw/arm/Kconfig-607- default y hw/arm/Kconfig:608: depends on TCG && AARCH64 $ git grep -wW TARGET_AARCH64 hw/arm | fgrep -4 MACHINE_TYPE_NAME ... hw/arm/aspeed.c:1939:#ifdef TARGET_AARCH64 hw/arm/aspeed.c-1940- }, { hw/arm/aspeed.c-1941- .name = MACHINE_TYPE_NAME("ast2700a0-evb"), hw/arm/aspeed.c-1949- .name = MACHINE_TYPE_NAME("ast2700a1-evb"), hw/arm/raspi.c:420:#ifdef TARGET_AARCH64 hw/arm/raspi.c-421- }, { hw/arm/raspi.c-422- .name = MACHINE_TYPE_NAME("raspi3ap"), hw/arm/raspi.c-429- }, { hw/arm/raspi.c-430- .name = MACHINE_TYPE_NAME("raspi3b"), This can be verified as: $ diff -u0 <(qemu-system-arm -M help) <(qemu-system-aarch64 -M help) @@ -5,3 +4,0 @@ -ast2700-evb Aspeed AST2700 A0 EVB (Cortex-A35) (alias of ast2700a0-evb) -ast2700a0-evb Aspeed AST2700 A0 EVB (Cortex-A35) -ast2700a1-evb Aspeed AST2700 A1 EVB (Cortex-A35) @@ -22 +18,0 @@ -imx8mp-evk NXP i.MX 8M Plus EVK Board @@ -49 +44,0 @@ -npcm845-evb Nuvoton NPCM845 Evaluation Board (Cortex-A35) @@ -63,3 +57,0 @@ -raspi3ap Raspberry Pi 3A+ (revision 1.0) -raspi3b Raspberry Pi 3B (revision 1.2) -raspi4b Raspberry Pi 4B (revision 1.5) @@ -72 +63,0 @@ -sbsa-ref QEMU 'SBSA Reference' ARM Virtual Machine @@ -116,2 +106,0 @@ -xlnx-versal-virt Xilinx Versal Virtual development board -xlnx-zcu102 Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on the value of smp Register the TYPE_TARGET_ARM_MACHINE interface for all the machines not listed previously. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Pierrick Bouvier --- hw/arm/aspeed.c | 109 +++++++++++++++++++++++++++++++++++++ hw/arm/b-l475e-iot01a.c | 6 ++ hw/arm/bananapi_m2u.c | 6 ++ hw/arm/bcm2836.c | 1 + hw/arm/collie.c | 6 ++ hw/arm/cubieboard.c | 6 ++ hw/arm/digic_boards.c | 6 ++ hw/arm/exynos4_boards.c | 11 ++++ hw/arm/fby35.c | 6 ++ hw/arm/highbank.c | 11 ++++ hw/arm/imx25_pdk.c | 6 ++ hw/arm/imx8mp-evk.c | 5 ++ hw/arm/integratorcp.c | 6 ++ hw/arm/kzm.c | 6 ++ hw/arm/mcimx6ul-evk.c | 6 ++ hw/arm/mcimx7d-sabre.c | 6 ++ hw/arm/microbit.c | 6 ++ hw/arm/mps2-tz.c | 21 +++++++ hw/arm/mps2.c | 21 +++++++ hw/arm/mps3r.c | 6 ++ hw/arm/msf2-som.c | 6 ++ hw/arm/musca.c | 11 ++++ hw/arm/musicpal.c | 6 ++ hw/arm/netduino2.c | 6 ++ hw/arm/netduinoplus2.c | 6 ++ hw/arm/npcm7xx_boards.c | 26 +++++++++ hw/arm/npcm8xx_boards.c | 5 ++ hw/arm/olimex-stm32-h405.c | 6 ++ hw/arm/omap_sx1.c | 11 ++++ hw/arm/orangepi.c | 6 ++ hw/arm/raspi.c | 24 ++++++++ hw/arm/raspi4b.c | 5 ++ hw/arm/realview.c | 21 +++++++ hw/arm/sabrelite.c | 6 ++ hw/arm/sbsa-ref.c | 5 ++ hw/arm/stellaris.c | 11 ++++ hw/arm/stm32vldiscovery.c | 6 ++ hw/arm/versatilepb.c | 11 ++++ hw/arm/vexpress.c | 11 ++++ hw/arm/virt.c | 6 ++ hw/arm/xilinx_zynq.c | 6 ++ hw/arm/xlnx-versal-virt.c | 5 ++ hw/arm/xlnx-zcu102.c | 5 ++ 43 files changed, 468 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 82f42582fa3..ce4d49a9f59 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -15,6 +15,7 @@ #include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" #include "hw/arm/aspeed_eeprom.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "hw/i2c/i2c_mux_pca954x.h" #include "hw/i2c/smbus_eeprom.h" @@ -1760,91 +1761,199 @@ static const TypeInfo aspeed_machine_types[] = { .name = MACHINE_TYPE_NAME("palmetto-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_palmetto_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_supermicrox11_bmc_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("ast2500-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2500_evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("romulus-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_romulus_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("sonorapass-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_sonorapass_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("witherspoon-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_witherspoon_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("ast2600-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2600_evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_yosemitev2_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("tiogapass-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_tiogapass_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("g220a-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_g220a_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_qcom_firework_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_fp5280g2_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_quanta_q71l_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("rainier-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_rainier_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("fuji-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_fuji_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("bletchley-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_bletchley_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("fby35-bmc"), .parent = MACHINE_TYPE_NAME("ast2600-evb"), .class_init = aspeed_machine_fby35_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("ast1030-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, #ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("ast2700a0-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2700a0_evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("ast2700a1-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2700a1_evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, #endif }, { .name = TYPE_ASPEED_MACHINE, diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index c9a5209216c..7af7db3dbb3 100644 --- a/hw/arm/b-l475e-iot01a.c +++ b/hw/arm/b-l475e-iot01a.c @@ -29,6 +29,7 @@ #include "qemu/error-report.h" #include "hw/arm/boot.h" #include "hw/core/split-irq.h" +#include "hw/arm/machines-qom.h" #include "hw/arm/stm32l4x5_soc.h" #include "hw/gpio/stm32l4x5_gpio.h" #include "hw/display/dm163.h" @@ -131,6 +132,11 @@ static const TypeInfo bl475e_machine_type[] = { .parent = TYPE_MACHINE, .instance_size = sizeof(Bl475eMachineState), .class_init = bl475e_machine_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, } }; diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c index 724ee4b05e5..5104a45390b 100644 --- a/hw/arm/bananapi_m2u.c +++ b/hw/arm/bananapi_m2u.c @@ -27,6 +27,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-r40.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" static struct arm_boot_info bpim2u_binfo; @@ -150,6 +151,11 @@ static const TypeInfo bananapi_machine_types[] = { .name = MACHINE_TYPE_NAME("bpim2u"), .parent = TYPE_MACHINE, .class_init = bpim2u_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 95e16806fa1..f60489983ba 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -14,6 +14,7 @@ #include "qemu/module.h" #include "hw/arm/bcm2836.h" #include "hw/arm/raspi_platform.h" +#include "hw/arm/machines-qom.h" #include "hw/sysbus.h" #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" diff --git a/hw/arm/collie.c b/hw/arm/collie.c index e83aee58c6b..458ed53f0f6 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -15,6 +15,7 @@ #include "hw/boards.h" #include "strongarm.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "system/address-spaces.h" #include "qom/object.h" @@ -86,6 +87,11 @@ static const TypeInfo collie_machine_typeinfo = { .parent = TYPE_MACHINE, .class_init = collie_machine_class_init, .instance_size = sizeof(CollieMachineState), + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void collie_machine_register_types(void) diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index 36062ac7037..00656169b72 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -22,6 +22,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-a10.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/i2c/i2c.h" static struct arm_boot_info cubieboard_binfo = { @@ -131,6 +132,11 @@ static const TypeInfo cubieboard_machine_types[] = { .name = MACHINE_TYPE_NAME("cubieboard"), .parent = TYPE_MACHINE, .class_init = cubieboard_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index 3c0cc6e4370..7b9fbb5524b 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -29,6 +29,7 @@ #include "hw/boards.h" #include "qemu/error-report.h" #include "hw/arm/digic.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "hw/loader.h" #include "system/qtest.h" @@ -152,6 +153,11 @@ static const TypeInfo digic_machine_types[] = { .name = MACHINE_TYPE_NAME("canon-a1100"), .parent = TYPE_MACHINE, .class_init = digic_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index 2d8f2d73265..71601a0d6f0 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -28,6 +28,7 @@ #include "hw/sysbus.h" #include "net/net.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "system/address-spaces.h" #include "hw/arm/exynos4210.h" #include "hw/net/lan9118.h" @@ -172,6 +173,11 @@ static const TypeInfo nuri_type = { .name = MACHINE_TYPE_NAME("nuri"), .parent = TYPE_MACHINE, .class_init = nuri_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void smdkc210_class_init(ObjectClass *oc, void *data) @@ -192,6 +198,11 @@ static const TypeInfo smdkc210_type = { .name = MACHINE_TYPE_NAME("smdkc210"), .parent = TYPE_MACHINE, .class_init = smdkc210_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void exynos4_machines_init(void) diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c index 6d3663f14a1..84b65844b34 100644 --- a/hw/arm/fby35.c +++ b/hw/arm/fby35.c @@ -14,6 +14,7 @@ #include "hw/qdev-clock.h" #include "hw/arm/aspeed_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #define TYPE_FBY35 MACHINE_TYPE_NAME("fby35") OBJECT_DECLARE_SIMPLE_TYPE(Fby35State, FBY35); @@ -187,6 +188,11 @@ static const TypeInfo fby35_types[] = { .class_init = fby35_class_init, .instance_size = sizeof(Fby35State), .instance_init = fby35_instance_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 0f3c207d548..d26346ea8ad 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -23,6 +23,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/loader.h" #include "net/net.h" #include "system/runstate.h" @@ -363,6 +364,11 @@ static const TypeInfo highbank_type = { .name = MACHINE_TYPE_NAME("highbank"), .parent = TYPE_MACHINE, .class_init = highbank_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void midway_class_init(ObjectClass *oc, void *data) @@ -387,6 +393,11 @@ static const TypeInfo midway_type = { .name = MACHINE_TYPE_NAME("midway"), .parent = TYPE_MACHINE, .class_init = midway_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void calxeda_machines_init(void) diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index a90def7f1a2..86f0855c929 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -28,6 +28,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/fsl-imx25.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "qemu/error-report.h" #include "system/qtest.h" @@ -157,6 +158,11 @@ static const TypeInfo imx25_machine_types[] = { .name = MACHINE_TYPE_NAME("imx25-pdk"), .parent = TYPE_MACHINE, .class_init = imx25_pdk_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c index c7d87d99230..44f704b9bd3 100644 --- a/hw/arm/imx8mp-evk.c +++ b/hw/arm/imx8mp-evk.c @@ -10,6 +10,7 @@ #include "system/address-spaces.h" #include "hw/arm/boot.h" #include "hw/arm/fsl-imx8mp.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "system/qtest.h" @@ -79,6 +80,10 @@ static const TypeInfo imx8_machine_types[] = { .name = MACHINE_TYPE_NAME("imx8mp-evk"), .parent = TYPE_MACHINE, .class_init = imx8mp_evk_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index f95916b517d..efe1075ecc0 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -13,6 +13,7 @@ #include "migration/vmstate.h" #include "hw/boards.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/misc/arm_integrator_debug.h" #include "hw/net/smc91c111.h" #include "net/net.h" @@ -760,6 +761,11 @@ static const TypeInfo integratorcp_machine_types[] = { .name = MACHINE_TYPE_NAME("integratorcp"), .parent = TYPE_MACHINE, .class_init = integratorcp_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index b56cabe9f94..02ece3c0139 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -17,6 +17,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx31.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "qemu/error-report.h" #include "system/address-spaces.h" @@ -146,6 +147,11 @@ static const TypeInfo kzm_machine_types[] = { .name = MACHINE_TYPE_NAME("kzm"), .parent = TYPE_MACHINE, .class_init = kzm_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index d947836d2be..ea636fa2e7c 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -14,6 +14,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx6ul.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" @@ -84,6 +85,11 @@ static const TypeInfo imx6_machine_types[] = { .name = MACHINE_TYPE_NAME("mcimx6ul-evk"), .parent = TYPE_MACHINE, .class_init = mcimx6ul_evk_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index f5dc9c211dd..b236a6587eb 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -16,6 +16,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx7.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" @@ -84,6 +85,11 @@ static const TypeInfo imx7_machine_types[] = { .name = MACHINE_TYPE_NAME("mcimx7d-sabre"), .parent = TYPE_MACHINE, .class_init = mcimx7d_sabre_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index ade363daaa4..d34b1c675e5 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -12,6 +12,7 @@ #include "qapi/error.h" #include "hw/boards.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "system/system.h" #include "system/address-spaces.h" @@ -74,6 +75,11 @@ static const TypeInfo microbit_info = { .parent = TYPE_MACHINE, .instance_size = sizeof(MicrobitMachineState), .class_init = microbit_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void microbit_machine_init(void) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index b0633a5a69e..12512477977 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -52,6 +52,7 @@ #include "qemu/error-report.h" #include "hw/arm/boot.h" #include "hw/arm/armv7m.h" +#include "hw/arm/machines-qom.h" #include "hw/or-irq.h" #include "hw/boards.h" #include "system/address-spaces.h" @@ -1463,24 +1464,44 @@ static const TypeInfo mps2tz_an505_info = { .name = TYPE_MPS2TZ_AN505_MACHINE, .parent = TYPE_MPS2TZ_MACHINE, .class_init = mps2tz_an505_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps2tz_an521_info = { .name = TYPE_MPS2TZ_AN521_MACHINE, .parent = TYPE_MPS2TZ_MACHINE, .class_init = mps2tz_an521_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps3tz_an524_info = { .name = TYPE_MPS3TZ_AN524_MACHINE, .parent = TYPE_MPS2TZ_MACHINE, .class_init = mps3tz_an524_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps3tz_an547_info = { .name = TYPE_MPS3TZ_AN547_MACHINE, .parent = TYPE_MPS2TZ_MACHINE, .class_init = mps3tz_an547_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void mps2tz_machine_init(void) diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 6958485a668..f39176c0005 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -31,6 +31,7 @@ #include "qemu/error-report.h" #include "hw/arm/boot.h" #include "hw/arm/armv7m.h" +#include "hw/arm/machines-qom.h" #include "hw/or-irq.h" #include "hw/boards.h" #include "system/address-spaces.h" @@ -563,24 +564,44 @@ static const TypeInfo mps2_an385_info = { .name = TYPE_MPS2_AN385_MACHINE, .parent = TYPE_MPS2_MACHINE, .class_init = mps2_an385_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps2_an386_info = { .name = TYPE_MPS2_AN386_MACHINE, .parent = TYPE_MPS2_MACHINE, .class_init = mps2_an386_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps2_an500_info = { .name = TYPE_MPS2_AN500_MACHINE, .parent = TYPE_MPS2_MACHINE, .class_init = mps2_an500_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps2_an511_info = { .name = TYPE_MPS2_AN511_MACHINE, .parent = TYPE_MPS2_MACHINE, .class_init = mps2_an511_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void mps2_machine_init(void) diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c index 4dd1e8a7180..8bcf5a4d69f 100644 --- a/hw/arm/mps3r.c +++ b/hw/arm/mps3r.c @@ -37,6 +37,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/boot.h" #include "hw/arm/bsa.h" +#include "hw/arm/machines-qom.h" #include "hw/char/cmsdk-apb-uart.h" #include "hw/i2c/arm_sbcon_i2c.h" #include "hw/intc/arm_gicv3.h" @@ -634,6 +635,11 @@ static const TypeInfo mps3r_machine_types[] = { .name = TYPE_MPS3R_AN536_MACHINE, .parent = TYPE_MPS3R_MACHINE, .class_init = mps3r_an536_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 6ce47eaa27a..3f7aefc0ba4 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -32,6 +32,7 @@ #include "hw/boards.h" #include "hw/qdev-properties.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/qdev-clock.h" #include "system/address-spaces.h" #include "hw/arm/msf2-soc.h" @@ -114,6 +115,11 @@ static const TypeInfo msf2_machine_types[] = { .name = MACHINE_TYPE_NAME("emcraft-sf2"), .parent = TYPE_MACHINE, .class_init = emcraft_sf2_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/musca.c b/hw/arm/musca.c index a4f43f1992b..608f16f69b2 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -26,6 +26,7 @@ #include "system/system.h" #include "hw/arm/boot.h" #include "hw/arm/armsse.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/char/pl011.h" #include "hw/core/split-irq.h" @@ -657,12 +658,22 @@ static const TypeInfo musca_a_info = { .name = TYPE_MUSCA_A_MACHINE, .parent = TYPE_MUSCA_MACHINE, .class_init = musca_a_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo musca_b1_info = { .name = TYPE_MUSCA_B1_MACHINE, .parent = TYPE_MUSCA_MACHINE, .class_init = musca_b1_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void musca_machine_init(void) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index f7c488cd1d6..e2a65f72095 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -15,6 +15,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "net/net.h" #include "system/system.h" #include "hw/boards.h" @@ -1381,6 +1382,11 @@ static const TypeInfo musicpal_types[] = { .name = MACHINE_TYPE_NAME("musicpal"), .parent = TYPE_MACHINE, .class_init = musicpal_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 52c30055d44..2e615276902 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -30,6 +30,7 @@ #include "qemu/error-report.h" #include "hw/arm/stm32f205_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" /* Main SYSCLK frequency in Hz (120MHz) */ #define SYSCLK_FRQ 120000000ULL @@ -71,6 +72,11 @@ static const TypeInfo netduino_machine_types[] = { .name = MACHINE_TYPE_NAME("netduino2"), .parent = TYPE_MACHINE, .class_init = netduino2_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index 2735d3a0e2b..e12f78599c4 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -30,6 +30,7 @@ #include "qemu/error-report.h" #include "hw/arm/stm32f405_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" /* Main SYSCLK frequency in Hz (168MHz) */ #define SYSCLK_FRQ 168000000ULL @@ -71,6 +72,11 @@ static const TypeInfo netduino_machine_types[] = { .name = MACHINE_TYPE_NAME("netduinoplus2"), .parent = TYPE_MACHINE, .class_init = netduinoplus2_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index eb28b97ad83..4b6d3443d53 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -17,6 +17,7 @@ #include "qemu/osdep.h" #include "hw/arm/npcm7xx.h" +#include "hw/arm/machines-qom.h" #include "hw/core/cpu.h" #include "hw/i2c/i2c_mux_pca954x.h" #include "hw/i2c/smbus_eeprom.h" @@ -549,22 +550,47 @@ static const TypeInfo npcm7xx_machine_types[] = { .name = MACHINE_TYPE_NAME("npcm750-evb"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = npcm750_evb_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("quanta-gsj"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = gsj_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("quanta-gbs-bmc"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = gbs_bmc_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("kudo-bmc"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = kudo_bmc_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("mori-bmc"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = mori_bmc_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c index 3fb8478e72e..919c14dd809 100644 --- a/hw/arm/npcm8xx_boards.c +++ b/hw/arm/npcm8xx_boards.c @@ -19,6 +19,7 @@ #include "chardev/char.h" #include "hw/boards.h" #include "hw/arm/npcm8xx.h" +#include "hw/arm/machines-qom.h" #include "hw/core/cpu.h" #include "hw/loader.h" #include "hw/qdev-core.h" @@ -248,6 +249,10 @@ static const TypeInfo npcm8xx_machine_types[] = { .name = MACHINE_TYPE_NAME("npcm845-evb"), .parent = TYPE_NPCM8XX_MACHINE, .class_init = npcm845_evb_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c index 795218c93cf..f81f4094149 100644 --- a/hw/arm/olimex-stm32-h405.c +++ b/hw/arm/olimex-stm32-h405.c @@ -31,6 +31,7 @@ #include "qemu/error-report.h" #include "hw/arm/stm32f405_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" /* olimex-stm32-h405 implementation is derived from netduinoplus2 */ @@ -77,6 +78,11 @@ static const TypeInfo olimex_stm32_machine_types[] = { .name = MACHINE_TYPE_NAME("olimex-stm32-h405"), .parent = TYPE_MACHINE, .class_init = olimex_stm32_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index aa1e96b3ad7..2537045c1ac 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -32,6 +32,7 @@ #include "hw/arm/omap.h" #include "hw/boards.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "system/qtest.h" #include "system/address-spaces.h" @@ -219,6 +220,11 @@ static const TypeInfo sx1_machine_v2_type = { .name = MACHINE_TYPE_NAME("sx1"), .parent = TYPE_MACHINE, .class_init = sx1_machine_v2_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void sx1_machine_v1_class_init(ObjectClass *oc, void *data) @@ -238,6 +244,11 @@ static const TypeInfo sx1_machine_v1_type = { .name = MACHINE_TYPE_NAME("sx1-v1"), .parent = TYPE_MACHINE, .class_init = sx1_machine_v1_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void sx1_machine_init(void) diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index 6821033bfd7..4e333d428a2 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -26,6 +26,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-h3.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" static struct arm_boot_info orangepi_binfo; @@ -130,6 +131,11 @@ static const TypeInfo orangepi_machine_types[] = { .name = MACHINE_TYPE_NAME("orangepi-pc"), .parent = TYPE_MACHINE, .class_init = orangepi_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index dce35ca11aa..69cccdbb6b1 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -25,6 +25,7 @@ #include "hw/boards.h" #include "hw/loader.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "qom/object.h" #define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common") @@ -394,23 +395,46 @@ static const TypeInfo raspi_machine_types[] = { .name = MACHINE_TYPE_NAME("raspi0"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi0_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("raspi1ap"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi1ap_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("raspi2b"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi2b_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, #ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("raspi3ap"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi3ap_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("raspi3b"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi3b_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, #endif }, { .name = TYPE_RASPI_MACHINE, diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c index f6de103a3e1..8fda6d3b0ca 100644 --- a/hw/arm/raspi4b.c +++ b/hw/arm/raspi4b.c @@ -11,6 +11,7 @@ #include "qemu/cutils.h" #include "qapi/error.h" #include "qapi/visitor.h" +#include "hw/arm/machines-qom.h" #include "hw/arm/raspi_platform.h" #include "hw/display/bcm2835_fb.h" #include "hw/registerfields.h" @@ -127,6 +128,10 @@ static const TypeInfo raspi4b_machine_type = { .parent = TYPE_RASPI_BASE_MACHINE, .instance_size = sizeof(Raspi4bMachineState), .class_init = raspi4b_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void raspi4b_machine_register_type(void) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 008eeaf049a..aed864bcd4f 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -13,6 +13,7 @@ #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" +#include "hw/arm/machines-qom.h" #include "hw/core/split-irq.h" #include "hw/net/lan9118.h" #include "hw/net/smc91c111.h" @@ -431,6 +432,11 @@ static const TypeInfo realview_eb_type = { .name = MACHINE_TYPE_NAME("realview-eb"), .parent = TYPE_MACHINE, .class_init = realview_eb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data) @@ -452,6 +458,11 @@ static const TypeInfo realview_eb_mpcore_type = { .name = MACHINE_TYPE_NAME("realview-eb-mpcore"), .parent = TYPE_MACHINE, .class_init = realview_eb_mpcore_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void realview_pb_a8_class_init(ObjectClass *oc, void *data) @@ -471,6 +482,11 @@ static const TypeInfo realview_pb_a8_type = { .name = MACHINE_TYPE_NAME("realview-pb-a8"), .parent = TYPE_MACHINE, .class_init = realview_pb_a8_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void realview_pbx_a9_class_init(ObjectClass *oc, void *data) @@ -491,6 +507,11 @@ static const TypeInfo realview_pbx_a9_type = { .name = MACHINE_TYPE_NAME("realview-pbx-a9"), .parent = TYPE_MACHINE, .class_init = realview_pbx_a9_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void realview_machine_init(void) diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index ea59ba301e7..bc472dcad2c 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -14,6 +14,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx6.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" @@ -120,6 +121,11 @@ static const TypeInfo sabrelite_machine_types[] = { .name = MACHINE_TYPE_NAME("sabrelite"), .parent = TYPE_MACHINE, .class_init = sabrelite_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index aa09d7a0917..6584097fc25 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -34,6 +34,7 @@ #include "hw/arm/bsa.h" #include "hw/arm/fdt.h" #include "hw/arm/smmuv3.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "hw/boards.h" #include "hw/ide/ide-bus.h" @@ -920,6 +921,10 @@ static const TypeInfo sbsa_ref_info = { .instance_init = sbsa_ref_instance_init, .class_init = sbsa_ref_class_init, .instance_size = sizeof(SBSAMachineState), + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void sbsa_ref_machine_init(void) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index cbe914c93e9..8dc68c145c1 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -15,6 +15,7 @@ #include "hw/sd/sd.h" #include "hw/ssi/ssi.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "qemu/timer.h" #include "hw/i2c/i2c.h" #include "net/net.h" @@ -1427,6 +1428,11 @@ static const TypeInfo lm3s811evb_type = { .name = MACHINE_TYPE_NAME("lm3s811evb"), .parent = TYPE_MACHINE, .class_init = lm3s811evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; /* @@ -1448,6 +1454,11 @@ static const TypeInfo lm3s6965evb_type = { .name = MACHINE_TYPE_NAME("lm3s6965evb"), .parent = TYPE_MACHINE, .class_init = lm3s6965evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void stellaris_machine_init(void) diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 3a9728ca719..b7eb948bc2d 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -31,6 +31,7 @@ #include "qemu/error-report.h" #include "hw/arm/stm32f100_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" /* stm32vldiscovery implementation is derived from netduinoplus2 */ @@ -74,6 +75,11 @@ static const TypeInfo stm32vldiscovery_machine_types[] = { .name = MACHINE_TYPE_NAME("stm32vldiscovery"), .parent = TYPE_MACHINE, .class_init = stm32vldiscovery_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 35766445fa4..defc4d7d170 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -12,6 +12,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/net/smc91c111.h" #include "net/net.h" #include "system/system.h" @@ -431,6 +432,11 @@ static const TypeInfo versatilepb_type = { .name = MACHINE_TYPE_NAME("versatilepb"), .parent = TYPE_MACHINE, .class_init = versatilepb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void versatileab_class_init(ObjectClass *oc, void *data) @@ -452,6 +458,11 @@ static const TypeInfo versatileab_type = { .name = MACHINE_TYPE_NAME("versatileab"), .parent = TYPE_MACHINE, .class_init = versatileab_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void versatile_machine_init(void) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 76c6107766c..38b203b52da 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -27,6 +27,7 @@ #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" +#include "hw/arm/machines-qom.h" #include "hw/net/lan9118.h" #include "hw/i2c/i2c.h" #include "net/net.h" @@ -850,6 +851,11 @@ static const TypeInfo vexpress_a9_info = { .parent = TYPE_VEXPRESS_MACHINE, .class_init = vexpress_a9_class_init, .instance_init = vexpress_a9_instance_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo vexpress_a15_info = { @@ -857,6 +863,11 @@ static const TypeInfo vexpress_a15_info = { .parent = TYPE_VEXPRESS_MACHINE, .class_init = vexpress_a15_class_init, .instance_init = vexpress_a15_instance_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void vexpress_machine_init(void) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a96452f17a4..a3c9ffe29eb 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -37,6 +37,7 @@ #include "hw/arm/boot.h" #include "hw/arm/primecell.h" #include "hw/arm/virt.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "hw/vfio/vfio-calxeda-xgmac.h" #include "hw/vfio/vfio-amd-xgbe.h" @@ -123,6 +124,11 @@ static void arm_virt_compat_set(MachineClass *mc) .name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \ .parent = TYPE_VIRT_MACHINE, \ .class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \ + .interfaces = (InterfaceInfo[]) { \ + { TYPE_TARGET_ARM_MACHINE }, \ + { TYPE_TARGET_AARCH64_MACHINE }, \ + { }, \ + }, \ }; \ static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \ { \ diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index b8916665ed6..433907093fa 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -20,6 +20,7 @@ #include "qapi/error.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "net/net.h" #include "system/system.h" #include "hw/boards.h" @@ -480,6 +481,11 @@ static const TypeInfo zynq_machine_type = { .parent = TYPE_MACHINE, .class_init = zynq_machine_class_init, .instance_size = sizeof(ZynqMachineState), + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void zynq_machine_register_types(void) diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 0c6f0359e3d..cb7466f7250 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -20,6 +20,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/xlnx-versal.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "target/arm/multiprocessing.h" #include "qom/object.h" @@ -833,6 +834,10 @@ static const TypeInfo versal_virt_machine_init_typeinfo = { .instance_init = versal_virt_machine_instance_init, .instance_size = sizeof(VersalVirt), .instance_finalize = versal_virt_machine_finalize, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void versal_virt_machine_init_register_types(void) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 4fdb153e4d8..f730dbbd908 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -19,6 +19,7 @@ #include "qapi/error.h" #include "hw/arm/xlnx-zynqmp.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "qemu/error-report.h" #include "qemu/log.h" @@ -303,6 +304,10 @@ static const TypeInfo xlnx_zcu102_machine_init_typeinfo = { .class_init = xlnx_zcu102_machine_class_init, .instance_init = xlnx_zcu102_machine_instance_init, .instance_size = sizeof(XlnxZCU102), + .interfaces = (InterfaceInfo[]) { + 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d5bbc81sm28942445e9.19.2025.04.18.10.29.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Apr 2025 10:29:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v3 07/14] meson: Prepare to accept per-binary TargetInfo structure implementation Date: Fri, 18 Apr 2025 19:29:01 +0200 Message-ID: <20250418172908.25147-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250418172908.25147-1-philmd@linaro.org> References: <20250418172908.25147-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If a file defining the binary TargetInfo structure is available, link with it. Otherwise keep using the stub. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- meson.build | 9 ++++++++- configs/targets/meson.build | 3 +++ 2 files changed, 11 insertions(+), 1 deletion(-) create mode 100644 configs/targets/meson.build diff --git a/meson.build b/meson.build index 168b07b5887..b0d4a9fcd36 100644 --- a/meson.build +++ b/meson.build @@ -3216,6 +3216,7 @@ config_devices_mak_list = [] config_devices_h = {} config_target_h = {} config_target_mak = {} +config_target_info = {} disassemblers = { 'alpha' : ['CONFIG_ALPHA_DIS'], @@ -3809,9 +3810,9 @@ specific_ss.add(files('page-target.c', 'page-vary-target.c')) common_ss.add(files('target_info.c')) system_ss.add(files('target_info-qom.c')) -specific_ss.add(files('target_info-stub.c')) subdir('backends') +subdir('configs/targets') subdir('disas') subdir('migration') subdir('monitor') @@ -4272,6 +4273,12 @@ foreach target : target_dirs arch_srcs += gdbstub_xml endif + if target in config_target_info + arch_srcs += config_target_info[target] + else + arch_srcs += files('target_info-stub.c') + endif + t = target_arch[target_base_arch].apply(config_target, strict: false) arch_srcs += t.sources() arch_deps += t.dependencies() diff --git a/configs/targets/meson.build b/configs/targets/meson.build new file mode 100644 index 00000000000..e9a5f7b078e --- /dev/null +++ b/configs/targets/meson.build @@ -0,0 +1,3 @@ +foreach target : ['arm-softmmu', 'aarch64-softmmu'] + config_target_info += {target : files(target + '.c')} +endforeach From patchwork Fri Apr 18 17:29:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882337 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp918513wrs; Fri, 18 Apr 2025 10:35:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXt4U5pt6RidD+e5n278tRisYTEbjWEAKwN3LXw+hgY+7t804SmDk9rUTag7viaWQPXU/N3OQ==@linaro.org X-Google-Smtp-Source: AGHT+IF5FMAmmVrxAp90I/CTl0ZFgF3IF/QYnabRklYTSzafwcAcfAzSE0uzyDyZoLPiukYAsXmV X-Received: by 2002:a05:620a:1aa4:b0:7c5:65ab:5001 with SMTP id af79cd13be357-7c92800eb4dmr466364485a.39.1744997745670; Fri, 18 Apr 2025 10:35:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1744997745; cv=none; d=google.com; s=arc-20240605; b=TDouNv3tguZChJOiYPoU94GFX9VlyppZUmZubIRs/sc23/bsX1gSQ8MKZWvsc+4cIt 7V+k1WWQpUTGEmur8xyQJjZmd5FFmAcWO5+9oG4zrwkr1uI2x6nOfcy3En1s/iHA40wr 1Bi9smfbZZVpDxDj25pJ+U24LSJdX8C4Ii5m1PMQJsEakEfHkIFEv7FzYbUhTil2Ru6/ UP5i7QEek8TsjoX2+1SLmuPmy2CtQajifSvsmAyRjpuJ6vjBBTZKf7m9ORVO7zLYGuex x0h43giDQZyfuwKazvm9oroZTtRUKSvWHetAd4MXfPGCiDktitAqNi81mQgV22HlGTiE ohOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6OTzCxiNHZ+8AXW9TgiIPvSY8FhsX6JUubS418pDWIg=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=RdfE3yn19riA+kKK8BGvQ9CVwUMaQiMHjFfqaK+2hAY54aSSpXYgMde6EwikjoClE3 2sQklV+Cy9yX+CRtAuvfvyxhenqaGZAbjba/LezOUt4topiVTHaM+zLHPjmANWlmFj1X 47HAcbRgAxR8xhrC8vUbNPDZHUWW9I91ba2Ie9OplE35XZs4Vlhm+apI1+KrQcNNt9by JTulrXUxzjkdNX/MVnPgpUuqGhqPsKPkxQt+ZmmzCQ4Bf3H1KDdW4cH9XyNm0vSAksE2 rGnuPmcSOFIkXgp4QBguBGV4o+vDmSbOX2WrgZ2UsqbtsdM7hP9/jPgQXDUf72bP5b0f DBBg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XlmYDhMo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4a4d67sm3339815f8f.94.2025.04.18.10.29.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Apr 2025 10:29:46 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v3 08/14] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) Date: Fri, 18 Apr 2025 19:29:02 +0200 Message-ID: <20250418172908.25147-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250418172908.25147-1-philmd@linaro.org> References: <20250418172908.25147-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Implement the TargetInfo structure for qemu-system-arm and qemu-system-aarch64 binaries. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- configs/targets/aarch64-softmmu.c | 22 ++++++++++++++++++++++ configs/targets/arm-softmmu.c | 22 ++++++++++++++++++++++ 2 files changed, 44 insertions(+) create mode 100644 configs/targets/aarch64-softmmu.c create mode 100644 configs/targets/arm-softmmu.c diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c new file mode 100644 index 00000000000..03f48bad326 --- /dev/null +++ b/configs/targets/aarch64-softmmu.c @@ -0,0 +1,22 @@ +/* + * QEMU binary/target API (qemu-system-aarch64) + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target_info-impl.h" +#include "hw/arm/machines-qom.h" +#include "target/arm/cpu-qom.h" + +static const TargetInfo target_info_aarch64_system = { + .target_name = "aarch64", + .machine_typename = TYPE_TARGET_AARCH64_MACHINE, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_aarch64_system; +} diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c new file mode 100644 index 00000000000..07285f7f3b3 --- /dev/null +++ b/configs/targets/arm-softmmu.c @@ -0,0 +1,22 @@ +/* + * QEMU binary/target API (qemu-system-arm) + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target_info-impl.h" +#include "hw/arm/machines-qom.h" +#include "target/arm/cpu-qom.h" + +static const TargetInfo target_info_arm_system = { + .target_name = "arm", + .machine_typename = TYPE_TARGET_ARM_MACHINE, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_arm_system; +} From patchwork Fri Apr 18 17:29:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882333 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp917020wrs; Fri, 18 Apr 2025 10:31:42 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV/qv/a5ph8vPsAZJBSykiuWX+ShSSRlSbKSqIiPCCfe31EAKON7guNb4DiA8mC+6uZpUYdIA==@linaro.org X-Google-Smtp-Source: AGHT+IH7hI/UVI7lTR+G386JWkAVNiZEQmae8W59q+H8P7Zho5B4qtVwSXLv6N+8o18neDwuypOU X-Received: by 2002:a05:620a:444e:b0:7c5:5859:1b81 with SMTP id af79cd13be357-7c9280633bamr567978685a.57.1744997502116; Fri, 18 Apr 2025 10:31:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1744997502; cv=none; d=google.com; s=arc-20240605; b=ZWTwQBAs7wmlFUPiuOan2M6zWnyPR3kH/HKd6h0ZSh88BLVHmaJvrr0J1g3fM84NWT JIZIlS1Hnmcx9gRLE5seUTlFlvP0UNZP9UUC4CXjnvods93Q1cEOVQ3oU1wqVeME+Lcn MPQx6Lw8qy1IQ3TMlktpcJmocXw2DL0itXpC14qYUyh+18/U5CqwXpf5VrOGE5gSc0r5 LCkavGRaxS8aeXavRh2bGH//r+R9uTkkuVUeZrilco6WkOdi9hlWfd0uyMK2bbz9OVoz 9pSD0p4amsWIiQAqJOiBOPB7aIhQ+CkAZTGJg2T9Df+ZgmzYE2DUNttxGdrVWaEpE1K7 ZcYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MPk7GJ/Q7Awhqe4M7LOu5PgmoZQozcGdMhSTLUXghio=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=RmAWi3OEEE+uSWuO8Xns7io4i2Lp+H1bqukx+Vzgc8v+rpHvve8q45rr+i0GRT60ed 7OtXTiuwwxqUPmfS8Dnj/3/+d2hoprdbWEf63aMEJ0Spbcq7So8zbguxpaVMkf72W9+V wfDoxnABWaiUVOvGzT3mpfJivnxHuwduZ/4d07GFHZNSjTYbdkQwnMjt1zUPZvCobvQx DDj5tZaJCsHdLM/KguwnY4gZkwslqhKNy0Z0NXygA6yNehqJ/vLhRREStBeh8o29k1jH ydpD2J3LPEdM8iRgG0lPuQW7psI9I11o33dlRLqSEzvcVtsxmFAHrP6PdszashrzS0dY F9Tw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="FQEKWm2/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d6e034csm29164575e9.39.2025.04.18.10.29.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Apr 2025 10:29:51 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v3 09/14] hw/arm/aspeed: Build objects once Date: Fri, 18 Apr 2025 19:29:03 +0200 Message-ID: <20250418172908.25147-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250418172908.25147-1-philmd@linaro.org> References: <20250418172908.25147-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now than Aspeed machines can be filtered when running a qemu-system-arm or qemu-system-aarch64 binary, we can remove the TARGET_AARCH64 #ifdef'ry and compile the aspeed.c file once, moving it from arm_ss[] source set to arm_common_ss[]. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/arm/aspeed.c | 6 ------ hw/arm/meson.build | 4 ++-- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index ce4d49a9f59..6de61505a09 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -180,13 +180,11 @@ struct AspeedMachineState { #define AST2600_EVB_HW_STRAP1 0x000000C0 #define AST2600_EVB_HW_STRAP2 0x00000003 -#ifdef TARGET_AARCH64 /* AST2700 evb hardware value */ /* SCU HW Strap1 */ #define AST2700_EVB_HW_STRAP1 0x00000800 /* SCUIO HW Strap1 */ #define AST2700_EVB_HW_STRAP2 0x00000700 -#endif /* Rainier hardware value: (QEMU prototype) */ #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) @@ -1664,7 +1662,6 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); } -#ifdef TARGET_AARCH64 static void ast2700_evb_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc = bmc->soc; @@ -1714,7 +1711,6 @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, void *data) mc->default_ram_size = 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); } -#endif static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, void *data) @@ -1937,7 +1933,6 @@ static const TypeInfo aspeed_machine_types[] = { { TYPE_TARGET_AARCH64_MACHINE }, { }, }, -#ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("ast2700a0-evb"), .parent = TYPE_ASPEED_MACHINE, @@ -1954,7 +1949,6 @@ static const TypeInfo aspeed_machine_types[] = { { TYPE_TARGET_AARCH64_MACHINE }, { }, }, -#endif }, { .name = TYPE_ASPEED_MACHINE, .parent = TYPE_MACHINE, diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 09b1cfe5b57..f76e7fb229f 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -39,15 +39,15 @@ arm_common_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'x arm_common_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c')) -arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( +arm_common_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed.c', 'aspeed_soc_common.c', 'aspeed_ast2400.c', 'aspeed_ast2600.c', 'aspeed_ast10x0.c', + 'aspeed_ast27x0.c', 'aspeed_eeprom.c', 'fby35.c')) -arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c')) arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c')) From patchwork Fri Apr 18 17:29:04 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d5acc82sm29739315e9.11.2025.04.18.10.29.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Apr 2025 10:29:56 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v3 10/14] hw/arm/raspi: Build objects once Date: Fri, 18 Apr 2025 19:29:04 +0200 Message-ID: <20250418172908.25147-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250418172908.25147-1-philmd@linaro.org> References: <20250418172908.25147-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now than Raspi machines can be filtered when running a qemu-system-arm or qemu-system-aarch64 binary, we can remove the TARGET_AARCH64 #ifdef'ry and compile the aspeed.c file once, moving it from arm_ss[] source set to arm_common_ss[]. Note, we expose the TYPE_BCM2837 type to qemu-system-arm, but it is not user-creatable, so not an issue. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/arm/bcm2836.c | 4 ---- hw/arm/raspi.c | 4 ---- hw/arm/meson.build | 8 ++++++-- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index f60489983ba..454ea2208d7 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -196,7 +196,6 @@ static void bcm2836_class_init(ObjectClass *oc, void *data) dc->realize = bcm2836_realize; }; -#ifdef TARGET_AARCH64 static void bcm2837_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -209,7 +208,6 @@ static void bcm2837_class_init(ObjectClass *oc, void *data) bc->clusterid = 0x0; dc->realize = bcm2836_realize; }; -#endif static const TypeInfo bcm283x_types[] = { { @@ -220,12 +218,10 @@ static const TypeInfo bcm283x_types[] = { .name = TYPE_BCM2836, .parent = TYPE_BCM283X, .class_init = bcm2836_class_init, -#ifdef TARGET_AARCH64 }, { .name = TYPE_BCM2837, .parent = TYPE_BCM283X, .class_init = bcm2837_class_init, -#endif }, { .name = TYPE_BCM283X, .parent = TYPE_BCM283X_BASE, diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 69cccdbb6b1..641e231db61 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -368,7 +368,6 @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data) raspi_machine_class_init(mc, rmc->board_rev); }; -#ifdef TARGET_AARCH64 static void raspi3ap_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -388,7 +387,6 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data) rmc->board_rev = 0xa02082; raspi_machine_class_init(mc, rmc->board_rev); }; -#endif /* TARGET_AARCH64 */ static const TypeInfo raspi_machine_types[] = { { @@ -418,7 +416,6 @@ static const TypeInfo raspi_machine_types[] = { { TYPE_TARGET_AARCH64_MACHINE }, { }, }, -#ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("raspi3ap"), .parent = TYPE_RASPI_MACHINE, @@ -435,7 +432,6 @@ static const TypeInfo raspi_machine_types[] = { { TYPE_TARGET_AARCH64_MACHINE }, { }, }, -#endif }, { .name = TYPE_RASPI_MACHINE, .parent = TYPE_RASPI_BASE_MACHINE, diff --git a/hw/arm/meson.build b/hw/arm/meson.build index f76e7fb229f..f52034ff6a2 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -27,8 +27,12 @@ arm_common_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c')) -arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) -arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c')) +arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files( + 'bcm2836.c', + 'bcm2838.c', + 'raspi.c', + 'raspi4b.c', +)) arm_common_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) arm_common_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) arm_common_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) From patchwork Fri Apr 18 17:29:05 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d6e0183sm29554895e9.37.2025.04.18.10.30.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Apr 2025 10:30:01 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v3 11/14] hw/core/machine: Allow dynamic registration of valid CPU types Date: Fri, 18 Apr 2025 19:29:05 +0200 Message-ID: <20250418172908.25147-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250418172908.25147-1-philmd@linaro.org> References: <20250418172908.25147-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add MachineClass::valid_cpu_types_list, a dynamic list of strings. CPU types can be registered with machine_class_add_valid_cpu_type(). Suggested-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé --- include/hw/boards.h | 8 ++++++++ hw/core/machine.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/include/hw/boards.h b/include/hw/boards.h index 02f43ac5d4d..647a29ff04d 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -56,6 +56,13 @@ void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache, bool machine_check_smp_cache(const MachineState *ms, Error **errp); void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t size); +/** + * machine_class_add_valid_cpu_type: Add type to list of valid CPUs + * @mc: Machine class + * @type: CPU type to allow (should be a subtype of TYPE_CPU) + */ +void machine_class_add_valid_cpu_type(MachineClass *mc, const char *type); + /** * machine_class_allow_dynamic_sysbus_dev: Add type to list of valid devices * @mc: Machine class @@ -306,6 +313,7 @@ struct MachineClass { bool ignore_memory_transaction_failures; int numa_mem_align_shift; const char * const *valid_cpu_types; + GList *valid_cpu_types_list; strList *allowed_dynamic_sysbus_devices; bool auto_enable_numa_with_memhp; bool auto_enable_numa_with_memdev; diff --git a/hw/core/machine.c b/hw/core/machine.c index f52a4f2273b..ff27d533b5c 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1538,6 +1538,12 @@ const char *machine_class_default_cpu_type(MachineClass *mc) return mc->default_cpu_type; } +void machine_class_add_valid_cpu_type(MachineClass *mc, const char *type) +{ + mc->valid_cpu_types_list = g_list_prepend(mc->valid_cpu_types_list, + g_strdup(type)); +} + static bool is_cpu_type_supported(const MachineState *machine, Error **errp) { MachineClass *mc = MACHINE_GET_CLASS(machine); @@ -1581,6 +1587,30 @@ static bool is_cpu_type_supported(const MachineState *machine, Error **errp) return false; } } + if (mc->valid_cpu_types_list) { + bool valid = false; + unsigned count = 0; + GList *l; + + for (l = mc->valid_cpu_types_list; !valid && l != NULL; l = l->next) { + valid |= !!object_class_dynamic_cast(oc, l->data); + count++; + } + + if (!valid) { + g_autofree char *requested = cpu_model_from_type(machine->cpu_type); + mc->valid_cpu_types_list = g_list_reverse(mc->valid_cpu_types_list); + error_setg(errp, "Invalid CPU model: %s", requested); + error_append_hint(errp, "The valid models are: "); + for (l = mc->valid_cpu_types_list; l != NULL; l = l->next) { + g_autofree char *model = cpu_model_from_type(l->data); + error_append_hint(errp, "%s%s", model, --count ? ", " : ""); + } + error_append_hint(errp, "\n"); + + return false; + } + } /* Check if CPU type is deprecated and warn if so */ cc = CPU_CLASS(oc); From patchwork Fri Apr 18 17:29:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882331 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp916811wrs; Fri, 18 Apr 2025 10:31:15 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV5RtgvU1UnrgAMfNPxUs3UZGh049JwKk1w7RFINgoA2ZkbO0YUoMVzU7qdzJ4WKnB1o6dl1g==@linaro.org X-Google-Smtp-Source: AGHT+IENS07s9fEs81znr4qFpREk/g8rreqegoF9wLtc+mxZiBx+R0HY0CxbW33nlgW+8ZTY/AEf X-Received: by 2002:a05:6214:5005:b0:6f2:b551:a63 with SMTP id 6a1803df08f44-6f2c450b587mr58865626d6.3.1744997475138; Fri, 18 Apr 2025 10:31:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1744997475; cv=none; d=google.com; s=arc-20240605; b=OG/jcRFao0q5Rrnn2SKUSR65IGSnRcE6XgGIRcVhZ04u6cdc3qU2w7f2OMmg2ONsbL S1srmdJZp26U0EkxxIg/2mAoYWWQ6zHCEcTGdNu06SRaOrE3IcuUV4vditoouOpyHThw opSuJGdPH0Wsclz7FXP1sDpDzZeh70IJMrNtRLuah4lcGl21K9KE8hP2sbUac6uH5k8n j+M6jPH13Me8PPrnW8sAoKqACTXXcQmlHaTHoj5ECjba5ROQ8eKejYjLNvZQr9Yp3y5z 3UrOvrKLAIXWd+1yu6d4/9iF6IblHJrmyRW7nbqQQv2Nld/AK/0cqMMxCMDKFYcIj+d6 UqPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fLlTlwFK7dyLEOdkaOnpCuG5I1s9eWFIuaNy+YiBC94=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=HHYLGNOc8Jec7LvyB0MZMu127FRyUj23DKbNda1f/q5wUplXzbFAb61wk254tLajAm os3lPKwVdcahiFXACl4DSsmFvTU5yQKL6vSLi5iwL+MqGwc7Un2dMO0CRlRY2XqZkeAn f/jFpQqQgCThS3dDMVfQq2Ze0wOz43cs6FY2pF6hYTUvQm4XEuVhHesgfmR4I/GValp3 X5TzTwf2H9vLhwSiiL3Wo7rJ5GTPKuBAKFFNqFaK51QepczF4dVLWVVF3iiP+CpfrKvp ErfYE+h+ChCuBIYENdA22DtlBhM9hx0WS+CdaaM3yEYxqMviCelZtLHAXMWknyBSSaLX 02Ng==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nH8uJ5O8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa433429sm3341407f8f.37.2025.04.18.10.30.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Apr 2025 10:30:06 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v3 12/14] hw/arm/virt: Register valid CPU types dynamically Date: Fri, 18 Apr 2025 19:29:06 +0200 Message-ID: <20250418172908.25147-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250418172908.25147-1-philmd@linaro.org> References: <20250418172908.25147-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 35 ++++++++++++++++------------------- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a3c9ffe29eb..48a0c3588ce 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3134,32 +3134,30 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); - static const char * const valid_cpu_types[] = { + #ifdef CONFIG_TCG - ARM_CPU_TYPE_NAME("cortex-a7"), - ARM_CPU_TYPE_NAME("cortex-a15"), + machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a7")); + machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a15")); #ifdef TARGET_AARCH64 - ARM_CPU_TYPE_NAME("cortex-a35"), - ARM_CPU_TYPE_NAME("cortex-a55"), - ARM_CPU_TYPE_NAME("cortex-a72"), - ARM_CPU_TYPE_NAME("cortex-a76"), - ARM_CPU_TYPE_NAME("cortex-a710"), - ARM_CPU_TYPE_NAME("a64fx"), - ARM_CPU_TYPE_NAME("neoverse-n1"), - ARM_CPU_TYPE_NAME("neoverse-v1"), - ARM_CPU_TYPE_NAME("neoverse-n2"), + machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a35")); + machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a55")); + machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a72")); + machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a76")); + machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a710")); + machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("a64fx")); + machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-n1")); + machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-v1")); + machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-n2")); #endif /* TARGET_AARCH64 */ #endif /* CONFIG_TCG */ #ifdef TARGET_AARCH64 - ARM_CPU_TYPE_NAME("cortex-a53"), - ARM_CPU_TYPE_NAME("cortex-a57"), + machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a53")); + machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a57")); #if defined(CONFIG_KVM) || defined(CONFIG_HVF) - ARM_CPU_TYPE_NAME("host"), + machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("host")); #endif /* CONFIG_KVM || CONFIG_HVF */ #endif /* TARGET_AARCH64 */ - ARM_CPU_TYPE_NAME("max"), - NULL - }; + machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("max")); mc->init = machvirt_init; /* Start with max_cpus set to 512, which is the maximum supported by KVM. @@ -3187,7 +3185,6 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) #else mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); #endif - mc->valid_cpu_types = valid_cpu_types; mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; mc->kvm_type = virt_kvm_type; mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range; From patchwork Fri Apr 18 17:29:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882332 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp916859wrs; Fri, 18 Apr 2025 10:31:21 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVRIQvdjmutXvc7FPfiMA/8RlD0WgivbOkhvylJNEtsTgC5YvdiVCYNCclYZoUsCHsrRZ/31w==@linaro.org X-Google-Smtp-Source: AGHT+IHPM72eTvLv5WTdUZobBg/v7tL5GXGi6f10Z0Xx70P+TMahfTadWfqCX2MFP5F3gC0J4skc X-Received: by 2002:a05:6214:5007:b0:6e8:97d2:9999 with SMTP id 6a1803df08f44-6f2c4656825mr64871996d6.28.1744997480897; Fri, 18 Apr 2025 10:31:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1744997480; cv=none; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa43d22esm3374615f8f.52.2025.04.18.10.30.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Apr 2025 10:30:11 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v3 13/14] qemu/target_info: Add target_aarch64() helper Date: Fri, 18 Apr 2025 19:29:07 +0200 Message-ID: <20250418172908.25147-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250418172908.25147-1-philmd@linaro.org> References: <20250418172908.25147-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a helper to distinct the binary is targetting Aarch64 or not. Start with a dump strcmp() implementation, leaving room for future optimizations. Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/target_info.h | 7 +++++++ target_info.c | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/include/qemu/target_info.h b/include/qemu/target_info.h index c67b97d66f3..9b7575ce632 100644 --- a/include/qemu/target_info.h +++ b/include/qemu/target_info.h @@ -24,4 +24,11 @@ const char *target_name(void); */ const char *target_machine_typename(void); +/** + * target_aarch64: + * + * Returns whether the target architecture is Aarch64. + */ +bool target_aarch64(void); + #endif diff --git a/target_info.c b/target_info.c index 1de4334ecc5..87dd1d51778 100644 --- a/target_info.c +++ b/target_info.c @@ -19,3 +19,8 @@ const char *target_machine_typename(void) { return target_info()->machine_typename; } + +bool target_aarch64(void) +{ + return !strcmp(target_name(), "aarch64"); +} From patchwork Fri Apr 18 17:29:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882338 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp918522wrs; Fri, 18 Apr 2025 10:35:47 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVYy4AXmvD0nzA1Fo1rGECYCvdxpJX2oU02bIxqj35r0ZpxAn11vfHPwUMjRJZ9wI2gJe1Dqg==@linaro.org X-Google-Smtp-Source: AGHT+IG23j6XWlrc7R4wrRjaYEWaPYS7lDJ/QtMTrwj7F0bOhgrqmUH6i6h1bo9+5x6a5Dtlp1IB X-Received: by 2002:a05:620a:199e:b0:7c5:4b6a:d862 with SMTP id af79cd13be357-7c927fb6570mr593213885a.33.1744997747171; Fri, 18 Apr 2025 10:35:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1744997747; cv=none; d=google.com; s=arc-20240605; b=ScKmHlz8RYVV5BTHCj6IWDM3u/JHRa0wOLv4KSZ0oUGAs6vm6z9ClrJxE60QnXZDlI w149HHssQ2ZIPcvscLtXR+MMB4HIbzLV0UPJQT/Mb9v88zPksUSr5rOBV7pltVH9Ju8w FKd+wgjZVpJvBFLzkDyIQCTz3XXLGVwee9RA79VRwLj79bfc3g6eja0nIS2bKC4rsWZN b5Qxxgejcl4K419pkWI1mywT5LbjPCdVNS9e6xMLdM9weDA4xY4jek13WLKKuUmWZD5v YOs4tPGzwkFSj+smvwtjrT4HR2cy6pShp0sDF6FZFPhkrxvtwjnhcxbDJTIap3PLN3pP QLhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GhL1v0cmtQmFme3kTdHNuEhx26pxzpv3A7FOxyh5pOk=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=Cuiww0Bfu5aXQT/kagIvJcwtAG2jj0qskY1O1Rae/+bHB4WhZPsLm2sjld8nkm+c15 6SALmyIu8CO+iw5wAe9Xic4dUfcWylBZfG9Lx1BTVYx1v2a0OS3n4qa+eUdEr5u5TcAq rmcCOyn4i3lF6zvX7B05Njx3/csrZjvfE5UVg4ZDs6Ff2RzSJ5Y2MHP7ozL+DR1o/469 5cBe8ZjARM4WEhsP6Sqa1vsgSQeLcRAYVNS71F0Xc5SAup2WI7pPHVyuPbpyuhduSTJL 1xiei7bXBhvgEsoyH8yBJ3ccbdmefe5j1AWyOF2ZROubTf8cnGl2UhYdMnx9KWErInGq V9Tw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iSJMdVf5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa43ca78sm3293378f8f.47.2025.04.18.10.30.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 18 Apr 2025 10:30:15 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v3 14/14] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Date: Fri, 18 Apr 2025 19:29:08 +0200 Message-ID: <20250418172908.25147-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250418172908.25147-1-philmd@linaro.org> References: <20250418172908.25147-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the target-specific TARGET_AARCH64 definition by a call to the generic target_aarch64() helper. Signed-off-by: Philippe Mathieu-Daudé --- This removes the last TARGET_AARCH64 in hw/arm/. --- hw/arm/virt.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 48a0c3588ce..d5bb9cf0e8f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -32,6 +32,7 @@ #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/option.h" +#include "qemu/target_info.h" #include "monitor/qdev.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" @@ -3138,7 +3139,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) #ifdef CONFIG_TCG machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a7")); machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a15")); -#ifdef TARGET_AARCH64 + if (target_aarch64()) { machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a35")); machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a55")); machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a72")); @@ -3148,15 +3149,15 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-n1")); machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-v1")); machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-n2")); -#endif /* TARGET_AARCH64 */ + } #endif /* CONFIG_TCG */ -#ifdef TARGET_AARCH64 + if (target_aarch64()) { machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a53")); machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a57")); #if defined(CONFIG_KVM) || defined(CONFIG_HVF) machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("host")); #endif /* CONFIG_KVM || CONFIG_HVF */ -#endif /* TARGET_AARCH64 */ + } machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("max")); mc->init = machvirt_init;