From patchwork Mon May 11 18:06:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Honnappa Nagarahalli X-Patchwork-Id: 186485 Delivered-To: patch@linaro.org Received: by 2002:a92:8d81:0:0:0:0:0 with SMTP id w1csp2340565ill; Mon, 11 May 2020 11:07:02 -0700 (PDT) X-Google-Smtp-Source: APiQypLXVNusYU0MCLxwn5DwU1xStMZjeZ33m6aGmdrlxdPloxje3ZG/okITgGoCh8O3SnIXs+6b X-Received: by 2002:a05:6402:1adc:: with SMTP id ba28mr14594793edb.12.1589220422847; Mon, 11 May 2020 11:07:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589220422; cv=none; d=google.com; s=arc-20160816; b=k9cVmnZibs5MEsuApNWBrZninO5NKZ9J57QB0cJb8zgHrAwYZeb1bEPj+Ee2x54CSD yfAZn94Bk86cFAvo7bBoxSXY4D4mu8Q/O6rHx3kS1GHXPxOUiWIpLUqB5Mi3I8PsEC1d nssKcUBE9jvaQnJjmhviVoanHNW1DmSd3EeiZdtfvLgIWIea99dGG/z+LjGV7OKgzBJF kFgXWzmZ1eeCGsjsaCvqpzF5wj9EhVBAPF3fefoycLhtUSs2nKGrDfR9bxzr1x6arMCo /3/l/ZMo1CqyGk/1gcTSlqtbjmY67e9MEw9gSeIZ86dbdmJbDzg0Q7Gc2/MOPczJsAJl tAcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=w08nTVAtz8Tp3MLmmV7ucHU3R83lAsAVeePzir+INU0=; b=F17SsXGPckyrnAH1Ofsyzuk4RI2HUKwLSSmNHKXvgUXGGlxJpwi1id2BadOCnJpNNk KFWMlVcU15haqA7Hs9a3LxNky2fvlb3BAX2A/FvlvJj3wxwxxO/vFENHkd5aAHIAuh8W MLdSRFYMJVe8Cs3rN2mbRMs5OPoy53VXDq7FhA2NAJIhCvnY3PxDRieMLLk/GN7gUahe aIUOUqOW8CPtzhiIBh/mQbdcHq/ldI4mAHvgJrqYWWGmWik9x2qrod4XCrGWT7hwzfWc C+KbGFvZ4O6zA9fWYVPLksy+H+o1qz/LwXmqd3BXoB97M7LKbhetEMiHeuAwM7yP9jxA alSg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id cq1si6431126edb.116.2020.05.11.11.07.02; Mon, 11 May 2020 11:07:02 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5D2821BFC9; Mon, 11 May 2020 20:07:01 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 9E00F1BE99 for ; Mon, 11 May 2020 20:07:00 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1472D30E; Mon, 11 May 2020 11:07:00 -0700 (PDT) Received: from qc2400f-1.austin.arm.com (qc2400f-1.austin.arm.com [10.118.14.48]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F3FF33F305; Mon, 11 May 2020 11:06:59 -0700 (PDT) From: Honnappa Nagarahalli To: dev@dpdk.org, jerinj@marvell.com, hemant.agrawal@nxp.com, ajit.khaparde@broadcom.com, igorch@amazon.com, thomas@monjalon.net, viacheslavo@mellanox.com, arybchenko@solarflare.com, honnappa.nagarahalli@arm.com Cc: ruifeng.wang@arm.com, nd@arm.com Date: Mon, 11 May 2020 13:06:37 -0500 Message-Id: <20200511180637.22200-1-honnappa.nagarahalli@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200410164127.54229-1-gavin.hu@arm.com> References: <20200410164127.54229-1-gavin.hu@arm.com> Subject: [dpdk-dev] [RFC] eal: adjust barriers for IO on Armv8-a X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Change the barrier APIs for IO to reflect that Armv8-a is other-multi-copy atomicity memory model. Armv8-a memory model has been strengthened to require other-multi-copy atomicity. This property requires memory accesses from an observer to become visible to all other observers simultaneously [3]. This means a) A write arriving at an endpoint shared between multiple CPUs is visible to all CPUs b) A write that is visible to all CPUs is also visible to all other observers in the shareability domain This allows for using cheaper DMB instructions in the place of DSB for devices that are visible to all CPUs (i.e. devices that DPDK caters to). Please refer to [1], [2] and [3] for more information. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=22ec71615d824f4f11d38d0e55a88d8956b7e45f [2] https://www.youtube.com/watch?v=i6DayghhA8Q [3] https://www.cl.cam.ac.uk/~pes20/armv8-mca/ Signed-off-by: Honnappa Nagarahalli --- lib/librte_eal/arm/include/rte_atomic_64.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.17.1 Tested-by: Ruifeng Wang diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h b/lib/librte_eal/arm/include/rte_atomic_64.h index 7b7099cdc..e406411bb 100644 --- a/lib/librte_eal/arm/include/rte_atomic_64.h +++ b/lib/librte_eal/arm/include/rte_atomic_64.h @@ -19,11 +19,11 @@ extern "C" { #include #include -#define rte_mb() asm volatile("dsb sy" : : : "memory") +#define rte_mb() asm volatile("dmb osh" : : : "memory") -#define rte_wmb() asm volatile("dsb st" : : : "memory") +#define rte_wmb() asm volatile("dmb oshst" : : : "memory") -#define rte_rmb() asm volatile("dsb ld" : : : "memory") +#define rte_rmb() asm volatile("dmb oshld" : : : "memory") #define rte_smp_mb() asm volatile("dmb ish" : : : "memory") @@ -37,9 +37,9 @@ extern "C" { #define rte_io_rmb() rte_rmb() -#define rte_cio_wmb() asm volatile("dmb oshst" : : : "memory") +#define rte_cio_wmb() rte_wmb() -#define rte_cio_rmb() asm volatile("dmb oshld" : : : "memory") +#define rte_cio_rmb() rte_rmb() /*------------------------ 128 bit atomic operations -------------------------*/