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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931c3sm15429955f8f.77.2025.04.22.07.55.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:55:07 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 01/19] qapi: Rename TargetInfo structure as QemuTargetInfo Date: Tue, 22 Apr 2025 16:54:43 +0200 Message-ID: <20250422145502.70770-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The QAPI-generated 'TargetInfo' structure name is only used in a single file. We want to heavily use another structure similarly named. Rename the QAPI one, since structure names are not part of the public API. Suggested-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson Reviewed-by: Markus Armbruster --- qapi/machine.json | 10 +++++----- hw/core/machine-qmp-cmds.c | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/qapi/machine.json b/qapi/machine.json index a6b8795b09e..6889cba2c75 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -275,15 +275,15 @@ { 'command': 'query-current-machine', 'returns': 'CurrentMachineParams' } ## -# @TargetInfo: +# @QemuTargetInfo: # -# Information describing the QEMU target. +# Information on the target configuration built into the QEMU binary. # # @arch: the target architecture # # Since: 1.2 ## -{ 'struct': 'TargetInfo', +{ 'struct': 'QemuTargetInfo', 'data': { 'arch': 'SysEmuTarget' } } ## @@ -291,11 +291,11 @@ # # Return information about the target for this QEMU # -# Returns: TargetInfo +# Returns: QemuTargetInfo # # Since: 1.2 ## -{ 'command': 'query-target', 'returns': 'TargetInfo' } +{ 'command': 'query-target', 'returns': 'QemuTargetInfo' } ## # @UuidInfo: diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c index 3130c5cd456..0e9ca1b90e2 100644 --- a/hw/core/machine-qmp-cmds.c +++ b/hw/core/machine-qmp-cmds.c @@ -132,9 +132,9 @@ CurrentMachineParams *qmp_query_current_machine(Error **errp) return params; } -TargetInfo *qmp_query_target(Error **errp) +QemuTargetInfo *qmp_query_target(Error **errp) { - TargetInfo *info = g_malloc0(sizeof(*info)); + QemuTargetInfo *info = g_malloc0(sizeof(*info)); info->arch = qapi_enum_parse(&SysEmuTarget_lookup, target_name(), -1, &error_abort); From patchwork Tue Apr 22 14:54:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882986 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2456418wrs; Tue, 22 Apr 2025 07:55:52 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUkWUXCT5jAmNCdV4T3TKcw9J8/Y1SNjeQf2V9H+F+Xexz167he8lo+8gK6vBzh8sunfk2g9g==@linaro.org X-Google-Smtp-Source: AGHT+IFJlrJhu07UU0WVCs4smr7/0rNXPbb9iHEQWPMIQaDVy3qfvZ4FhPhU8qiTmg4Lp8Dh+plj X-Received: by 2002:a05:620a:1aa6:b0:7c5:e3ad:fa19 with SMTP id af79cd13be357-7c927f9a090mr2041081885a.16.1745333752630; Tue, 22 Apr 2025 07:55:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745333752; cv=none; d=google.com; s=arc-20240605; b=lRu2TUpZSJQflwNOAmi9BSf5fRbu7RalDqq3K+gCcc58doVQ52MCkkcTkYV9/J4+o6 z3u5IPZObRopuzk+1AkwBb2/pQkIYbwZTb2acrSvHWYLyz9VZytn+vwhCj+o62D/TtYW hnq6W3BzR0qMPocVKppc/JauDQrEG1TQj5O8CCmANQUzsb+IaEf5rAa96wThkK4SmxSQ GVoXrsGs9nRRmA8CvjB9aT5FVUP68ZaTrXr3CpEInLCMZEmVqcdRH0QFY6VcioNt82ZQ CLSxVEmL8steIVxlvtZiLosS/EPGOEbgxHjgsKVz2VcO8ELwlxLXdLZdbW0hfYMChY53 +Qjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RyJ6wMig2dFnUaLZ2DU4/UiCbn+0wTktCowVmGSdV8Y=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=CG8JylipjVo6E+mRjc0RZcmL9z8UThDXvBs2oJe2GMFpGP1HPr07BIdNUi+QqG5iT1 +L3bxmYbxSxfm+n8mxATQ7gM7rji4m9uuCHomC1OA29T6ABxjN1o7dUvJ9+0UGsWxQqY x+89vuCxNU3hsM6QwnqRG3bznXqNt6qT5yKMnfyxSibjy11ZdxJTcyOHEkW/9N5I/C8B zvSEECZEgL2pmqe+KtGOyxnormr13sY8+wbeZUJoYoWUGGKG2DutSKqtxay4sLjzkooE 0Xoc362m8H5lnNktVxr9Fp8DfUy7Pw37FPsC8uK+/dP+sOtCtSufHZUmNBSEjL5SeYT9 f0/w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q7I7UhlQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4a4be2sm15260364f8f.83.2025.04.22.07.55.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:55:12 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 02/19] qemu: Convert target_name() to TargetInfo API Date: Tue, 22 Apr 2025 16:54:44 +0200 Message-ID: <20250422145502.70770-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have target_name() be a target-agnostic method, dispatching to a per-target TargetInfo singleton structure. By default a stub singleton is used. No logical change expected. Inspired-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- MAINTAINERS | 7 +++++++ meson.build | 3 +++ include/hw/core/cpu.h | 2 -- include/qemu/target-info-impl.h | 28 ++++++++++++++++++++++++++++ include/qemu/target-info.h | 19 +++++++++++++++++++ cpu-target.c | 5 ----- hw/core/machine-qmp-cmds.c | 1 + plugins/loader.c | 2 +- system/vl.c | 2 +- target-info-stub.c | 19 +++++++++++++++++++ target-info.c | 16 ++++++++++++++++ 11 files changed, 95 insertions(+), 9 deletions(-) create mode 100644 include/qemu/target-info-impl.h create mode 100644 include/qemu/target-info.h create mode 100644 target-info-stub.c create mode 100644 target-info.c diff --git a/MAINTAINERS b/MAINTAINERS index c7083ab1d93..a055f67b5fc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1913,6 +1913,13 @@ F: tests/functional/test_empty_cpu_model.py F: tests/unit/test-smp-parse.c T: git https://gitlab.com/ehabkost/qemu.git machine-next +TargetInfo API +M: Pierrick Bouvier +M: Philippe Mathieu-Daudé +S: Supported +F: include/qemu/target-info*.h +F: target-info*.c + Xtensa Machines --------------- sim diff --git a/meson.build b/meson.build index bcb9d39a387..09b16e2f7ae 100644 --- a/meson.build +++ b/meson.build @@ -3807,6 +3807,9 @@ endif common_ss.add(pagevary) specific_ss.add(files('page-target.c', 'page-vary-target.c')) +common_ss.add(files('target-info.c')) +specific_ss.add(files('target-info-stub.c')) + subdir('backends') subdir('disas') subdir('migration') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5b645df59f5..9d9448341d1 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1115,8 +1115,6 @@ bool cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); void cpu_exec_reset_hold(CPUState *cpu); -const char *target_name(void); - #ifdef COMPILING_PER_TARGET extern const VMStateDescription vmstate_cpu_common; diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h new file mode 100644 index 00000000000..c276b84ceca --- /dev/null +++ b/include/qemu/target-info-impl.h @@ -0,0 +1,28 @@ +/* + * QEMU TargetInfo structure definition + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef QEMU_TARGET_INFO_IMPL_H +#define QEMU_TARGET_INFO_IMPL_H + +#include "qemu/target-info.h" + +typedef struct TargetInfo { + + /* runtime equivalent of TARGET_NAME definition */ + const char *const target_name; + +} TargetInfo; + +/** + * target_info: + * + * Returns: The TargetInfo structure definition for this target binary. + */ +const TargetInfo *target_info(void); + +#endif diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h new file mode 100644 index 00000000000..1007dc9a5e4 --- /dev/null +++ b/include/qemu/target-info.h @@ -0,0 +1,19 @@ +/* + * QEMU target info API + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef QEMU_TARGET_INFO_H +#define QEMU_TARGET_INFO_H + +/** + * target_name: + * + * Returns: Canonical target name (i.e. "i386"). + */ +const char *target_name(void); + +#endif diff --git a/cpu-target.c b/cpu-target.c index c99d208a7c4..3f82d3ea444 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -165,8 +165,3 @@ bool target_words_bigendian(void) { return TARGET_BIG_ENDIAN; } - -const char *target_name(void) -{ - return TARGET_NAME; -} diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c index 0e9ca1b90e2..529ce8dd9a0 100644 --- a/hw/core/machine-qmp-cmds.c +++ b/hw/core/machine-qmp-cmds.c @@ -19,6 +19,7 @@ #include "qapi/qobject-input-visitor.h" #include "qapi/type-helpers.h" #include "qemu/uuid.h" +#include "qemu/target-info.h" #include "qom/qom-qobject.h" #include "system/hostmem.h" #include "system/hw_accel.h" diff --git a/plugins/loader.c b/plugins/loader.c index 7523d554f03..ccde83414d6 100644 --- a/plugins/loader.c +++ b/plugins/loader.c @@ -29,7 +29,7 @@ #include "qemu/xxhash.h" #include "qemu/plugin.h" #include "qemu/memalign.h" -#include "hw/core/cpu.h" +#include "qemu/target-info.h" #include "exec/tb-flush.h" #include "plugin.h" diff --git a/system/vl.c b/system/vl.c index c17945c4939..cdf6eb9ee49 100644 --- a/system/vl.c +++ b/system/vl.c @@ -40,6 +40,7 @@ #include "qemu/help_option.h" #include "qemu/hw-version.h" #include "qemu/uuid.h" +#include "qemu/target-info.h" #include "system/reset.h" #include "system/runstate.h" #include "system/runstate-action.h" @@ -79,7 +80,6 @@ #include "hw/block/block.h" #include "hw/i386/x86.h" #include "hw/i386/pc.h" -#include "hw/core/cpu.h" #include "migration/cpr.h" #include "migration/misc.h" #include "migration/snapshot.h" diff --git a/target-info-stub.c b/target-info-stub.c new file mode 100644 index 00000000000..076b9254dd0 --- /dev/null +++ b/target-info-stub.c @@ -0,0 +1,19 @@ +/* + * QEMU target info stubs + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" + +static const TargetInfo target_info_stub = { + .target_name = TARGET_NAME, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_stub; +} diff --git a/target-info.c b/target-info.c new file mode 100644 index 00000000000..84b18931e7e --- /dev/null +++ b/target-info.c @@ -0,0 +1,16 @@ +/* + * QEMU target info helpers + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info.h" +#include "qemu/target-info-impl.h" + +const char *target_name(void) +{ + return target_info()->target_name; +} From patchwork Tue Apr 22 14:54:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882988 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2456698wrs; Tue, 22 Apr 2025 07:56:37 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUl27MNosRlzPfri1QmQaxpJqcpMRDtxaJboo0ksvzzps4YdpIk0wG31yhUpAYfA/+FFVu8ig==@linaro.org X-Google-Smtp-Source: AGHT+IGHoumNl4eKt2ZpBCP4WW5t6Heur2hCydVejV88uZ4R/zqTlwkN/HWnJanScPiPlfavKb4X X-Received: by 2002:a05:620a:2a11:b0:7c5:602f:51fc with SMTP id af79cd13be357-7c9280119a9mr2441638385a.44.1745333797400; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4408d19ffe8sm10525865e9.3.2025.04.22.07.55.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:55:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 03/19] system/vl: Filter machine list available for a particular target binary Date: Tue, 22 Apr 2025 16:54:45 +0200 Message-ID: <20250422145502.70770-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Binaries can register a QOM type to filter their machines by filling their TargetInfo::machine_typename field. This can be used by example by main() -> machine_help_func() to filter the machines list. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- meson.build | 1 + include/qemu/target-info-impl.h | 3 +++ include/qemu/target-info.h | 8 ++++++++ system/vl.c | 3 ++- target-info-qom.c | 15 +++++++++++++++ target-info-stub.c | 2 ++ target-info.c | 5 +++++ 7 files changed, 36 insertions(+), 1 deletion(-) create mode 100644 target-info-qom.c diff --git a/meson.build b/meson.build index 09b16e2f7ae..a1109b6db3f 100644 --- a/meson.build +++ b/meson.build @@ -3808,6 +3808,7 @@ common_ss.add(pagevary) specific_ss.add(files('page-target.c', 'page-vary-target.c')) common_ss.add(files('target-info.c')) +system_ss.add(files('target-info-qom.c')) specific_ss.add(files('target-info-stub.c')) subdir('backends') diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h index c276b84ceca..4ef54c5136a 100644 --- a/include/qemu/target-info-impl.h +++ b/include/qemu/target-info-impl.h @@ -16,6 +16,9 @@ typedef struct TargetInfo { /* runtime equivalent of TARGET_NAME definition */ const char *const target_name; + /* QOM typename machines for this binary must implement */ + const char *const machine_typename; + } TargetInfo; /** diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 1007dc9a5e4..0224b35b166 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -16,4 +16,12 @@ */ const char *target_name(void); +/** + * target_machine_typename: + * + * Returns: Name of the QOM interface implemented by machines + * usable on this target binary. + */ +const char *target_machine_typename(void); + #endif diff --git a/system/vl.c b/system/vl.c index cdf6eb9ee49..e8706a9ce87 100644 --- a/system/vl.c +++ b/system/vl.c @@ -27,6 +27,7 @@ #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/module.h" +#include "qemu/target-info.h" #include "exec/cpu-common.h" #include "exec/page-vary.h" #include "hw/qdev-properties.h" @@ -1564,7 +1565,7 @@ static void machine_help_func(const QDict *qdict) GSList *el; const char *type = qdict_get_try_str(qdict, "type"); - machines = object_class_get_list(TYPE_MACHINE, false); + machines = object_class_get_list(target_machine_typename(), false); if (type) { ObjectClass *machine_class = OBJECT_CLASS(find_machine(type, machines)); if (machine_class) { diff --git a/target-info-qom.c b/target-info-qom.c new file mode 100644 index 00000000000..a6fd8f1d5a3 --- /dev/null +++ b/target-info-qom.c @@ -0,0 +1,15 @@ +/* + * QEMU binary/target API (QOM types) + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qom/object.h" + +static const TypeInfo target_info_types[] = { +}; + +DEFINE_TYPES(target_info_types) diff --git a/target-info-stub.c b/target-info-stub.c index 076b9254dd0..218e5898e7f 100644 --- a/target-info-stub.c +++ b/target-info-stub.c @@ -8,9 +8,11 @@ #include "qemu/osdep.h" #include "qemu/target-info-impl.h" +#include "hw/boards.h" static const TargetInfo target_info_stub = { .target_name = TARGET_NAME, + .machine_typename = TYPE_MACHINE, }; const TargetInfo *target_info(void) diff --git a/target-info.c b/target-info.c index 84b18931e7e..0042769e3a2 100644 --- a/target-info.c +++ b/target-info.c @@ -14,3 +14,8 @@ const char *target_name(void) { return target_info()->target_name; } + +const char *target_machine_typename(void) +{ + return target_info()->machine_typename; +} From patchwork Tue Apr 22 14:54:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883002 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2457795wrs; Tue, 22 Apr 2025 07:59:10 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVf3nASOfkfHzylNF9N2AT+bssG9nrav1vO8MXE2fYa/Y/x/HUmAH2F5IfIInIliT8RCNWTqg==@linaro.org X-Google-Smtp-Source: AGHT+IH4+IoCA+1f6TRDYky4/6f7Try7Vf3Hn67mnnfD98AVMLkTYjHKFlCjPxnRH+97ZjDr6MMR X-Received: by 2002:ac8:5fc5:0:b0:476:5fd5:4df8 with SMTP id d75a77b69052e-47aec4c36f6mr203449741cf.45.1745333950157; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa43ce6bsm15633259f8f.55.2025.04.22.07.55.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:55:22 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 04/19] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces Date: Tue, 22 Apr 2025 16:54:46 +0200 Message-ID: <20250422145502.70770-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Define the TYPE_TARGET_ARM_MACHINE and TYPE_TARGET_AARCH64_MACHINE QOM interface names to allow machines to implement them. Register these interfaces in common code in target_info-qom.c used by all binaries because QOM interfaces must be registered before being checked (see next commit with the 'none' machine). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/hw/arm/machines-qom.h | 18 ++++++++++++++++++ target-info-qom.c | 9 +++++++++ 2 files changed, 27 insertions(+) create mode 100644 include/hw/arm/machines-qom.h diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h new file mode 100644 index 00000000000..a17225f5f92 --- /dev/null +++ b/include/hw/arm/machines-qom.h @@ -0,0 +1,18 @@ +/* + * QOM type definitions for ARM / Aarch64 machines + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_MACHINES_QOM_H +#define HW_ARM_MACHINES_QOM_H + +#define TYPE_TARGET_ARM_MACHINE \ + "target-info-arm-machine" + +#define TYPE_TARGET_AARCH64_MACHINE \ + "target-info-aarch64-machine" + +#endif diff --git a/target-info-qom.c b/target-info-qom.c index a6fd8f1d5a3..7fd58d24818 100644 --- a/target-info-qom.c +++ b/target-info-qom.c @@ -8,8 +8,17 @@ #include "qemu/osdep.h" #include "qom/object.h" +#include "hw/arm/machines-qom.h" static const TypeInfo target_info_types[] = { + { + .name = TYPE_TARGET_ARM_MACHINE, + .parent = TYPE_INTERFACE, + }, + { + .name = TYPE_TARGET_AARCH64_MACHINE, + .parent = TYPE_INTERFACE, + }, }; DEFINE_TYPES(target_info_types) From patchwork Tue Apr 22 14:54:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882985 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2456417wrs; Tue, 22 Apr 2025 07:55:52 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUHa8N6BGln3BEBhgFcdgbTCERsNcyu//a7Zk1QnplEEPBg+F1IA3aFUch7UPO7yVmQ+BLjJA==@linaro.org X-Google-Smtp-Source: AGHT+IFOwVXivdNPZd73Jy8zxJk+gneT3yf7KGO9y5zilMZP62QuvlkwWa+tyZKxI1Er8WlwPSha X-Received: by 2002:a05:622a:1354:b0:478:f69b:ac9 with SMTP id d75a77b69052e-47aec480b64mr254174581cf.11.1745333752591; Tue, 22 Apr 2025 07:55:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745333752; cv=none; d=google.com; s=arc-20240605; b=fqVmT5KbLXS5p/sFW2BOqN9upeuGQ94AIWY0lNQMUuxCtfHUNtpn3lxa6af0HMxSy7 qaR7AEPazNKltV9bVULe9ZFhP0mMcmaZwEp+9URVGBDZ0hXUSCV+N04gp/9s66D2ZXjp aXit5WsRL7ZZ3/k4l17QHqj/UyNw7RM7HX0Dtw/gwOJusNvCMWeQ/D32+jRTyL24GLHs J0W8DZFYdvYTotUlXU9FSjdUEYDnw6BQDnhMsDKhYRdAwbeo7EizSISyUZvPBu/iMpQS T4EOb++gSPUqur2EovsEpK3oFSYW8lApVhzkHk+Nc+CdOTNtR68jBCVPvx1b/E2o9Pwp PpTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1cjOcSs5mbhxyNi9CGbhSoHxduGzG92ImG84oID1+1U=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=Vk1BIWOgyoTx9elxHutbkjNLD//zNZM1XqKsQyp8RRts+ErEZLBX3Ag823SwqqP/tA NAR30gFGJ1SWUbkuisagvN6vBil0M5BuzxBQ0iUQdSZaKnds0MNf57+mg8tvyPS4HXqM rDU+mtGY9RzCTTfBJNwElEanCIlHxWj47J8TAHhLk0TWPhjD6AP+ZCX9cnufAQbUWaLj /QN2CcfXzgeexPO3+E9K7dnucfakarpFWHYPRxs2QjZLzmZ/itbeCyeCKLG1pCP75mn8 h0AsvEnMXT4fi89DwNTaJQQOM2BQvtD1pFe7ok7/UraXGBLpuIx3+4fUOieK7AJJhiXg eo0A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Mp/7mUk/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4a49b5sm15482164f8f.86.2025.04.22.07.55.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:55:27 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 05/19] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine Date: Tue, 22 Apr 2025 16:54:47 +0200 Message-ID: <20250422145502.70770-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When we'll start to use target_machine_typename() to filter machines for the ARM/Aarch64 binaries, the 'none' machine will be filtered out. Register the proper interfaces to keep it available. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/core/null-machine.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c index 1ccaf652eb4..dd56d7cb7e5 100644 --- a/hw/core/null-machine.c +++ b/hw/core/null-machine.c @@ -16,6 +16,7 @@ #include "hw/boards.h" #include "system/address-spaces.h" #include "hw/core/cpu.h" +#include "hw/arm/machines-qom.h" static void machine_none_init(MachineState *mch) { @@ -62,6 +63,11 @@ static const TypeInfo null_machine_types[] = { .name = MACHINE_TYPE_NAME("none"), .parent = TYPE_MACHINE, .class_init = null_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; From patchwork Tue Apr 22 14:54:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882992 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2456814wrs; Tue, 22 Apr 2025 07:56:56 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVjoxmTZlor1/xg7uh9If4e9KRLIAk1cpqTj99OKshNcmU6xA0+BeNfuHur2w9UsxxojyQPPw==@linaro.org X-Google-Smtp-Source: AGHT+IHCXvufMGRRD3oaCGna4/KTPnNLDdiJe249zBQlTQrMoT4ipNAMMo16OZDS9yRsozZwjFyo X-Received: by 2002:a05:620a:4045:b0:7c5:fa85:1ac3 with SMTP id af79cd13be357-7c928018a04mr2548698585a.45.1745333816516; Tue, 22 Apr 2025 07:56:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745333816; cv=none; d=google.com; s=arc-20240605; b=EO30Wcwoo0esDSaKeLlREjK1NiapuuyFI25DLdqczYHmahkh5vf5OQt0GYl9A95+QT 33UOmNlaQ/L6YxAeiT0IeY/97RDrdH33pqYqskWdBSw7b4M3VKtSymK64avuFVe5SoMc iFZrEXG4LqSwGNSkBnSLIVAW5bUcZcXFiLoJJmTAwObdsi4IA/x2Jf62COI4iHIWqI93 lo5W/lMudmfiJBxfoehnEEWD6VM/2ESWPBa6xP6ymEtVdAQqiXUaUZ6qAf43oF5CLg3L UE0Fl3pzERqrygViBZCWf1+aaXoY3Phm5Zi1CTWKUiX/1SLTvrlGD96Paa4zXgBOakvj A75A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wt4qKJ0+qbDFtV5JdYISjNhnPLXIq7IfaAn6j0T22LM=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=DemKaFQsXJ1m041/Vkg/hUGOzUl4ezildmpFLUGEE724qG48p/9rgUalJaRoGPctZC Fzoyc6luVSW8AtH+XvykCg/zTAuAuBaSq1mBFjGWpjCTkwffiUBuQuZdUvJbZoMxKfA8 HdEGrglM0CdA9chsmNECvjvq/zyrduSZFkTQU0LHivhTTOD6GEjCRBuavYNi1JP+70aL rKTCmV/byhI3TkoIkfREKzc0uscR5GkzSeRcLeMSaJyQfwDXRJmB8VtIKUekoAd2gDEl cIDocP8baWjgwagU1PidryEeGLgOl5e+3omTJ2rvBa/z1EHDxc0IKdCcoRoa9CiJi126 uHkg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EAUiC5Gq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d5acc9esm180567865e9.13.2025.04.22.07.55.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:55:31 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 06/19] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Date: Tue, 22 Apr 2025 16:54:48 +0200 Message-ID: <20250422145502.70770-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since the qemu-system-aarch64 binary is able to run all machines indistinctly, simply register the TYPE_TARGET_AARCH64_MACHINE interface for all existing machines under the hw/arm/ directory. Very few machines are restricted to the qemu-system-aarch64 binary: $ git grep TARGET_AARCH64 hw/arm/meson.build hw/arm/meson.build:31:arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c')) hw/arm/meson.build:50:arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c')) $ git grep -W AARCH64 hw/arm/Kconfig hw/arm/Kconfig=185=config SBSA_REF hw/arm/Kconfig-186- bool hw/arm/Kconfig-187- default y hw/arm/Kconfig:188: depends on TCG && AARCH64 -- hw/arm/Kconfig=413=config XLNX_ZYNQMP_ARM hw/arm/Kconfig-414- bool hw/arm/Kconfig-415- default y if PIXMAN hw/arm/Kconfig:416: depends on TCG && AARCH64 -- hw/arm/Kconfig=435=config XLNX_VERSAL hw/arm/Kconfig-436- bool hw/arm/Kconfig-437- default y hw/arm/Kconfig:438: depends on TCG && AARCH64 -- hw/arm/Kconfig=475=config NPCM8XX hw/arm/Kconfig-476- bool hw/arm/Kconfig-477- default y hw/arm/Kconfig:478: depends on TCG && AARCH64 -- hw/arm/Kconfig=605=config FSL_IMX8MP_EVK hw/arm/Kconfig-606- bool hw/arm/Kconfig-607- default y hw/arm/Kconfig:608: depends on TCG && AARCH64 $ git grep -wW TARGET_AARCH64 hw/arm | fgrep -4 MACHINE_TYPE_NAME ... hw/arm/aspeed.c:1939:#ifdef TARGET_AARCH64 hw/arm/aspeed.c-1940- }, { hw/arm/aspeed.c-1941- .name = MACHINE_TYPE_NAME("ast2700a0-evb"), hw/arm/aspeed.c-1949- .name = MACHINE_TYPE_NAME("ast2700a1-evb"), hw/arm/raspi.c:420:#ifdef TARGET_AARCH64 hw/arm/raspi.c-421- }, { hw/arm/raspi.c-422- .name = MACHINE_TYPE_NAME("raspi3ap"), hw/arm/raspi.c-429- }, { hw/arm/raspi.c-430- .name = MACHINE_TYPE_NAME("raspi3b"), This can be verified as: $ diff -u0 <(qemu-system-arm -M help) <(qemu-system-aarch64 -M help) @@ -5,3 +4,0 @@ -ast2700-evb Aspeed AST2700 A0 EVB (Cortex-A35) (alias of ast2700a0-evb) -ast2700a0-evb Aspeed AST2700 A0 EVB (Cortex-A35) -ast2700a1-evb Aspeed AST2700 A1 EVB (Cortex-A35) @@ -22 +18,0 @@ -imx8mp-evk NXP i.MX 8M Plus EVK Board @@ -49 +44,0 @@ -npcm845-evb Nuvoton NPCM845 Evaluation Board (Cortex-A35) @@ -63,3 +57,0 @@ -raspi3ap Raspberry Pi 3A+ (revision 1.0) -raspi3b Raspberry Pi 3B (revision 1.2) -raspi4b Raspberry Pi 4B (revision 1.5) @@ -72 +63,0 @@ -sbsa-ref QEMU 'SBSA Reference' ARM Virtual Machine @@ -116,2 +106,0 @@ -xlnx-versal-virt Xilinx Versal Virtual development board -xlnx-zcu102 Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on the value of smp Register the TYPE_TARGET_ARM_MACHINE interface for all the machines not listed previously. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/arm/aspeed.c | 109 +++++++++++++++++++++++++++++++++++++ hw/arm/b-l475e-iot01a.c | 6 ++ hw/arm/bananapi_m2u.c | 6 ++ hw/arm/bcm2836.c | 1 + hw/arm/collie.c | 6 ++ hw/arm/cubieboard.c | 6 ++ hw/arm/digic_boards.c | 6 ++ hw/arm/exynos4_boards.c | 11 ++++ hw/arm/fby35.c | 6 ++ hw/arm/highbank.c | 11 ++++ hw/arm/imx25_pdk.c | 6 ++ hw/arm/imx8mp-evk.c | 5 ++ hw/arm/integratorcp.c | 6 ++ hw/arm/kzm.c | 6 ++ hw/arm/mcimx6ul-evk.c | 6 ++ hw/arm/mcimx7d-sabre.c | 6 ++ hw/arm/microbit.c | 6 ++ hw/arm/mps2-tz.c | 21 +++++++ hw/arm/mps2.c | 21 +++++++ hw/arm/mps3r.c | 6 ++ hw/arm/msf2-som.c | 6 ++ hw/arm/musca.c | 11 ++++ hw/arm/musicpal.c | 6 ++ hw/arm/netduino2.c | 6 ++ hw/arm/netduinoplus2.c | 6 ++ hw/arm/npcm7xx_boards.c | 26 +++++++++ hw/arm/npcm8xx_boards.c | 5 ++ hw/arm/olimex-stm32-h405.c | 6 ++ hw/arm/omap_sx1.c | 11 ++++ hw/arm/orangepi.c | 6 ++ hw/arm/raspi.c | 24 ++++++++ hw/arm/raspi4b.c | 5 ++ hw/arm/realview.c | 21 +++++++ hw/arm/sabrelite.c | 6 ++ hw/arm/sbsa-ref.c | 5 ++ hw/arm/stellaris.c | 11 ++++ hw/arm/stm32vldiscovery.c | 6 ++ hw/arm/versatilepb.c | 11 ++++ hw/arm/vexpress.c | 11 ++++ hw/arm/virt.c | 6 ++ hw/arm/xilinx_zynq.c | 6 ++ hw/arm/xlnx-versal-virt.c | 5 ++ hw/arm/xlnx-zcu102.c | 5 ++ 43 files changed, 468 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 82f42582fa3..ce4d49a9f59 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -15,6 +15,7 @@ #include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" #include "hw/arm/aspeed_eeprom.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "hw/i2c/i2c_mux_pca954x.h" #include "hw/i2c/smbus_eeprom.h" @@ -1760,91 +1761,199 @@ static const TypeInfo aspeed_machine_types[] = { .name = MACHINE_TYPE_NAME("palmetto-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_palmetto_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_supermicrox11_bmc_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("ast2500-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2500_evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("romulus-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_romulus_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("sonorapass-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_sonorapass_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("witherspoon-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_witherspoon_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("ast2600-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2600_evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_yosemitev2_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("tiogapass-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_tiogapass_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("g220a-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_g220a_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_qcom_firework_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_fp5280g2_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_quanta_q71l_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("rainier-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_rainier_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("fuji-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_fuji_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("bletchley-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_bletchley_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("fby35-bmc"), .parent = MACHINE_TYPE_NAME("ast2600-evb"), .class_init = aspeed_machine_fby35_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("ast1030-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, #ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("ast2700a0-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2700a0_evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("ast2700a1-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2700a1_evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, #endif }, { .name = TYPE_ASPEED_MACHINE, diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index c9a5209216c..7af7db3dbb3 100644 --- a/hw/arm/b-l475e-iot01a.c +++ b/hw/arm/b-l475e-iot01a.c @@ -29,6 +29,7 @@ #include "qemu/error-report.h" #include "hw/arm/boot.h" #include "hw/core/split-irq.h" +#include "hw/arm/machines-qom.h" #include "hw/arm/stm32l4x5_soc.h" #include "hw/gpio/stm32l4x5_gpio.h" #include "hw/display/dm163.h" @@ -131,6 +132,11 @@ static const TypeInfo bl475e_machine_type[] = { .parent = TYPE_MACHINE, .instance_size = sizeof(Bl475eMachineState), .class_init = bl475e_machine_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, } }; diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c index 724ee4b05e5..5104a45390b 100644 --- a/hw/arm/bananapi_m2u.c +++ b/hw/arm/bananapi_m2u.c @@ -27,6 +27,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-r40.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" static struct arm_boot_info bpim2u_binfo; @@ -150,6 +151,11 @@ static const TypeInfo bananapi_machine_types[] = { .name = MACHINE_TYPE_NAME("bpim2u"), .parent = TYPE_MACHINE, .class_init = bpim2u_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 95e16806fa1..f60489983ba 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -14,6 +14,7 @@ #include "qemu/module.h" #include "hw/arm/bcm2836.h" #include "hw/arm/raspi_platform.h" +#include "hw/arm/machines-qom.h" #include "hw/sysbus.h" #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" diff --git a/hw/arm/collie.c b/hw/arm/collie.c index e83aee58c6b..458ed53f0f6 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -15,6 +15,7 @@ #include "hw/boards.h" #include "strongarm.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "system/address-spaces.h" #include "qom/object.h" @@ -86,6 +87,11 @@ static const TypeInfo collie_machine_typeinfo = { .parent = TYPE_MACHINE, .class_init = collie_machine_class_init, .instance_size = sizeof(CollieMachineState), + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void collie_machine_register_types(void) diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index 36062ac7037..00656169b72 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -22,6 +22,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-a10.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/i2c/i2c.h" static struct arm_boot_info cubieboard_binfo = { @@ -131,6 +132,11 @@ static const TypeInfo cubieboard_machine_types[] = { .name = MACHINE_TYPE_NAME("cubieboard"), .parent = TYPE_MACHINE, .class_init = cubieboard_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index 3c0cc6e4370..7b9fbb5524b 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -29,6 +29,7 @@ #include "hw/boards.h" #include "qemu/error-report.h" #include "hw/arm/digic.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "hw/loader.h" #include "system/qtest.h" @@ -152,6 +153,11 @@ static const TypeInfo digic_machine_types[] = { .name = MACHINE_TYPE_NAME("canon-a1100"), .parent = TYPE_MACHINE, .class_init = digic_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index 2d8f2d73265..71601a0d6f0 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -28,6 +28,7 @@ #include "hw/sysbus.h" #include "net/net.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "system/address-spaces.h" #include "hw/arm/exynos4210.h" #include "hw/net/lan9118.h" @@ -172,6 +173,11 @@ static const TypeInfo nuri_type = { .name = MACHINE_TYPE_NAME("nuri"), .parent = TYPE_MACHINE, .class_init = nuri_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void smdkc210_class_init(ObjectClass *oc, void *data) @@ -192,6 +198,11 @@ static const TypeInfo smdkc210_type = { .name = MACHINE_TYPE_NAME("smdkc210"), .parent = TYPE_MACHINE, .class_init = smdkc210_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void exynos4_machines_init(void) diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c index 6d3663f14a1..84b65844b34 100644 --- a/hw/arm/fby35.c +++ b/hw/arm/fby35.c @@ -14,6 +14,7 @@ #include "hw/qdev-clock.h" #include "hw/arm/aspeed_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #define TYPE_FBY35 MACHINE_TYPE_NAME("fby35") OBJECT_DECLARE_SIMPLE_TYPE(Fby35State, FBY35); @@ -187,6 +188,11 @@ static const TypeInfo fby35_types[] = { .class_init = fby35_class_init, .instance_size = sizeof(Fby35State), .instance_init = fby35_instance_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 0f3c207d548..d26346ea8ad 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -23,6 +23,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/loader.h" #include "net/net.h" #include "system/runstate.h" @@ -363,6 +364,11 @@ static const TypeInfo highbank_type = { .name = MACHINE_TYPE_NAME("highbank"), .parent = TYPE_MACHINE, .class_init = highbank_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void midway_class_init(ObjectClass *oc, void *data) @@ -387,6 +393,11 @@ static const TypeInfo midway_type = { .name = MACHINE_TYPE_NAME("midway"), .parent = TYPE_MACHINE, .class_init = midway_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void calxeda_machines_init(void) diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index a90def7f1a2..86f0855c929 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -28,6 +28,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/fsl-imx25.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "qemu/error-report.h" #include "system/qtest.h" @@ -157,6 +158,11 @@ static const TypeInfo imx25_machine_types[] = { .name = MACHINE_TYPE_NAME("imx25-pdk"), .parent = TYPE_MACHINE, .class_init = imx25_pdk_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c index c7d87d99230..44f704b9bd3 100644 --- a/hw/arm/imx8mp-evk.c +++ b/hw/arm/imx8mp-evk.c @@ -10,6 +10,7 @@ #include "system/address-spaces.h" #include "hw/arm/boot.h" #include "hw/arm/fsl-imx8mp.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "system/qtest.h" @@ -79,6 +80,10 @@ static const TypeInfo imx8_machine_types[] = { .name = MACHINE_TYPE_NAME("imx8mp-evk"), .parent = TYPE_MACHINE, .class_init = imx8mp_evk_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index f95916b517d..efe1075ecc0 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -13,6 +13,7 @@ #include "migration/vmstate.h" #include "hw/boards.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/misc/arm_integrator_debug.h" #include "hw/net/smc91c111.h" #include "net/net.h" @@ -760,6 +761,11 @@ static const TypeInfo integratorcp_machine_types[] = { .name = MACHINE_TYPE_NAME("integratorcp"), .parent = TYPE_MACHINE, .class_init = integratorcp_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index b56cabe9f94..02ece3c0139 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -17,6 +17,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx31.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "qemu/error-report.h" #include "system/address-spaces.h" @@ -146,6 +147,11 @@ static const TypeInfo kzm_machine_types[] = { .name = MACHINE_TYPE_NAME("kzm"), .parent = TYPE_MACHINE, .class_init = kzm_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index d947836d2be..ea636fa2e7c 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -14,6 +14,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx6ul.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" @@ -84,6 +85,11 @@ static const TypeInfo imx6_machine_types[] = { .name = MACHINE_TYPE_NAME("mcimx6ul-evk"), .parent = TYPE_MACHINE, .class_init = mcimx6ul_evk_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index f5dc9c211dd..b236a6587eb 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -16,6 +16,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx7.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" @@ -84,6 +85,11 @@ static const TypeInfo imx7_machine_types[] = { .name = MACHINE_TYPE_NAME("mcimx7d-sabre"), .parent = TYPE_MACHINE, .class_init = mcimx7d_sabre_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index ade363daaa4..d34b1c675e5 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -12,6 +12,7 @@ #include "qapi/error.h" #include "hw/boards.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "system/system.h" #include "system/address-spaces.h" @@ -74,6 +75,11 @@ static const TypeInfo microbit_info = { .parent = TYPE_MACHINE, .instance_size = sizeof(MicrobitMachineState), .class_init = microbit_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void microbit_machine_init(void) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index b0633a5a69e..12512477977 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -52,6 +52,7 @@ #include "qemu/error-report.h" #include "hw/arm/boot.h" #include "hw/arm/armv7m.h" +#include "hw/arm/machines-qom.h" #include "hw/or-irq.h" #include "hw/boards.h" #include "system/address-spaces.h" @@ -1463,24 +1464,44 @@ static const TypeInfo mps2tz_an505_info = { .name = TYPE_MPS2TZ_AN505_MACHINE, .parent = TYPE_MPS2TZ_MACHINE, .class_init = mps2tz_an505_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps2tz_an521_info = { .name = TYPE_MPS2TZ_AN521_MACHINE, .parent = TYPE_MPS2TZ_MACHINE, .class_init = mps2tz_an521_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps3tz_an524_info = { .name = TYPE_MPS3TZ_AN524_MACHINE, .parent = TYPE_MPS2TZ_MACHINE, .class_init = mps3tz_an524_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps3tz_an547_info = { .name = TYPE_MPS3TZ_AN547_MACHINE, .parent = TYPE_MPS2TZ_MACHINE, .class_init = mps3tz_an547_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void mps2tz_machine_init(void) diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 6958485a668..f39176c0005 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -31,6 +31,7 @@ #include "qemu/error-report.h" #include "hw/arm/boot.h" #include "hw/arm/armv7m.h" +#include "hw/arm/machines-qom.h" #include "hw/or-irq.h" #include "hw/boards.h" #include "system/address-spaces.h" @@ -563,24 +564,44 @@ static const TypeInfo mps2_an385_info = { .name = TYPE_MPS2_AN385_MACHINE, .parent = TYPE_MPS2_MACHINE, .class_init = mps2_an385_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps2_an386_info = { .name = TYPE_MPS2_AN386_MACHINE, .parent = TYPE_MPS2_MACHINE, .class_init = mps2_an386_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps2_an500_info = { .name = TYPE_MPS2_AN500_MACHINE, .parent = TYPE_MPS2_MACHINE, .class_init = mps2_an500_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo mps2_an511_info = { .name = TYPE_MPS2_AN511_MACHINE, .parent = TYPE_MPS2_MACHINE, .class_init = mps2_an511_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void mps2_machine_init(void) diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c index 4dd1e8a7180..8bcf5a4d69f 100644 --- a/hw/arm/mps3r.c +++ b/hw/arm/mps3r.c @@ -37,6 +37,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/boot.h" #include "hw/arm/bsa.h" +#include "hw/arm/machines-qom.h" #include "hw/char/cmsdk-apb-uart.h" #include "hw/i2c/arm_sbcon_i2c.h" #include "hw/intc/arm_gicv3.h" @@ -634,6 +635,11 @@ static const TypeInfo mps3r_machine_types[] = { .name = TYPE_MPS3R_AN536_MACHINE, .parent = TYPE_MPS3R_MACHINE, .class_init = mps3r_an536_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 6ce47eaa27a..3f7aefc0ba4 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -32,6 +32,7 @@ #include "hw/boards.h" #include "hw/qdev-properties.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/qdev-clock.h" #include "system/address-spaces.h" #include "hw/arm/msf2-soc.h" @@ -114,6 +115,11 @@ static const TypeInfo msf2_machine_types[] = { .name = MACHINE_TYPE_NAME("emcraft-sf2"), .parent = TYPE_MACHINE, .class_init = emcraft_sf2_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/musca.c b/hw/arm/musca.c index a4f43f1992b..608f16f69b2 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -26,6 +26,7 @@ #include "system/system.h" #include "hw/arm/boot.h" #include "hw/arm/armsse.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/char/pl011.h" #include "hw/core/split-irq.h" @@ -657,12 +658,22 @@ static const TypeInfo musca_a_info = { .name = TYPE_MUSCA_A_MACHINE, .parent = TYPE_MUSCA_MACHINE, .class_init = musca_a_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo musca_b1_info = { .name = TYPE_MUSCA_B1_MACHINE, .parent = TYPE_MUSCA_MACHINE, .class_init = musca_b1_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void musca_machine_init(void) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index f7c488cd1d6..e2a65f72095 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -15,6 +15,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "net/net.h" #include "system/system.h" #include "hw/boards.h" @@ -1381,6 +1382,11 @@ static const TypeInfo musicpal_types[] = { .name = MACHINE_TYPE_NAME("musicpal"), .parent = TYPE_MACHINE, .class_init = musicpal_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 52c30055d44..2e615276902 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -30,6 +30,7 @@ #include "qemu/error-report.h" #include "hw/arm/stm32f205_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" /* Main SYSCLK frequency in Hz (120MHz) */ #define SYSCLK_FRQ 120000000ULL @@ -71,6 +72,11 @@ static const TypeInfo netduino_machine_types[] = { .name = MACHINE_TYPE_NAME("netduino2"), .parent = TYPE_MACHINE, .class_init = netduino2_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index 2735d3a0e2b..e12f78599c4 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -30,6 +30,7 @@ #include "qemu/error-report.h" #include "hw/arm/stm32f405_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" /* Main SYSCLK frequency in Hz (168MHz) */ #define SYSCLK_FRQ 168000000ULL @@ -71,6 +72,11 @@ static const TypeInfo netduino_machine_types[] = { .name = MACHINE_TYPE_NAME("netduinoplus2"), .parent = TYPE_MACHINE, .class_init = netduinoplus2_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index eb28b97ad83..4b6d3443d53 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -17,6 +17,7 @@ #include "qemu/osdep.h" #include "hw/arm/npcm7xx.h" +#include "hw/arm/machines-qom.h" #include "hw/core/cpu.h" #include "hw/i2c/i2c_mux_pca954x.h" #include "hw/i2c/smbus_eeprom.h" @@ -549,22 +550,47 @@ static const TypeInfo npcm7xx_machine_types[] = { .name = MACHINE_TYPE_NAME("npcm750-evb"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = npcm750_evb_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("quanta-gsj"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = gsj_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("quanta-gbs-bmc"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = gbs_bmc_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("kudo-bmc"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = kudo_bmc_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("mori-bmc"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = mori_bmc_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c index 3fb8478e72e..919c14dd809 100644 --- a/hw/arm/npcm8xx_boards.c +++ b/hw/arm/npcm8xx_boards.c @@ -19,6 +19,7 @@ #include "chardev/char.h" #include "hw/boards.h" #include "hw/arm/npcm8xx.h" +#include "hw/arm/machines-qom.h" #include "hw/core/cpu.h" #include "hw/loader.h" #include "hw/qdev-core.h" @@ -248,6 +249,10 @@ static const TypeInfo npcm8xx_machine_types[] = { .name = MACHINE_TYPE_NAME("npcm845-evb"), .parent = TYPE_NPCM8XX_MACHINE, .class_init = npcm845_evb_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c index 795218c93cf..f81f4094149 100644 --- a/hw/arm/olimex-stm32-h405.c +++ b/hw/arm/olimex-stm32-h405.c @@ -31,6 +31,7 @@ #include "qemu/error-report.h" #include "hw/arm/stm32f405_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" /* olimex-stm32-h405 implementation is derived from netduinoplus2 */ @@ -77,6 +78,11 @@ static const TypeInfo olimex_stm32_machine_types[] = { .name = MACHINE_TYPE_NAME("olimex-stm32-h405"), .parent = TYPE_MACHINE, .class_init = olimex_stm32_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index aa1e96b3ad7..2537045c1ac 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -32,6 +32,7 @@ #include "hw/arm/omap.h" #include "hw/boards.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "system/qtest.h" #include "system/address-spaces.h" @@ -219,6 +220,11 @@ static const TypeInfo sx1_machine_v2_type = { .name = MACHINE_TYPE_NAME("sx1"), .parent = TYPE_MACHINE, .class_init = sx1_machine_v2_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void sx1_machine_v1_class_init(ObjectClass *oc, void *data) @@ -238,6 +244,11 @@ static const TypeInfo sx1_machine_v1_type = { .name = MACHINE_TYPE_NAME("sx1-v1"), .parent = TYPE_MACHINE, .class_init = sx1_machine_v1_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void sx1_machine_init(void) diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index 6821033bfd7..4e333d428a2 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -26,6 +26,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-h3.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" static struct arm_boot_info orangepi_binfo; @@ -130,6 +131,11 @@ static const TypeInfo orangepi_machine_types[] = { .name = MACHINE_TYPE_NAME("orangepi-pc"), .parent = TYPE_MACHINE, .class_init = orangepi_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index dce35ca11aa..69cccdbb6b1 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -25,6 +25,7 @@ #include "hw/boards.h" #include "hw/loader.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "qom/object.h" #define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common") @@ -394,23 +395,46 @@ static const TypeInfo raspi_machine_types[] = { .name = MACHINE_TYPE_NAME("raspi0"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi0_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("raspi1ap"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi1ap_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("raspi2b"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi2b_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, #ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("raspi3ap"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi3ap_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("raspi3b"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi3b_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, #endif }, { .name = TYPE_RASPI_MACHINE, diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c index f6de103a3e1..8fda6d3b0ca 100644 --- a/hw/arm/raspi4b.c +++ b/hw/arm/raspi4b.c @@ -11,6 +11,7 @@ #include "qemu/cutils.h" #include "qapi/error.h" #include "qapi/visitor.h" +#include "hw/arm/machines-qom.h" #include "hw/arm/raspi_platform.h" #include "hw/display/bcm2835_fb.h" #include "hw/registerfields.h" @@ -127,6 +128,10 @@ static const TypeInfo raspi4b_machine_type = { .parent = TYPE_RASPI_BASE_MACHINE, .instance_size = sizeof(Raspi4bMachineState), .class_init = raspi4b_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void raspi4b_machine_register_type(void) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 008eeaf049a..aed864bcd4f 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -13,6 +13,7 @@ #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" +#include "hw/arm/machines-qom.h" #include "hw/core/split-irq.h" #include "hw/net/lan9118.h" #include "hw/net/smc91c111.h" @@ -431,6 +432,11 @@ static const TypeInfo realview_eb_type = { .name = MACHINE_TYPE_NAME("realview-eb"), .parent = TYPE_MACHINE, .class_init = realview_eb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data) @@ -452,6 +458,11 @@ static const TypeInfo realview_eb_mpcore_type = { .name = MACHINE_TYPE_NAME("realview-eb-mpcore"), .parent = TYPE_MACHINE, .class_init = realview_eb_mpcore_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void realview_pb_a8_class_init(ObjectClass *oc, void *data) @@ -471,6 +482,11 @@ static const TypeInfo realview_pb_a8_type = { .name = MACHINE_TYPE_NAME("realview-pb-a8"), .parent = TYPE_MACHINE, .class_init = realview_pb_a8_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void realview_pbx_a9_class_init(ObjectClass *oc, void *data) @@ -491,6 +507,11 @@ static const TypeInfo realview_pbx_a9_type = { .name = MACHINE_TYPE_NAME("realview-pbx-a9"), .parent = TYPE_MACHINE, .class_init = realview_pbx_a9_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void realview_machine_init(void) diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index ea59ba301e7..bc472dcad2c 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -14,6 +14,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx6.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" @@ -120,6 +121,11 @@ static const TypeInfo sabrelite_machine_types[] = { .name = MACHINE_TYPE_NAME("sabrelite"), .parent = TYPE_MACHINE, .class_init = sabrelite_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index aa09d7a0917..6584097fc25 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -34,6 +34,7 @@ #include "hw/arm/bsa.h" #include "hw/arm/fdt.h" #include "hw/arm/smmuv3.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "hw/boards.h" #include "hw/ide/ide-bus.h" @@ -920,6 +921,10 @@ static const TypeInfo sbsa_ref_info = { .instance_init = sbsa_ref_instance_init, .class_init = sbsa_ref_class_init, .instance_size = sizeof(SBSAMachineState), + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void sbsa_ref_machine_init(void) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index cbe914c93e9..8dc68c145c1 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -15,6 +15,7 @@ #include "hw/sd/sd.h" #include "hw/ssi/ssi.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "qemu/timer.h" #include "hw/i2c/i2c.h" #include "net/net.h" @@ -1427,6 +1428,11 @@ static const TypeInfo lm3s811evb_type = { .name = MACHINE_TYPE_NAME("lm3s811evb"), .parent = TYPE_MACHINE, .class_init = lm3s811evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; /* @@ -1448,6 +1454,11 @@ static const TypeInfo lm3s6965evb_type = { .name = MACHINE_TYPE_NAME("lm3s6965evb"), .parent = TYPE_MACHINE, .class_init = lm3s6965evb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void stellaris_machine_init(void) diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 3a9728ca719..b7eb948bc2d 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -31,6 +31,7 @@ #include "qemu/error-report.h" #include "hw/arm/stm32f100_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" /* stm32vldiscovery implementation is derived from netduinoplus2 */ @@ -74,6 +75,11 @@ static const TypeInfo stm32vldiscovery_machine_types[] = { .name = MACHINE_TYPE_NAME("stm32vldiscovery"), .parent = TYPE_MACHINE, .class_init = stm32vldiscovery_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }, }; diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 35766445fa4..defc4d7d170 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -12,6 +12,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/net/smc91c111.h" #include "net/net.h" #include "system/system.h" @@ -431,6 +432,11 @@ static const TypeInfo versatilepb_type = { .name = MACHINE_TYPE_NAME("versatilepb"), .parent = TYPE_MACHINE, .class_init = versatilepb_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void versatileab_class_init(ObjectClass *oc, void *data) @@ -452,6 +458,11 @@ static const TypeInfo versatileab_type = { .name = MACHINE_TYPE_NAME("versatileab"), .parent = TYPE_MACHINE, .class_init = versatileab_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void versatile_machine_init(void) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 76c6107766c..38b203b52da 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -27,6 +27,7 @@ #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" +#include "hw/arm/machines-qom.h" #include "hw/net/lan9118.h" #include "hw/i2c/i2c.h" #include "net/net.h" @@ -850,6 +851,11 @@ static const TypeInfo vexpress_a9_info = { .parent = TYPE_VEXPRESS_MACHINE, .class_init = vexpress_a9_class_init, .instance_init = vexpress_a9_instance_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static const TypeInfo vexpress_a15_info = { @@ -857,6 +863,11 @@ static const TypeInfo vexpress_a15_info = { .parent = TYPE_VEXPRESS_MACHINE, .class_init = vexpress_a15_class_init, .instance_init = vexpress_a15_instance_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void vexpress_machine_init(void) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a96452f17a4..a3c9ffe29eb 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -37,6 +37,7 @@ #include "hw/arm/boot.h" #include "hw/arm/primecell.h" #include "hw/arm/virt.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "hw/vfio/vfio-calxeda-xgmac.h" #include "hw/vfio/vfio-amd-xgbe.h" @@ -123,6 +124,11 @@ static void arm_virt_compat_set(MachineClass *mc) .name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \ .parent = TYPE_VIRT_MACHINE, \ .class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \ + .interfaces = (InterfaceInfo[]) { \ + { TYPE_TARGET_ARM_MACHINE }, \ + { TYPE_TARGET_AARCH64_MACHINE }, \ + { }, \ + }, \ }; \ static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \ { \ diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index b8916665ed6..433907093fa 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -20,6 +20,7 @@ #include "qapi/error.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "net/net.h" #include "system/system.h" #include "hw/boards.h" @@ -480,6 +481,11 @@ static const TypeInfo zynq_machine_type = { .parent = TYPE_MACHINE, .class_init = zynq_machine_class_init, .instance_size = sizeof(ZynqMachineState), + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void zynq_machine_register_types(void) diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 0c6f0359e3d..cb7466f7250 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -20,6 +20,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/xlnx-versal.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "target/arm/multiprocessing.h" #include "qom/object.h" @@ -833,6 +834,10 @@ static const TypeInfo versal_virt_machine_init_typeinfo = { .instance_init = versal_virt_machine_instance_init, .instance_size = sizeof(VersalVirt), .instance_finalize = versal_virt_machine_finalize, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { }, + }, }; static void versal_virt_machine_init_register_types(void) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 4fdb153e4d8..f730dbbd908 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -19,6 +19,7 @@ #include "qapi/error.h" #include "hw/arm/xlnx-zynqmp.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "qemu/error-report.h" #include "qemu/log.h" @@ -303,6 +304,10 @@ static const TypeInfo xlnx_zcu102_machine_init_typeinfo = { .class_init = xlnx_zcu102_machine_class_init, .instance_init = xlnx_zcu102_machine_instance_init, .instance_size = sizeof(XlnxZCU102), + .interfaces = (InterfaceInfo[]) { + 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa5a2300sm15291826f8f.101.2025.04.22.07.55.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:55:36 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 07/19] meson: Prepare to accept per-binary TargetInfo structure implementation Date: Tue, 22 Apr 2025 16:54:49 +0200 Message-ID: <20250422145502.70770-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If a file defining the binary TargetInfo structure is available, link with it. Otherwise keep using the stub. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- meson.build | 9 ++++++++- configs/targets/meson.build | 3 +++ 2 files changed, 11 insertions(+), 1 deletion(-) create mode 100644 configs/targets/meson.build diff --git a/meson.build b/meson.build index a1109b6db3f..69f60755377 100644 --- a/meson.build +++ b/meson.build @@ -3216,6 +3216,7 @@ config_devices_mak_list = [] config_devices_h = {} config_target_h = {} config_target_mak = {} +config_target_info = {} disassemblers = { 'alpha' : ['CONFIG_ALPHA_DIS'], @@ -3809,9 +3810,9 @@ specific_ss.add(files('page-target.c', 'page-vary-target.c')) common_ss.add(files('target-info.c')) system_ss.add(files('target-info-qom.c')) -specific_ss.add(files('target-info-stub.c')) subdir('backends') +subdir('configs/targets') subdir('disas') subdir('migration') subdir('monitor') @@ -4272,6 +4273,12 @@ foreach target : target_dirs arch_srcs += gdbstub_xml endif + if target in config_target_info + arch_srcs += config_target_info[target] + else + arch_srcs += files('target-info-stub.c') + endif + t = target_arch[target_base_arch].apply(config_target, strict: false) arch_srcs += t.sources() arch_deps += t.dependencies() diff --git a/configs/targets/meson.build b/configs/targets/meson.build new file mode 100644 index 00000000000..e9a5f7b078e --- /dev/null +++ b/configs/targets/meson.build @@ -0,0 +1,3 @@ +foreach target : ['arm-softmmu', 'aarch64-softmmu'] + config_target_info += {target : files(target + '.c')} +endforeach From patchwork Tue Apr 22 14:54:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883001 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2457674wrs; Tue, 22 Apr 2025 07:58:53 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU3Zxtd6qdw+5GrvsUxra8MDlHBTWl4VnbD7Zm7eP6ezxvxdQVcD3vIrS8BYlxiw5zty7l6YA==@linaro.org X-Google-Smtp-Source: AGHT+IF6ST8e9HEwpJmLth1XjW6Mymg6RTI8LPREKf85JjZOs1ixEgXV0yLu9vSNZ83fXVjUEOcl X-Received: by 2002:a05:620a:471e:b0:7c5:5d32:2612 with SMTP id af79cd13be357-7c9280660e9mr2357228485a.58.1745333933505; Tue, 22 Apr 2025 07:58:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745333933; cv=none; d=google.com; s=arc-20240605; b=HWqTQURzv/lb89Fny78Cyx02RphY/2wkUjtOvDyJSbtIkNlOmsz7W65fYh31Xaynhb fI/ZMch3l+cQr2csnMLNzSArZo82uI+IurUsOWXYoVbqVEZnuaqCWkUdpow1huku4XJv hp8v1LGkLIe5sTAiZ8kps7x3b8JJ95hNxYbSO300hIIHBcQRiwM888Dq5Dv1z3IOmQvw 5XGJ/FQ+KOPXbvYKbg++pYAsDanKAAA8q5iell/LV/NuQ0n7qDZMAL8lEB+sGAMToiP6 x8VnOeZnatHpzwVJ2sa1yBxqJ7ypV5YoJOht1EZ5LoBjCSkE/c/GH9399xX357halBjp O/lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=22LQQOm056H4PYfBCVwoRoEL66DvS4+UOozPRWo0Okc=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=ADyKgF4L30p1+xyE7tbOI4LIRgktJlu+QFkWxjx83u3wcKD+lqB/j+cd44vFk/ZSwd aD5j6ucxkjLhc/2I/49VDdf8pm/R1J8WjmQ7zz0ERnMQKInAggbfcDGk6evgqcSunRAV 9iVSfaUdg2Jg1x8y7CAXsmD805D2SpNdqiPr9po83R1ZWGzezO4Oy71SZbBe1ITufZX6 3eAqoP8n4mxGvweF1o/wfLyjBZ8hhWrnbUr7FF5KV88xa4APo6T1BAN62CzA9rYj5ScV ZKMcqclF5W57GkUyKlxx+HmZ0mH6ak1rdcDyHGhOSmzlOsQNACQ0yu8NpjgcDcLQQOcO Pa6Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qO48SXY0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d6db131sm176255965e9.28.2025.04.22.07.55.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:55:41 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 08/19] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) Date: Tue, 22 Apr 2025 16:54:50 +0200 Message-ID: <20250422145502.70770-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Implement the TargetInfo structure for qemu-system-arm and qemu-system-aarch64 binaries. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- MAINTAINERS | 1 + configs/targets/aarch64-softmmu.c | 22 ++++++++++++++++++++++ configs/targets/arm-softmmu.c | 22 ++++++++++++++++++++++ 3 files changed, 45 insertions(+) create mode 100644 configs/targets/aarch64-softmmu.c create mode 100644 configs/targets/arm-softmmu.c diff --git a/MAINTAINERS b/MAINTAINERS index a055f67b5fc..4edd1ba696a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1919,6 +1919,7 @@ M: Philippe Mathieu-Daudé S: Supported F: include/qemu/target-info*.h F: target-info*.c +F: configs/targets/*.c Xtensa Machines --------------- diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c new file mode 100644 index 00000000000..375e6fa0b7b --- /dev/null +++ b/configs/targets/aarch64-softmmu.c @@ -0,0 +1,22 @@ +/* + * QEMU binary/target API (qemu-system-aarch64) + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" +#include "hw/arm/machines-qom.h" +#include "target/arm/cpu-qom.h" + +static const TargetInfo target_info_aarch64_system = { + .target_name = "aarch64", + .machine_typename = TYPE_TARGET_AARCH64_MACHINE, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_aarch64_system; +} diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c new file mode 100644 index 00000000000..d4acdae64f3 --- /dev/null +++ b/configs/targets/arm-softmmu.c @@ -0,0 +1,22 @@ +/* + * QEMU binary/target API (qemu-system-arm) + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" +#include "hw/arm/machines-qom.h" +#include "target/arm/cpu-qom.h" + +static const TargetInfo target_info_arm_system = { + .target_name = "arm", + .machine_typename = TYPE_TARGET_ARM_MACHINE, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_arm_system; +} From patchwork Tue Apr 22 14:54:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882991 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2456762wrs; Tue, 22 Apr 2025 07:56:46 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUSBrTg2YJubYnpNV4lYllTzZbY3C5j4Frx4mZ8EEpquUQbkpsLy3lD8hddN6fwn4vJ2KWU9A==@linaro.org X-Google-Smtp-Source: AGHT+IGhilBLbOcUSpGkhMiKx3vhEmSIgYjnCceuCUw9Xb/Xv9nsDUeUYcCA+0w4q65P8lrEaQLL X-Received: by 2002:a05:620a:454a:b0:7c5:e92a:cba3 with SMTP id af79cd13be357-7c92804027emr2702253185a.49.1745333805740; Tue, 22 Apr 2025 07:56:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745333805; cv=none; d=google.com; s=arc-20240605; b=XrEmWn8xDa0BByrC3dctVIP37n41zrzlrqNSQ80wlwzOtNVnZczsurDimkmNSpKhM2 HwTm8IDOfw2Ke3xh4Iw4tUpQByUuCMF9S+CejDbaBYsYixSRY20fBbv0c2PQi02VWzWB 6AK+/xx3k1vndndeCnmEvTUP+qALLI1Q+EirjEckD57F88aqqplfY5/5b22bAIs6j5/Z zudUWxR6qZ+TrWLKek2MMxrYwVmGNXFrci55hXI8htYnA7GGDmeqsPk0+L7M/ULdubJf PbXP9r+s9wA5uaZJf4CiseyX6+y0o79UMpKDfkAbk4/qO5tSmYDJZnB5n57ISNrBNn3S avZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MPk7GJ/Q7Awhqe4M7LOu5PgmoZQozcGdMhSTLUXghio=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=VBvTU2UjIu3rLLJ1/8ItjP2OpZrBtItYSl6xuMSBlw0ZnnvVQNGb1lU4JWQz75lepC TWWAb5hNtXK5JZiwa1uwtU19cS3RkNSnf2W8v5VnE7SpMvkTdoXP1syAbeXCVnymrWIN L5oHCUXaF12neTvtIv+3OEhjhXGhecAcJUjYLgVe6OxojOdXBjQfMeQ+gdfq7w4Xcl3L M3qEJyKD26KgKk6oJgQqoW5wbwkKpn7ZyJE8UBulmLuHiJFilJzTmlx3odslNlT8h65/ bDJPWWDCETK3WT7KDVpJh2Nvj1SIrY4gOeCCk7PwYdgvDsCaGpBKw1aiRddQTnqGoBwo ouoA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JtpCxqdO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d6db131sm176258285e9.28.2025.04.22.07.55.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:55:45 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 09/19] hw/arm/aspeed: Build objects once Date: Tue, 22 Apr 2025 16:54:51 +0200 Message-ID: <20250422145502.70770-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now than Aspeed machines can be filtered when running a qemu-system-arm or qemu-system-aarch64 binary, we can remove the TARGET_AARCH64 #ifdef'ry and compile the aspeed.c file once, moving it from arm_ss[] source set to arm_common_ss[]. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- hw/arm/aspeed.c | 6 ------ hw/arm/meson.build | 4 ++-- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index ce4d49a9f59..6de61505a09 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -180,13 +180,11 @@ struct AspeedMachineState { #define AST2600_EVB_HW_STRAP1 0x000000C0 #define AST2600_EVB_HW_STRAP2 0x00000003 -#ifdef TARGET_AARCH64 /* AST2700 evb hardware value */ /* SCU HW Strap1 */ #define AST2700_EVB_HW_STRAP1 0x00000800 /* SCUIO HW Strap1 */ #define AST2700_EVB_HW_STRAP2 0x00000700 -#endif /* Rainier hardware value: (QEMU prototype) */ #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) @@ -1664,7 +1662,6 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); } -#ifdef TARGET_AARCH64 static void ast2700_evb_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc = bmc->soc; @@ -1714,7 +1711,6 @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, void *data) mc->default_ram_size = 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); } -#endif static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, void *data) @@ -1937,7 +1933,6 @@ static const TypeInfo aspeed_machine_types[] = { { TYPE_TARGET_AARCH64_MACHINE }, { }, }, -#ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("ast2700a0-evb"), .parent = TYPE_ASPEED_MACHINE, @@ -1954,7 +1949,6 @@ static const TypeInfo aspeed_machine_types[] = { { TYPE_TARGET_AARCH64_MACHINE }, { }, }, -#endif }, { .name = TYPE_ASPEED_MACHINE, .parent = TYPE_MACHINE, diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 09b1cfe5b57..f76e7fb229f 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -39,15 +39,15 @@ arm_common_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'x arm_common_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c')) -arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( +arm_common_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed.c', 'aspeed_soc_common.c', 'aspeed_ast2400.c', 'aspeed_ast2600.c', 'aspeed_ast10x0.c', + 'aspeed_ast27x0.c', 'aspeed_eeprom.c', 'fby35.c')) -arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c')) arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c')) From patchwork Tue Apr 22 14:54:52 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d5bbcfesm180029645e9.23.2025.04.22.07.55.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:55:50 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 10/19] hw/arm/raspi: Build objects once Date: Tue, 22 Apr 2025 16:54:52 +0200 Message-ID: <20250422145502.70770-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now than Raspi machines can be filtered when running a qemu-system-arm or qemu-system-aarch64 binary, we can remove the TARGET_AARCH64 #ifdef'ry and compile the aspeed.c file once, moving it from arm_ss[] source set to arm_common_ss[]. Note, we expose the TYPE_BCM2837 type to qemu-system-arm, but it is not user-creatable, so not an issue. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- hw/arm/bcm2836.c | 4 ---- hw/arm/raspi.c | 4 ---- hw/arm/meson.build | 8 ++++++-- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index f60489983ba..454ea2208d7 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -196,7 +196,6 @@ static void bcm2836_class_init(ObjectClass *oc, void *data) dc->realize = bcm2836_realize; }; -#ifdef TARGET_AARCH64 static void bcm2837_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -209,7 +208,6 @@ static void bcm2837_class_init(ObjectClass *oc, void *data) bc->clusterid = 0x0; dc->realize = bcm2836_realize; }; -#endif static const TypeInfo bcm283x_types[] = { { @@ -220,12 +218,10 @@ static const TypeInfo bcm283x_types[] = { .name = TYPE_BCM2836, .parent = TYPE_BCM283X, .class_init = bcm2836_class_init, -#ifdef TARGET_AARCH64 }, { .name = TYPE_BCM2837, .parent = TYPE_BCM283X, .class_init = bcm2837_class_init, -#endif }, { .name = TYPE_BCM283X, .parent = TYPE_BCM283X_BASE, diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 69cccdbb6b1..641e231db61 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -368,7 +368,6 @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data) raspi_machine_class_init(mc, rmc->board_rev); }; -#ifdef TARGET_AARCH64 static void raspi3ap_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -388,7 +387,6 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data) rmc->board_rev = 0xa02082; raspi_machine_class_init(mc, rmc->board_rev); }; -#endif /* TARGET_AARCH64 */ static const TypeInfo raspi_machine_types[] = { { @@ -418,7 +416,6 @@ static const TypeInfo raspi_machine_types[] = { { TYPE_TARGET_AARCH64_MACHINE }, { }, }, -#ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("raspi3ap"), .parent = TYPE_RASPI_MACHINE, @@ -435,7 +432,6 @@ static const TypeInfo raspi_machine_types[] = { { TYPE_TARGET_AARCH64_MACHINE }, { }, }, -#endif }, { .name = TYPE_RASPI_MACHINE, .parent = TYPE_RASPI_BASE_MACHINE, diff --git a/hw/arm/meson.build b/hw/arm/meson.build index f76e7fb229f..f52034ff6a2 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -27,8 +27,12 @@ arm_common_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c')) -arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) -arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c')) +arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files( + 'bcm2836.c', + 'bcm2838.c', + 'raspi.c', + 'raspi4b.c', +)) arm_common_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) arm_common_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) arm_common_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) From patchwork Tue Apr 22 14:54:53 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa433133sm15305288f8f.28.2025.04.22.07.55.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:55:54 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 11/19] hw/core/machine: Allow dynamic registration of valid CPU types Date: Tue, 22 Apr 2025 16:54:53 +0200 Message-ID: <20250422145502.70770-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add MachineClass::get_valid_cpu_types(), a helper that returns a dynamic list of CPU types. Since the helper takes a MachineState argument, we know the machine is created by the time we call it. Suggested-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé --- include/hw/boards.h | 4 ++++ hw/core/machine.c | 27 +++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/include/hw/boards.h b/include/hw/boards.h index 02f43ac5d4d..be0c0f04804 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -259,6 +259,9 @@ typedef struct { * @smbios_memory_device_size: * Default size of memory device, * SMBIOS 3.1.0 "7.18 Memory Device (Type 17)" + * @get_valid_cpu_types: + * Returns a list of valid CPU types for this board. May be NULL + * if not needed. */ struct MachineClass { /*< private >*/ @@ -306,6 +309,7 @@ struct MachineClass { bool ignore_memory_transaction_failures; int numa_mem_align_shift; const char * const *valid_cpu_types; + GSList *(*get_valid_cpu_types)(const MachineState *ms); strList *allowed_dynamic_sysbus_devices; bool auto_enable_numa_with_memhp; bool auto_enable_numa_with_memdev; diff --git a/hw/core/machine.c b/hw/core/machine.c index f52a4f2273b..8b40735ef98 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1581,6 +1581,33 @@ static bool is_cpu_type_supported(const MachineState *machine, Error **errp) return false; } } + if (mc->get_valid_cpu_types) { + GSList *vct = mc->get_valid_cpu_types(machine); + bool valid = false; + unsigned count = 0; + GSList *l; + + for (l = vct; !valid && l != NULL; l = l->next) { + valid |= !!object_class_dynamic_cast(oc, l->data); + count++; + } + + if (!valid) { + g_autofree char *requested = cpu_model_from_type(machine->cpu_type); + vct = g_slist_reverse(vct); + error_setg(errp, "Invalid CPU model: %s", requested); + error_append_hint(errp, "The valid models are: "); + for (l = vct; l != NULL; l = l->next) { + g_autofree char *model = cpu_model_from_type(l->data); + error_append_hint(errp, "%s%s", model, --count ? ", " : ""); + } + error_append_hint(errp, "\n"); + } + g_slist_free_full(vct, g_free); + if (!valid) { + return false; + } + } /* Check if CPU type is deprecated and warn if so */ cc = CPU_CLASS(oc); From patchwork Tue Apr 22 14:54:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882990 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2456755wrs; Tue, 22 Apr 2025 07:56:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVSRA1MtyhksQVr91M0RSygx3UA3lRxqgttdbFle3uhpto31OIF06Jejhn+aluxPRhC8QNpyA==@linaro.org X-Google-Smtp-Source: AGHT+IGMnDanrHM1qQh7eqABUeeViMpS2DqVP4h7QmO10LpVwm6MEdsLbmkb/U7+vIkdcnM6fOao X-Received: by 2002:ad4:5fcc:0:b0:6f2:d25e:8f60 with SMTP id 6a1803df08f44-6f2d25e95f8mr193692386d6.22.1745333805197; Tue, 22 Apr 2025 07:56:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745333805; cv=none; d=google.com; s=arc-20240605; b=Y/7DuBR9nkemqNM+CvqUNPy736/cZ2Ew7Su0M3Wb27757rjRmE5DhD1UOSDABtEEiI Y0mB5JvdQ0Jh7wK5+UrE8fhbez/zeXOcjE7YTcU1A8o4HvX7zTg/8AkWeIINRAAzHVTI qT6aWkhtGkGvWN1WujVVAZzM1pOZF5cSK6CEg7Tke0KI5MEFmR5ULCi6kiQemG5Z6/He s/q0fBgDH6flCXbNSs+tUNh+4dce2FsQGGuCeCqBJRX66REZNaQ/LMxoRuUPzoI5sNdL 8em1JJf0SVnt0aAEn9n6fRA0PZ9d7PVM2hRc7wr6XdXggXv2alDMKL2/mFla4EHG5qbR r90w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=x2KEV2AEYEUZLZcRsBIKfpHBlRW4GmRUJdostUxtMx4=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=DHfiOnPS4Eeik88C4fNMWATGuMP7Ookv4hjH/Ici/T2prjU1hErH+HdUtIO1GNJ2PM XCeyInhyxvhD1/Abt//JsyxtaRQnm+ZCnAUw+oVrjjR1MNVWRkoqKWkXE6LalgrMkSL8 U47XEZWMyq/zNWXXTXC1RCYXqhapXmSk+VgHWAF6vFthoP/w+oAUh1MNxMqXOwnMiZDN bb7qscrsJdpNLsafC1gFx7W7h7n0LqMDy09HINmeRoxgDVQpDhlQ1ltXQcySYGGDXNgr 34RCvzWCCiXcwXdNoSUfjUOD2/O9ZvRhUQpbtkYM4LJsbiRCvBi9kSQ8HneslVao++h3 syGQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Sgjuf9kx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d5bbd8asm177010515e9.23.2025.04.22.07.55.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:55:59 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 12/19] hw/arm/virt: Register valid CPU types dynamically Date: Tue, 22 Apr 2025 16:54:54 +0200 Message-ID: <20250422145502.70770-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the static array returned as MachineClass::valid_cpu_types[] by a runtime one generated by MachineClass::get_valid_cpu_types() once the machine is created (its options being processed). Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 59 ++++++++++++++++++++++++++++----------------------- 1 file changed, 32 insertions(+), 27 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a3c9ffe29eb..c6ae7cc1705 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3130,36 +3130,41 @@ static int virt_hvf_get_physical_address_range(MachineState *ms) return requested_ipa_size; } +static GSList *virt_get_valid_cpu_types(const MachineState *ms) +{ + GSList *vct = NULL; + +#ifdef CONFIG_TCG + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); +#ifdef TARGET_AARCH64 + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a55"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a72"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a76"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a710"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("a64fx"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); +#endif /* TARGET_AARCH64 */ +#endif /* CONFIG_TCG */ +#ifdef TARGET_AARCH64 + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57"))); +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("host"))); +#endif /* CONFIG_KVM || CONFIG_HVF */ +#endif /* TARGET_AARCH64 */ + vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("max"))); + + return vct; +} + static void virt_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); - static const char * const valid_cpu_types[] = { -#ifdef CONFIG_TCG - ARM_CPU_TYPE_NAME("cortex-a7"), - ARM_CPU_TYPE_NAME("cortex-a15"), -#ifdef TARGET_AARCH64 - ARM_CPU_TYPE_NAME("cortex-a35"), - ARM_CPU_TYPE_NAME("cortex-a55"), - ARM_CPU_TYPE_NAME("cortex-a72"), - ARM_CPU_TYPE_NAME("cortex-a76"), - ARM_CPU_TYPE_NAME("cortex-a710"), - ARM_CPU_TYPE_NAME("a64fx"), - ARM_CPU_TYPE_NAME("neoverse-n1"), - ARM_CPU_TYPE_NAME("neoverse-v1"), - ARM_CPU_TYPE_NAME("neoverse-n2"), -#endif /* TARGET_AARCH64 */ -#endif /* CONFIG_TCG */ -#ifdef TARGET_AARCH64 - ARM_CPU_TYPE_NAME("cortex-a53"), - ARM_CPU_TYPE_NAME("cortex-a57"), -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) - ARM_CPU_TYPE_NAME("host"), -#endif /* CONFIG_KVM || CONFIG_HVF */ -#endif /* TARGET_AARCH64 */ - ARM_CPU_TYPE_NAME("max"), - NULL - }; mc->init = machvirt_init; /* Start with max_cpus set to 512, which is the maximum supported by KVM. @@ -3187,7 +3192,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) #else mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); #endif - mc->valid_cpu_types = valid_cpu_types; + mc->get_valid_cpu_types = virt_get_valid_cpu_types; mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; mc->kvm_type = virt_kvm_type; mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range; From patchwork Tue Apr 22 14:54:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882998 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2457163wrs; Tue, 22 Apr 2025 07:57:39 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXlcDXQ755SOS8E2r0CCjJThxDgT/s0slwL0V/Q4VjDre5EtXFxT8UafhAU5Eo+PEM/S/i4wA==@linaro.org X-Google-Smtp-Source: AGHT+IF9JpiFDWibuutIxuv/gMrwkd4lwL3geEN2OfOo/XuNtYiDRORhxuSF5xCUOa90hPUWw0ar X-Received: by 2002:ac8:5d04:0:b0:477:6f28:8c16 with SMTP id d75a77b69052e-47aec3658cemr249982371cf.6.1745333859184; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d5ccd38sm174691505e9.28.2025.04.22.07.56.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:56:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 13/19] hw/arm/virt: Check accelerator availability at runtime Date: Tue, 22 Apr 2025 16:54:55 +0200 Message-ID: <20250422145502.70770-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace compile-time check on CONFIG_{ACCEL} by runtime check on {accel}_enabled() helpers. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/virt.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c6ae7cc1705..d7197958f7c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3134,7 +3134,7 @@ static GSList *virt_get_valid_cpu_types(const MachineState *ms) { GSList *vct = NULL; -#ifdef CONFIG_TCG + if (tcg_enabled()) { vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); #ifdef TARGET_AARCH64 @@ -3148,13 +3148,13 @@ static GSList *virt_get_valid_cpu_types(const MachineState *ms) vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); #endif /* TARGET_AARCH64 */ -#endif /* CONFIG_TCG */ + } #ifdef TARGET_AARCH64 vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57"))); -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) + if (kvm_enabled() || hvf_enabled()) { vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("host"))); -#endif /* CONFIG_KVM || CONFIG_HVF */ + } #endif /* TARGET_AARCH64 */ vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("max"))); From patchwork Tue Apr 22 14:54:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882999 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2457172wrs; Tue, 22 Apr 2025 07:57:39 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUpmStwfrm4yzlOPahrKSf/97K+WHRXG1N5CV/kzHC0BdwuS6PPQO2I7EY+qO78wyqMJ7Y6Dg==@linaro.org X-Google-Smtp-Source: AGHT+IG5Wq6TOOoEcnLfC48fT2GM8S4Hqeb3TBGuCjj4X18XRr4ZULSPg9mCT6X42FpoLy1DNzfO X-Received: by 2002:ac8:5892:0:b0:476:9847:7c6e with SMTP id d75a77b69052e-47aec3d078amr275753961cf.19.1745333859681; Tue, 22 Apr 2025 07:57:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745333859; cv=none; d=google.com; s=arc-20240605; b=YS62T6MK8rYBYdYfCAgzKsFCMVKkqSz/u195RNKRy4XjRxYN9RL4XU+zpXUWs2j3k3 YI+Sl8EwMMytl+dsQ0c848OsNB7Ycz8mH5AqJb1cdRfH+N5BWLEuJYeu2kh/zZxjdILY RiSoAEJGzhpLagULk1xKkNjwe80nIiXDQhpOJhKY+FlbU60qfmHhOgN6HfB6VzPy4PGx y1gh3U28YQ9GfgVWgYqKuCVZ8+p4p+rAWicdGLpVbu4+SXnoKnV9aZzSMtRR+d7fCoBJ 6BzCy7XA8vD/6A1jdw3ydO2VHGa5le+OVclVJRhJTAnAMf99v3XOyHDA1cDDJfpyd0zi KMwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ys1CVx2S8BFm0hdd9mmIlkJ/zaau9sSCXoT1k+qUtnQ=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=k+ZuyJjy4sed0weLXrRLwItdwF5i+XcjgDD2jNSfoG4GKO0jsd/WAgTmg/n+wOcmb9 8icmtU7+VFzvlG835zHhpW1g4K4MLRZXamWnW4qjpP8kn4EdikvVcTINW0ra7FZZCpvD 6cZ9CqolmLd5Z/zw/66tV9F2qWBiRWsZtRPcf90CBCaaQ33B5aj3mH8RSHms6DJOYsrH VDVDjq88exb2Ezp/InoGYlX/q7VaiWnYVHtsGXyykno8dcVD7TNzLx1JoJIBAQsBTgGI Ax049WpyQk7nnXLL+JjbIRLfvdC39LviEb8S2DVjicc7rEzTGRFC9P+eC380hf103Alf MfJg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="zeS/n/2E"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4332c1sm15299896f8f.27.2025.04.22.07.56.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:56:08 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 14/19] qemu/target_info: Add %target_arch field to TargetInfo Date: Tue, 22 Apr 2025 16:54:56 +0200 Message-ID: <20250422145502.70770-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/qemu/target-info-impl.h | 4 ++++ configs/targets/aarch64-softmmu.c | 1 + configs/targets/arm-softmmu.c | 1 + target-info-stub.c | 1 + 4 files changed, 7 insertions(+) diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h index 4ef54c5136a..e5cd169b49a 100644 --- a/include/qemu/target-info-impl.h +++ b/include/qemu/target-info-impl.h @@ -10,12 +10,16 @@ #define QEMU_TARGET_INFO_IMPL_H #include "qemu/target-info.h" +#include "qapi/qapi-types-machine.h" typedef struct TargetInfo { /* runtime equivalent of TARGET_NAME definition */ const char *const target_name; + /* related to TARGET_ARCH definition */ + SysEmuTarget target_arch; + /* QOM typename machines for this binary must implement */ const char *const machine_typename; diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c index 375e6fa0b7b..ff89401ea34 100644 --- a/configs/targets/aarch64-softmmu.c +++ b/configs/targets/aarch64-softmmu.c @@ -13,6 +13,7 @@ static const TargetInfo target_info_aarch64_system = { .target_name = "aarch64", + .target_arch = SYS_EMU_TARGET_AARCH64, .machine_typename = TYPE_TARGET_AARCH64_MACHINE, }; diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c index d4acdae64f3..22ec9e4faa3 100644 --- a/configs/targets/arm-softmmu.c +++ b/configs/targets/arm-softmmu.c @@ -13,6 +13,7 @@ static const TargetInfo target_info_arm_system = { .target_name = "arm", + .target_arch = SYS_EMU_TARGET_ARM, .machine_typename = TYPE_TARGET_ARM_MACHINE, }; diff --git a/target-info-stub.c b/target-info-stub.c index 218e5898e7f..e573f5c1975 100644 --- a/target-info-stub.c +++ b/target-info-stub.c @@ -12,6 +12,7 @@ static const TargetInfo target_info_stub = { .target_name = TARGET_NAME, + .target_arch = -1, .machine_typename = TYPE_MACHINE, }; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d5acddfsm177355865e9.15.2025.04.22.07.56.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:56:13 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 15/19] qemu/target_info: Add target_aarch64() helper Date: Tue, 22 Apr 2025 16:54:57 +0200 Message-ID: <20250422145502.70770-16-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a helper to distinct the binary is targetting Aarch64 or not. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/qemu/target-info.h | 7 +++++++ target-info.c | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 0224b35b166..395c009baf2 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -24,4 +24,11 @@ const char *target_name(void); */ const char *target_machine_typename(void); +/** + * target_aarch64: + * + * Returns whether the target architecture is Aarch64. + */ +bool target_aarch64(void); + #endif diff --git a/target-info.c b/target-info.c index 0042769e3a2..7f1758ae34f 100644 --- a/target-info.c +++ b/target-info.c @@ -19,3 +19,8 @@ const char *target_machine_typename(void) { return target_info()->machine_typename; } + +bool target_aarch64(void) +{ + return target_info()->target_arch == SYS_EMU_TARGET_AARCH64; +} From patchwork Tue Apr 22 14:54:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882989 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2456720wrs; Tue, 22 Apr 2025 07:56:40 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX6FDaWz9kJ3vN2knrAIk1GbL4WdfUF55wBPLAEI4AnYmczHmlStOl1WCHByWyfQQcChjScEQ==@linaro.org X-Google-Smtp-Source: AGHT+IFKgNlxr9+xoaAjOL9EFFKp8/0XU65/4JmXGjmKm/bz9nN8mNrUl9ridj65VsLwSxr/aFS3 X-Received: by 2002:a05:6214:414:b0:6e8:fde9:5d07 with SMTP id 6a1803df08f44-6f2c457c34bmr262163076d6.26.1745333800066; Tue, 22 Apr 2025 07:56:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745333800; cv=none; d=google.com; s=arc-20240605; b=aCedUEYbMcwNEIZm4fhKwagEfxscAX3prdeMT8t8n3adi2l5Qs6pSEfRPpFnP496rJ mbBfv1LRZGe5HVqqqm7DjhlkQw8ARR26MNLs/oQV29oRMMN8OA4aghg+Lou8q6rl+o9n nGFIOw6I/qh4MLLRlVTO4NHaian36uqX9NWiQ9x7q4z56S9XLU4vOsrI6bENwmwuCdUV 4fYudP7DypGO0Na9fXE1TN1v9qk/Jdr42Cs3RAgtct+T4+gSRAj5ZQd8Hyuonbjy+sbj X0Q4PSoFHlQ1QbOu6UmV0y4hsifPaXNOyXzTvv7hGcdEHwF7jpX5SZqzPKPckSIdVwtc /mCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cV3mM0ENqcZ01CB1iRk+m5MtZMh95fPFHAPIzsRChqE=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=NR56D/Hj0Zu7eFnCpMkEhTXU79OGHelCfil5yTesMyECa1d09oMGZvB2zuwYB7xaw0 OTNOHl6OFJsNJGYrCtszS3ec+T5H3XQ2MqGQB4v2faDk75gHRcMFNgMPtg1/46uL6cz2 uFgdDSqM/qPRaK6jy28ERMCiOyMaH60a9XnNc7+jHhsBdyxdU/BoGJmzrfYXARVDH79p niexWc49NRVcx9KAJThcputcDsNBazTr8fM6yWkxs4so89Juil+qhkcR9xwlYalCfKPl 20XaLlk+nQj51wqwSJnL7+H3TM0nXW06o2UxFvZcAtSKHmLGvMv5V4vN4rKcysr6LVAr ODVQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q5IyOefQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d6dfe2esm179084965e9.34.2025.04.22.07.56.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:56:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 16/19] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Date: Tue, 22 Apr 2025 16:54:58 +0200 Message-ID: <20250422145502.70770-17-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the target-specific TARGET_AARCH64 definition by a call to the generic target_aarch64() helper. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- This removes the last TARGET_AARCH64 in hw/arm/. --- hw/arm/virt.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d7197958f7c..4e11272a3ac 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -32,6 +32,7 @@ #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/option.h" +#include "qemu/target-info.h" #include "monitor/qdev.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" @@ -3137,7 +3138,8 @@ static GSList *virt_get_valid_cpu_types(const MachineState *ms) if (tcg_enabled()) { vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); -#ifdef TARGET_AARCH64 + } + if (tcg_enabled() && target_aarch64()) { vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a55"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a72"))); @@ -3147,15 +3149,14 @@ static GSList *virt_get_valid_cpu_types(const MachineState *ms) vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); -#endif /* TARGET_AARCH64 */ } -#ifdef TARGET_AARCH64 + if (target_aarch64()) { vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57"))); if (kvm_enabled() || hvf_enabled()) { vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("host"))); } -#endif /* TARGET_AARCH64 */ + } vct = g_slist_prepend(vct, g_strdup(ARM_CPU_TYPE_NAME("max"))); return vct; From patchwork Tue Apr 22 14:54:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882996 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2457090wrs; Tue, 22 Apr 2025 07:57:28 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXxXhVNkb7fRI7fTg5MKo0yVDiSclvFYNvdUtabkXuVAbNIhCU/PqUcbVQ5Y1M8do2adWfMGg==@linaro.org X-Google-Smtp-Source: AGHT+IFWUUtvaft29aNiSGKxy3rB1Xu8T5w2IKxD/R/aEXw45cggNCe7CMQdnbnXO2BQkbH7aeD4 X-Received: by 2002:a05:620a:1917:b0:7c7:a604:d28e with SMTP id af79cd13be357-7c927fa7a22mr2339882185a.33.1745333848653; Tue, 22 Apr 2025 07:57:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745333848; cv=none; d=google.com; s=arc-20240605; b=jflcebzgag96BXZWOwRKGl3/xlHv+5ix7CxQTW/zwMSzRrU/zEotDzS82bILkMiuDQ ozjSLc7EGKqgSgu8dWYZZSWzB1xjGGFOk6U+7qn/+6rusF9v1ZOM20L1ZkG/Eb7+WKkG MepP7iSKTfT8oCxjU8BdekMgocdgkHWDo61n//3WK57x0B35t2qZeF8OlA5KWUcWz/7D hVsAJl3AGO8ju2A4ylufNSHRyKifVhKpu8S6OftdjS2vgL7qJd8xrXACbm7vVmtcLD7h vVNFhT++CdOqi9iKIsPSKzE/eMRvMIDvG6DpGozLAeMKEqXLaOp+3tFJVbbCHA3ms4dE 42Kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=//lWNuvQ6UGw8pV9YB76t13j7KMrlQtFLuwBcbqd4aA=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=JmCx8AV0tCmgjDVzP5fMbr590a5KryXuj8f1PIy8BkYHDsBkhiMM9RsrHYdXbuK0A7 i6+c4tKgulUlHKg3C4iwJP1bvBXkzIuJNoiem+Ewe6xXE/xQmapa5MB/kuuOZSuSZuy3 FQBn8LyxXTsxf83D9ALiojRJjXMzQE+KduEnsiQWkcsSgA22tJlYQG5ykaOt/3BZ3iP4 Ekj3ooWm1dgVF6J1LYUDiSjEqcV+wMMC5njSoGtE5ytr9AzWyRFOLXDrQ5ldtLYVWYgu uao22wOgOO3nRitXMuxSWvcrt5k9Lfl0Q9rPyDcFfAtAj+vyqKxvyxXTj1XoXrVU9r5F zbMA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Nigl8Uwa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4408c7cfcabsm13658495e9.0.2025.04.22.07.56.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:56:22 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 17/19] hw/core: Get default_cpu_type calling machine_class_default_cpu_type() Date: Tue, 22 Apr 2025 16:54:59 +0200 Message-ID: <20250422145502.70770-18-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since commit 62b4a227a33 the default cpu type can come from the valid_cpu_types[] array. Call the machine_class_default_cpu_type() instead of accessing MachineClass::default_cpu_type field. Cc: qemu-stable@nongnu.org Fixes: 62b4a227a33 ("hw/core: Add machine_class_default_cpu_type()") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- Cc: Gavin Shan --- hw/core/machine-qmp-cmds.c | 5 +++-- target/ppc/cpu_init.c | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c index 529ce8dd9a0..a8f8f8c8138 100644 --- a/hw/core/machine-qmp-cmds.c +++ b/hw/core/machine-qmp-cmds.c @@ -73,6 +73,7 @@ MachineInfoList *qmp_query_machines(bool has_compat_props, bool compat_props, for (el = machines; el; el = el->next) { MachineClass *mc = el->data; + const char *default_cpu_type = machine_class_default_cpu_type(mc); MachineInfo *info; info = g_malloc0(sizeof(*info)); @@ -91,8 +92,8 @@ MachineInfoList *qmp_query_machines(bool has_compat_props, bool compat_props, info->numa_mem_supported = mc->numa_mem_supported; info->deprecated = !!mc->deprecation_reason; info->acpi = !!object_class_property_find(OBJECT_CLASS(mc), "acpi"); - if (mc->default_cpu_type) { - info->default_cpu_type = g_strdup(mc->default_cpu_type); + if (default_cpu_type) { + info->default_cpu_type = g_strdup(default_cpu_type); } if (mc->default_ram_id) { info->default_ram_id = g_strdup(mc->default_ram_id); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index a3dff0814d1..2c0db2a05a9 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7081,7 +7081,7 @@ ObjectClass *ppc_cpu_class_by_name(const char *name) if (strcmp(name, "max") == 0) { MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); if (mc) { - return object_class_by_name(mc->default_cpu_type); + return object_class_by_name(machine_class_default_cpu_type(mc)); } } #endif From patchwork Tue Apr 22 14:55:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 882993 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2456883wrs; Tue, 22 Apr 2025 07:57:03 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXADhcteo2WLMDeeBemMhql7aKDpT/sEECzxYqI7mqJOqixlFMDJka4ArIJKO4UWJHvW2THQA==@linaro.org X-Google-Smtp-Source: AGHT+IGNZPqCEQGqwkBGF9bL18vRauqMl30nrkORKJsFg6FUdLLTOObWWUQH0p+tpjdpLUjLWtdC X-Received: by 2002:ac8:7c50:0:b0:476:881e:eeda with SMTP id d75a77b69052e-47aec3c43bemr217934121cf.24.1745333823324; Tue, 22 Apr 2025 07:57:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745333823; cv=none; d=google.com; s=arc-20240605; b=Lgqs8YuOYHBGF1JcjEb0oIej7fAfHaAiid6A3kZ1bJ5lr256GcpYNV0Septzayyi5P 4pPb6ppKeiTFo6obwS0oUd1jLOtIXStZ39aAhZQLhp8AEwOUYm78MiRlOFb63NpcGkQv jvYZU7N8LJd+fnFGalE10NRUpGHm9tJI8DpwoMCROKdeSYO/eXZgC7yB4L9uHQIUhGPW OrZUrNn8FzzXKLiLsKLYwU3oRM+X2lTQfO6W9MY6iqBXrRxVhM36kEBo0UuNa51fNTWO smrR34cG8yn8kYB1sTfufy3IchHsz74wm/t+h8zqEmF7eHh59MkSfulpMdFy/TnVah06 Q+bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gKvZwIjHssYNiGyKthzi4mDa1O4lfY8uqFgDa2um9gk=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=Nl4pn0NrS5Wmt04dQUUAi8lWwmVNp2j9hVU0I5mSNXLya1UTuKvE8wIjW0Df4/iftT CWnnguevh3mUTaPpymqezHlH/gWy0kK0dklB4zvuaMtoGRzdKBHYEnf7eSyhuKnhbxLl 6ic2bmVDJpM7D3Xz/QjCtuwwf6gNjuGtwwxcC6wsuL+HhJdMdWIuGX1zUl2fFNfLGfse ySVo9Ba3uisW7tVkO7v0m5yErQMyE6KMlEyanHlmN6qyukHkvyjQdd3N8e9GE9z8JFs2 gLqvzjW1m34P+PNSYi66xAAPb09qCA9sXKqeyFIPFKSuwPbddY+mKi0J4PnwFLRqdUQS 7eYA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ChmoK2cF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d5bbcdasm176925945e9.20.2025.04.22.07.56.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:56:26 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 18/19] hw/core: Introduce MachineClass::get_default_cpu_type() helper Date: Tue, 22 Apr 2025 16:55:00 +0200 Message-ID: <20250422145502.70770-19-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org MachineClass::get_default_cpu_type() runs once the machine is created, being able to evaluate runtime checks; it returns the machine default CPU type. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/hw/boards.h | 6 ++++++ hw/core/machine.c | 10 ++++++++++ system/vl.c | 2 +- 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index be0c0f04804..6a0b02db42e 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -25,6 +25,11 @@ OBJECT_DECLARE_TYPE(MachineState, MachineClass, MACHINE) extern MachineState *current_machine; +/** + * machine_default_cpu_type: Return the machine default CPU type. + * @ms: Machine state + */ +const char *machine_default_cpu_type(const MachineState *ms); /** * machine_class_default_cpu_type: Return the machine default CPU type. * @mc: Machine class @@ -310,6 +315,7 @@ struct MachineClass { int numa_mem_align_shift; const char * const *valid_cpu_types; GSList *(*get_valid_cpu_types)(const MachineState *ms); + const char *(*get_default_cpu_type)(const MachineState *ms); strList *allowed_dynamic_sysbus_devices; bool auto_enable_numa_with_memhp; bool auto_enable_numa_with_memdev; diff --git a/hw/core/machine.c b/hw/core/machine.c index 8b40735ef98..89169a2dbae 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1538,6 +1538,16 @@ const char *machine_class_default_cpu_type(MachineClass *mc) return mc->default_cpu_type; } +const char *machine_default_cpu_type(const MachineState *ms) +{ + MachineClass *mc = MACHINE_GET_CLASS(ms); + + if (mc->get_default_cpu_type) { + return mc->get_default_cpu_type(ms); + } + return machine_class_default_cpu_type(mc); +} + static bool is_cpu_type_supported(const MachineState *machine, Error **errp) { MachineClass *mc = MACHINE_GET_CLASS(machine); diff --git a/system/vl.c b/system/vl.c index e8706a9ce87..338f9d75289 100644 --- a/system/vl.c +++ b/system/vl.c @@ -3825,7 +3825,7 @@ void qemu_init(int argc, char **argv) migration_object_init(); /* parse features once if machine provides default cpu_type */ - current_machine->cpu_type = machine_class_default_cpu_type(machine_class); + current_machine->cpu_type = machine_default_cpu_type(current_machine); if (cpu_option) { current_machine->cpu_type = parse_cpu_option(cpu_option); } From patchwork Tue Apr 22 14:55:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883003 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp2459730wrs; Tue, 22 Apr 2025 08:02:09 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX1H5vzJFB7g1oSvDqM4WAQ8JZgplIHYOXuRzeUzRycV5qKhr22fOOe15EycLP6nyXgubtjYQ==@linaro.org X-Google-Smtp-Source: AGHT+IFn4OdnBnRENjiiPSdXQt6BkxU3I959DLch4rBAJ3cfLRRQARsWWui9kNPFJsfDp4mT5NGW X-Received: by 2002:a05:651c:542:b0:30b:b00f:9507 with SMTP id 38308e7fff4ca-31090501b07mr39238381fa.24.1745334128626; Tue, 22 Apr 2025 08:02:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745334128; cv=none; d=google.com; s=arc-20240605; b=RDJvhx6Fuo3DBGGFRfnq3uiL4upWVtqPNu8ymTJv6Wrgei52mAhNeqtS8hiwBUDjBW tHOAQsdd6FGPFa6bBH22XIkulSZaHEw61/Vjk+1HAhIBi6c599bC68M7+6Lol6sW195F +PYBtXYsU7hqf8exOaP7Y7MBx8hjN1a0doinHmX+Pa7mVdIJ0vJCsUbVkwLtEfoiOqHp j0l4GVakpaHC2z8ECJ6Kj5uC6lpgb2tjtagHvtw5QlpnEtocGToYwvWDEECaG1wJhybL 3x9NozuQeox/Qdj9ruJ9/T8+aDJThW0NIgMWWd5ADtWlqDt1urCI+4f4ddgebSFLoPqC W9WQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oZGQgvHwQWyT1UXG05e/L40v1r7rbpXm4CP7YDA65nc=; fh=98FKcUbfHOMAWlQQi9/5y14VVYgcGa56vjU1mKYkvXI=; b=M8YfJ5CL1jmDjmH3+UuwQjVd4T6R7mAsjkCr6Yi8dXDoIUnblg9Cc7HclFQq3zHsvY R1z14d/TNR394Hetxk6FZ9us7iiSzfDAzmRilnouNjYwso+6741soRsIaatGCgvFJFKL XvVpzxnXTfE1S8vbSu9xIklL8yyI92SFxUhe4zXyVL5k3qMh9VbE7ixATuFBkbidJBY0 tohsl3OL32rHzXtR1cv6DB+Q29W+YQQoIm+FBZwuMq8SQuH9N2ZDm4ffbJIEjCoO3a4g BUOAhBx194bpuDjZmM0KmF/VRGlrslZqnDyeybxq9Tz4gf/cDUo90rl9WjyFHOjskPdt k/Qg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IGIH7LQt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d5ace47sm175128875e9.15.2025.04.22.07.56.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:56:31 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 19/19] hw/arm/virt: Get default CPU type at runtime Date: Tue, 22 Apr 2025 16:55:01 +0200 Message-ID: <20250422145502.70770-20-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250422145502.70770-1-philmd@linaro.org> References: <20250422145502.70770-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Prefer MachineClass::get_default_cpu_type() over MachineClass::default_cpu_type to get CPU type, evaluating TCG availability at runtime calling tcg_enabled(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- This removes the last use of CONFIG_TCG in hw/arm/. --- hw/arm/virt.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 4e11272a3ac..df8dda812cc 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3131,6 +3131,12 @@ static int virt_hvf_get_physical_address_range(MachineState *ms) return requested_ipa_size; } +static const char *virt_get_default_cpu_type(const MachineState *ms) +{ + return tcg_enabled() ? ARM_CPU_TYPE_NAME("cortex-a15") + : ARM_CPU_TYPE_NAME("max"); +} + static GSList *virt_get_valid_cpu_types(const MachineState *ms) { GSList *vct = NULL; @@ -3188,11 +3194,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) mc->minimum_page_bits = 12; mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = virt_cpu_index_to_props; -#ifdef CONFIG_TCG - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); -#else - mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); -#endif + mc->get_default_cpu_type = virt_get_default_cpu_type; mc->get_valid_cpu_types = virt_get_valid_cpu_types; mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; mc->kvm_type = virt_kvm_type;