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Tue, 22 Apr 2025 04:04:16 -0700 (PDT) From: Stephan Gerhold Date: Tue, 22 Apr 2025 13:03:49 +0200 Subject: [PATCH v2 2/6] arm64: dts: qcom: msm8916/39: Introduce new UART console pinctrl Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250422-msm8916-console-pinctrl-v2-2-f345b7a53c91@linaro.org> References: <20250422-msm8916-console-pinctrl-v2-0-f345b7a53c91@linaro.org> In-Reply-To: <20250422-msm8916-console-pinctrl-v2-0-f345b7a53c91@linaro.org> To: Bjorn Andersson , Konrad Dybcio Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sam Day , Casey Connolly , Konrad Dybcio X-Mailer: b4 0.14.2 At the moment, msm8916/39.dtsi have two inconsistent UART pinctrl templates that are used by all the boards: - &blsp_uart1_default configures all 4 pins (TX, RX, CTS, RTS), some boards then limit this to just RX and TX - &blsp_uart2_default only configures 2 pins (TX, RX), even though UART2 also supports CTS/RTS It's difficult to define a generic pinctrl template for all UART use cases, since they are quite different in practice. The main use case for most of the 40+ MSM8916/39-based boards upstream is the UART debug console. The current generic template is lacking some properties to work properly: - bias-pull-up for RX: Generally, UART is push-pull and does not need pull up/down. Both sides drive TX, so RX should never be floating. This is why the current pinctrl in msm8916/39.dtsi uses bias-disable. However, this assumes that UART is always connected. For the debug console this will be rarely the case on mobile devices, only during debugging sessions. The rest of the time, the RX pin is floating. This has never caused massive problems, but it's obvious now that this needs fixing: (1) In U-Boot, we have been fighting with problems with autoboot for years. Most of the time, there is a single \0 byte ("break event") read during boot, which interrupts the autoboot process. I tried to work around that by inserting some random delay [1], but it turned out this is also not working reliably on all boards. What happens is: Since RX is floating, it switches randomly between high or low. A long low state is interpreted as "break event" (\0). (2) In postmarketOS, we used to have the "magic SysRq key" enabled by default for the serial console. We had to disable this at some point, because there was a small number of users who were reporting sysrq spam in the kernel log, possibly even crashes/panics triggered by sysrq. What likely happened is: SysRq is triggered by sending a "break event", like in (1). With enough luck, you could even trigger any of the SysRq actions if the RX pin switches between high and low (e.g. because of noise introduced by the LTE radio close by). We can fix this using bias-pull-up, but this may be unneeded, unexpected, or even unwanted for other UART use cases. - bootph-all: U-Boot needs to know which pinctrl to apply during early boot stages, so we should specify "bootph-all" for the console UART pinctrl. Without bootph-all, the bias-pull-up won't be applied early enough in U-Boot to avoid the problem with autoboot in point (1) above. It doesn't make sense to specify this for the other UART instances. bootph-all is a generic property documented in dt-schema bootph.yaml. Define these two additional properties only for the debug UART console, by defining a new pinctrl template specifically for that. In the following commits, boards will be converted to use these where appropriate. [1]: https://source.denx.de/u-boot/u-boot/-/commit/ad7e967738a9c639e07cf50b83ffccdf9a8537b0 Reviewed-by: Konrad Dybcio Signed-off-by: Stephan Gerhold --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 45 ++++++++++++++++++++++++++++++++++- arch/arm64/boot/dts/qcom/msm8939.dtsi | 45 ++++++++++++++++++++++++++++++++++- 2 files changed, 88 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 733c17d0495617e683d362d7b7aae59078f2a0b0..07ae0b921afa1fec7350467cf1b299fe91112a60 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1247,6 +1247,31 @@ blsp_uart1_sleep: blsp-uart1-sleep-state { bias-pull-down; }; + blsp_uart1_console_default: blsp-uart1-console-default-state { + tx-pins { + pins = "gpio0"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-disable; + bootph-all; + }; + + rx-pins { + pins = "gpio1"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-pull-up; + bootph-all; + }; + }; + + blsp_uart1_console_sleep: blsp-uart1-console-sleep-state { + pins = "gpio0", "gpio1"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + blsp_uart2_default: blsp-uart2-default-state { pins = "gpio4", "gpio5"; function = "blsp_uart2"; @@ -1254,7 +1279,25 @@ blsp_uart2_default: blsp-uart2-default-state { bias-disable; }; - blsp_uart2_sleep: blsp-uart2-sleep-state { + blsp_uart2_console_default: blsp-uart2-console-default-state { + tx-pins { + pins = "gpio4"; + function = "blsp_uart2"; + drive-strength = <16>; + bias-disable; + bootph-all; + }; + + rx-pins { + pins = "gpio5"; + function = "blsp_uart2"; + drive-strength = <16>; + bias-pull-up; + bootph-all; + }; + }; + + blsp_uart2_sleep: blsp_uart2_console_sleep: blsp-uart2-sleep-state { pins = "gpio4", "gpio5"; function = "gpio"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 67ff2ffc6e455fa5ad8a664a161873507cab6391..52a99aea210e04f04f3d25696ecd6b9c604c743a 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -919,6 +919,31 @@ blsp_uart1_sleep: blsp-uart1-sleep-state { bias-pull-down; }; + blsp_uart1_console_default: blsp-uart1-console-default-state { + tx-pins { + pins = "gpio0"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-disable; + bootph-all; + }; + + rx-pins { + pins = "gpio1"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-pull-up; + bootph-all; + }; + }; + + blsp_uart1_console_sleep: blsp-uart1-console-sleep-state { + pins = "gpio0", "gpio1"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + blsp_uart2_default: blsp-uart2-default-state { pins = "gpio4", "gpio5"; function = "blsp_uart2"; @@ -926,7 +951,25 @@ blsp_uart2_default: blsp-uart2-default-state { bias-disable; }; - blsp_uart2_sleep: blsp-uart2-sleep-state { + blsp_uart2_console_default: blsp-uart2-console-default-state { + tx-pins { + pins = "gpio4"; + function = "blsp_uart2"; + drive-strength = <16>; + bias-disable; + bootph-all; + }; + + rx-pins { + pins = "gpio5"; + function = "blsp_uart2"; + drive-strength = <16>; + bias-pull-up; + bootph-all; + }; + }; + + blsp_uart2_sleep: blsp_uart2_console_sleep: blsp-uart2-sleep-state { pins = "gpio4", "gpio5"; function = "gpio"; drive-strength = <2>; From patchwork Tue Apr 22 11:03:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 883211 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B1FA27703B for ; Tue, 22 Apr 2025 11:04:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745319863; cv=none; b=mk/PABnXqNvwPo+PCxgBVBViGeYSjW3I02njLEicI8bzH8Nz88mgkFgR8PUrfsHnpgAhh70nB+oA4llaCVsKW3rD9z7r2YdlNQewtRWqKu2e5UGZ6GqDWcJluS/cy6Gf3UKJSOJ4TlrNRPWOTRZGDKUNrj6SyK0Irj6hrJi8lJY= ARC-Message-Signature: i=1; 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Tue, 22 Apr 2025 04:04:19 -0700 (PDT) Received: from [127.0.0.2] ([2a02:2454:ff21:ef41:8847:e39a:2a2f:e614]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d5acddfsm169609725e9.15.2025.04.22.04.04.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 04:04:18 -0700 (PDT) From: Stephan Gerhold Date: Tue, 22 Apr 2025 13:03:51 +0200 Subject: [PATCH v2 4/6] arm64: dts: qcom: msm8916-motorola: Use UART1 console pinctrl Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250422-msm8916-console-pinctrl-v2-4-f345b7a53c91@linaro.org> References: <20250422-msm8916-console-pinctrl-v2-0-f345b7a53c91@linaro.org> In-Reply-To: <20250422-msm8916-console-pinctrl-v2-0-f345b7a53c91@linaro.org> To: Bjorn Andersson , Konrad Dybcio Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sam Day , Casey Connolly , Konrad Dybcio X-Mailer: b4 0.14.2 The Motorola MSM8916-based smartphones all use UART1 with 2 pins (TX, RX) as debug UART console, so make use of the new &blsp_uart1_console_default template. This applies the needed bias-pull-up to avoid garbage input, bootph-all for U-Boot and avoids having to override the UART pins. Reviewed-by: Konrad Dybcio Signed-off-by: Stephan Gerhold --- arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi index 48134e5ff524fd5708db7b9c3a567ec3f751868c..4e202e7ed7db1921f347ca8b4a01ccec593a8d8e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi @@ -69,8 +69,8 @@ rmi4-f11@11 { }; &blsp_uart1 { - pinctrl-0 = <&blsp_uart1_default>; - pinctrl-1 = <&blsp_uart1_sleep>; + pinctrl-0 = <&blsp_uart1_console_default>; + pinctrl-1 = <&blsp_uart1_console_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; }; @@ -132,14 +132,6 @@ &wcnss_mem { status = "okay"; }; -/* CTS/RTX are not used */ -&blsp_uart1_default { - pins = "gpio0", "gpio1"; -}; -&blsp_uart1_sleep { - pins = "gpio0", "gpio1"; -}; - &tlmm { gpio_keys_default: gpio-keys-default-state { pins = "gpio107"; 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Tue, 22 Apr 2025 04:04:20 -0700 (PDT) From: Stephan Gerhold Date: Tue, 22 Apr 2025 13:03:53 +0200 Subject: [PATCH v2 6/6] arm64: dts: qcom: msm8939: Drop generic UART pinctrl templates Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250422-msm8916-console-pinctrl-v2-6-f345b7a53c91@linaro.org> References: <20250422-msm8916-console-pinctrl-v2-0-f345b7a53c91@linaro.org> In-Reply-To: <20250422-msm8916-console-pinctrl-v2-0-f345b7a53c91@linaro.org> To: Bjorn Andersson , Konrad Dybcio Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sam Day , Casey Connolly X-Mailer: b4 0.14.2 Remove the generic UART pinctrl templates from msm8939.dtsi and copy the definition for the custom UART use cases into the board DT files. This makes it clear that the set of pins/pull etc are specific to the board and UART use case. No functional change. Signed-off-by: Stephan Gerhold --- arch/arm64/boot/dts/qcom/apq8039-t2.dts | 22 ++++++++++++++-------- arch/arm64/boot/dts/qcom/msm8939.dtsi | 23 +---------------------- 2 files changed, 15 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts index 4aa0ad19bc0f7fde6f5f3a93cdb6be19fb4f1f65..38c281f0fe65ccfc49de70eaef2a970323ecebc8 100644 --- a/arch/arm64/boot/dts/qcom/apq8039-t2.dts +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -122,14 +122,6 @@ &blsp_uart1 { status = "okay"; }; -&blsp_uart1_default { - pins = "gpio0", "gpio1"; -}; - -&blsp_uart1_sleep { - pins = "gpio0", "gpio1"; -}; - &blsp_uart2 { pinctrl-0 = <&blsp_uart2_console_default>; pinctrl-1 = <&blsp_uart2_console_sleep>; @@ -329,6 +321,20 @@ &tlmm { "USBC_GPIO7_1V8", /* GPIO_120 */ "NC"; + blsp_uart1_default: blsp-uart1-default-state { + pins = "gpio0", "gpio1"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-disable; + }; + + blsp_uart1_sleep: blsp-uart1-sleep-state { + pins = "gpio0", "gpio1"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + pinctrl_backlight: backlight-state { pins = "gpio98"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 52a99aea210e04f04f3d25696ecd6b9c604c743a..68b92fdb996c26e7a1aadedf0f52e1afca85c4ab 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -905,20 +905,6 @@ blsp_spi6_sleep: blsp-spi6-sleep-state { bias-pull-down; }; - blsp_uart1_default: blsp-uart1-default-state { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "blsp_uart1"; - drive-strength = <16>; - bias-disable; - }; - - blsp_uart1_sleep: blsp-uart1-sleep-state { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - blsp_uart1_console_default: blsp-uart1-console-default-state { tx-pins { pins = "gpio0"; @@ -944,13 +930,6 @@ blsp_uart1_console_sleep: blsp-uart1-console-sleep-state { bias-pull-down; }; - blsp_uart2_default: blsp-uart2-default-state { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - drive-strength = <16>; - bias-disable; - }; - blsp_uart2_console_default: blsp-uart2-console-default-state { tx-pins { pins = "gpio4"; @@ -969,7 +948,7 @@ rx-pins { }; }; - blsp_uart2_sleep: blsp_uart2_console_sleep: blsp-uart2-sleep-state { + blsp_uart2_console_sleep: blsp-uart2-console-sleep-state { pins = "gpio4", "gpio5"; function = "gpio"; drive-strength = <2>;