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[209.85.220.65]) by mx.google.com with SMTPS id r5sor21760675pgs.13.2020.05.13.05.31.11 for (Google Transport Security); Wed, 13 May 2020 05:31:11 -0700 (PDT) Received-SPF: pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="PS+YsMZ/"; spf=pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=sumit.garg@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=35pGnu9GnHmW69MSaocb29vu4F27l0KIarsDVNEAZrs=; b=PS+YsMZ/Zjl8zLt8n+vVIoBmdHhsi2Dq4e+dcodSYmh3RnrU2XIcdXMN1kTpJOKFMq qsWfzjJQYbsRL8bodPEB10TbDvQti37IU6Z4D9w3dJZ7l0y5sBpSGOZI8JVV38sDR1jm mWmc0nJ4Y/OcUoleFHZRSyoV1rpS+GAZs+0w9oitF95/cBVWAsr3kLWZlH/DyMV1Q+Zn i7fCY0dhEoUukvrrqrb3fjX8wqjzPilsP30olrCUiD1yNqjQIYTnDlVQPfpmXv1hKZU5 2UUEhsBdJPXe6vTkqxv2Mc0ilxzlCgcERIOpEcTByOvAXFiyISv2FJB3Y8RzkwZ+6/sQ akzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=35pGnu9GnHmW69MSaocb29vu4F27l0KIarsDVNEAZrs=; b=rdPFd1KXrYYzQo3/T/kifUQ/h9DnD3cDySSuEa21SmKksLJH0Iw5N7a8EJvktmTLc0 UXAWjNiZqhGPE5Srr/6yZZwB5tUiaMen6upCpQGcB+ly2kyDwNFQ+1+nWkVBNwrWdOtw H/gcp89npL6waLLULCZapEJqDPCXXhLNfzdVIA6FV/2xwTk5gOCBcJSp0PPAhoiCTAA5 hZgnMVhJdQD604stmAVhOnnCYx0CPr4wihEL4l3VeR5mjO92E3yaax57EqsqWUoKESv0 Ijvv61sQwchDjAIQnEJK8mtWezrHoPlydlkIimbfRlp0U6Fnfa/o7zVl3lellGDlVcuO O0eQ== X-Gm-Message-State: AOAM531wG+tYD/U/aREAHdYubxLOdyhl9ndFC93zicHeMFqAySWHQOXr RFnxQl6fQsEkX1ADmu4a2IS+UuAt X-Google-Smtp-Source: ABdhPJxLldqgbMP5eVVTJluH5ZmwQtIC0uDaN81mQ20EuPGBFbF3oNGnbNKXc5raeq63o7StTBxnHg== X-Received: by 2002:a63:a042:: with SMTP id u2mr6517369pgn.346.1589373071240; Wed, 13 May 2020 05:31:11 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([117.252.68.136]) by smtp.gmail.com with ESMTPSA id x23sm12936669pgf.32.2020.05.13.05.31.07 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 May 2020 05:31:10 -0700 (PDT) From: Sumit Garg To: daniel.thompson@linaro.org Cc: patches@linaro.org, Sumit Garg Subject: [RFC] arm64: Enable perf events based hard lockup detector Date: Wed, 13 May 2020 18:00:48 +0530 Message-Id: <1589373048-25932-1-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 With the recent feature added to enable perf events to use pseudo NMIs as interrupts on platforms which support GICv3 or later, its now been possible to enable hard lockup detector (or NMI watchdog) on arm64 platforms. So enable corresponding support. One thing to note here is that normally lockup detector is initialized just after the early initcalls but PMU on arm64 comes up much later as device_initcall(). So we need to re-initialize lockup detection once PMU has been initialized. Signed-off-by: Sumit Garg --- This patch is dependent on perf NMI patch-set [1]. [1] https://patchwork.kernel.org/cover/11047407/ arch/arm64/Kconfig | 2 ++ arch/arm64/kernel/perf_event.c | 32 ++++++++++++++++++++++++++++++-- drivers/perf/arm_pmu.c | 11 +++++++++++ include/linux/perf/arm_pmu.h | 2 ++ 4 files changed, 45 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 40fb05d..36f75c2 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -160,6 +160,8 @@ config ARM64 select HAVE_NMI select HAVE_PATA_PLATFORM select HAVE_PERF_EVENTS + select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI + select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP select HAVE_REGS_AND_STACK_ACCESS_API diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 3ad5c8f..df57360 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include /* ARMv8 Cortex-A53 specific event types. */ #define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2 @@ -1190,10 +1192,21 @@ static struct platform_driver armv8_pmu_driver = { static int __init armv8_pmu_driver_init(void) { + int ret; + if (acpi_disabled) - return platform_driver_register(&armv8_pmu_driver); + ret = platform_driver_register(&armv8_pmu_driver); else - return arm_pmu_acpi_probe(armv8_pmuv3_init); + ret = arm_pmu_acpi_probe(armv8_pmuv3_init); + + /* + * Try to re-initialize lockup detector after PMU init in + * case PMU events are triggered via NMIs. + */ + if (arm_pmu_irq_is_nmi()) + lockup_detector_init(); + + return ret; } device_initcall(armv8_pmu_driver_init) @@ -1225,3 +1238,18 @@ void arch_perf_update_userpage(struct perf_event *event, userpg->time_shift = (u16)shift; userpg->time_offset = -now; } + +#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF +#define SAFE_MAX_CPU_FREQ 4000000000UL // 4 GHz +u64 hw_nmi_get_sample_period(int watchdog_thresh) +{ + unsigned int cpu = smp_processor_id(); + unsigned int max_cpu_freq; + + max_cpu_freq = cpufreq_get_hw_max_freq(cpu); + if (max_cpu_freq) + return (u64)max_cpu_freq * 1000 * watchdog_thresh; + else + return (u64)SAFE_MAX_CPU_FREQ * watchdog_thresh; +} +#endif diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index f96cfc4..691dfc9 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -718,6 +718,17 @@ static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu) return per_cpu(hw_events->irq, cpu); } +bool arm_pmu_irq_is_nmi(void) +{ + const struct pmu_irq_ops *irq_ops; + + irq_ops = per_cpu(cpu_irq_ops, smp_processor_id()); + if (irq_ops == &pmunmi_ops || irq_ops == &percpu_pmunmi_ops) + return true; + else + return false; +} + /* * PMU hardware loses all context when a CPU goes offline. * When a CPU is hotplugged back in, since some hardware registers are diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index d9b8b76..a71f029 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -155,6 +155,8 @@ int arm_pmu_acpi_probe(armpmu_init_fn init_fn); static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; } #endif +bool arm_pmu_irq_is_nmi(void); + /* Internal functions only for core arm_pmu code */ struct arm_pmu *armpmu_alloc(void); struct arm_pmu *armpmu_alloc_atomic(void);