From patchwork Wed Apr 23 17:56:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chen, Jason Z" X-Patchwork-Id: 883684 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54B56281363 for ; Wed, 23 Apr 2025 17:55:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745430952; cv=none; b=VDnzBGZt0Z0cZQcoe7837t7/sGG8Xk0Qwge1d5VnZYiLcfQyjnNHsTjcxdqTqt7oQLJKfZNICQj0Xz/AenJ6AONYWur4Co6GYvH0jegX0oZsyimiG/me1h9FzHS+7fa/rzpN07uKYEoZQEISWgH9sf5ojMFS1/89wJBo42blxGc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745430952; c=relaxed/simple; bh=NGiRyAURXNjN5sw3Hg5tgXh76+lIlQ3q7/NzpzuqUgI=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=WY2lY6vEUmMl6t8AgxxL76tW33eiIr889CO7GvccicmTxlU4GPulabZiOHRkQoT+XgbzRwsact+Pip5Pp74UoSshBF+xuB3H8r/UxLSe4Yaq8Xkg6/55J5RDdZJwj/g6hhCiML2fgFBiZqQPp43zCXwtZL4yqC+uwVeZPF5R2Ps= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=fxZXmqIZ; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="fxZXmqIZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1745430951; x=1776966951; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=NGiRyAURXNjN5sw3Hg5tgXh76+lIlQ3q7/NzpzuqUgI=; b=fxZXmqIZrumQAklQXZCi9Drhu4WF0+V3L7zc8h788MdqwtAEQ2IS2r/D SNU4k/XjieiNyza263zxi8onslSV1mEKasRioMc/eF7i+VckZtVcfdmX3 fxvfnCAQO/V5gcR3tLdh1Ne/kgOPOcrGiurzGu0snmod9WNMaQ04iZfkR xvbOaLLnC2CAlYdsa5JHDeEHW5SfAamatiR9Hs3LbyaygX+7JgYcTPjYS mveipV9EDVtDvHU7FhLEEyjLpgh93puiHUfMme17w7wWz/Eb9EvhYVEQI qHXj3ar8sHIf+zObB7W/V0OyzGhIKWbVdkPWuH/Yp5KQY3B8u38rruHAc w==; X-CSE-ConnectionGUID: xzOw3OKlRoGZNbfteFSjTQ== X-CSE-MsgGUID: CyOGEBckRGGzbhrj0PloVQ== X-IronPort-AV: E=McAfee;i="6700,10204,11412"; a="69529306" X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="69529306" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2025 10:55:50 -0700 X-CSE-ConnectionGUID: U037Fo1FT6ySVE/hdwdKiA== X-CSE-MsgGUID: VD8MLz6ATMKgYcpSUurNQA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="137467682" Received: from jasonz-ms-7d25.itwn.intel.com ([10.225.65.15]) by fmviesa004.fm.intel.com with ESMTP; 23 Apr 2025 10:55:47 -0700 From: "Chen, Jason Z" To: linux-media@vger.kernel.org Cc: sakari.ailus@linux.intel.com, bingbu.cao@linux.intel.com, jimmy.su@intel.com, daxing.li@intel.com, hao.yao@intel.com, qingwu.zhang@intel.com, arun.t@intel.com, Jason Chen Subject: [PATCH v8 1/6] media: ov08x40: Separate the lane configuration and PLL settings Date: Thu, 24 Apr 2025 01:56:31 +0800 Message-Id: <20250423175636.1338374-1-jason.z.chen@intel.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Jason Chen To prepare upcoming support of multiple sensor modes, this change separates the lane configuration and PLL settings from the original mode-specific settings. Signed-off-by: Jason Chen --- drivers/media/i2c/ov08x40.c | 56 ++++++++----------------------------- 1 file changed, 12 insertions(+), 44 deletions(-) diff --git a/drivers/media/i2c/ov08x40.c b/drivers/media/i2c/ov08x40.c index b9682264e2f5..11899d4feb06 100644 --- a/drivers/media/i2c/ov08x40.c +++ b/drivers/media/i2c/ov08x40.c @@ -168,17 +168,7 @@ static const struct ov08x40_reg mipi_data_rate_800mbps[] = { {0x5a1f, 0x0e}, {0x5a27, 0x0e}, {0x6002, 0x2e}, -}; - -static const struct ov08x40_reg mode_3856x2416_regs[] = { - {0x5000, 0x5d}, - {0x5001, 0x20}, - {0x5008, 0xb0}, - {0x50c1, 0x00}, - {0x53c1, 0x00}, - {0x5f40, 0x00}, - {0x5f41, 0x40}, - {0x0300, 0x3a}, + {0x0300, 0x3a}, /* PLL CTRL */ {0x0301, 0xc8}, {0x0302, 0x31}, {0x0303, 0x03}, @@ -211,6 +201,17 @@ static const struct ov08x40_reg mode_3856x2416_regs[] = { {0x032f, 0xa0}, {0x0350, 0x00}, {0x0360, 0x01}, + {0x3012, 0x41}, /* MIPI SC Lanes */ +}; + +static const struct ov08x40_reg mode_3856x2416_regs[] = { + {0x5000, 0x5d}, + {0x5001, 0x20}, + {0x5008, 0xb0}, + {0x50c1, 0x00}, + {0x53c1, 0x00}, + {0x5f40, 0x00}, + {0x5f41, 0x40}, {0x1216, 0x60}, {0x1217, 0x5b}, {0x1218, 0x00}, @@ -690,39 +691,6 @@ static const struct ov08x40_reg mode_1928x1208_regs[] = { {0x53c1, 0x00}, {0x5f40, 0x00}, {0x5f41, 0x40}, - {0x0300, 0x3a}, - {0x0301, 0xc8}, - {0x0302, 0x31}, - {0x0303, 0x03}, - {0x0304, 0x01}, - {0x0305, 0xa1}, - {0x0306, 0x04}, - {0x0307, 0x01}, - {0x0308, 0x03}, - {0x0309, 0x03}, - {0x0310, 0x0a}, - {0x0311, 0x02}, - {0x0312, 0x01}, - {0x0313, 0x08}, - {0x0314, 0x66}, - {0x0315, 0x00}, - {0x0316, 0x34}, - {0x0320, 0x02}, - {0x0321, 0x03}, - {0x0323, 0x05}, - {0x0324, 0x01}, - {0x0325, 0xb8}, - {0x0326, 0x4a}, - {0x0327, 0x04}, - {0x0329, 0x00}, - {0x032a, 0x05}, - {0x032b, 0x00}, - {0x032c, 0x00}, - {0x032d, 0x00}, - {0x032e, 0x02}, - {0x032f, 0xa0}, - {0x0350, 0x00}, - {0x0360, 0x01}, {0x1216, 0x60}, {0x1217, 0x5b}, {0x1218, 0x00}, From patchwork Wed Apr 23 17:56:32 2025 Content-Type: text/plain; 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23 Apr 2025 10:55:50 -0700 From: "Chen, Jason Z" To: linux-media@vger.kernel.org Cc: sakari.ailus@linux.intel.com, bingbu.cao@linux.intel.com, jimmy.su@intel.com, daxing.li@intel.com, hao.yao@intel.com, qingwu.zhang@intel.com, arun.t@intel.com, Jason Chen Subject: [PATCH v8 2/6] media: ov08x40: Add support for 2/4 lanes at 1500 Mbps Date: Thu, 24 Apr 2025 01:56:32 +0800 Message-Id: <20250423175636.1338374-2-jason.z.chen@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250423175636.1338374-1-jason.z.chen@intel.com> References: <20250423175636.1338374-1-jason.z.chen@intel.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Jason Chen Add register settings for 1500Mbps to support both 2-lane and 4-lane configurations Signed-off-by: Jason Chen --- drivers/media/i2c/ov08x40.c | 441 ++++++++++++++++++++++++++++++++++++ 1 file changed, 441 insertions(+) diff --git a/drivers/media/i2c/ov08x40.c b/drivers/media/i2c/ov08x40.c index 11899d4feb06..56d330bca2de 100644 --- a/drivers/media/i2c/ov08x40.c +++ b/drivers/media/i2c/ov08x40.c @@ -107,6 +107,7 @@ enum { OV08X40_LINK_FREQ_400MHZ_INDEX, + OV08X40_LINK_FREQ_749MHZ_INDEX, }; struct ov08x40_reg { @@ -204,6 +205,392 @@ static const struct ov08x40_reg mipi_data_rate_800mbps[] = { {0x3012, 0x41}, /* MIPI SC Lanes */ }; +static const struct ov08x40_reg mipi_data_rate_1500mbps[] = { + {0x0103, 0x01}, + {0x1000, 0x00}, + {0x1601, 0xd0}, + {0x1001, 0x04}, + {0x5004, 0x53}, + {0x5110, 0x00}, + {0x5111, 0x14}, + {0x5112, 0x01}, + {0x5113, 0x7b}, + {0x5114, 0x00}, + {0x5152, 0xa3}, + {0x5a52, 0x1f}, + {0x5a1a, 0x0e}, + {0x5a1b, 0x10}, + {0x5a1f, 0x0e}, + {0x5a27, 0x0e}, + {0x6002, 0x2e}, + {0x0300, 0x3a}, /* PLL */ + {0x0301, 0x88}, + {0x0302, 0x31}, + {0x0303, 0x05}, + {0x0304, 0x01}, + {0x0305, 0x38}, + {0x0306, 0x04}, + {0x0307, 0x00}, + {0x0308, 0x03}, + {0x0309, 0x02}, + {0x0310, 0x0a}, + {0x0311, 0x02}, + {0x0312, 0x01}, + {0x0313, 0x08}, + {0x0314, 0x00}, + {0x0315, 0x00}, + {0x0316, 0x2c}, + {0x0320, 0x02}, + {0x0321, 0x03}, + {0x0323, 0x05}, + {0x0324, 0x01}, + {0x0325, 0xb8}, + {0x0326, 0x4a}, + {0x0327, 0x04}, + {0x0329, 0x00}, + {0x032a, 0x05}, + {0x032b, 0x00}, + {0x032c, 0x00}, + {0x032d, 0x00}, + {0x032e, 0x02}, + {0x032f, 0xa0}, + {0x0350, 0x00}, + {0x0360, 0x01}, + {0x3012, 0x21}, /* MIPI SC Lanes */ +}; + +static const struct ov08x40_reg mode_3856x2176_regs_800mbps[] = { + {0x5000, 0x5d}, + {0x5001, 0x20}, + {0x3012, 0x41}, + {0x3400, 0x1c}, + {0x3419, 0x13}, + {0x341a, 0x89}, + {0x3426, 0x00}, + {0x3501, 0x02}, + {0x3502, 0x00}, + {0x3508, 0x01}, + {0x3509, 0x00}, + {0x3541, 0x01}, + {0x3542, 0x00}, + {0x3548, 0x01}, + {0x3712, 0x51}, + {0x3714, 0x24}, + {0x3761, 0x17}, + {0x376e, 0x03}, + {0x37b0, 0x00}, + {0x37b1, 0xab}, + {0x37b3, 0x82}, + {0x37b4, 0x00}, + {0x37b5, 0xe4}, + {0x37b6, 0x01}, + {0x37b7, 0xee}, + {0x3820, 0x00}, + {0x3821, 0x04}, + {0x3823, 0x04}, + {0x384d, 0x80}, + {0x3894, 0x00}, + {0x400b, 0x08}, + {0x400d, 0x08}, + {0x4016, 0x2d}, + {0x4501, 0x00}, + {0x4542, 0x00}, + {0x4837, 0x14}, + {0x4850, 0x42}, + {0x3a20, 0x00}, + {0x3939, 0x9d}, + {0x3902, 0x0e}, + {0x3903, 0x0e}, + {0x3904, 0x0e}, + {0x3905, 0x0e}, + {0x3906, 0x07}, + {0x3907, 0x0d}, + {0x3908, 0x11}, + {0x3909, 0x12}, + {0x390c, 0x33}, + {0x390d, 0x66}, + {0x390e, 0xaa}, + {0x3915, 0x90}, + {0x3917, 0x90}, + {0x3440, 0xa4}, + {0x3a26, 0x1d}, + {0x3a2c, 0x4a}, + {0x3a32, 0x55}, + {0x392d, 0x02}, + {0x3930, 0x08}, + {0x3933, 0x0c}, + {0x392a, 0x54}, + {0x392b, 0xa8}, + {0x380d, 0x80}, + {0x380e, 0x13}, + {0x380f, 0x88}, + {0x3803, 0x70}, + {0x3807, 0x0f}, + {0x3808, 0x0f}, + {0x3809, 0x10}, + {0x380a, 0x08}, + {0x380b, 0x80}, + {0x3811, 0x08}, + {0x3813, 0x10}, + {0x3501, 0x10}, + {0x3508, 0x0f}, + {0x3509, 0x80}, + {0x3813, 0x0f}, +}; + +/* OV08X 1C 3856x2176_DPHY1500M-2L */ +static const struct ov08x40_reg mode_3856x2176_regs_1500mbps[] = { + {0x5000, 0x5d}, + {0x5001, 0x20}, + {0x3012, 0x21}, + {0x3400, 0x1c}, + {0x3419, 0x12}, + {0x341a, 0x99}, + {0x3426, 0x00}, + {0x3501, 0x02}, + {0x3502, 0x00}, + {0x3508, 0x01}, + {0x3509, 0x00}, + {0x3541, 0x01}, + {0x3542, 0x00}, + {0x3548, 0x01}, + {0x3712, 0x51}, + {0x3714, 0x24}, + {0x3761, 0x17}, + {0x376e, 0x03}, + {0x37b0, 0x00}, + {0x37b1, 0xab}, + {0x37b3, 0x82}, + {0x37b4, 0x00}, + {0x37b5, 0xe4}, + {0x37b6, 0x01}, + {0x37b7, 0xee}, + {0x3803, 0x70}, + {0x3807, 0x0f}, + {0x3808, 0x0f}, + {0x3809, 0x10}, + {0x380a, 0x08}, + {0x380b, 0x80}, + {0x380d, 0xa0}, + {0x380e, 0x12}, + {0x380f, 0x98}, + {0x3811, 0x08}, + {0x3813, 0x10}, + {0x3820, 0x00}, + {0x3821, 0x04}, + {0x3823, 0x04}, + {0x384d, 0xa0}, + {0x3894, 0x00}, + {0x400b, 0x08}, + {0x400d, 0x08}, + {0x4016, 0x2d}, + {0x4501, 0x00}, + {0x4542, 0x00}, + {0x4837, 0x0a}, + {0x4850, 0x47}, + {0x3a20, 0x00}, + {0x3939, 0x9d}, + {0x3902, 0x0e}, + {0x3903, 0x0e}, + {0x3904, 0x0e}, + {0x3905, 0x0e}, + {0x3906, 0x07}, + {0x3907, 0x0d}, + {0x3908, 0x11}, + {0x3909, 0x12}, + {0x390c, 0x33}, + {0x390d, 0x66}, + {0x390e, 0xaa}, + {0x3915, 0x90}, + {0x3917, 0x90}, + {0x3440, 0xa4}, + {0x3a26, 0x1d}, + {0x3a2c, 0x4a}, + {0x3a32, 0x55}, + {0x392d, 0x02}, + {0x3930, 0x08}, + {0x3933, 0x0c}, + {0x392a, 0x54}, + {0x392b, 0xa8}, + {0x3501, 0x10}, + {0x3508, 0x0f}, + {0x3509, 0x80}, + {0x3813, 0x0f}, +}; + +/* OV08X 4C1stg 1928x1088_DPHY1500M-2L 30fps */ +static const struct ov08x40_reg mode_1928x1088_regs_1500mbps[] = { + {0x5000, 0x55}, + {0x5001, 0x00}, + {0x3012, 0x21}, + {0x3400, 0x30}, + {0x3419, 0x08}, + {0x341a, 0x4f}, + {0x3426, 0x00}, + {0x3501, 0x02}, + {0x3502, 0x00}, + {0x3508, 0x01}, + {0x3509, 0x00}, + {0x3541, 0x01}, + {0x3542, 0x00}, + {0x3548, 0x01}, + {0x3712, 0x50}, + {0x3714, 0x21}, + {0x3761, 0x28}, + {0x376e, 0x07}, + {0x37b0, 0x01}, + {0x37b1, 0x0f}, + {0x37b3, 0xd6}, + {0x37b4, 0x01}, + {0x37b5, 0x48}, + {0x37b6, 0x02}, + {0x37b7, 0x40}, + {0x3803, 0x78}, + {0x3807, 0x07}, + {0x3808, 0x07}, + {0x3809, 0x88}, + {0x380a, 0x04}, + {0x380b, 0x40}, + {0x380d, 0xf0}, + {0x380e, 0x08}, + {0x380f, 0x4e}, + {0x3811, 0x04}, + {0x3813, 0x03}, + {0x3820, 0x02}, + {0x3821, 0x14}, + {0x3823, 0x84}, + {0x384d, 0xf0}, + {0x3894, 0x03}, + {0x400b, 0x04}, + {0x400d, 0x04}, + {0x4016, 0x27}, + {0x4501, 0x10}, + {0x4542, 0x01}, + {0x4837, 0x0a}, + {0x4850, 0x47}, + {0x4911, 0x00}, + {0x4919, 0x00}, + {0x491a, 0x40}, + {0x4920, 0x04}, + {0x4921, 0x00}, + {0x4922, 0x04}, + {0x4923, 0x00}, + {0x4924, 0x04}, + {0x4925, 0x00}, + {0x4926, 0x04}, + {0x4927, 0x00}, + {0x4930, 0x00}, + {0x4931, 0x00}, + {0x4932, 0x00}, + {0x4933, 0x00}, + {0x4934, 0x00}, + {0x4935, 0x00}, + {0x4936, 0x00}, + {0x4937, 0x00}, + {0x4940, 0x00}, + {0x4941, 0x80}, + {0x4942, 0x00}, + {0x4943, 0x80}, + {0x4944, 0x00}, + {0x4945, 0x80}, + {0x4946, 0x00}, + {0x4947, 0x80}, + {0x4960, 0x00}, + {0x4961, 0x00}, + {0x4962, 0x00}, + {0x4963, 0x00}, + {0x4964, 0x00}, + {0x4965, 0x00}, + {0x4966, 0x00}, + {0x4967, 0x00}, + {0x4968, 0x00}, + {0x4969, 0x00}, + {0x496a, 0x00}, + {0x496b, 0x00}, + {0x496c, 0x00}, + {0x496d, 0x00}, + {0x496e, 0x00}, + {0x496f, 0x00}, + {0x4970, 0x00}, + {0x4971, 0x00}, + {0x4972, 0x00}, + {0x4973, 0x00}, + {0x4974, 0x00}, + {0x4975, 0x00}, + {0x4976, 0x00}, + {0x4977, 0x00}, + {0x4978, 0x00}, + {0x4979, 0x00}, + {0x497a, 0x00}, + {0x497b, 0x00}, + {0x497c, 0x00}, + {0x497d, 0x00}, + {0x497e, 0x00}, + {0x497f, 0x00}, + {0x49e0, 0x00}, + {0x49e1, 0x00}, + {0x49e2, 0x00}, + {0x49e3, 0x00}, + {0x49e4, 0x00}, + {0x49e5, 0x00}, + {0x49e6, 0x00}, + {0x49e7, 0x00}, + {0x49e8, 0x00}, + {0x49e9, 0x80}, + {0x49ea, 0x00}, + {0x49eb, 0x80}, + {0x49ec, 0x00}, + {0x49ed, 0x80}, + {0x49ee, 0x00}, + {0x49ef, 0x80}, + {0x49f0, 0x02}, + {0x49f1, 0x04}, + {0x3a20, 0x05}, + {0x3939, 0x6b}, + {0x3902, 0x10}, + {0x3903, 0x10}, + {0x3904, 0x10}, + {0x3905, 0x10}, + {0x3906, 0x01}, + {0x3907, 0x0b}, + {0x3908, 0x10}, + {0x3909, 0x13}, + {0x390b, 0x11}, + {0x390c, 0x21}, + {0x390d, 0x32}, + {0x390e, 0x76}, + {0x3a1a, 0x1c}, + {0x3a26, 0x17}, + {0x3a2c, 0x50}, + {0x3a32, 0x4f}, + {0x3ace, 0x01}, + {0x3ad2, 0x01}, + {0x3ad6, 0x01}, + {0x3ada, 0x01}, + {0x3ade, 0x01}, + {0x3ae2, 0x01}, + {0x3aee, 0x01}, + {0x3af2, 0x01}, + {0x3af6, 0x01}, + {0x3afa, 0x01}, + {0x3afe, 0x01}, + {0x3b02, 0x01}, + {0x3b06, 0x01}, + {0x392d, 0x01}, + {0x3930, 0x09}, + {0x3933, 0x0d}, + {0x392a, 0x52}, + {0x392b, 0xa3}, + {0x340b, 0x1b}, + {0x3501, 0x01}, + {0x3508, 0x0f}, + {0x3509, 0x00}, + {0x3541, 0x00}, + {0x3542, 0x80}, + {0x3548, 0x0f}, + {0x3813, 0x03}, +}; + static const struct ov08x40_reg mode_3856x2416_regs[] = { {0x5000, 0x5d}, {0x5001, 0x20}, @@ -1185,6 +1572,7 @@ static const char * const ov08x40_test_pattern_menu[] = { /* Configurations for supported link frequencies */ #define OV08X40_LINK_FREQ_400MHZ 400000000ULL +#define OV08X40_LINK_FREQ_749MHZ 749000000ULL #define OV08X40_SCLK_96MHZ 96000000ULL #define OV08X40_XVCLK 19200000 #define OV08X40_DATA_LANES 4 @@ -1204,6 +1592,7 @@ static u64 link_freq_to_pixel_rate(u64 f) /* Menu items for LINK_FREQ V4L2 control */ static const s64 link_freq_menu_items[] = { OV08X40_LINK_FREQ_400MHZ, + OV08X40_LINK_FREQ_749MHZ, }; /* Link frequency configs */ @@ -1214,6 +1603,12 @@ static const struct ov08x40_link_freq_config link_freq_configs[] = { .regs = mipi_data_rate_800mbps, } }, + [OV08X40_LINK_FREQ_749MHZ_INDEX] = { + .reg_list = { + .num_of_regs = ARRAY_SIZE(mipi_data_rate_1500mbps), + .regs = mipi_data_rate_1500mbps, + } + }, }; /* Mode configs */ @@ -1233,6 +1628,22 @@ static const struct ov08x40_mode supported_modes[] = { .exposure_shift = 1, .exposure_margin = OV08X40_EXPOSURE_MAX_MARGIN, }, + { + .width = 3856, + .height = 2176, + .vts_def = OV08X40_VTS_30FPS, + .vts_min = OV08X40_VTS_30FPS, + .llp = 0x10aa, /* in normal mode, tline time = 2 * HTS / SCLK */ + .lanes = 4, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_3856x2176_regs_800mbps), + .regs = mode_3856x2176_regs_800mbps, + }, + .link_freq_index = OV08X40_LINK_FREQ_400MHZ_INDEX, + .exposure_shift = 1, + .exposure_margin = OV08X40_EXPOSURE_MAX_MARGIN, + }, + { .width = 1928, .height = 1208, @@ -1248,6 +1659,36 @@ static const struct ov08x40_mode supported_modes[] = { .exposure_shift = 0, .exposure_margin = OV08X40_EXPOSURE_BIN_MAX_MARGIN, }, + { + .width = 3856, + .height = 2176, + .vts_def = OV08X40_VTS_30FPS, + .vts_min = OV08X40_VTS_30FPS, + .llp = 0x10aa, /* in normal mode, tline time = 2 * HTS / SCLK */ + .lanes = 2, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_3856x2176_regs_1500mbps), + .regs = mode_3856x2176_regs_1500mbps, + }, + .link_freq_index = OV08X40_LINK_FREQ_749MHZ_INDEX, + .exposure_shift = 1, + .exposure_margin = OV08X40_EXPOSURE_MAX_MARGIN, + }, + { + .width = 1928, + .height = 1088, + .vts_def = OV08X40_VTS_BIN_30FPS, + .vts_min = OV08X40_VTS_BIN_30FPS, + .llp = 0x960, + .lanes = 2, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_1928x1088_regs_1500mbps), + .regs = mode_1928x1088_regs_1500mbps, + }, + .link_freq_index = OV08X40_LINK_FREQ_749MHZ_INDEX, + .exposure_shift = 0, + .exposure_margin = OV08X40_EXPOSURE_MAX_MARGIN, + }, }; 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23 Apr 2025 10:55:54 -0700 From: "Chen, Jason Z" To: linux-media@vger.kernel.org Cc: sakari.ailus@linux.intel.com, bingbu.cao@linux.intel.com, jimmy.su@intel.com, daxing.li@intel.com, hao.yao@intel.com, qingwu.zhang@intel.com, arun.t@intel.com, Jason Chen Subject: [PATCH v8 3/6] media: ov08x40: Remove common register settings from resolution-specific table Date: Thu, 24 Apr 2025 01:56:33 +0800 Message-Id: <20250423175636.1338374-3-jason.z.chen@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250423175636.1338374-1-jason.z.chen@intel.com> References: <20250423175636.1338374-1-jason.z.chen@intel.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Jason Chen Prepare for refactoring register table by removing register entries that are common across all modes from resolution-specific table These will be moved into a shared common register array in the next commit. Signed-off-by: Jason Chen --- drivers/media/i2c/ov08x40.c | 802 ------------------------------------ 1 file changed, 802 deletions(-) diff --git a/drivers/media/i2c/ov08x40.c b/drivers/media/i2c/ov08x40.c index 56d330bca2de..4cd4ef77e0aa 100644 --- a/drivers/media/i2c/ov08x40.c +++ b/drivers/media/i2c/ov08x40.c @@ -594,426 +594,52 @@ static const struct ov08x40_reg mode_1928x1088_regs_1500mbps[] = { static const struct ov08x40_reg mode_3856x2416_regs[] = { {0x5000, 0x5d}, {0x5001, 0x20}, - {0x5008, 0xb0}, - {0x50c1, 0x00}, - {0x53c1, 0x00}, - {0x5f40, 0x00}, - {0x5f41, 0x40}, - {0x1216, 0x60}, - {0x1217, 0x5b}, - {0x1218, 0x00}, - {0x1220, 0x24}, - {0x198a, 0x00}, - {0x198b, 0x01}, - {0x198e, 0x00}, - {0x198f, 0x01}, - {0x3009, 0x04}, {0x3012, 0x41}, - {0x3015, 0x00}, - {0x3016, 0xb0}, - {0x3017, 0xf0}, - {0x3018, 0xf0}, - {0x3019, 0xd2}, - {0x301a, 0xb0}, - {0x301c, 0x81}, - {0x301d, 0x02}, - {0x301e, 0x80}, - {0x3022, 0xf0}, - {0x3025, 0x89}, - {0x3030, 0x03}, - {0x3044, 0xc2}, - {0x3050, 0x35}, - {0x3051, 0x60}, - {0x3052, 0x25}, - {0x3053, 0x00}, - {0x3054, 0x00}, - {0x3055, 0x02}, - {0x3056, 0x80}, - {0x3057, 0x80}, - {0x3058, 0x80}, - {0x3059, 0x00}, - {0x3107, 0x86}, {0x3400, 0x1c}, - {0x3401, 0x80}, - {0x3402, 0x8c}, {0x3419, 0x13}, {0x341a, 0x89}, - {0x341b, 0x30}, - {0x3420, 0x00}, - {0x3421, 0x00}, - {0x3422, 0x00}, - {0x3423, 0x00}, - {0x3424, 0x00}, - {0x3425, 0x00}, {0x3426, 0x00}, - {0x3427, 0x00}, - {0x3428, 0x0f}, - {0x3429, 0x00}, - {0x342a, 0x00}, - {0x342b, 0x00}, - {0x342c, 0x00}, - {0x342d, 0x00}, - {0x342e, 0x00}, - {0x342f, 0x11}, - {0x3430, 0x11}, - {0x3431, 0x10}, - {0x3432, 0x00}, - {0x3433, 0x00}, - {0x3434, 0x00}, - {0x3435, 0x00}, - {0x3436, 0x00}, - {0x3437, 0x00}, - {0x3442, 0x02}, - {0x3443, 0x02}, - {0x3444, 0x07}, - {0x3450, 0x00}, - {0x3451, 0x00}, - {0x3452, 0x18}, - {0x3453, 0x18}, - {0x3454, 0x00}, - {0x3455, 0x80}, - {0x3456, 0x08}, - {0x3500, 0x00}, {0x3501, 0x02}, {0x3502, 0x00}, - {0x3504, 0x4c}, - {0x3506, 0x30}, - {0x3507, 0x00}, {0x3508, 0x01}, {0x3509, 0x00}, - {0x350a, 0x01}, - {0x350b, 0x00}, - {0x350c, 0x00}, - {0x3540, 0x00}, {0x3541, 0x01}, {0x3542, 0x00}, - {0x3544, 0x4c}, - {0x3546, 0x30}, - {0x3547, 0x00}, {0x3548, 0x01}, - {0x3549, 0x00}, - {0x354a, 0x01}, - {0x354b, 0x00}, - {0x354c, 0x00}, - {0x3688, 0x02}, - {0x368a, 0x2e}, - {0x368e, 0x71}, - {0x3696, 0xd1}, - {0x3699, 0x00}, - {0x369a, 0x00}, - {0x36a4, 0x00}, - {0x36a6, 0x00}, - {0x3711, 0x00}, {0x3712, 0x51}, - {0x3713, 0x00}, {0x3714, 0x24}, - {0x3716, 0x00}, - {0x3718, 0x07}, - {0x371a, 0x1c}, - {0x371b, 0x00}, - {0x3720, 0x08}, - {0x3725, 0x32}, - {0x3727, 0x05}, - {0x3760, 0x02}, {0x3761, 0x17}, - {0x3762, 0x02}, - {0x3763, 0x02}, - {0x3764, 0x02}, - {0x3765, 0x2c}, - {0x3766, 0x04}, - {0x3767, 0x2c}, - {0x3768, 0x02}, - {0x3769, 0x00}, - {0x376b, 0x20}, {0x376e, 0x03}, {0x37b0, 0x00}, {0x37b1, 0xab}, - {0x37b2, 0x01}, {0x37b3, 0x82}, {0x37b4, 0x00}, {0x37b5, 0xe4}, {0x37b6, 0x01}, {0x37b7, 0xee}, - {0x3800, 0x00}, - {0x3801, 0x00}, - {0x3802, 0x00}, {0x3803, 0x00}, - {0x3804, 0x0f}, - {0x3805, 0x1f}, - {0x3806, 0x09}, {0x3807, 0x7f}, {0x3808, 0x0f}, {0x3809, 0x10}, {0x380a, 0x09}, {0x380b, 0x70}, - {0x380c, 0x02}, {0x380d, 0x80}, {0x380e, 0x13}, {0x380f, 0x88}, - {0x3810, 0x00}, {0x3811, 0x08}, - {0x3812, 0x00}, {0x3813, 0x07}, - {0x3814, 0x11}, - {0x3815, 0x11}, {0x3820, 0x00}, {0x3821, 0x04}, - {0x3822, 0x00}, {0x3823, 0x04}, - {0x3828, 0x0f}, - {0x382a, 0x80}, - {0x382e, 0x41}, - {0x3837, 0x08}, - {0x383a, 0x81}, - {0x383b, 0x81}, - {0x383c, 0x11}, - {0x383d, 0x11}, - {0x383e, 0x00}, - {0x383f, 0x38}, - {0x3840, 0x00}, - {0x3847, 0x00}, - {0x384a, 0x00}, - {0x384c, 0x02}, {0x384d, 0x80}, - {0x3856, 0x50}, - {0x3857, 0x30}, - {0x3858, 0x80}, - {0x3859, 0x40}, - {0x3860, 0x00}, - {0x3888, 0x00}, - {0x3889, 0x00}, - {0x388a, 0x00}, - {0x388b, 0x00}, - {0x388c, 0x00}, - {0x388d, 0x00}, - {0x388e, 0x00}, - {0x388f, 0x00}, {0x3894, 0x00}, - {0x3895, 0x00}, - {0x3c84, 0x00}, - {0x3d85, 0x8b}, - {0x3daa, 0x80}, - {0x3dab, 0x14}, - {0x3dac, 0x80}, - {0x3dad, 0xc8}, - {0x3dae, 0x81}, - {0x3daf, 0x7b}, - {0x3f00, 0x10}, - {0x3f01, 0x11}, - {0x3f06, 0x0d}, - {0x3f07, 0x0b}, - {0x3f08, 0x0d}, - {0x3f09, 0x0b}, - {0x3f0a, 0x01}, - {0x3f0b, 0x11}, - {0x3f0c, 0x33}, - {0x4001, 0x07}, - {0x4007, 0x20}, - {0x4008, 0x00}, - {0x4009, 0x05}, - {0x400a, 0x00}, {0x400b, 0x08}, - {0x400c, 0x00}, {0x400d, 0x08}, - {0x400e, 0x14}, - {0x4010, 0xf4}, - {0x4011, 0x03}, - {0x4012, 0x55}, - {0x4015, 0x00}, {0x4016, 0x2d}, - {0x4017, 0x00}, - {0x4018, 0x0f}, - {0x401b, 0x08}, - {0x401c, 0x00}, - {0x401d, 0x10}, - {0x401e, 0x02}, - {0x401f, 0x00}, - {0x4050, 0x06}, - {0x4051, 0xff}, - {0x4052, 0xff}, - {0x4053, 0xff}, - {0x4054, 0xff}, - {0x4055, 0xff}, - {0x4056, 0xff}, - {0x4057, 0x7f}, - {0x4058, 0x00}, - {0x4059, 0x00}, - {0x405a, 0x00}, - {0x405b, 0x00}, - {0x405c, 0x07}, - {0x405d, 0xff}, - {0x405e, 0x07}, - {0x405f, 0xff}, - {0x4080, 0x78}, - {0x4081, 0x78}, - {0x4082, 0x78}, - {0x4083, 0x78}, - {0x4019, 0x00}, - {0x401a, 0x40}, - {0x4020, 0x04}, - {0x4021, 0x00}, - {0x4022, 0x04}, - {0x4023, 0x00}, - {0x4024, 0x04}, - {0x4025, 0x00}, - {0x4026, 0x04}, - {0x4027, 0x00}, - {0x4030, 0x00}, - {0x4031, 0x00}, - {0x4032, 0x00}, - {0x4033, 0x00}, - {0x4034, 0x00}, - {0x4035, 0x00}, - {0x4036, 0x00}, - {0x4037, 0x00}, - {0x4040, 0x00}, - {0x4041, 0x80}, - {0x4042, 0x00}, - {0x4043, 0x80}, - {0x4044, 0x00}, - {0x4045, 0x80}, - {0x4046, 0x00}, - {0x4047, 0x80}, - {0x4060, 0x00}, - {0x4061, 0x00}, - {0x4062, 0x00}, - {0x4063, 0x00}, - {0x4064, 0x00}, - {0x4065, 0x00}, - {0x4066, 0x00}, - {0x4067, 0x00}, - {0x4068, 0x00}, - {0x4069, 0x00}, - {0x406a, 0x00}, - {0x406b, 0x00}, - {0x406c, 0x00}, - {0x406d, 0x00}, - {0x406e, 0x00}, - {0x406f, 0x00}, - {0x4070, 0x00}, - {0x4071, 0x00}, - {0x4072, 0x00}, - {0x4073, 0x00}, - {0x4074, 0x00}, - {0x4075, 0x00}, - {0x4076, 0x00}, - {0x4077, 0x00}, - {0x4078, 0x00}, - {0x4079, 0x00}, - {0x407a, 0x00}, - {0x407b, 0x00}, - {0x407c, 0x00}, - {0x407d, 0x00}, - {0x407e, 0x00}, - {0x407f, 0x00}, - {0x40e0, 0x00}, - {0x40e1, 0x00}, - {0x40e2, 0x00}, - {0x40e3, 0x00}, - {0x40e4, 0x00}, - {0x40e5, 0x00}, - {0x40e6, 0x00}, - {0x40e7, 0x00}, - {0x40e8, 0x00}, - {0x40e9, 0x80}, - {0x40ea, 0x00}, - {0x40eb, 0x80}, - {0x40ec, 0x00}, - {0x40ed, 0x80}, - {0x40ee, 0x00}, - {0x40ef, 0x80}, - {0x40f0, 0x02}, - {0x40f1, 0x04}, - {0x4300, 0x00}, - {0x4301, 0x00}, - {0x4302, 0x00}, - {0x4303, 0x00}, - {0x4304, 0x00}, - {0x4305, 0x00}, - {0x4306, 0x00}, - {0x4307, 0x00}, - {0x4308, 0x00}, - {0x4309, 0x00}, - {0x430a, 0x00}, - {0x430b, 0xff}, - {0x430c, 0xff}, - {0x430d, 0x00}, - {0x430e, 0x00}, - {0x4315, 0x00}, - {0x4316, 0x00}, - {0x4317, 0x00}, - {0x4318, 0x00}, - {0x4319, 0x00}, - {0x431a, 0x00}, - {0x431b, 0x00}, - {0x431c, 0x00}, - {0x4500, 0x07}, {0x4501, 0x00}, - {0x4502, 0x00}, - {0x4503, 0x0f}, - {0x4504, 0x80}, - {0x4506, 0x01}, - {0x4509, 0x05}, - {0x450c, 0x00}, - {0x450d, 0x20}, - {0x450e, 0x00}, - {0x450f, 0x00}, - {0x4510, 0x00}, - {0x4523, 0x00}, - {0x4526, 0x00}, {0x4542, 0x00}, - {0x4543, 0x00}, - {0x4544, 0x00}, - {0x4545, 0x00}, - {0x4546, 0x00}, - {0x4547, 0x10}, - {0x4602, 0x00}, - {0x4603, 0x15}, - {0x460b, 0x07}, - {0x4680, 0x11}, - {0x4686, 0x00}, - {0x4687, 0x00}, - {0x4700, 0x00}, - {0x4800, 0x64}, - {0x4806, 0x40}, - {0x480b, 0x10}, - {0x480c, 0x80}, - {0x480f, 0x32}, - {0x4813, 0xe4}, {0x4837, 0x14}, {0x4850, 0x42}, - {0x4884, 0x04}, - {0x4c00, 0xf8}, - {0x4c01, 0x44}, - {0x4c03, 0x00}, - {0x4d00, 0x00}, - {0x4d01, 0x16}, - {0x4d04, 0x10}, - {0x4d05, 0x00}, - {0x4d06, 0x0c}, - {0x4d07, 0x00}, - {0x3d84, 0x04}, - {0x3680, 0xa4}, - {0x3682, 0x80}, - {0x3601, 0x40}, - {0x3602, 0x90}, - {0x3608, 0x0a}, - {0x3938, 0x09}, - {0x3a74, 0x84}, - {0x3a99, 0x84}, - {0x3ab9, 0xa6}, - {0x3aba, 0xba}, - {0x3b12, 0x84}, - {0x3b14, 0xbb}, - {0x3b15, 0xbf}, - {0x3a29, 0x26}, - {0x3a1f, 0x8a}, - {0x3a22, 0x91}, - {0x3a25, 0x96}, - {0x3a28, 0xb4}, - {0x3a2b, 0xba}, - {0x3a2e, 0xbf}, - {0x3a31, 0xc1}, {0x3a20, 0x00}, {0x3939, 0x9d}, {0x3902, 0x0e}, @@ -1024,48 +650,21 @@ static const struct ov08x40_reg mode_3856x2416_regs[] = { {0x3907, 0x0d}, {0x3908, 0x11}, {0x3909, 0x12}, - {0x360f, 0x99}, {0x390c, 0x33}, {0x390d, 0x66}, {0x390e, 0xaa}, - {0x3911, 0x90}, - {0x3913, 0x90}, {0x3915, 0x90}, {0x3917, 0x90}, - {0x3b3f, 0x9d}, - {0x3b45, 0x9d}, - {0x3b1b, 0xc9}, - {0x3b21, 0xc9}, {0x3440, 0xa4}, - {0x3a23, 0x15}, {0x3a26, 0x1d}, {0x3a2c, 0x4a}, - {0x3a2f, 0x18}, {0x3a32, 0x55}, - {0x3b0a, 0x01}, - {0x3b0b, 0x00}, - {0x3b0e, 0x01}, - {0x3b0f, 0x00}, - {0x392c, 0x02}, {0x392d, 0x02}, - {0x392e, 0x04}, - {0x392f, 0x03}, {0x3930, 0x08}, - {0x3931, 0x07}, - {0x3932, 0x10}, {0x3933, 0x0c}, - {0x3609, 0x08}, - {0x3921, 0x0f}, - {0x3928, 0x15}, - {0x3929, 0x2a}, {0x392a, 0x54}, {0x392b, 0xa8}, - {0x3426, 0x10}, - {0x3407, 0x01}, - {0x3404, 0x01}, - {0x3500, 0x00}, {0x3501, 0x10}, - {0x3502, 0x10}, {0x3508, 0x0f}, {0x3509, 0x80}, }; @@ -1073,426 +672,52 @@ static const struct ov08x40_reg mode_3856x2416_regs[] = { static const struct ov08x40_reg mode_1928x1208_regs[] = { {0x5000, 0x55}, {0x5001, 0x00}, - {0x5008, 0xb0}, - {0x50c1, 0x00}, - {0x53c1, 0x00}, - {0x5f40, 0x00}, - {0x5f41, 0x40}, - {0x1216, 0x60}, - {0x1217, 0x5b}, - {0x1218, 0x00}, - {0x1220, 0x24}, - {0x198a, 0x00}, - {0x198b, 0x01}, - {0x198e, 0x00}, - {0x198f, 0x01}, - {0x3009, 0x04}, {0x3012, 0x41}, - {0x3015, 0x00}, - {0x3016, 0xb0}, - {0x3017, 0xf0}, - {0x3018, 0xf0}, - {0x3019, 0xd2}, - {0x301a, 0xb0}, - {0x301c, 0x81}, - {0x301d, 0x02}, - {0x301e, 0x80}, - {0x3022, 0xf0}, - {0x3025, 0x89}, - {0x3030, 0x03}, - {0x3044, 0xc2}, - {0x3050, 0x35}, - {0x3051, 0x60}, - {0x3052, 0x25}, - {0x3053, 0x00}, - {0x3054, 0x00}, - {0x3055, 0x02}, - {0x3056, 0x80}, - {0x3057, 0x80}, - {0x3058, 0x80}, - {0x3059, 0x00}, - {0x3107, 0x86}, {0x3400, 0x1c}, - {0x3401, 0x80}, - {0x3402, 0x8c}, {0x3419, 0x08}, {0x341a, 0xaf}, - {0x341b, 0x30}, - {0x3420, 0x00}, - {0x3421, 0x00}, - {0x3422, 0x00}, - {0x3423, 0x00}, - {0x3424, 0x00}, - {0x3425, 0x00}, {0x3426, 0x00}, - {0x3427, 0x00}, - {0x3428, 0x0f}, - {0x3429, 0x00}, - {0x342a, 0x00}, - {0x342b, 0x00}, - {0x342c, 0x00}, - {0x342d, 0x00}, - {0x342e, 0x00}, - {0x342f, 0x11}, - {0x3430, 0x11}, - {0x3431, 0x10}, - {0x3432, 0x00}, - {0x3433, 0x00}, - {0x3434, 0x00}, - {0x3435, 0x00}, - {0x3436, 0x00}, - {0x3437, 0x00}, - {0x3442, 0x02}, - {0x3443, 0x02}, - {0x3444, 0x07}, - {0x3450, 0x00}, - {0x3451, 0x00}, - {0x3452, 0x18}, - {0x3453, 0x18}, - {0x3454, 0x00}, - {0x3455, 0x80}, - {0x3456, 0x08}, - {0x3500, 0x00}, {0x3501, 0x02}, {0x3502, 0x00}, - {0x3504, 0x4c}, - {0x3506, 0x30}, - {0x3507, 0x00}, {0x3508, 0x01}, {0x3509, 0x00}, - {0x350a, 0x01}, - {0x350b, 0x00}, - {0x350c, 0x00}, - {0x3540, 0x00}, {0x3541, 0x01}, {0x3542, 0x00}, - {0x3544, 0x4c}, - {0x3546, 0x30}, - {0x3547, 0x00}, {0x3548, 0x01}, - {0x3549, 0x00}, - {0x354a, 0x01}, - {0x354b, 0x00}, - {0x354c, 0x00}, - {0x3688, 0x02}, - {0x368a, 0x2e}, - {0x368e, 0x71}, - {0x3696, 0xd1}, - {0x3699, 0x00}, - {0x369a, 0x00}, - {0x36a4, 0x00}, - {0x36a6, 0x00}, - {0x3711, 0x00}, {0x3712, 0x50}, - {0x3713, 0x00}, {0x3714, 0x21}, - {0x3716, 0x00}, - {0x3718, 0x07}, - {0x371a, 0x1c}, - {0x371b, 0x00}, - {0x3720, 0x08}, - {0x3725, 0x32}, - {0x3727, 0x05}, - {0x3760, 0x02}, {0x3761, 0x28}, - {0x3762, 0x02}, - {0x3763, 0x02}, - {0x3764, 0x02}, - {0x3765, 0x2c}, - {0x3766, 0x04}, - {0x3767, 0x2c}, - {0x3768, 0x02}, - {0x3769, 0x00}, - {0x376b, 0x20}, {0x376e, 0x07}, {0x37b0, 0x01}, {0x37b1, 0x0f}, - {0x37b2, 0x01}, {0x37b3, 0xd6}, {0x37b4, 0x01}, {0x37b5, 0x48}, {0x37b6, 0x02}, {0x37b7, 0x40}, - {0x3800, 0x00}, - {0x3801, 0x00}, - {0x3802, 0x00}, {0x3803, 0x00}, - {0x3804, 0x0f}, - {0x3805, 0x1f}, - {0x3806, 0x09}, {0x3807, 0x7f}, {0x3808, 0x07}, {0x3809, 0x88}, {0x380a, 0x04}, {0x380b, 0xb8}, - {0x380c, 0x02}, {0x380d, 0xd0}, {0x380e, 0x11}, {0x380f, 0x5c}, - {0x3810, 0x00}, {0x3811, 0x04}, - {0x3812, 0x00}, {0x3813, 0x03}, - {0x3814, 0x11}, - {0x3815, 0x11}, {0x3820, 0x02}, {0x3821, 0x14}, - {0x3822, 0x00}, {0x3823, 0x04}, - {0x3828, 0x0f}, - {0x382a, 0x80}, - {0x382e, 0x41}, - {0x3837, 0x08}, - {0x383a, 0x81}, - {0x383b, 0x81}, - {0x383c, 0x11}, - {0x383d, 0x11}, - {0x383e, 0x00}, - {0x383f, 0x38}, - {0x3840, 0x00}, - {0x3847, 0x00}, - {0x384a, 0x00}, - {0x384c, 0x02}, {0x384d, 0xd0}, - {0x3856, 0x50}, - {0x3857, 0x30}, - {0x3858, 0x80}, - {0x3859, 0x40}, - {0x3860, 0x00}, - {0x3888, 0x00}, - {0x3889, 0x00}, - {0x388a, 0x00}, - {0x388b, 0x00}, - {0x388c, 0x00}, - {0x388d, 0x00}, - {0x388e, 0x00}, - {0x388f, 0x00}, {0x3894, 0x00}, - {0x3895, 0x00}, - {0x3c84, 0x00}, - {0x3d85, 0x8b}, - {0x3daa, 0x80}, - {0x3dab, 0x14}, - {0x3dac, 0x80}, - {0x3dad, 0xc8}, - {0x3dae, 0x81}, - {0x3daf, 0x7b}, - {0x3f00, 0x10}, - {0x3f01, 0x11}, - {0x3f06, 0x0d}, - {0x3f07, 0x0b}, - {0x3f08, 0x0d}, - {0x3f09, 0x0b}, - {0x3f0a, 0x01}, - {0x3f0b, 0x11}, - {0x3f0c, 0x33}, - {0x4001, 0x07}, - {0x4007, 0x20}, - {0x4008, 0x00}, - {0x4009, 0x05}, - {0x400a, 0x00}, {0x400b, 0x04}, - {0x400c, 0x00}, {0x400d, 0x04}, - {0x400e, 0x14}, - {0x4010, 0xf4}, - {0x4011, 0x03}, - {0x4012, 0x55}, - {0x4015, 0x00}, {0x4016, 0x27}, - {0x4017, 0x00}, - {0x4018, 0x0f}, - {0x401b, 0x08}, - {0x401c, 0x00}, - {0x401d, 0x10}, - {0x401e, 0x02}, - {0x401f, 0x00}, - {0x4050, 0x06}, - {0x4051, 0xff}, - {0x4052, 0xff}, - {0x4053, 0xff}, - {0x4054, 0xff}, - {0x4055, 0xff}, - {0x4056, 0xff}, - {0x4057, 0x7f}, - {0x4058, 0x00}, - {0x4059, 0x00}, - {0x405a, 0x00}, - {0x405b, 0x00}, - {0x405c, 0x07}, - {0x405d, 0xff}, - {0x405e, 0x07}, - {0x405f, 0xff}, - {0x4080, 0x78}, - {0x4081, 0x78}, - {0x4082, 0x78}, - {0x4083, 0x78}, - {0x4019, 0x00}, - {0x401a, 0x40}, - {0x4020, 0x04}, - {0x4021, 0x00}, - {0x4022, 0x04}, - {0x4023, 0x00}, - {0x4024, 0x04}, - {0x4025, 0x00}, - {0x4026, 0x04}, - {0x4027, 0x00}, - {0x4030, 0x00}, - {0x4031, 0x00}, - {0x4032, 0x00}, - {0x4033, 0x00}, - {0x4034, 0x00}, - {0x4035, 0x00}, - {0x4036, 0x00}, - {0x4037, 0x00}, - {0x4040, 0x00}, - {0x4041, 0x80}, - {0x4042, 0x00}, - {0x4043, 0x80}, - {0x4044, 0x00}, - {0x4045, 0x80}, - {0x4046, 0x00}, - {0x4047, 0x80}, - {0x4060, 0x00}, - {0x4061, 0x00}, - {0x4062, 0x00}, - {0x4063, 0x00}, - {0x4064, 0x00}, - {0x4065, 0x00}, - {0x4066, 0x00}, - {0x4067, 0x00}, - {0x4068, 0x00}, - {0x4069, 0x00}, - {0x406a, 0x00}, - {0x406b, 0x00}, - {0x406c, 0x00}, - {0x406d, 0x00}, - {0x406e, 0x00}, - {0x406f, 0x00}, - {0x4070, 0x00}, - {0x4071, 0x00}, - {0x4072, 0x00}, - {0x4073, 0x00}, - {0x4074, 0x00}, - {0x4075, 0x00}, - {0x4076, 0x00}, - {0x4077, 0x00}, - {0x4078, 0x00}, - {0x4079, 0x00}, - {0x407a, 0x00}, - {0x407b, 0x00}, - {0x407c, 0x00}, - {0x407d, 0x00}, - {0x407e, 0x00}, - {0x407f, 0x00}, - {0x40e0, 0x00}, - {0x40e1, 0x00}, - {0x40e2, 0x00}, - {0x40e3, 0x00}, - {0x40e4, 0x00}, - {0x40e5, 0x00}, - {0x40e6, 0x00}, - {0x40e7, 0x00}, - {0x40e8, 0x00}, - {0x40e9, 0x80}, - {0x40ea, 0x00}, - {0x40eb, 0x80}, - {0x40ec, 0x00}, - {0x40ed, 0x80}, - {0x40ee, 0x00}, - {0x40ef, 0x80}, - {0x40f0, 0x02}, - {0x40f1, 0x04}, - {0x4300, 0x00}, - {0x4301, 0x00}, - {0x4302, 0x00}, - {0x4303, 0x00}, - {0x4304, 0x00}, - {0x4305, 0x00}, - {0x4306, 0x00}, - {0x4307, 0x00}, - {0x4308, 0x00}, - {0x4309, 0x00}, - {0x430a, 0x00}, - {0x430b, 0xff}, - {0x430c, 0xff}, - {0x430d, 0x00}, - {0x430e, 0x00}, - {0x4315, 0x00}, - {0x4316, 0x00}, - {0x4317, 0x00}, - {0x4318, 0x00}, - {0x4319, 0x00}, - {0x431a, 0x00}, - {0x431b, 0x00}, - {0x431c, 0x00}, - {0x4500, 0x07}, {0x4501, 0x10}, - {0x4502, 0x00}, - {0x4503, 0x0f}, - {0x4504, 0x80}, - {0x4506, 0x01}, - {0x4509, 0x05}, - {0x450c, 0x00}, - {0x450d, 0x20}, - {0x450e, 0x00}, - {0x450f, 0x00}, - {0x4510, 0x00}, - {0x4523, 0x00}, - {0x4526, 0x00}, {0x4542, 0x00}, - {0x4543, 0x00}, - {0x4544, 0x00}, - {0x4545, 0x00}, - {0x4546, 0x00}, - {0x4547, 0x10}, - {0x4602, 0x00}, - {0x4603, 0x15}, - {0x460b, 0x07}, - {0x4680, 0x11}, - {0x4686, 0x00}, - {0x4687, 0x00}, - {0x4700, 0x00}, - {0x4800, 0x64}, - {0x4806, 0x40}, - {0x480b, 0x10}, - {0x480c, 0x80}, - {0x480f, 0x32}, - {0x4813, 0xe4}, {0x4837, 0x14}, {0x4850, 0x42}, - {0x4884, 0x04}, - {0x4c00, 0xf8}, - {0x4c01, 0x44}, - {0x4c03, 0x00}, - {0x4d00, 0x00}, - {0x4d01, 0x16}, - {0x4d04, 0x10}, - {0x4d05, 0x00}, - {0x4d06, 0x0c}, - {0x4d07, 0x00}, - {0x3d84, 0x04}, - {0x3680, 0xa4}, - {0x3682, 0x80}, - {0x3601, 0x40}, - {0x3602, 0x90}, - {0x3608, 0x0a}, - {0x3938, 0x09}, - {0x3a74, 0x84}, - {0x3a99, 0x84}, - {0x3ab9, 0xa6}, - {0x3aba, 0xba}, - {0x3b12, 0x84}, - {0x3b14, 0xbb}, - {0x3b15, 0xbf}, - {0x3a29, 0x26}, - {0x3a1f, 0x8a}, - {0x3a22, 0x91}, - {0x3a25, 0x96}, - {0x3a28, 0xb4}, - {0x3a2b, 0xba}, - {0x3a2e, 0xbf}, - {0x3a31, 0xc1}, {0x3a20, 0x05}, {0x3939, 0x6b}, {0x3902, 0x10}, @@ -1503,22 +728,13 @@ static const struct ov08x40_reg mode_1928x1208_regs[] = { {0x3907, 0x0b}, {0x3908, 0x10}, {0x3909, 0x13}, - {0x360f, 0x99}, {0x390b, 0x11}, {0x390c, 0x21}, {0x390d, 0x32}, {0x390e, 0x76}, - {0x3911, 0x90}, - {0x3913, 0x90}, - {0x3b3f, 0x9d}, - {0x3b45, 0x9d}, - {0x3b1b, 0xc9}, - {0x3b21, 0xc9}, {0x3a1a, 0x1c}, - {0x3a23, 0x15}, {0x3a26, 0x17}, {0x3a2c, 0x50}, - {0x3a2f, 0x18}, {0x3a32, 0x4f}, {0x3ace, 0x01}, {0x3ad2, 0x01}, @@ -1533,31 +749,13 @@ static const struct ov08x40_reg mode_1928x1208_regs[] = { {0x3afe, 0x01}, {0x3b02, 0x01}, {0x3b06, 0x01}, - {0x3b0a, 0x01}, - {0x3b0b, 0x00}, - {0x3b0e, 0x01}, - {0x3b0f, 0x00}, - {0x392c, 0x02}, {0x392d, 0x01}, - {0x392e, 0x04}, - {0x392f, 0x03}, {0x3930, 0x09}, - {0x3931, 0x07}, - {0x3932, 0x10}, {0x3933, 0x0d}, - {0x3609, 0x08}, - {0x3921, 0x0f}, - {0x3928, 0x15}, - {0x3929, 0x2a}, {0x392a, 0x52}, {0x392b, 0xa3}, {0x340b, 0x1b}, - {0x3426, 0x10}, - {0x3407, 0x01}, - {0x3404, 0x01}, - {0x3500, 0x00}, {0x3501, 0x08}, - {0x3502, 0x10}, {0x3508, 0x04}, {0x3509, 0x00}, }; From patchwork Wed Apr 23 17:56:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chen, Jason Z" X-Patchwork-Id: 884136 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 358F728D846 for ; Wed, 23 Apr 2025 17:56:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745430962; cv=none; b=Hn2ufMUMoqLKlm6rXbreR8fAvdqA4q5RC6ZyCFbREIdY/0qmpgCKC32KzlO2R7+81vNF281EYztx4Bhq3p0GXCpBBliVTrjQwB7LY+njhGLbuyGbzuHiDoxw57WV1aJ0sn5fgr5meJZBbDTNdW7znypzHOydOb38O07ym7w4Yrg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745430962; c=relaxed/simple; bh=mD9dTZ+ncMoYeSfz6udgbuez4GjmMTPCvxfMA73Snnw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JJJEd++J7pwcWy0sQ7pLXRQMiGpN2IxxM9es4p6XXJLkBdQvZ4dpjVss331ao7jEtp/Uo5Q46StA26uyIrk+3a67pgZx/M2nSjDTVC+IAdZggnwifT1qkqSA6z4edN+zk2k2QNzULxU4vaEUfq45V4nBa/JM/2dC3eJFoL9IYIs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=izAEgfwj; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="izAEgfwj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1745430961; x=1776966961; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mD9dTZ+ncMoYeSfz6udgbuez4GjmMTPCvxfMA73Snnw=; b=izAEgfwjBeS9SedgjCKll12tMbJozjtd35I3bikdA7Y8XrCulX534+0I YAIMY9rMT8mw3Ny864bpBQTzWYtkXRo8WkQ/spaRVV4v8BxWbF3Pnp+CK r5hdy3nWhqqY1ZBTf1UD+6IYcm4TGpgMhEYThnQL8UvV3e+Gvk9bnwOSM z7d6UEyKU5VnJB3aXZgWJS5OrIaPatoGJpNYw0OUF1He4iumyAG0vXcb4 lwHx+escUJvwaHQqT737IftWXl5Nl3cUwxr28UfC0TxqLN9+MRIVg6ehf hEd0GRPSbz3KhZGph4tfo72d605iZRngpabX2xo/FKjDtFPIeAfWhx+Q/ g==; X-CSE-ConnectionGUID: 2igc2EqmRZSzEds2B/2Azw== X-CSE-MsgGUID: +BT6a6gFQXCYO15Tuj7psg== X-IronPort-AV: E=McAfee;i="6700,10204,11412"; a="69529328" X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="69529328" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2025 10:56:00 -0700 X-CSE-ConnectionGUID: wd6F09SKTC2nhYS1caYasw== X-CSE-MsgGUID: cbE7TyY8RfmmB8CrBICzLw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="137467709" Received: from jasonz-ms-7d25.itwn.intel.com ([10.225.65.15]) by fmviesa004.fm.intel.com with ESMTP; 23 Apr 2025 10:55:57 -0700 From: "Chen, Jason Z" To: linux-media@vger.kernel.org Cc: sakari.ailus@linux.intel.com, bingbu.cao@linux.intel.com, jimmy.su@intel.com, daxing.li@intel.com, hao.yao@intel.com, qingwu.zhang@intel.com, arun.t@intel.com, Jason Chen Subject: [PATCH v8 4/6] media: ov08x40: Add shared global register list Date: Thu, 24 Apr 2025 01:56:34 +0800 Message-Id: <20250423175636.1338374-4-jason.z.chen@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250423175636.1338374-1-jason.z.chen@intel.com> References: <20250423175636.1338374-1-jason.z.chen@intel.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Jason Chen This follows the previous cleanup commit where duplicate entries were removed from each mode's register list. Signed-off-by: Jason Chen --- drivers/media/i2c/ov08x40.c | 416 ++++++++++++++++++++++++++++++++++++ 1 file changed, 416 insertions(+) diff --git a/drivers/media/i2c/ov08x40.c b/drivers/media/i2c/ov08x40.c index 4cd4ef77e0aa..140598642845 100644 --- a/drivers/media/i2c/ov08x40.c +++ b/drivers/media/i2c/ov08x40.c @@ -151,6 +151,414 @@ struct ov08x40_mode { u16 exposure_shift; }; +static const struct ov08x40_reg ov08x40_global_regs[] = { + {0x1216, 0x60}, + {0x1217, 0x5b}, + {0x1218, 0x00}, + {0x1220, 0x24}, + {0x198a, 0x00}, + {0x198b, 0x01}, + {0x198e, 0x00}, + {0x198f, 0x01}, + {0x3009, 0x04}, + {0x3015, 0x00}, + {0x3016, 0xb0}, + {0x3017, 0xf0}, + {0x3018, 0xf0}, + {0x3019, 0xd2}, + {0x301a, 0xb0}, + {0x301c, 0x81}, + {0x301d, 0x02}, + {0x301e, 0x80}, + {0x3022, 0xf0}, + {0x3025, 0x89}, + {0x3030, 0x03}, + {0x3044, 0xc2}, + {0x3050, 0x35}, + {0x3051, 0x60}, + {0x3052, 0x25}, + {0x3053, 0x00}, + {0x3054, 0x00}, + {0x3055, 0x02}, + {0x3056, 0x80}, + {0x3057, 0x80}, + {0x3058, 0x80}, + {0x3059, 0x00}, + {0x3107, 0x86}, + {0x3401, 0x80}, + {0x3402, 0x8c}, + {0x3404, 0x01}, + {0x3407, 0x01}, + {0x341b, 0x30}, + {0x3420, 0x00}, + {0x3421, 0x00}, + {0x3422, 0x00}, + {0x3423, 0x00}, + {0x3424, 0x00}, + {0x3425, 0x00}, + {0x3426, 0x10}, + {0x3427, 0x00}, + {0x3428, 0x0f}, + {0x3429, 0x00}, + {0x342a, 0x00}, + {0x342b, 0x00}, + {0x342c, 0x00}, + {0x342d, 0x00}, + {0x342e, 0x00}, + {0x342f, 0x11}, + {0x3430, 0x11}, + {0x3431, 0x10}, + {0x3432, 0x00}, + {0x3433, 0x00}, + {0x3434, 0x00}, + {0x3435, 0x00}, + {0x3436, 0x00}, + {0x3437, 0x00}, + {0x3442, 0x02}, + {0x3443, 0x02}, + {0x3444, 0x07}, + {0x3450, 0x00}, + {0x3451, 0x00}, + {0x3452, 0x18}, + {0x3453, 0x18}, + {0x3454, 0x00}, + {0x3455, 0x80}, + {0x3456, 0x08}, + {0x3500, 0x00}, + {0x3502, 0x10}, + {0x3504, 0x4c}, + {0x3506, 0x30}, + {0x3507, 0x00}, + {0x350a, 0x01}, + {0x350b, 0x00}, + {0x350c, 0x00}, + {0x3540, 0x00}, + {0x3544, 0x4c}, + {0x3546, 0x30}, + {0x3547, 0x00}, + {0x3549, 0x00}, + {0x354a, 0x01}, + {0x354b, 0x00}, + {0x354c, 0x00}, + {0x3601, 0x40}, + {0x3602, 0x90}, + {0x3608, 0x0a}, + {0x3609, 0x08}, + {0x360f, 0x99}, + {0x3680, 0xa4}, + {0x3682, 0x80}, + {0x3688, 0x02}, + {0x368a, 0x2e}, + {0x368e, 0x71}, + {0x3696, 0xd1}, + {0x3699, 0x00}, + {0x369a, 0x00}, + {0x36a4, 0x00}, + {0x36a6, 0x00}, + {0x3711, 0x00}, + {0x3713, 0x00}, + {0x3716, 0x00}, + {0x3718, 0x07}, + {0x371a, 0x1c}, + {0x371b, 0x00}, + {0x3720, 0x08}, + {0x3725, 0x32}, + {0x3727, 0x05}, + {0x3760, 0x02}, + {0x3762, 0x02}, + {0x3763, 0x02}, + {0x3764, 0x02}, + {0x3765, 0x2c}, + {0x3766, 0x04}, + {0x3767, 0x2c}, + {0x3768, 0x02}, + {0x3769, 0x00}, + {0x376b, 0x20}, + {0x37b2, 0x01}, + {0x3800, 0x00}, + {0x3801, 0x00}, + {0x3802, 0x00}, + {0x3804, 0x0f}, + {0x3805, 0x1f}, + {0x3806, 0x09}, + {0x380c, 0x02}, + {0x3810, 0x00}, + {0x3812, 0x00}, + {0x3814, 0x11}, + {0x3815, 0x11}, + {0x3822, 0x00}, + {0x3828, 0x0f}, + {0x382a, 0x80}, + {0x382e, 0x41}, + {0x3837, 0x08}, + {0x383a, 0x81}, + {0x383b, 0x81}, + {0x383c, 0x11}, + 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{0x4510, 0x00}, + {0x4523, 0x00}, + {0x4526, 0x00}, + {0x4543, 0x00}, + {0x4544, 0x00}, + {0x4545, 0x00}, + {0x4546, 0x00}, + {0x4547, 0x10}, + {0x4602, 0x00}, + {0x4603, 0x15}, + {0x460b, 0x07}, + {0x4680, 0x11}, + {0x4686, 0x00}, + {0x4687, 0x00}, + {0x4700, 0x00}, + {0x4800, 0x64}, + {0x4806, 0x40}, + {0x480b, 0x10}, + {0x480c, 0x80}, + {0x480f, 0x32}, + {0x4813, 0xe4}, + {0x4884, 0x04}, + {0x4c00, 0xf8}, + {0x4c01, 0x44}, + {0x4c03, 0x00}, + {0x4d00, 0x00}, + {0x4d01, 0x16}, + {0x4d04, 0x10}, + {0x4d05, 0x00}, + {0x4d06, 0x0c}, + {0x4d07, 0x00}, + {0x5008, 0xb0}, + {0x50c1, 0x00}, + {0x53c1, 0x00}, + {0x5f40, 0x00}, + {0x5f41, 0x40}, +}; + +static const struct ov08x40_reg_list ov08x40_global_setting = { + .num_of_regs = ARRAY_SIZE(ov08x40_global_regs), + .regs = ov08x40_global_regs, +}; + static const struct ov08x40_reg mipi_data_rate_800mbps[] = { {0x0103, 0x01}, {0x1000, 0x00}, @@ -1503,6 +1911,14 @@ static int ov08x40_start_streaming(struct ov08x40 *ov08x) return ret; } + reg_list = &ov08x40_global_setting; + ret = ov08x40_write_reg_list(ov08x, reg_list); + if (ret) { + dev_err(&client->dev, "%s failed to set global setting\n", + __func__); + return ret; + } + /* Apply default values of current mode */ reg_list = &ov08x->cur_mode->reg_list; ret = ov08x40_write_reg_list(ov08x, reg_list); From patchwork Wed Apr 23 17:56:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chen, Jason Z" X-Patchwork-Id: 883682 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B0AD28D846 for ; Wed, 23 Apr 2025 17:56:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745430965; cv=none; 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E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="69529329" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2025 10:56:04 -0700 X-CSE-ConnectionGUID: AcWPYq9PQGKiaNWQjHE/uQ== X-CSE-MsgGUID: rshmhG77TqKuPStszh1Fcw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="137467722" Received: from jasonz-ms-7d25.itwn.intel.com ([10.225.65.15]) by fmviesa004.fm.intel.com with ESMTP; 23 Apr 2025 10:56:01 -0700 From: "Chen, Jason Z" To: linux-media@vger.kernel.org Cc: sakari.ailus@linux.intel.com, bingbu.cao@linux.intel.com, jimmy.su@intel.com, daxing.li@intel.com, hao.yao@intel.com, qingwu.zhang@intel.com, arun.t@intel.com, Jason Chen Subject: [PATCH v8 5/6] media: ov08x40: Use v4l2_link_freq_to_bitmap helper Date: Thu, 24 Apr 2025 01:56:35 +0800 Message-Id: <20250423175636.1338374-5-jason.z.chen@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250423175636.1338374-1-jason.z.chen@intel.com> References: <20250423175636.1338374-1-jason.z.chen@intel.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Jason Chen Use the v4l2_link_freq_to_bitmap() helper to figure out which driver-supported link frequencies can be used on a given system. Signed-off-by: Jason Chen --- drivers/media/i2c/ov08x40.c | 28 ++++++++++------------------ 1 file changed, 10 insertions(+), 18 deletions(-) diff --git a/drivers/media/i2c/ov08x40.c b/drivers/media/i2c/ov08x40.c index 140598642845..37ce6595a7d8 100644 --- a/drivers/media/i2c/ov08x40.c +++ b/drivers/media/i2c/ov08x40.c @@ -1327,6 +1327,8 @@ struct ov08x40 { /* True if the device has been identified */ bool identified; + + unsigned long link_freq_bitmap; }; #define to_ov08x40(_sd) container_of(_sd, struct ov08x40, sd) @@ -2073,8 +2075,8 @@ static int ov08x40_init_controls(struct ov08x40 *ov08x) ov08x->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov08x40_ctrl_ops, V4L2_CID_LINK_FREQ, - max, - 0, + __fls(ov08x->link_freq_bitmap), + __ffs(ov08x->link_freq_bitmap), link_freq_menu_items); if (ov08x->link_freq) ov08x->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; @@ -2170,7 +2172,7 @@ static int ov08x40_check_hwcfg(struct ov08x40 *ov08x, struct device *dev) }; struct fwnode_handle *ep; struct fwnode_handle *fwnode = dev_fwnode(dev); - unsigned int i, j; + unsigned int i; int ret; u32 xvclk_rate; @@ -2236,21 +2238,11 @@ static int ov08x40_check_hwcfg(struct ov08x40 *ov08x, struct device *dev) ret = -EINVAL; goto out_err; } - - for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { - for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { - if (link_freq_menu_items[i] == - bus_cfg.link_frequencies[j]) - break; - } - - if (j == bus_cfg.nr_of_link_frequencies) { - dev_err(dev, "no link frequency %lld supported", - link_freq_menu_items[i]); - ret = -EINVAL; - goto out_err; - } - } + ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies, + bus_cfg.nr_of_link_frequencies, + link_freq_menu_items, + ARRAY_SIZE(link_freq_menu_items), + &ov08x->link_freq_bitmap); out_err: v4l2_fwnode_endpoint_free(&bus_cfg); From patchwork Wed Apr 23 17:56:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chen, Jason Z" X-Patchwork-Id: 884135 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CC4328D846 for ; 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a="69529330" X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="69529330" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2025 10:56:07 -0700 X-CSE-ConnectionGUID: 534j+vAWRQSdAdNmMVfOhA== X-CSE-MsgGUID: l+Qv5EsgRje6pUsKdTu26w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="137467730" Received: from jasonz-ms-7d25.itwn.intel.com ([10.225.65.15]) by fmviesa004.fm.intel.com with ESMTP; 23 Apr 2025 10:56:04 -0700 From: "Chen, Jason Z" To: linux-media@vger.kernel.org Cc: sakari.ailus@linux.intel.com, bingbu.cao@linux.intel.com, jimmy.su@intel.com, daxing.li@intel.com, hao.yao@intel.com, qingwu.zhang@intel.com, arun.t@intel.com, Jason Chen Subject: [PATCH v8 6/6] media: ov08x40: Select mode based on mipi lane count Date: Thu, 24 Apr 2025 01:56:36 +0800 Message-Id: <20250423175636.1338374-6-jason.z.chen@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250423175636.1338374-1-jason.z.chen@intel.com> References: <20250423175636.1338374-1-jason.z.chen@intel.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Jason Chen Use the v4l2_find_nearest_size_conditional() helper to figure out which drive-supported lane can be used on a given system. Also avoid exposing duplicate frame sizes to userspace when multiple modes share the same resolution but differ in lane count. Signed-off-by: Jason Chen --- drivers/media/i2c/ov08x40.c | 55 +++++++++++++++++++++++++++++-------- 1 file changed, 43 insertions(+), 12 deletions(-) diff --git a/drivers/media/i2c/ov08x40.c b/drivers/media/i2c/ov08x40.c index 37ce6595a7d8..d44a8f1a09c5 100644 --- a/drivers/media/i2c/ov08x40.c +++ b/drivers/media/i2c/ov08x40.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -1325,6 +1326,9 @@ struct ov08x40 { /* Mutex for serialized access */ struct mutex mutex; + /* data lanes */ + u8 mipi_lanes; + /* True if the device has been identified */ bool identified; @@ -1749,6 +1753,15 @@ static int ov08x40_set_ctrl(struct v4l2_ctrl *ctrl) return ret; } +static bool filter_by_mipi_lanes(const void *array, size_t index, + const void *context) +{ + const struct ov08x40_mode *mode = array; + const struct ov08x40 *ov08x = context; + + return mode->lanes == ov08x->mipi_lanes; +} + static const struct v4l2_ctrl_ops ov08x40_ctrl_ops = { .s_ctrl = ov08x40_set_ctrl, }; @@ -1770,18 +1783,28 @@ static int ov08x40_enum_frame_size(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_frame_size_enum *fse) { - if (fse->index >= ARRAY_SIZE(supported_modes)) - return -EINVAL; + struct ov08x40 *ov08x = to_ov08x40(sd); + size_t i, count = 0; if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) return -EINVAL; - fse->min_width = supported_modes[fse->index].width; - fse->max_width = fse->min_width; - fse->min_height = supported_modes[fse->index].height; - fse->max_height = fse->min_height; + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + if (!filter_by_mipi_lanes(&supported_modes[i], i, ov08x)) + continue; - return 0; + if (count == fse->index) { + fse->min_width = supported_modes[i].width; + fse->max_width = fse->min_width; + fse->min_height = supported_modes[i].height; + fse->max_height = fse->min_height; + return 0; + } + + count++; + } + + return -EINVAL; } static void ov08x40_update_pad_format(const struct ov08x40_mode *mode, @@ -1844,10 +1867,13 @@ ov08x40_set_pad_format(struct v4l2_subdev *sd, if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10) fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; - mode = v4l2_find_nearest_size(supported_modes, - ARRAY_SIZE(supported_modes), - width, height, - fmt->format.width, fmt->format.height); + mode = v4l2_find_nearest_size_conditional(supported_modes, + ARRAY_SIZE(supported_modes), + width, height, + fmt->format.width, + fmt->format.height, + filter_by_mipi_lanes, + ov08x); ov08x40_update_pad_format(mode, fmt); if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad); @@ -2226,7 +2252,12 @@ static int ov08x40_check_hwcfg(struct ov08x40 *ov08x, struct device *dev) if (ret) return ret; - if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV08X40_DATA_LANES) { + switch (bus_cfg.bus.mipi_csi2.num_data_lanes) { + case 2: + case 4: + ov08x->mipi_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes; + break; + default: dev_err(dev, "number of CSI2 data lanes %d is not supported", bus_cfg.bus.mipi_csi2.num_data_lanes); ret = -EINVAL;