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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073ca5219sm508551f8f.27.2025.04.24.15.21.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:21:18 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Markus Armbruster Subject: [RFC PATCH v5 01/21] qapi: Rename TargetInfo structure as QemuTargetInfo Date: Fri, 25 Apr 2025 00:20:52 +0200 Message-ID: <20250424222112.36194-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The QAPI-generated 'TargetInfo' structure name is only used in a single file. We want to heavily use another structure similarly named. Rename the QAPI one, since structure names are not part of the public API. Suggested-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson Reviewed-by: Markus Armbruster Message-Id: <20250422145502.70770-2-philmd@linaro.org> --- qapi/machine.json | 10 +++++----- hw/core/machine-qmp-cmds.c | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/qapi/machine.json b/qapi/machine.json index a9ff8076317..c8feb9fe17b 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -275,15 +275,15 @@ { 'command': 'query-current-machine', 'returns': 'CurrentMachineParams' } ## -# @TargetInfo: +# @QemuTargetInfo: # -# Information describing the QEMU target. +# Information on the target configuration built into the QEMU binary. # # @arch: the target architecture # # Since: 1.2 ## -{ 'struct': 'TargetInfo', +{ 'struct': 'QemuTargetInfo', 'data': { 'arch': 'SysEmuTarget' } } ## @@ -291,11 +291,11 @@ # # Return information about the target for this QEMU # -# Returns: TargetInfo +# Returns: QemuTargetInfo # # Since: 1.2 ## -{ 'command': 'query-target', 'returns': 'TargetInfo' } +{ 'command': 'query-target', 'returns': 'QemuTargetInfo' } ## # @UuidInfo: diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c index 9447e345b3c..a5e635152dc 100644 --- a/hw/core/machine-qmp-cmds.c +++ b/hw/core/machine-qmp-cmds.c @@ -134,9 +134,9 @@ CurrentMachineParams *qmp_query_current_machine(Error **errp) return params; } -TargetInfo *qmp_query_target(Error **errp) +QemuTargetInfo *qmp_query_target(Error **errp) { - TargetInfo *info = g_malloc0(sizeof(*info)); + QemuTargetInfo *info = g_malloc0(sizeof(*info)); info->arch = qapi_enum_parse(&SysEmuTarget_lookup, target_name(), -1, &error_abort); From patchwork Thu Apr 24 22:20:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883990 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3672744wrs; Thu, 24 Apr 2025 15:23:22 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWLFfRArIRHPKQhJ7gOhWrNptPloYYHGnR2P1v/Ve9T2jA2eGELwaDY7sm2gYGRLQl39BhXCg==@linaro.org X-Google-Smtp-Source: AGHT+IEpwB8HZ4BhtHYDa4chfRJPbw24boiElBl457B/woaco8KQo5jC9JHnQd51X3eWenVmMNl2 X-Received: by 2002:a05:620a:610a:b0:7c5:5584:dc1b with SMTP id af79cd13be357-7c9607ac70amr40179085a.54.1745533402296; Thu, 24 Apr 2025 15:23:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745533402; cv=none; d=google.com; s=arc-20240605; b=aWUbmlPjKvMuPL5cNHtFjzGSj5kTK94xzoK5U9b0z4kg87c4HdNtNetsgBoBakQ45r fjfwNUr+CofTItwmiTPhrGtmlCg1TgsWHWAchPh+Gn5oe3vg3sy1MjF7mnlVZMsgCox4 7HSA6KF4QSYM48ZZzDk4LIfLeaeoGXvi6fvSOzu6zxgBOxwBTqk7Xvq4Z5q1bPFDAspU mpibkT4Kobm5R0ffMRxkmvJj43OhcbXVGgAun/QM22VOjNOcI7Xt706VlEt/hDC4Of58 puZ+WmHCbyOk571LM4tVL4p04sK4mOA+6HjlOYb8HcpHS7g1UYyGtOxzak5kSja64rOE QcWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=JBHgXf1VILUQD/n0uYXLzK5bDjPq3G+VbeYo1f99nf0=; fh=3N/q6M9yUku/eipnexU2QUS8NxsXJQoyfq8XixFMPB4=; b=AsxU+/vL/ncGYGB2itlJjx7xdzVEPbZLJhskwPo3ifer0cHoEdQ+Nbj+bd+eRyt9fi Q/KgXkmQlV4ZKizZazRKsEJ6OwLfRVvfT5LJOlsN8f7zHXpE1sY9eFIioi7fLUbS1lYt lbYCBgvLFiP3QEfecgBDGJfOzPz9O5cYQ9a88UtIAYC/qVhdi8m/vA/W450H3CQk/0Ho P0bhHe9O4UW1Bfxu9stTt3OUSYvd8fpBuF8R26N4n51kVT9o8ob8Al7X+93N/krtNwzN rLxVAsf163Jt7TRGhfNgQVk1NfZ6Wd027uf2L5IkTvs5SIHf6jxglvEwxRGIvbnjOUZB 5L8Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=shJfuCPy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-440a5a74314sm1923935e9.4.2025.04.24.15.21.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:21:23 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 02/21] qemu: Convert target_name() to TargetInfo API Date: Fri, 25 Apr 2025 00:20:53 +0200 Message-ID: <20250424222112.36194-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Have target_name() be a target-agnostic method, dispatching to a per-target TargetInfo singleton structure. By default a stub singleton is used. No logical change expected. Inspired-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- MAINTAINERS | 7 +++++++ meson.build | 3 +++ include/hw/core/cpu.h | 2 -- include/qemu/target-info-impl.h | 26 ++++++++++++++++++++++++++ include/qemu/target-info.h | 19 +++++++++++++++++++ cpu-target.c | 5 ----- hw/core/machine-qmp-cmds.c | 1 + plugins/loader.c | 2 +- system/vl.c | 2 +- target-info-stub.c | 19 +++++++++++++++++++ target-info.c | 16 ++++++++++++++++ 11 files changed, 93 insertions(+), 9 deletions(-) create mode 100644 include/qemu/target-info-impl.h create mode 100644 include/qemu/target-info.h create mode 100644 target-info-stub.c create mode 100644 target-info.c diff --git a/MAINTAINERS b/MAINTAINERS index d82d962f1a4..451e2778888 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1926,6 +1926,13 @@ F: tests/functional/test_empty_cpu_model.py F: tests/unit/test-smp-parse.c T: git https://gitlab.com/ehabkost/qemu.git machine-next +TargetInfo API +M: Pierrick Bouvier +M: Philippe Mathieu-Daudé +S: Supported +F: include/qemu/target-info*.h +F: target-info*.c + Xtensa Machines --------------- sim diff --git a/meson.build b/meson.build index c736a6f4c4b..8ae70dbe45a 100644 --- a/meson.build +++ b/meson.build @@ -3795,6 +3795,9 @@ endif common_ss.add(pagevary) specific_ss.add(files('page-target.c', 'page-vary-target.c')) +common_ss.add(files('target-info.c')) +specific_ss.add(files('target-info-stub.c')) + subdir('backends') subdir('disas') subdir('migration') diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5b645df59f5..9d9448341d1 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1115,8 +1115,6 @@ bool cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); void cpu_exec_reset_hold(CPUState *cpu); -const char *target_name(void); - #ifdef COMPILING_PER_TARGET extern const VMStateDescription vmstate_cpu_common; diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h new file mode 100644 index 00000000000..d30805f7f28 --- /dev/null +++ b/include/qemu/target-info-impl.h @@ -0,0 +1,26 @@ +/* + * QEMU TargetInfo structure definition + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef QEMU_TARGET_INFO_IMPL_H +#define QEMU_TARGET_INFO_IMPL_H + +#include "qemu/target-info.h" + +typedef struct TargetInfo { + /* runtime equivalent of TARGET_NAME definition */ + const char *target_name; +} TargetInfo; + +/** + * target_info: + * + * Returns: The TargetInfo structure definition for this target binary. + */ +const TargetInfo *target_info(void); + +#endif diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h new file mode 100644 index 00000000000..1007dc9a5e4 --- /dev/null +++ b/include/qemu/target-info.h @@ -0,0 +1,19 @@ +/* + * QEMU target info API + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef QEMU_TARGET_INFO_H +#define QEMU_TARGET_INFO_H + +/** + * target_name: + * + * Returns: Canonical target name (i.e. "i386"). + */ +const char *target_name(void); + +#endif diff --git a/cpu-target.c b/cpu-target.c index c99d208a7c4..3f82d3ea444 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -165,8 +165,3 @@ bool target_words_bigendian(void) { return TARGET_BIG_ENDIAN; } - -const char *target_name(void) -{ - return TARGET_NAME; -} diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c index a5e635152dc..d82043e1c68 100644 --- a/hw/core/machine-qmp-cmds.c +++ b/hw/core/machine-qmp-cmds.c @@ -19,6 +19,7 @@ #include "qapi/qobject-input-visitor.h" #include "qapi/type-helpers.h" #include "qemu/uuid.h" +#include "qemu/target-info.h" #include "qom/qom-qobject.h" #include "system/hostmem.h" #include "system/hw_accel.h" diff --git a/plugins/loader.c b/plugins/loader.c index 0d6e082e170..8f0d75c9049 100644 --- a/plugins/loader.c +++ b/plugins/loader.c @@ -29,7 +29,7 @@ #include "qemu/xxhash.h" #include "qemu/plugin.h" #include "qemu/memalign.h" -#include "hw/core/cpu.h" +#include "qemu/target-info.h" #include "exec/tb-flush.h" #include "plugin.h" diff --git a/system/vl.c b/system/vl.c index c17945c4939..cdf6eb9ee49 100644 --- a/system/vl.c +++ b/system/vl.c @@ -40,6 +40,7 @@ #include "qemu/help_option.h" #include "qemu/hw-version.h" #include "qemu/uuid.h" +#include "qemu/target-info.h" #include "system/reset.h" #include "system/runstate.h" #include "system/runstate-action.h" @@ -79,7 +80,6 @@ #include "hw/block/block.h" #include "hw/i386/x86.h" #include "hw/i386/pc.h" -#include "hw/core/cpu.h" #include "migration/cpr.h" #include "migration/misc.h" #include "migration/snapshot.h" diff --git a/target-info-stub.c b/target-info-stub.c new file mode 100644 index 00000000000..076b9254dd0 --- /dev/null +++ b/target-info-stub.c @@ -0,0 +1,19 @@ +/* + * QEMU target info stubs + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" + +static const TargetInfo target_info_stub = { + .target_name = TARGET_NAME, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_stub; +} diff --git a/target-info.c b/target-info.c new file mode 100644 index 00000000000..84b18931e7e --- /dev/null +++ b/target-info.c @@ -0,0 +1,16 @@ +/* + * QEMU target info helpers + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info.h" +#include "qemu/target-info-impl.h" + +const char *target_name(void) +{ + return target_info()->target_name; +} From patchwork Thu Apr 24 22:20:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883987 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3672680wrs; Thu, 24 Apr 2025 15:23:13 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWYlewzrWyq/RzOlfMzXi0aJnf2Ay5rzDOokNAEtvIodiFZjDNfbCYDhTh/FamnvpFTZ7luFA==@linaro.org X-Google-Smtp-Source: AGHT+IG9LuWIE3kTtTYuNac6SDgySieTya2tCSTHuFDxcUGTQ4nmkpl0zmFybxNVGwCLcXQhcfPs X-Received: by 2002:a05:6214:1bcd:b0:6e6:6c39:cb71 with SMTP id 6a1803df08f44-6f4cbb59928mr2824286d6.45.1745533393355; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4409d29ba29sm37164625e9.7.2025.04.24.15.21.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:21:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 03/21] system/vl: Filter machine list available for a particular target binary Date: Fri, 25 Apr 2025 00:20:54 +0200 Message-ID: <20250424222112.36194-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Binaries can register a QOM type to filter their machines by filling their TargetInfo::machine_typename field. This can be used by example by main() -> machine_help_func() to filter the machines list. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/qemu/target-info-impl.h | 2 ++ include/qemu/target-info.h | 8 ++++++++ system/vl.c | 3 ++- target-info-stub.c | 2 ++ target-info.c | 5 +++++ 5 files changed, 19 insertions(+), 1 deletion(-) diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h index d30805f7f28..d0e8c86176c 100644 --- a/include/qemu/target-info-impl.h +++ b/include/qemu/target-info-impl.h @@ -14,6 +14,8 @@ typedef struct TargetInfo { /* runtime equivalent of TARGET_NAME definition */ const char *target_name; + /* QOM typename machines for this binary must implement */ + const char *machine_typename; } TargetInfo; /** diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 1007dc9a5e4..0224b35b166 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -16,4 +16,12 @@ */ const char *target_name(void); +/** + * target_machine_typename: + * + * Returns: Name of the QOM interface implemented by machines + * usable on this target binary. + */ +const char *target_machine_typename(void); + #endif diff --git a/system/vl.c b/system/vl.c index cdf6eb9ee49..e8706a9ce87 100644 --- a/system/vl.c +++ b/system/vl.c @@ -27,6 +27,7 @@ #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/module.h" +#include "qemu/target-info.h" #include "exec/cpu-common.h" #include "exec/page-vary.h" #include "hw/qdev-properties.h" @@ -1564,7 +1565,7 @@ static void machine_help_func(const QDict *qdict) GSList *el; const char *type = qdict_get_try_str(qdict, "type"); - machines = object_class_get_list(TYPE_MACHINE, false); + machines = object_class_get_list(target_machine_typename(), false); if (type) { ObjectClass *machine_class = OBJECT_CLASS(find_machine(type, machines)); if (machine_class) { diff --git a/target-info-stub.c b/target-info-stub.c index 076b9254dd0..218e5898e7f 100644 --- a/target-info-stub.c +++ b/target-info-stub.c @@ -8,9 +8,11 @@ #include "qemu/osdep.h" #include "qemu/target-info-impl.h" +#include "hw/boards.h" static const TargetInfo target_info_stub = { .target_name = TARGET_NAME, + .machine_typename = TYPE_MACHINE, }; const TargetInfo *target_info(void) diff --git a/target-info.c b/target-info.c index 84b18931e7e..0042769e3a2 100644 --- a/target-info.c +++ b/target-info.c @@ -14,3 +14,8 @@ const char *target_name(void) { return target_info()->target_name; } + +const char *target_machine_typename(void) +{ + return target_info()->machine_typename; +} From patchwork Thu Apr 24 22:20:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883998 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3673577wrs; Thu, 24 Apr 2025 15:26:20 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVgmPGJgVlhy+ndOggHWto2NxEV1gs44NCRuwjtHa8DI5+0jN7HILYHqabdPinmCglnw8DQRw==@linaro.org X-Google-Smtp-Source: AGHT+IGPdHzpTyTL0KSVJ4G3ZqaIXyB+dvbxW1EpxKp6PdDLKDHPP1+adg66m15SBrWzE0feyXqO X-Received: by 2002:a05:620a:2b88:b0:7c9:4df8:6b88 with SMTP id af79cd13be357-7c9606a5416mr56579885a.7.1745533579838; Thu, 24 Apr 2025 15:26:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745533579; cv=none; d=google.com; s=arc-20240605; b=ZXkj4qYpIewD7AOUtMqasksmKRVCnBBnek1AB2Txdu3P7b89JLKAQSoWk7VFFUEKl1 MulC6qpO5VCLqu6IW68r1kq5JC36Dr2ZC/ntlj4dMA0SEFcpcGMsPWnvYhaq6nn2/xF8 qKzesEkSqQ+9UrXba5Bu0i41FSTdPU+xFL6eQwn1VqERPLGJ+nXV8F6GWNpO9E1AI/E1 /ZIYANZQsSCI79YNKhyw9waTOEhU8zI+9Vw2shaac36E1ppHsKLhPU/9qzuG/QKA4Mej kBu4oyRXn8mfoFwF2Zc0rq1cm7Acgfm18JTjHpmnX4FuAcwt3ToYbtaNDindAiEOHp3d GYIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3/h/8JlKQTj5C7D4ksIw0VPKDSTa8HWXtIX5aCCEMPI=; fh=0htP/E62RePjDPlH7cln4AEjpwt/VA0EePtBoJU71HU=; b=BLffRqhGfqafhKjQuoMiYH+PGoSwBD4b1FyRgWuVyp+GyKSvBJn9NlgjWFky+lbdBr 2AKh3wYpXylXjU3yKdwvqHVo+vA3cpedMeWQGZ408nsX/nKyxLc4EOWhuLtpcczD+srk oUvQWJvN7TlHWnVyRYmyac59G5mjPCa6iJtKIrSJT8rVj13aRKxyC74/CJsXe24cKCgn mEVotV169JOEPnbr395AWj9CWS851u36fPN+xrwRLpGCuUfqMiPC95PVAudXqbx3TCSH g918eKbRqVUCxCTb8M67BIPxIWC4fSLUI/QuPS6Yw5r9xbM/HG4QqESk0piDrLS7DxV3 3UhQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WU5ToOAZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-440a53044besm3258715e9.14.2025.04.24.15.21.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:21:33 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 04/21] hw/core/null-machine: Define machine as generic QOM type Date: Fri, 25 Apr 2025 00:20:55 +0200 Message-ID: <20250424222112.36194-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org While DEFINE_MACHINE() is a succinct macro, it doesn't allow registering QOM interfaces to the defined machine. Convert to the generic DEFINE_TYPES() in preparation to register interfaces. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/core/null-machine.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c index a6e477a2d88..3e03771d570 100644 --- a/hw/core/null-machine.c +++ b/hw/core/null-machine.c @@ -42,8 +42,10 @@ static void machine_none_init(MachineState *mch) } } -static void machine_none_machine_init(MachineClass *mc) +static void null_machine_class_init(ObjectClass *oc, const void *data) { + MachineClass *mc = MACHINE_CLASS(oc); + mc->desc = "empty machine"; mc->init = machine_none_init; mc->max_cpus = 1; @@ -55,4 +57,12 @@ static void machine_none_machine_init(MachineClass *mc) mc->no_cdrom = 1; } -DEFINE_MACHINE("none", machine_none_machine_init) +static const TypeInfo null_machine_types[] = { + { + .name = MACHINE_TYPE_NAME("none"), + .parent = TYPE_MACHINE, + .class_init = null_machine_class_init, + }, +}; + +DEFINE_TYPES(null_machine_types) From patchwork Thu Apr 24 22:20:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883984 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3672568wrs; Thu, 24 Apr 2025 15:22:49 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVbCruT3Dn3kzgc1OLq2THFlfOWO8Vg4vz4PEqiAGaU/xeLL29FzvUhoAsjnghc5Wk0EfUKDg==@linaro.org X-Google-Smtp-Source: AGHT+IHSqoxK3X/Hr4Ato7pglgLCZ1VGjOFbCG2xQN+JIXmbV3PD56x1rEF4JLbPKxnpsEdAhJ77 X-Received: by 2002:a05:620a:424c:b0:7c5:6b46:e1f6 with SMTP id af79cd13be357-7c95859ad28mr587601385a.1.1745533368883; Thu, 24 Apr 2025 15:22:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745533368; cv=none; d=google.com; s=arc-20240605; b=IijO63X9r01m7LMYAnu9VZRx04R3hapbVi8BaRafKWyBPyY7rH9gy39wiNulO28wM5 T5slBYLJfGiIy2BaMb+/V47LpiJtVTQmO53K2HUJ39/u7okhh1Upia5E6AYGT+OEfH13 TKUnG+iMD4KrxRxmgfYfUyRn4oe+p94uISB2QTUTnfYdLPpw2Vp+QYb1KCLfHS+mkS1m P+gn5DFLlreL8rapjXDNPe1G1KR3tqhxrV2MUgs6LlpWjvecME7LDJBShzcVsKx2fYuV FA493przVcy3IKQTBBioZ4X0sDZx25wNO/zvITjfGA7M+u/50OMGVkQnb7OgvG7hYUsL mDjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=FP3LPIP8VvEj5FRhb7z5N8ONbnNZZViAztLoLjie/dQ=; fh=RZSHb1k+0zB8xuV27Uafr3EGaxUvsl1jFUfkobAkFfE=; b=lEEF2fXMt/epw3F6jxeotGcmgpIF5zkDhAnwaAKLk9OZgH+lQdLPpBR/fEeMHIXavx gpAbl0b7FefG89lB8V4Qk1UlhcrnKBjtFAE647AS430wFmEYl0jTFAoqMIjrPXzswczM BUiogPoPYlOWGvoVmMu+qRNgwaHIV4jkYS2b6PTerwNplJiv1bZi1ISp0p4mlD+BVyqq /aVM4OLYDr/AMVs1hzM0pd4zCa4X6LP1bO11xjtFW/xSvhsR4DaUqBdDmxEEoxyT/3LF bSMQvRqu2FwhFaqpAd1Bj9ZpG6Vsrf8U+3e3WsBEvE+TAnqNniZSykBzDaw67JkWXAX7 yuTA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O+nek3iG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073ca556bsm516466f8f.37.2025.04.24.15.21.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:21:39 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 05/21] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces Date: Fri, 25 Apr 2025 00:20:56 +0200 Message-ID: <20250424222112.36194-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Define the TYPE_TARGET_ARM_MACHINE and TYPE_TARGET_AARCH64_MACHINE QOM interface names to allow machines to implement them. Register these interfaces in common code in target_info-qom.c used by all binaries because QOM interfaces must be registered before being checked (see next commit with the 'none' machine). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- meson.build | 1 + include/hw/arm/machines-qom.h | 18 ++++++++++++++++++ target-info-qom.c | 24 ++++++++++++++++++++++++ 3 files changed, 43 insertions(+) create mode 100644 include/hw/arm/machines-qom.h create mode 100644 target-info-qom.c diff --git a/meson.build b/meson.build index 8ae70dbe45a..32e6aeb295d 100644 --- a/meson.build +++ b/meson.build @@ -3796,6 +3796,7 @@ common_ss.add(pagevary) specific_ss.add(files('page-target.c', 'page-vary-target.c')) common_ss.add(files('target-info.c')) +system_ss.add(files('target-info-qom.c')) specific_ss.add(files('target-info-stub.c')) subdir('backends') diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h new file mode 100644 index 00000000000..a17225f5f92 --- /dev/null +++ b/include/hw/arm/machines-qom.h @@ -0,0 +1,18 @@ +/* + * QOM type definitions for ARM / Aarch64 machines + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_MACHINES_QOM_H +#define HW_ARM_MACHINES_QOM_H + +#define TYPE_TARGET_ARM_MACHINE \ + "target-info-arm-machine" + +#define TYPE_TARGET_AARCH64_MACHINE \ + "target-info-aarch64-machine" + +#endif diff --git a/target-info-qom.c b/target-info-qom.c new file mode 100644 index 00000000000..7fd58d24818 --- /dev/null +++ b/target-info-qom.c @@ -0,0 +1,24 @@ +/* + * QEMU binary/target API (QOM types) + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qom/object.h" +#include "hw/arm/machines-qom.h" + +static const TypeInfo target_info_types[] = { + { + .name = TYPE_TARGET_ARM_MACHINE, + .parent = TYPE_INTERFACE, + }, + { + .name = TYPE_TARGET_AARCH64_MACHINE, + .parent = TYPE_INTERFACE, + }, +}; + +DEFINE_TYPES(target_info_types) From patchwork Thu Apr 24 22:20:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883979 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3672380wrs; Thu, 24 Apr 2025 15:22:11 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU32zJ61zU0iNdYvhfDBjXq+1WnvFvgixzHZRs2XCefTbZZz5d2AA3cCfU0IT/fLOvvhIM/xQ==@linaro.org X-Google-Smtp-Source: AGHT+IEUiIexqaC503YCoCQDD1LLkedfHm0bByKu0AulsWCBPmgdwBRYx+N6tZGYbssR8PTk0KBK X-Received: by 2002:ac8:7fc1:0:b0:477:7007:7055 with SMTP id d75a77b69052e-4801c7938cbmr1920711cf.12.1745533330915; Thu, 24 Apr 2025 15:22:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745533330; cv=none; d=google.com; s=arc-20240605; b=CvD8f1DuEqFZ0IXqD6N8K2xi1QoksCWGpVe2JKjKXGzDO/ThL2k7WdYdn0MTdho1yk k5n5lwpSMVXdEqtoTZWhd/f7w6JuyZXy8VgmkHgxmiXNZjXXUgqaCQpE4HGXwel1+TuP ct75z1lZYgAV67EJTeuQhcxVJGgZxdrz1PT9XNIijuuidc+RottHgpzXD5e/liTaEPqq ycBXF6w2cDpb/wfag0o87KNBfS6Tb8GniaqBU9EMPFSDNwm3pGwZZedJjBCF47QQeiIK frZfzPb+Wi2SjQ5FIklMYnelmefJzV4kzBV3umQs2zk0MmIBarPS15NBN67BkFIoP+on 0f8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dcKxk9xHLzn4vLPNgBhLM1l0n+4cuceTbVRIhADD9/E=; fh=uBcnXbgj+MsdcdOyDUafcBnllaSDqhe1MpDgmcooLTQ=; b=XtiGUkMapm1JP2sqzXjBXIneViU38fP5BNckfLZIJhpsOg9TOKkfR5Y8eOTZmVToJv EqaS/cv9QHe4IyhXxqJlPCCFDpkcYJM5wTKsbaYdEENqqRp7xnZCU8hbV8fKH+U0poE3 yHWOKWMYAhmwsSyUQDdUzditta5NvL4oF2kTZIOPoCLKSifKhx6XJJfRH3kG+NyFbmLJ 2Gq2ATL7jAlNivfjKH2z5VZLTgXKgLplbgnY5qsdqzZi36mCBy4Raf6EvAMUWyy3MCC+ Fq1624iaPPTubUnkaG2M4sEqt+KXwvXl5nlucCgqo45t9C9dpLP+7MM8zX9pj5ZVIhOn yvWQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cppKjg3t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073c8cd7fsm520024f8f.1.2025.04.24.15.21.43 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:21:43 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 06/21] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine Date: Fri, 25 Apr 2025 00:20:57 +0200 Message-ID: <20250424222112.36194-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When we'll start to use target_machine_typename() to filter machines for the ARM/Aarch64 binaries, the 'none' machine would be filtered out. Register the proper interfaces to keep it available. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/core/null-machine.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c index 3e03771d570..9009d3d96f5 100644 --- a/hw/core/null-machine.c +++ b/hw/core/null-machine.c @@ -16,6 +16,7 @@ #include "hw/boards.h" #include "system/address-spaces.h" #include "hw/core/cpu.h" +#include "hw/arm/machines-qom.h" static void machine_none_init(MachineState *mch) { @@ -62,6 +63,11 @@ static const TypeInfo null_machine_types[] = { .name = MACHINE_TYPE_NAME("none"), .parent = TYPE_MACHINE, .class_init = null_machine_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_TARGET_AARCH64_MACHINE }, + { TYPE_TARGET_ARM_MACHINE }, + { }, + }, }, }; From patchwork Thu Apr 24 22:20:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883977 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3672379wrs; Thu, 24 Apr 2025 15:22:11 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWzTbdPvKZSv8gO+ngzMqacjXGSYtC94pUwlbaVFWD6zc5EfuPfN6AIz5Nmy/dluXrT47BAgw==@linaro.org X-Google-Smtp-Source: AGHT+IFpGAsVzVfkArtVW4wphnithBy2+gbSyKSwmk2j/gKHU30NgaMneqeN52DJ/4FjDnPasBqe X-Received: by 2002:a05:620a:1a04:b0:7c5:49e8:993b with SMTP id af79cd13be357-7c9607ced5cmr44006985a.56.1745533330894; Thu, 24 Apr 2025 15:22:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745533330; cv=none; d=google.com; s=arc-20240605; b=Xz/STB/3HI+LsEe+OIjYE8Ppz9p6mZmB+UqHOP8oulwuUXiox8NHRiv73XRi0aa52m qpVylizZ5Xt0R1eal1RxbGGECxXzoBLNdxkC2JloKphcQEI1XPWyE6B4fX/PcBBHwUGg wPj0xgedOFRIxzeWGX965doIWRbFpIfMyhgBmRxnfABHVF+Li7Co/5crEhKy/mqmDdXR K14vniDVZhden9KKSe+5PiWhe6UNk4U7A8Ss3/gG8PujIGaJRADKiI7PdElfF+zjxTUy bPVOVybqI3Vwv1IhfGa2uu1OMUbS0Evca+rYRe9phc1K9b06ziNsvZl+KmyeHX8SYkK8 r3OQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ISCwHnamOi/ipI6KbYtyNzFTKPWQy4gkSjvWVBd5Fe0=; fh=BvfO80c+RfA/g1HCm0aY41XHDobI/X7leKfSifrFtsQ=; b=UzoCbQV5bdHHOrpPHtGg8afdDz3EOnAC81dh8HNSgmYiWcc4HXXtQklFJqP594ji1v ZyI2UuXRh9g6oYJUZAMKhF8bXCh42a4S3TRdbhhbsXXlGLtid6uoYIVJq7AQfCQ962U6 zaslUd2rznhsSWtYiIHC7TrWCyZPQfo5IffTGcfB+QRxnz6IeSMbA7QIilOhwYKPAJdq RFyT6Yi53BtD7Ja5edfyNnLZnPTZhC3oo1Dbpf5hfnZC5tYmE3/ya7c0hSCPAYQFdTUA iARYtMmLdniq02C9MdcZ1+7Eo/V01/HJDEYIswDBY6hPp++EedBEThHQO/GpXtmmzvVy rlyw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TrBi2cnh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4409d2e01bdsm36708995e9.38.2025.04.24.15.21.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:21:48 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 07/21] hw/boards: Introduce DEFINE_MACHINE_WITH_INTERFACES() macro Date: Fri, 25 Apr 2025 00:20:58 +0200 Message-ID: <20250424222112.36194-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org DEFINE_MACHINE_WITH_INTERFACES() is similar to DEFINE_MACHINE() but allows to pass a InterfaceInfo[] pointer. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/hw/boards.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index 765dc8dd35e..3573907d597 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -744,7 +744,7 @@ struct MachineState { } \ } while (0) -#define DEFINE_MACHINE(namestr, machine_initfn) \ +#define DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, ifaces) \ static void machine_initfn##_class_init(ObjectClass *oc, const void *data) \ { \ MachineClass *mc = MACHINE_CLASS(oc); \ @@ -754,6 +754,7 @@ struct MachineState { .name = MACHINE_TYPE_NAME(namestr), \ .parent = TYPE_MACHINE, \ .class_init = machine_initfn##_class_init, \ + .interfaces = ifaces, \ }; \ static void machine_initfn##_register_types(void) \ { \ @@ -761,6 +762,9 @@ struct MachineState { } \ type_init(machine_initfn##_register_types) +#define DEFINE_MACHINE(namestr, machine_initfn) \ + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, NULL) + extern GlobalProperty hw_compat_10_0[]; extern const size_t hw_compat_10_0_len; From patchwork Thu Apr 24 22:20:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883996 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3673114wrs; Thu, 24 Apr 2025 15:24:41 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXpAfxXTaRy0cMwFktEPm/C/PQQtIQ8kn6ITXffdZPXePbZkrGSsU/5TdbRRMvQG+oBDvf2jA==@linaro.org X-Google-Smtp-Source: AGHT+IH6tg/c4giNvwjArxO+Rx5Bqe8Vi2GPYqGmLKMd0eUpFMna9tW/jSqmsanveuBIEd/OWEF6 X-Received: by 2002:a05:620a:4116:b0:7c5:54d8:3d43 with SMTP id af79cd13be357-7c9607c49acmr37410185a.58.1745533481457; Thu, 24 Apr 2025 15:24:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745533481; cv=none; d=google.com; s=arc-20240605; b=d1mcj4H2WkWZrEQQWqHSAh2+YW8DZNhmAxVqI/JBVDpbUO2sCh691f/qfw7IPYhNmQ wEry+bnLzcrQ967hsQSUABeoAqa5rTpgwNJUlvkkBgkYr/3T5JgycXYlQ143ZraYmjFJ qlnyH04LYLITLHn4FN4/ly7Pr+T6W9xMylC5uUqPPBqhWf/UYsCbXkTxG8Su8krM/qsQ khJGSBOn8spT2BEExf7y/ntpljizV92SIx8zIdpIEfm1Gj8ue1Vn2dSoGwH4xL3vcmGI F+GPOHnUxcpsZ8byTpHX/M9HNDBxz/8jb7ZY/fzNaKSfCfwABm0EDoFxZBlY9QvdF5Vx ZVJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yIUYggzBbwK532QnEX63ouNuUzspZ2vfdklTznzqOpk=; fh=O1sGeJR8/pPJoMBQA+D2rIk4MFEu+dNnttw4WNe7Mfs=; b=TRRYwKhTUDUhdiholiQJqF+zM2zRAt7FFbWqlJdrFbKv+yyLJxke4O7j62Dh5pjbHo gaifKOEkerMcs8Z1DajVudKPuCyUDnFriRJJJg/3iaPn2qk5RNZEu/QYAEJAuwxohRKL ZgPF48DWIFc7CfSFtySMhLe23zCLs7yLe66Wl+hSEpTkZeIj0RDpGFmLpygY5EcBhr7E qVaEiWLYmYSAcVx9+4bS8q/0Iwo9KIINyz/B1zNLwajtLsJuE8JPmfmOdr0vu1JH13H0 9cVE0z75tlWMUZrphgiNVXXzl0fA9yl/20hFkP5EyKjG5B7XfB8VjB0lwMyj8WUMr5Y+ H6VQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GdYRwBUe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073ca497esm512937f8f.24.2025.04.24.15.21.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:21:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros Date: Fri, 25 Apr 2025 00:20:59 +0200 Message-ID: <20250424222112.36194-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org A machine defined with the DEFINE_MACHINE_ARM_AARCH64() macro will be available on qemu-system-arm and qemu-system-aarch64 binaries. One defined with DEFINE_MACHINE_AARCH64() will only be available in the qemu-system-aarch64 binary. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/hw/arm/machines-qom.h | 13 +++++++++++++ target/arm/machine.c | 12 ++++++++++++ 2 files changed, 25 insertions(+) diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h index a17225f5f92..6277ee986d9 100644 --- a/include/hw/arm/machines-qom.h +++ b/include/hw/arm/machines-qom.h @@ -9,10 +9,23 @@ #ifndef HW_ARM_MACHINES_QOM_H #define HW_ARM_MACHINES_QOM_H +#include "hw/boards.h" + #define TYPE_TARGET_ARM_MACHINE \ "target-info-arm-machine" #define TYPE_TARGET_AARCH64_MACHINE \ "target-info-aarch64-machine" +extern InterfaceInfo arm_aarch64_machine_interfaces[]; +extern InterfaceInfo aarch64_machine_interfaces[]; + +#define DEFINE_MACHINE_ARM_AARCH64(namestr, machine_initfn) \ + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \ + arm_aarch64_machine_interfaces) + +#define DEFINE_MACHINE_AARCH64(namestr, machine_initfn) \ + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \ + aarch64_machine_interfaces) + #endif diff --git a/target/arm/machine.c b/target/arm/machine.c index 978249fb71b..193c7a9cff0 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -8,6 +8,7 @@ #include "cpu-features.h" #include "migration/cpu.h" #include "target/arm/gtimer.h" +#include "hw/arm/machines-qom.h" static bool vfp_needed(void *opaque) { @@ -1111,3 +1112,14 @@ const VMStateDescription vmstate_arm_cpu = { NULL } }; + +InterfaceInfo arm_aarch64_machine_interfaces[] = { + { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_AARCH64_MACHINE }, + { } +}; + +InterfaceInfo aarch64_machine_interfaces[] = { + { TYPE_TARGET_AARCH64_MACHINE }, + { } +}; From patchwork Thu Apr 24 22:21:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883986 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3672658wrs; Thu, 24 Apr 2025 15:23:07 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXgQSCojEwptpmnZx7FUbsB6gtudJcsXmJGmUbj+s9qg7JSubBo766hNY/RWGEFguazCWMyVQ==@linaro.org X-Google-Smtp-Source: AGHT+IHQWye6iubJynRlBD+n9IVZooF3B7DvNN5T0v5mwGsGJsfQCFXfbBKaXhJYWZVW4kPsDsTl X-Received: by 2002:a05:620a:2989:b0:7c5:ad99:9e38 with SMTP id af79cd13be357-7c9607a34f8mr39084785a.43.1745533387272; Thu, 24 Apr 2025 15:23:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745533387; cv=none; d=google.com; s=arc-20240605; b=SHJs6s7N/4ZsL5ojJBwnrRSHeyPjlGRiAOrevXsUuiCYaSWPlRmvK33/bkigprZSJZ wUOnWQ7GSH5WXb7FMxm66fdANqyQx94GSOmabi7+n7ydG62O86LAIxY75hhV84KGzJAs eP60DgmIzEUA1BCwo8kmqBSVBfLK3VmHh16J7FRQ57AAD1ay4AbOYxayZWSAYk6g5qhv nJpXM92yvLEusbkP661Yf5BZ2uNBvxltDrBmtYl6Uh7QD9NNOs2aeyJwDPXVEzELuEeY IaPvzF4WNfzmlfjDrP2UfpDWmjwd6eg1Yi64uBlziy/WphmUrAShzaAxZQ1CDO+ABYH/ S1/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TRMg07MpXQjaKdKXGqzTyDi2UYEueXOVzRzuBPNarXE=; fh=+hNC3PnBPBwD23mlA9Ep26iYzJwFIZ7ZEz8s3EAfPfc=; b=WiIbuwizprQ/rLV/lu/dP57qsoYyMG3Pp8H8slejT8rOajytTyZWTa6v2yBfb9V6Qx oe4YdH6l4vydvjxYcfhEPvRy+h+nVUykMumNJuZPPqe+xvaHQbsoyiRJmz28pnj7NmGL OadKEa0mGMG7VC26/8HVF9M/Tf9OGP13HsdaD6VhzV39ePFZllSB4hPbEde1ROaqoO9F +3g4mWnKPUmik83z+ZBHEOe+IKmWpxQHMjQ590Yi0LQJObHU8LaRlRAEZo3xvMiotNcD cNeFreEkAwsp3i4wSFQUyySy+eOvOtC/CpDRTuKmtj4K2+CI3YIEkLz1RJc02z8pjuXu +YeA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XUV62e39; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073e5cffasm465814f8f.96.2025.04.24.15.21.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:21:58 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 09/21] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Date: Fri, 25 Apr 2025 00:21:00 +0200 Message-ID: <20250424222112.36194-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Register machines to be able to run with the qemu-system-arm and qemu-system-aarch64 binaries, except few machines which are only available on the qemu-system-aarch64 binary: $ git grep TARGET_AARCH64 hw/arm/meson.build hw/arm/meson.build:31:arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c')) hw/arm/meson.build:50:arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c')) $ git grep -W AARCH64 hw/arm/Kconfig hw/arm/Kconfig=185=config SBSA_REF hw/arm/Kconfig-186- bool hw/arm/Kconfig-187- default y hw/arm/Kconfig:188: depends on TCG && AARCH64 -- hw/arm/Kconfig=413=config XLNX_ZYNQMP_ARM hw/arm/Kconfig-414- bool hw/arm/Kconfig-415- default y if PIXMAN hw/arm/Kconfig:416: depends on TCG && AARCH64 -- hw/arm/Kconfig=435=config XLNX_VERSAL hw/arm/Kconfig-436- bool hw/arm/Kconfig-437- default y hw/arm/Kconfig:438: depends on TCG && AARCH64 -- hw/arm/Kconfig=475=config NPCM8XX hw/arm/Kconfig-476- bool hw/arm/Kconfig-477- default y hw/arm/Kconfig:478: depends on TCG && AARCH64 -- hw/arm/Kconfig=605=config FSL_IMX8MP_EVK hw/arm/Kconfig-606- bool hw/arm/Kconfig-607- default y hw/arm/Kconfig:608: depends on TCG && AARCH64 $ git grep -wW TARGET_AARCH64 hw/arm | fgrep -4 MACHINE_TYPE_NAME ... hw/arm/aspeed.c:1939:#ifdef TARGET_AARCH64 hw/arm/aspeed.c-1940- }, { hw/arm/aspeed.c-1941- .name = MACHINE_TYPE_NAME("ast2700a0-evb"), hw/arm/aspeed.c-1949- .name = MACHINE_TYPE_NAME("ast2700a1-evb"), hw/arm/raspi.c:420:#ifdef TARGET_AARCH64 hw/arm/raspi.c-421- }, { hw/arm/raspi.c-422- .name = MACHINE_TYPE_NAME("raspi3ap"), hw/arm/raspi.c-429- }, { hw/arm/raspi.c-430- .name = MACHINE_TYPE_NAME("raspi3b"), This can be verified as: $ diff -u0 <(qemu-system-arm -M help) <(qemu-system-aarch64 -M help) @@ -5,3 +4,0 @@ -ast2700-evb Aspeed AST2700 A0 EVB (Cortex-A35) (alias of ast2700a0-evb) -ast2700a0-evb Aspeed AST2700 A0 EVB (Cortex-A35) -ast2700a1-evb Aspeed AST2700 A1 EVB (Cortex-A35) @@ -22 +18,0 @@ -imx8mp-evk NXP i.MX 8M Plus EVK Board @@ -49 +44,0 @@ -npcm845-evb Nuvoton NPCM845 Evaluation Board (Cortex-A35) @@ -63,3 +57,0 @@ -raspi3ap Raspberry Pi 3A+ (revision 1.0) -raspi3b Raspberry Pi 3B (revision 1.2) -raspi4b Raspberry Pi 4B (revision 1.5) @@ -72 +63,0 @@ -sbsa-ref QEMU 'SBSA Reference' ARM Virtual Machine @@ -116,2 +106,0 @@ -xlnx-versal-virt Xilinx Versal Virtual development board -xlnx-zcu102 Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on the value of smp Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/arm/aspeed.c | 25 ++++++++++++++++++++++++- hw/arm/b-l475e-iot01a.c | 2 ++ hw/arm/bananapi_m2u.c | 3 ++- hw/arm/collie.c | 2 ++ hw/arm/cubieboard.c | 3 ++- hw/arm/digic_boards.c | 3 ++- hw/arm/exynos4_boards.c | 3 +++ hw/arm/fby35.c | 2 ++ hw/arm/highbank.c | 3 +++ hw/arm/imx25_pdk.c | 3 ++- hw/arm/imx8mp-evk.c | 4 +++- hw/arm/integratorcp.c | 3 ++- hw/arm/kzm.c | 3 ++- hw/arm/mcimx6ul-evk.c | 4 +++- hw/arm/mcimx7d-sabre.c | 4 +++- hw/arm/microbit.c | 2 ++ hw/arm/mps2-tz.c | 5 +++++ hw/arm/mps2.c | 5 +++++ hw/arm/mps3r.c | 2 ++ hw/arm/msf2-som.c | 3 ++- hw/arm/musca.c | 3 +++ hw/arm/musicpal.c | 3 ++- hw/arm/netduino2.c | 3 ++- hw/arm/netduinoplus2.c | 3 ++- hw/arm/npcm7xx_boards.c | 6 ++++++ hw/arm/npcm8xx_boards.c | 2 ++ hw/arm/olimex-stm32-h405.c | 3 ++- hw/arm/omap_sx1.c | 3 +++ hw/arm/orangepi.c | 3 ++- hw/arm/raspi.c | 6 ++++++ hw/arm/raspi4b.c | 2 ++ hw/arm/realview.c | 5 +++++ hw/arm/sabrelite.c | 3 ++- hw/arm/sbsa-ref.c | 2 ++ hw/arm/stellaris.c | 3 +++ hw/arm/stm32vldiscovery.c | 3 ++- hw/arm/versatilepb.c | 3 +++ hw/arm/vexpress.c | 3 +++ hw/arm/virt.c | 2 ++ hw/arm/xilinx_zynq.c | 2 ++ hw/arm/xlnx-versal-virt.c | 2 ++ hw/arm/xlnx-zcu102.c | 2 ++ 42 files changed, 133 insertions(+), 18 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 20f418fb63b..06a49343d4a 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -15,6 +15,7 @@ #include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" #include "hw/arm/aspeed_eeprom.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "hw/i2c/i2c_mux_pca954x.h" #include "hw/i2c/smbus_eeprom.h" @@ -1773,91 +1774,113 @@ static const TypeInfo aspeed_machine_types[] = { .name = MACHINE_TYPE_NAME("palmetto-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_palmetto_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_supermicrox11_bmc_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("ast2500-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2500_evb_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("romulus-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_romulus_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("sonorapass-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_sonorapass_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("witherspoon-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_witherspoon_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("ast2600-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2600_evb_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_yosemitev2_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("tiogapass-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_tiogapass_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("g220a-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_g220a_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_qcom_firework_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_fp5280g2_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_quanta_q71l_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("rainier-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_rainier_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("fuji-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_fuji_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("bletchley-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_bletchley_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("fby35-bmc"), .parent = MACHINE_TYPE_NAME("ast2600-evb"), .class_init = aspeed_machine_fby35_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("ast1030-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, + .interfaces = arm_aarch64_machine_interfaces, #ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("ast2700a0-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2700a0_evb_class_init, - }, { + .interfaces = aarch64_machine_interfaces, + }, { .name = MACHINE_TYPE_NAME("ast2700a1-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2700a1_evb_class_init, + .interfaces = aarch64_machine_interfaces, #endif }, { .name = TYPE_ASPEED_MACHINE, diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index 34ed2e0851b..ed275ecce9d 100644 --- a/hw/arm/b-l475e-iot01a.c +++ b/hw/arm/b-l475e-iot01a.c @@ -29,6 +29,7 @@ #include "qemu/error-report.h" #include "hw/arm/boot.h" #include "hw/core/split-irq.h" +#include "hw/arm/machines-qom.h" #include "hw/arm/stm32l4x5_soc.h" #include "hw/gpio/stm32l4x5_gpio.h" #include "hw/display/dm163.h" @@ -131,6 +132,7 @@ static const TypeInfo bl475e_machine_type[] = { .parent = TYPE_MACHINE, .instance_size = sizeof(Bl475eMachineState), .class_init = bl475e_machine_init, + .interfaces = arm_aarch64_machine_interfaces, } }; diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c index b750a575f72..90c3ec1c255 100644 --- a/hw/arm/bananapi_m2u.c +++ b/hw/arm/bananapi_m2u.c @@ -27,6 +27,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-r40.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" static struct arm_boot_info bpim2u_binfo; @@ -144,4 +145,4 @@ static void bpim2u_machine_init(MachineClass *mc) mc->auto_create_sdcard = true; } -DEFINE_MACHINE("bpim2u", bpim2u_machine_init) +DEFINE_MACHINE_ARM_AARCH64("bpim2u-pdk", bpim2u_machine_init) diff --git a/hw/arm/collie.c b/hw/arm/collie.c index 93bb190f1f9..ac841ef2b0a 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -15,6 +15,7 @@ #include "hw/boards.h" #include "strongarm.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "system/address-spaces.h" #include "qom/object.h" @@ -86,6 +87,7 @@ static const TypeInfo collie_machine_typeinfo = { .parent = TYPE_MACHINE, .class_init = collie_machine_class_init, .instance_size = sizeof(CollieMachineState), + .interfaces = arm_aarch64_machine_interfaces, }; static void collie_machine_register_types(void) diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index d665d4edd97..c66424effa0 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -22,6 +22,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-a10.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/i2c/i2c.h" static struct arm_boot_info cubieboard_binfo = { @@ -125,4 +126,4 @@ static void cubieboard_machine_init(MachineClass *mc) mc->auto_create_sdcard = true; } -DEFINE_MACHINE("cubieboard", cubieboard_machine_init) +DEFINE_MACHINE_ARM_AARCH64("cubieboard", cubieboard_machine_init) diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index 466b8b84c0e..f71c16be0fe 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -29,6 +29,7 @@ #include "hw/boards.h" #include "qemu/error-report.h" #include "hw/arm/digic.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "hw/loader.h" #include "system/qtest.h" @@ -145,4 +146,4 @@ static void canon_a1100_machine_init(MachineClass *mc) mc->default_ram_id = "ram"; } -DEFINE_MACHINE("canon-a1100", canon_a1100_machine_init) +DEFINE_MACHINE_ARM_AARCH64("canon-a1100", canon_a1100_machine_init) diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index 73049741312..e39a35df190 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -28,6 +28,7 @@ #include "hw/sysbus.h" #include "net/net.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "system/address-spaces.h" #include "hw/arm/exynos4210.h" #include "hw/net/lan9118.h" @@ -172,6 +173,7 @@ static const TypeInfo nuri_type = { .name = MACHINE_TYPE_NAME("nuri"), .parent = TYPE_MACHINE, .class_init = nuri_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void smdkc210_class_init(ObjectClass *oc, const void *data) @@ -192,6 +194,7 @@ static const TypeInfo smdkc210_type = { .name = MACHINE_TYPE_NAME("smdkc210"), .parent = TYPE_MACHINE, .class_init = smdkc210_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void exynos4_machines_init(void) diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c index e123fa69e19..7e00e8a0fc1 100644 --- a/hw/arm/fby35.c +++ b/hw/arm/fby35.c @@ -14,6 +14,7 @@ #include "hw/qdev-clock.h" #include "hw/arm/aspeed_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #define TYPE_FBY35 MACHINE_TYPE_NAME("fby35") OBJECT_DECLARE_SIMPLE_TYPE(Fby35State, FBY35); @@ -187,6 +188,7 @@ static const TypeInfo fby35_types[] = { .class_init = fby35_class_init, .instance_size = sizeof(Fby35State), .instance_init = fby35_instance_init, + .interfaces = arm_aarch64_machine_interfaces, }, }; diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 3ae26ebebdc..1656a82190d 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -23,6 +23,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/loader.h" #include "net/net.h" #include "system/runstate.h" @@ -363,6 +364,7 @@ static const TypeInfo highbank_type = { .name = MACHINE_TYPE_NAME("highbank"), .parent = TYPE_MACHINE, .class_init = highbank_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void midway_class_init(ObjectClass *oc, const void *data) @@ -387,6 +389,7 @@ static const TypeInfo midway_type = { .name = MACHINE_TYPE_NAME("midway"), .parent = TYPE_MACHINE, .class_init = midway_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void calxeda_machines_init(void) diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index e95ea5e4e18..87d3c8b91c5 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -28,6 +28,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/fsl-imx25.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "qemu/error-report.h" #include "system/qtest.h" @@ -150,4 +151,4 @@ static void imx25_pdk_machine_init(MachineClass *mc) mc->auto_create_sdcard = true; } -DEFINE_MACHINE("imx25-pdk", imx25_pdk_machine_init) +DEFINE_MACHINE_ARM_AARCH64("imx25-pdk", imx25_pdk_machine_init) diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c index b3082fa60d8..a40443fb0a7 100644 --- a/hw/arm/imx8mp-evk.c +++ b/hw/arm/imx8mp-evk.c @@ -10,6 +10,7 @@ #include "system/address-spaces.h" #include "hw/arm/boot.h" #include "hw/arm/fsl-imx8mp.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "system/qtest.h" @@ -100,4 +101,5 @@ static void imx8mp_evk_machine_init(MachineClass *mc) mc->max_cpus = FSL_IMX8MP_NUM_CPUS; mc->default_ram_id = "imx8mp-evk.ram"; } -DEFINE_MACHINE("imx8mp-evk", imx8mp_evk_machine_init) + +DEFINE_MACHINE_AARCH64("imx8mp", imx8mp_evk_machine_init) diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index b1d8fbd470a..9e10d0343c7 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -13,6 +13,7 @@ #include "migration/vmstate.h" #include "hw/boards.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/misc/arm_integrator_debug.h" #include "hw/net/smc91c111.h" #include "net/net.h" @@ -693,7 +694,7 @@ static void integratorcp_machine_init(MachineClass *mc) machine_add_audiodev_property(mc); } -DEFINE_MACHINE("integratorcp", integratorcp_machine_init) +DEFINE_MACHINE_ARM_AARCH64("integratorcp", integratorcp_machine_init) static const Property core_properties[] = { DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index 362c1454099..1de68b1c5d0 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -17,6 +17,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx31.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "qemu/error-report.h" #include "system/address-spaces.h" @@ -139,4 +140,4 @@ static void kzm_machine_init(MachineClass *mc) mc->default_ram_id = "kzm.ram"; } -DEFINE_MACHINE("kzm", kzm_machine_init) +DEFINE_MACHINE_ARM_AARCH64("kzm", kzm_machine_init) diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index 86982cb0772..cbc319fa737 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -14,6 +14,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx6ul.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" @@ -76,4 +77,5 @@ static void mcimx6ul_evk_machine_init(MachineClass *mc) mc->default_ram_id = "mcimx6ul-evk.ram"; mc->auto_create_sdcard = true; } -DEFINE_MACHINE("mcimx6ul-evk", mcimx6ul_evk_machine_init) + +DEFINE_MACHINE_ARM_AARCH64("mcimx6ul-evk", mcimx6ul_evk_machine_init) diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index 33119610113..349924dbb21 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -16,6 +16,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx7.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" @@ -76,4 +77,5 @@ static void mcimx7d_sabre_machine_init(MachineClass *mc) mc->default_ram_id = "mcimx7d-sabre.ram"; mc->auto_create_sdcard = true; } -DEFINE_MACHINE("mcimx7d-sabre", mcimx7d_sabre_machine_init) + +DEFINE_MACHINE_ARM_AARCH64("mcimx7d-sabre", mcimx7d_sabre_machine_init) diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index 525443fdb97..41db5715c3f 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -12,6 +12,7 @@ #include "qapi/error.h" #include "hw/boards.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "system/system.h" #include "system/address-spaces.h" @@ -74,6 +75,7 @@ static const TypeInfo microbit_info = { .parent = TYPE_MACHINE, .instance_size = sizeof(MicrobitMachineState), .class_init = microbit_machine_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void microbit_machine_init(void) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 5dd87cc0281..2d2637e5d4a 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -52,6 +52,7 @@ #include "qemu/error-report.h" #include "hw/arm/boot.h" #include "hw/arm/armv7m.h" +#include "hw/arm/machines-qom.h" #include "hw/or-irq.h" #include "hw/boards.h" #include "system/address-spaces.h" @@ -1463,24 +1464,28 @@ static const TypeInfo mps2tz_an505_info = { .name = TYPE_MPS2TZ_AN505_MACHINE, .parent = TYPE_MPS2TZ_MACHINE, .class_init = mps2tz_an505_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static const TypeInfo mps2tz_an521_info = { .name = TYPE_MPS2TZ_AN521_MACHINE, .parent = TYPE_MPS2TZ_MACHINE, .class_init = mps2tz_an521_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static const TypeInfo mps3tz_an524_info = { .name = TYPE_MPS3TZ_AN524_MACHINE, .parent = TYPE_MPS2TZ_MACHINE, .class_init = mps3tz_an524_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static const TypeInfo mps3tz_an547_info = { .name = TYPE_MPS3TZ_AN547_MACHINE, .parent = TYPE_MPS2TZ_MACHINE, .class_init = mps3tz_an547_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void mps2tz_machine_init(void) diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 58efb41e6db..523d56908ed 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -31,6 +31,7 @@ #include "qemu/error-report.h" #include "hw/arm/boot.h" #include "hw/arm/armv7m.h" +#include "hw/arm/machines-qom.h" #include "hw/or-irq.h" #include "hw/boards.h" #include "system/address-spaces.h" @@ -563,24 +564,28 @@ static const TypeInfo mps2_an385_info = { .name = TYPE_MPS2_AN385_MACHINE, .parent = TYPE_MPS2_MACHINE, .class_init = mps2_an385_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static const TypeInfo mps2_an386_info = { .name = TYPE_MPS2_AN386_MACHINE, .parent = TYPE_MPS2_MACHINE, .class_init = mps2_an386_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static const TypeInfo mps2_an500_info = { .name = TYPE_MPS2_AN500_MACHINE, .parent = TYPE_MPS2_MACHINE, .class_init = mps2_an500_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static const TypeInfo mps2_an511_info = { .name = TYPE_MPS2_AN511_MACHINE, .parent = TYPE_MPS2_MACHINE, .class_init = mps2_an511_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void mps2_machine_init(void) diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c index 48c73acc62e..683dd97ee09 100644 --- a/hw/arm/mps3r.c +++ b/hw/arm/mps3r.c @@ -37,6 +37,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/boot.h" #include "hw/arm/bsa.h" +#include "hw/arm/machines-qom.h" #include "hw/char/cmsdk-apb-uart.h" #include "hw/i2c/arm_sbcon_i2c.h" #include "hw/intc/arm_gicv3.h" @@ -634,6 +635,7 @@ static const TypeInfo mps3r_machine_types[] = { .name = TYPE_MPS3R_AN536_MACHINE, .parent = TYPE_MPS3R_MACHINE, .class_init = mps3r_an536_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, }; diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 29c76c68605..864b7e56aed 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -32,6 +32,7 @@ #include "hw/boards.h" #include "hw/qdev-properties.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/qdev-clock.h" #include "system/address-spaces.h" #include "hw/arm/msf2-soc.h" @@ -108,4 +109,4 @@ static void emcraft_sf2_machine_init(MachineClass *mc) mc->valid_cpu_types = valid_cpu_types; } -DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init) +DEFINE_MACHINE_ARM_AARCH64("emcraft-sf2", emcraft_sf2_machine_init) diff --git a/hw/arm/musca.c b/hw/arm/musca.c index 250b3b5bf84..64d4f41cd60 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -26,6 +26,7 @@ #include "system/system.h" #include "hw/arm/boot.h" #include "hw/arm/armsse.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/char/pl011.h" #include "hw/core/split-irq.h" @@ -657,12 +658,14 @@ static const TypeInfo musca_a_info = { .name = TYPE_MUSCA_A_MACHINE, .parent = TYPE_MUSCA_MACHINE, .class_init = musca_a_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static const TypeInfo musca_b1_info = { .name = TYPE_MUSCA_B1_MACHINE, .parent = TYPE_MUSCA_MACHINE, .class_init = musca_b1_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void musca_machine_init(void) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 329b162eb20..548c218a039 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -15,6 +15,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "net/net.h" #include "system/system.h" #include "hw/boards.h" @@ -1346,7 +1347,7 @@ static void musicpal_machine_init(MachineClass *mc) machine_add_audiodev_property(mc); } -DEFINE_MACHINE("musicpal", musicpal_machine_init) +DEFINE_MACHINE_ARM_AARCH64("musicpal", musicpal_machine_init) static void mv88w8618_wlan_class_init(ObjectClass *klass, const void *data) { diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index df793c77fe1..6b7fee0973f 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -30,6 +30,7 @@ #include "qemu/error-report.h" #include "hw/arm/stm32f205_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" /* Main SYSCLK frequency in Hz (120MHz) */ #define SYSCLK_FRQ 120000000ULL @@ -65,4 +66,4 @@ static void netduino2_machine_init(MachineClass *mc) mc->ignore_memory_transaction_failures = true; } -DEFINE_MACHINE("netduino2", netduino2_machine_init) +DEFINE_MACHINE_ARM_AARCH64("netduino2", netduino2_machine_init) diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index 81b6334cf72..4a666f226b0 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -30,6 +30,7 @@ #include "qemu/error-report.h" #include "hw/arm/stm32f405_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" /* Main SYSCLK frequency in Hz (168MHz) */ #define SYSCLK_FRQ 168000000ULL @@ -65,4 +66,4 @@ static void netduinoplus2_machine_init(MachineClass *mc) mc->valid_cpu_types = valid_cpu_types; } -DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init) +DEFINE_MACHINE_ARM_AARCH64("netduinoplus2", netduinoplus2_machine_init) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 465a0e5acec..2bd90847acd 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -17,6 +17,7 @@ #include "qemu/osdep.h" #include "hw/arm/npcm7xx.h" +#include "hw/arm/machines-qom.h" #include "hw/core/cpu.h" #include "hw/i2c/i2c_mux_pca954x.h" #include "hw/i2c/smbus_eeprom.h" @@ -549,22 +550,27 @@ static const TypeInfo npcm7xx_machine_types[] = { .name = MACHINE_TYPE_NAME("npcm750-evb"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = npcm750_evb_machine_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("quanta-gsj"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = gsj_machine_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("quanta-gbs-bmc"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = gbs_bmc_machine_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("kudo-bmc"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = kudo_bmc_machine_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("mori-bmc"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = mori_bmc_machine_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, }; diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c index 9d9f6d0c9a6..9167f1f4099 100644 --- a/hw/arm/npcm8xx_boards.c +++ b/hw/arm/npcm8xx_boards.c @@ -19,6 +19,7 @@ #include "chardev/char.h" #include "hw/boards.h" #include "hw/arm/npcm8xx.h" +#include "hw/arm/machines-qom.h" #include "hw/core/cpu.h" #include "hw/loader.h" #include "hw/qdev-core.h" @@ -248,6 +249,7 @@ static const TypeInfo npcm8xx_machine_types[] = { .name = MACHINE_TYPE_NAME("npcm845-evb"), .parent = TYPE_NPCM8XX_MACHINE, .class_init = npcm845_evb_machine_class_init, + .interfaces = aarch64_machine_interfaces, }, }; diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c index 1f15620f9fd..4300cfb8862 100644 --- a/hw/arm/olimex-stm32-h405.c +++ b/hw/arm/olimex-stm32-h405.c @@ -31,6 +31,7 @@ #include "qemu/error-report.h" #include "hw/arm/stm32f405_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" /* olimex-stm32-h405 implementation is derived from netduinoplus2 */ @@ -71,4 +72,4 @@ static void olimex_stm32_h405_machine_init(MachineClass *mc) mc->default_ram_size = 0; } -DEFINE_MACHINE("olimex-stm32-h405", olimex_stm32_h405_machine_init) +DEFINE_MACHINE_ARM_AARCH64("olimex-stm32-h405", olimex_stm32_h405_machine_init) diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index 1d89a202bb9..d53a9aa49e9 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -32,6 +32,7 @@ #include "hw/arm/omap.h" #include "hw/boards.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "system/qtest.h" #include "system/address-spaces.h" @@ -219,6 +220,7 @@ static const TypeInfo sx1_machine_v2_type = { .name = MACHINE_TYPE_NAME("sx1"), .parent = TYPE_MACHINE, .class_init = sx1_machine_v2_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void sx1_machine_v1_class_init(ObjectClass *oc, const void *data) @@ -238,6 +240,7 @@ static const TypeInfo sx1_machine_v1_type = { .name = MACHINE_TYPE_NAME("sx1-v1"), .parent = TYPE_MACHINE, .class_init = sx1_machine_v1_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void sx1_machine_init(void) diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index e0956880d11..3ea78811069 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -26,6 +26,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-h3.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" static struct arm_boot_info orangepi_binfo; @@ -124,4 +125,4 @@ static void orangepi_machine_init(MachineClass *mc) mc->auto_create_sdcard = true; } -DEFINE_MACHINE("orangepi-pc", orangepi_machine_init) +DEFINE_MACHINE_ARM_AARCH64("orangepi-pc", orangepi_machine_init) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 9d9af63d654..2a6b6aac0a6 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -25,6 +25,7 @@ #include "hw/boards.h" #include "hw/loader.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "qom/object.h" #define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common") @@ -394,23 +395,28 @@ static const TypeInfo raspi_machine_types[] = { .name = MACHINE_TYPE_NAME("raspi0"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi0_machine_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("raspi1ap"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi1ap_machine_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("raspi2b"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi2b_machine_class_init, + .interfaces = arm_aarch64_machine_interfaces, #ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("raspi3ap"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi3ap_machine_class_init, + .interfaces = arm_aarch64_machine_interfaces, }, { .name = MACHINE_TYPE_NAME("raspi3b"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi3b_machine_class_init, + .interfaces = arm_aarch64_machine_interfaces, #endif }, { .name = TYPE_RASPI_MACHINE, diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c index 20082d52667..b88af07b037 100644 --- a/hw/arm/raspi4b.c +++ b/hw/arm/raspi4b.c @@ -11,6 +11,7 @@ #include "qemu/cutils.h" #include "qapi/error.h" #include "qapi/visitor.h" +#include "hw/arm/machines-qom.h" #include "hw/arm/raspi_platform.h" #include "hw/display/bcm2835_fb.h" #include "hw/registerfields.h" @@ -127,6 +128,7 @@ static const TypeInfo raspi4b_machine_type = { .parent = TYPE_RASPI_BASE_MACHINE, .instance_size = sizeof(Raspi4bMachineState), .class_init = raspi4b_machine_class_init, + .interfaces = aarch64_machine_interfaces, }; static void raspi4b_machine_register_type(void) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 5c9050490b4..9deacbd6075 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -13,6 +13,7 @@ #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" +#include "hw/arm/machines-qom.h" #include "hw/core/split-irq.h" #include "hw/net/lan9118.h" #include "hw/net/smc91c111.h" @@ -431,6 +432,7 @@ static const TypeInfo realview_eb_type = { .name = MACHINE_TYPE_NAME("realview-eb"), .parent = TYPE_MACHINE, .class_init = realview_eb_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void realview_eb_mpcore_class_init(ObjectClass *oc, const void *data) @@ -452,6 +454,7 @@ static const TypeInfo realview_eb_mpcore_type = { .name = MACHINE_TYPE_NAME("realview-eb-mpcore"), .parent = TYPE_MACHINE, .class_init = realview_eb_mpcore_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void realview_pb_a8_class_init(ObjectClass *oc, const void *data) @@ -471,6 +474,7 @@ static const TypeInfo realview_pb_a8_type = { .name = MACHINE_TYPE_NAME("realview-pb-a8"), .parent = TYPE_MACHINE, .class_init = realview_pb_a8_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void realview_pbx_a9_class_init(ObjectClass *oc, const void *data) @@ -491,6 +495,7 @@ static const TypeInfo realview_pbx_a9_type = { .name = MACHINE_TYPE_NAME("realview-pbx-a9"), .parent = TYPE_MACHINE, .class_init = realview_pbx_a9_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void realview_machine_init(void) diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index df60d47c6fd..91c7467fdc2 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -14,6 +14,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx6.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" @@ -113,4 +114,4 @@ static void sabrelite_machine_init(MachineClass *mc) mc->auto_create_sdcard = true; } -DEFINE_MACHINE("sabrelite", sabrelite_machine_init) +DEFINE_MACHINE_ARM_AARCH64("sabrelite", sabrelite_machine_init) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index deae5cf9861..907c3c948cd 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -34,6 +34,7 @@ #include "hw/arm/bsa.h" #include "hw/arm/fdt.h" #include "hw/arm/smmuv3.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "hw/boards.h" #include "hw/ide/ide-bus.h" @@ -920,6 +921,7 @@ static const TypeInfo sbsa_ref_info = { .instance_init = sbsa_ref_instance_init, .class_init = sbsa_ref_class_init, .instance_size = sizeof(SBSAMachineState), + .interfaces = aarch64_machine_interfaces, }; static void sbsa_ref_machine_init(void) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 031ea3a24e7..9fea3b6e75e 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -15,6 +15,7 @@ #include "hw/sd/sd.h" #include "hw/ssi/ssi.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "qemu/timer.h" #include "hw/i2c/i2c.h" #include "net/net.h" @@ -1427,6 +1428,7 @@ static const TypeInfo lm3s811evb_type = { .name = MACHINE_TYPE_NAME("lm3s811evb"), .parent = TYPE_MACHINE, .class_init = lm3s811evb_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; /* @@ -1448,6 +1450,7 @@ static const TypeInfo lm3s6965evb_type = { .name = MACHINE_TYPE_NAME("lm3s6965evb"), .parent = TYPE_MACHINE, .class_init = lm3s6965evb_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void stellaris_machine_init(void) diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index e6c1f5b8d7d..d042bef0bd0 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -31,6 +31,7 @@ #include "qemu/error-report.h" #include "hw/arm/stm32f100_soc.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" /* stm32vldiscovery implementation is derived from netduinoplus2 */ @@ -68,4 +69,4 @@ static void stm32vldiscovery_machine_init(MachineClass *mc) mc->valid_cpu_types = valid_cpu_types; } -DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init) +DEFINE_MACHINE_ARM_AARCH64("stm32vldiscovery", stm32vldiscovery_machine_init) diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 5cf1a70d10d..8f2a34f8bd9 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -12,6 +12,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "hw/net/smc91c111.h" #include "net/net.h" #include "system/system.h" @@ -431,6 +432,7 @@ static const TypeInfo versatilepb_type = { .name = MACHINE_TYPE_NAME("versatilepb"), .parent = TYPE_MACHINE, .class_init = versatilepb_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void versatileab_class_init(ObjectClass *oc, const void *data) @@ -452,6 +454,7 @@ static const TypeInfo versatileab_type = { .name = MACHINE_TYPE_NAME("versatileab"), .parent = TYPE_MACHINE, .class_init = versatileab_class_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void versatile_machine_init(void) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 35f8d05ea17..6faecea2635 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -27,6 +27,7 @@ #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" +#include "hw/arm/machines-qom.h" #include "hw/net/lan9118.h" #include "hw/i2c/i2c.h" #include "net/net.h" @@ -850,6 +851,7 @@ static const TypeInfo vexpress_a9_info = { .parent = TYPE_VEXPRESS_MACHINE, .class_init = vexpress_a9_class_init, .instance_init = vexpress_a9_instance_init, + .interfaces = arm_aarch64_machine_interfaces, }; static const TypeInfo vexpress_a15_info = { @@ -857,6 +859,7 @@ static const TypeInfo vexpress_a15_info = { .parent = TYPE_VEXPRESS_MACHINE, .class_init = vexpress_a15_class_init, .instance_init = vexpress_a15_instance_init, + .interfaces = arm_aarch64_machine_interfaces, }; static void vexpress_machine_init(void) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 177f3dd22c1..6185ac1046f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -37,6 +37,7 @@ #include "hw/arm/boot.h" #include "hw/arm/primecell.h" #include "hw/arm/virt.h" +#include "hw/arm/machines-qom.h" #include "hw/block/flash.h" #include "hw/vfio/vfio-calxeda-xgmac.h" #include "hw/vfio/vfio-amd-xgbe.h" @@ -123,6 +124,7 @@ static void arm_virt_compat_set(MachineClass *mc) .name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \ .parent = TYPE_VIRT_MACHINE, \ .class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \ + .interfaces = arm_aarch64_machine_interfaces, \ }; \ static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \ { \ diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 0372cd0ac46..dd164e1b6a8 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -20,6 +20,7 @@ #include "qapi/error.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "net/net.h" #include "system/system.h" #include "hw/boards.h" @@ -480,6 +481,7 @@ static const TypeInfo zynq_machine_type = { .parent = TYPE_MACHINE, .class_init = zynq_machine_class_init, .instance_size = sizeof(ZynqMachineState), + .interfaces = arm_aarch64_machine_interfaces, }; static void zynq_machine_register_types(void) diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index adadbb72902..dee5cf8a3a9 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -20,6 +20,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/xlnx-versal.h" #include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" #include "target/arm/multiprocessing.h" #include "qom/object.h" @@ -833,6 +834,7 @@ static const TypeInfo versal_virt_machine_init_typeinfo = { .instance_init = versal_virt_machine_instance_init, .instance_size = sizeof(VersalVirt), .instance_finalize = versal_virt_machine_finalize, + .interfaces = aarch64_machine_interfaces, }; static void versal_virt_machine_init_register_types(void) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 14b6641a713..330f375f63a 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -19,6 +19,7 @@ #include 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4409d2ad112sm34996335e9.24.2025.04.24.15.22.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:22:03 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 10/21] meson: Prepare to accept per-binary TargetInfo structure implementation Date: Fri, 25 Apr 2025 00:21:01 +0200 Message-ID: <20250424222112.36194-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If a file defining the binary TargetInfo structure is available, link with it. Otherwise keep using the stub. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- MAINTAINERS | 1 + meson.build | 9 ++++++++- configs/targets/meson.build | 4 ++++ 3 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 configs/targets/meson.build diff --git a/MAINTAINERS b/MAINTAINERS index 451e2778888..63cf1e6ed5b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1932,6 +1932,7 @@ M: Philippe Mathieu-Daudé S: Supported F: include/qemu/target-info*.h F: target-info*.c +F: configs/targets/*.c Xtensa Machines --------------- diff --git a/meson.build b/meson.build index 32e6aeb295d..70ee7e838ed 100644 --- a/meson.build +++ b/meson.build @@ -3204,6 +3204,7 @@ config_devices_mak_list = [] config_devices_h = {} config_target_h = {} config_target_mak = {} +config_target_info = {} disassemblers = { 'alpha' : ['CONFIG_ALPHA_DIS'], @@ -3797,9 +3798,9 @@ specific_ss.add(files('page-target.c', 'page-vary-target.c')) common_ss.add(files('target-info.c')) system_ss.add(files('target-info-qom.c')) -specific_ss.add(files('target-info-stub.c')) subdir('backends') +subdir('configs/targets') subdir('disas') subdir('migration') subdir('monitor') @@ -4260,6 +4261,12 @@ foreach target : target_dirs arch_srcs += gdbstub_xml endif + if target in config_target_info + arch_srcs += config_target_info[target] + else + arch_srcs += files('target-info-stub.c') + endif + t = target_arch[target_base_arch].apply(config_target, strict: false) arch_srcs += t.sources() arch_deps += t.dependencies() diff --git a/configs/targets/meson.build b/configs/targets/meson.build new file mode 100644 index 00000000000..a9f6b24ec01 --- /dev/null +++ b/configs/targets/meson.build @@ -0,0 +1,4 @@ +foreach target : [ + ] + config_target_info += {target : files(target + '.c')} +endforeach From patchwork Thu Apr 24 22:21:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883980 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3672465wrs; Thu, 24 Apr 2025 15:22:28 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVWE09VAVSQQ72MMml+qlUNM7PWLDtLxK+muhL2UfPP+dO2ORSY0XV1HKxerHgwI/AHpxnj9w==@linaro.org X-Google-Smtp-Source: AGHT+IGPNmBKTrTuclgPK94569rSCD2yUzOrRF0QJtAxKk+b1Dqjf9m+t4xVm6vbYdPCW/q0lchT X-Received: by 2002:a05:620a:4083:b0:7c7:609d:d223 with SMTP id af79cd13be357-7c96077cdcdmr33802285a.42.1745533348406; Thu, 24 Apr 2025 15:22:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745533348; cv=none; d=google.com; s=arc-20240605; b=EF78bh+BW0Q+bwoGXRSTChrq1XgRWsiW+pyrfS8+jESEflVMYBKTTsDPLgfBIMYokU y0Bbf/y1Hsj+f1hJ+cT1xZyNs9oZ7dmThWSGEOb2MtfU7ZEco2FgidKRNk1ncxGuabH5 8X8sTQ0e/ZK8I5w2s9T/Pbx1z2LXrBC5kC1r4yIWX1/YBN1KO3mblhZ9H/yTcGpbq1yA 5Z5LszmEzOezAqYB8AMsnHun6Bl3qs8rneP31EDqNp4UpbgmhTT1YzoBnkHPfsQOa2wU 4yqKtGirAm8A36f73EcN5V0r7qS91z8C9W4YaGTr1qL6TAbADj3pFyLMpDI8J/1FRAgj 9oWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=B/LeVH0iEfwnigHnY2wTQENZ/qjw+iDaeRA3zB+Oyw4=; fh=9cOBtwzTPS8SVNoOdBluK3y5UcR063ckSsIeln67hu4=; b=eH3jxhIDnFgCxyAytv9RDO8YaI8sv6vnVxYPAdSGXQVEOgo+YzSAxhbaUqTEGyLOSI q5QUWCaQEyNFSd6goxK96PtlvLmnjsyllRzTV6ElVx1e/wgujpLbW3FbuEbOOmJPVtsc 6YEYToLtDKdluDgIU7KZFElQKiLPqmK5o7PALOtQoUQ+K5ItwKVF3nqlz8fSgI/VsqjF gX0GDsdplXpDNUxHAqnfBq2fhlCi4h3WJzr3MUBGYZjeeYYnlbHVF6cS6oyVG0c8puCU b31LWjIgrOReChgSHoT+dprthkfcOV6imxIgJz44qxRTU6VMIZcBZUKbcuuaY7vzDtYr AFHw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="nj/Dy4YE"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073c8c7a4sm538641f8f.14.2025.04.24.15.22.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:22:07 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 11/21] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) Date: Fri, 25 Apr 2025 00:21:02 +0200 Message-ID: <20250424222112.36194-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Implement the TargetInfo structure for qemu-system-arm and qemu-system-aarch64 binaries. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- configs/targets/aarch64-softmmu.c | 22 ++++++++++++++++++++++ configs/targets/arm-softmmu.c | 22 ++++++++++++++++++++++ configs/targets/meson.build | 1 + 3 files changed, 45 insertions(+) create mode 100644 configs/targets/aarch64-softmmu.c create mode 100644 configs/targets/arm-softmmu.c diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c new file mode 100644 index 00000000000..375e6fa0b7b --- /dev/null +++ b/configs/targets/aarch64-softmmu.c @@ -0,0 +1,22 @@ +/* + * QEMU binary/target API (qemu-system-aarch64) + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" +#include "hw/arm/machines-qom.h" +#include "target/arm/cpu-qom.h" + +static const TargetInfo target_info_aarch64_system = { + .target_name = "aarch64", + .machine_typename = TYPE_TARGET_AARCH64_MACHINE, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_aarch64_system; +} diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c new file mode 100644 index 00000000000..d4acdae64f3 --- /dev/null +++ b/configs/targets/arm-softmmu.c @@ -0,0 +1,22 @@ +/* + * QEMU binary/target API (qemu-system-arm) + * + * Copyright (c) Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" +#include "hw/arm/machines-qom.h" +#include "target/arm/cpu-qom.h" + +static const TargetInfo target_info_arm_system = { + .target_name = "arm", + .machine_typename = TYPE_TARGET_ARM_MACHINE, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_arm_system; +} diff --git a/configs/targets/meson.build b/configs/targets/meson.build index a9f6b24ec01..cca2514eb51 100644 --- a/configs/targets/meson.build +++ b/configs/targets/meson.build @@ -1,4 +1,5 @@ foreach target : [ + 'arm-softmmu', 'aarch64-softmmu', ] config_target_info += {target : files(target + '.c')} endforeach From patchwork Thu Apr 24 22:21:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883982 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3672538wrs; Thu, 24 Apr 2025 15:22:40 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWXQOH8mEevFh5qD0jGC2EVrAYrqrMUabm06FxWDZHbgGtqiRcldZNIKrlZ31ZgfAQsEaUw5A==@linaro.org X-Google-Smtp-Source: AGHT+IGULNMFEowDUbvzkNlEppfbiYLbPzR92ldVkKekqjty3SzHhsJr86QorZvWMs0G+OLuK9YD X-Received: by 2002:a05:622a:1487:b0:47a:e775:c100 with SMTP id d75a77b69052e-4801c2c16demr1982881cf.8.1745533360537; Thu, 24 Apr 2025 15:22:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745533360; cv=none; d=google.com; s=arc-20240605; b=gKWEMyVgu9hMsxKD99ylfMe4ItvojP5VkYDYTok3I8I9dvIrB4APd5Z8tk4gp8Yxn5 Eg/WJNYO6y9CzeH8dLTwA6yIhpksb6q/72G35biad0bQwqTGhPUulHVj6fHxU/DxY02G fZgMpL6YvB9LQ8viefwurGFPrzFnDycAY2TsXpLOpHjobltu7kI3arGBg0hx+ooDpZOs ktI2cwKNnto2grDH3Ylq5ffKkiTVB6wUQhClk1q3CXEiDXhBxl1RwJFeJsGr71TVgBGJ bUfpcfFsLCvSXZgjulOY8SHNdooeqS2K3YMvFnlj/+jQzoPrM0kdOJ7vNVmh5GXfKflR n3IQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=aBgCa6Sdg3OuqGwUu8T27tbAQFisBNWEy54fnvDVB+g=; fh=sOXOG87QLpy+nMyx88DlpI6gLL4tEbhR84FpsUX3oDU=; b=H0ZzmvxFO3EwS0OLqfuF5VA4m1oZGF52z+y07rKvOov4NkIegUzWSkwAV1/7QZDDxG MB1p+Hmy1mR8JHQ1w2Te17cWo+dc3O4xgI9EV6GNeTHBJTVhk0VHrGVS4PkD/K9xe7zb qH6/nPb2gJXf35yOl4sTRC6yw00kT7elK+NFFyFbr9wshaMHorhZNB6WyDVbj0/cKhDZ 4R3en2A63/wKE1ALXXbMLqPNu2/ro2rpYpgcwsrXZoOZr0rSgAVmueZ0Yk7JRLq3Ak3b lOJOc6l3XM/z6AO2YrrZrdwbyLCLug96/bfSAcrOsl/KB0saBpXFQ6wgVE3z6zVSkJHx qTAA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qAt46Ltd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-440a53874a9sm3029345e9.34.2025.04.24.15.22.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:22:12 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 12/21] hw/arm/aspeed: Build objects once Date: Fri, 25 Apr 2025 00:21:03 +0200 Message-ID: <20250424222112.36194-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now than Aspeed machines can be filtered when running a qemu-system-arm or qemu-system-aarch64 binary, we can remove the TARGET_AARCH64 #ifdef'ry and compile the aspeed.c file once, moving it from arm_ss[] source set to arm_common_ss[]. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- hw/arm/aspeed.c | 6 ------ hw/arm/meson.build | 4 ++-- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 06a49343d4a..0a5b603bc97 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -180,13 +180,11 @@ struct AspeedMachineState { #define AST2600_EVB_HW_STRAP1 0x000000C0 #define AST2600_EVB_HW_STRAP2 0x00000003 -#ifdef TARGET_AARCH64 /* AST2700 evb hardware value */ /* SCU HW Strap1 */ #define AST2700_EVB_HW_STRAP1 0x00000800 /* SCUIO HW Strap1 */ #define AST2700_EVB_HW_STRAP2 0x00000700 -#endif /* Rainier hardware value: (QEMU prototype) */ #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) @@ -1675,7 +1673,6 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); } -#ifdef TARGET_AARCH64 static void ast2700_evb_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc = bmc->soc; @@ -1727,7 +1724,6 @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, mc->default_ram_size = 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); } -#endif static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, const void *data) @@ -1870,7 +1866,6 @@ static const TypeInfo aspeed_machine_types[] = { .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, .interfaces = arm_aarch64_machine_interfaces, -#ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("ast2700a0-evb"), .parent = TYPE_ASPEED_MACHINE, @@ -1881,7 +1876,6 @@ static const TypeInfo aspeed_machine_types[] = { .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2700a1_evb_class_init, .interfaces = aarch64_machine_interfaces, -#endif }, { .name = TYPE_ASPEED_MACHINE, .parent = TYPE_MACHINE, diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 09b1cfe5b57..f76e7fb229f 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -39,15 +39,15 @@ arm_common_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'x arm_common_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c')) -arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( +arm_common_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed.c', 'aspeed_soc_common.c', 'aspeed_ast2400.c', 'aspeed_ast2600.c', 'aspeed_ast10x0.c', + 'aspeed_ast27x0.c', 'aspeed_eeprom.c', 'fby35.c')) -arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c')) arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c')) From patchwork Thu Apr 24 22:21:04 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073e4641csm461121f8f.80.2025.04.24.15.22.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:22:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 13/21] hw/arm/raspi: Build objects once Date: Fri, 25 Apr 2025 00:21:04 +0200 Message-ID: <20250424222112.36194-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now than Raspi machines can be filtered when running a qemu-system-arm or qemu-system-aarch64 binary, we can remove the TARGET_AARCH64 #ifdef'ry and compile the aspeed.c file once, moving it from arm_ss[] source set to arm_common_ss[]. Note, we expose the TYPE_BCM2837 type to qemu-system-arm, but it is not user-creatable, so not an issue. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- hw/arm/bcm2836.c | 4 ---- hw/arm/raspi.c | 4 ---- hw/arm/meson.build | 8 ++++++-- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index cd61ba15054..aaaff05624c 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -195,7 +195,6 @@ static void bcm2836_class_init(ObjectClass *oc, const void *data) dc->realize = bcm2836_realize; }; -#ifdef TARGET_AARCH64 static void bcm2837_class_init(ObjectClass *oc, const void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -208,7 +207,6 @@ static void bcm2837_class_init(ObjectClass *oc, const void *data) bc->clusterid = 0x0; dc->realize = bcm2836_realize; }; -#endif static const TypeInfo bcm283x_types[] = { { @@ -219,12 +217,10 @@ static const TypeInfo bcm283x_types[] = { .name = TYPE_BCM2836, .parent = TYPE_BCM283X, .class_init = bcm2836_class_init, -#ifdef TARGET_AARCH64 }, { .name = TYPE_BCM2837, .parent = TYPE_BCM283X, .class_init = bcm2837_class_init, -#endif }, { .name = TYPE_BCM283X, .parent = TYPE_BCM283X_BASE, diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 2a6b6aac0a6..d7d2920ad75 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -368,7 +368,6 @@ static void raspi2b_machine_class_init(ObjectClass *oc, const void *data) raspi_machine_class_init(mc, rmc->board_rev); }; -#ifdef TARGET_AARCH64 static void raspi3ap_machine_class_init(ObjectClass *oc, const void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -388,7 +387,6 @@ static void raspi3b_machine_class_init(ObjectClass *oc, const void *data) rmc->board_rev = 0xa02082; raspi_machine_class_init(mc, rmc->board_rev); }; -#endif /* TARGET_AARCH64 */ static const TypeInfo raspi_machine_types[] = { { @@ -406,7 +404,6 @@ static const TypeInfo raspi_machine_types[] = { .parent = TYPE_RASPI_MACHINE, .class_init = raspi2b_machine_class_init, .interfaces = arm_aarch64_machine_interfaces, -#ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("raspi3ap"), .parent = TYPE_RASPI_MACHINE, @@ -417,7 +414,6 @@ static const TypeInfo raspi_machine_types[] = { .parent = TYPE_RASPI_MACHINE, .class_init = raspi3b_machine_class_init, .interfaces = arm_aarch64_machine_interfaces, -#endif }, { .name = TYPE_RASPI_MACHINE, .parent = TYPE_RASPI_BASE_MACHINE, diff --git a/hw/arm/meson.build b/hw/arm/meson.build index f76e7fb229f..f52034ff6a2 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -27,8 +27,12 @@ arm_common_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c')) -arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) -arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c')) +arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files( + 'bcm2836.c', + 'bcm2838.c', + 'raspi.c', + 'raspi4b.c', +)) arm_common_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) arm_common_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) arm_common_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) From patchwork Thu Apr 24 22:21:05 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4409d2a152csm36281065e9.12.2025.04.24.15.22.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:22:22 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 14/21] hw/core/machine: Allow dynamic registration of valid CPU types Date: Fri, 25 Apr 2025 00:21:05 +0200 Message-ID: <20250424222112.36194-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add MachineClass::get_valid_cpu_types(), a helper that returns a dynamic list of CPU types. Since the helper takes a MachineState argument, we know the machine is created by the time we call it. Suggested-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/hw/boards.h | 4 ++++ hw/core/machine.c | 26 ++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/include/hw/boards.h b/include/hw/boards.h index 3573907d597..700e4f4ccf3 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -259,6 +259,9 @@ typedef struct { * @smbios_memory_device_size: * Default size of memory device, * SMBIOS 3.1.0 "7.18 Memory Device (Type 17)" + * @get_valid_cpu_types: + * Returns a list of valid CPU types for this board. May be NULL + * if not needed. */ struct MachineClass { /*< private >*/ @@ -306,6 +309,7 @@ struct MachineClass { bool ignore_memory_transaction_failures; int numa_mem_align_shift; const char * const *valid_cpu_types; + GPtrArray *(*get_valid_cpu_types)(const MachineState *ms); strList *allowed_dynamic_sysbus_devices; bool auto_enable_numa_with_memhp; bool auto_enable_numa_with_memdev; diff --git a/hw/core/machine.c b/hw/core/machine.c index ed01798d37c..0901a92b32a 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1581,6 +1581,32 @@ static bool is_cpu_type_supported(const MachineState *machine, Error **errp) error_append_hint(errp, "\n"); } + return false; + } + } else if (mc->get_valid_cpu_types) { + GPtrArray *vct = mc->get_valid_cpu_types(machine); + bool valid = false; + + for (i = 0; i < vct->len; i++) { + if (object_class_dynamic_cast(oc, vct->pdata[i])) { + valid = true; + break; + } + } + + if (!valid) { + g_autofree char *requested = cpu_model_from_type(machine->cpu_type); + + error_setg(errp, "Invalid CPU model: %s", requested); + error_append_hint(errp, "The valid models are: "); + for (i = 0; i < vct->len; i++) { + g_autofree char *model = cpu_model_from_type(vct->pdata[i]); + error_append_hint(errp, "%s%s", + model, i + 1 == vct->len ? "\n" : ", "); + } + } + g_ptr_array_free(vct, true); + if (!valid) { return false; } } From patchwork Thu Apr 24 22:21:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883995 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3673007wrs; Thu, 24 Apr 2025 15:24:24 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUqGBtoarPpc3KoPEc9CUOPFJ270p6KjbXS3TFsragnxq4w9saDTu2HM7vy5LbrUAVh1Hu0EQ==@linaro.org X-Google-Smtp-Source: AGHT+IGuYm4r9864w+G+Z8PhEtbOuvNEkOp5h7+kYHI96IrHWS5eGFqSSV4rCXWkGF4S+HV8X1W0 X-Received: by 2002:a05:620a:4627:b0:7c5:4278:d15f with SMTP id af79cd13be357-7c9606f9b14mr33863285a.17.1745533464098; Thu, 24 Apr 2025 15:24:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745533464; cv=none; d=google.com; s=arc-20240605; b=blI9ewBgApFhrXXBjgtwG1zlUysXR93Ax0YIIKWFL29DfH/o4HjYHH9YMYrucaTh7N 0bp8SVvC3tmYTd5Xwgdcow0qRQ7j4C6fykIaetN7UGy9+VuHFm9EB8+8IEcCYEx5Y+rd FsQDvLqi601zYMiwX4BcWk1/MmGyyB4riAti4rItUHGAw4ZSeXtr3J9mGSTyljQKQDZV I1Dz4BJptZOKZbbCJOCwyPu4Eqp50xwfnD10gKE+A1jHYus7Rl/IjJjjuopy7UfmyGgJ DWhKeaEKBGZ9oeQ7FZw0kshnYf5tCe9dOV6Oo5CgDKZocr+EKQEeAlFGE74dB58JlH5K Kz1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=X9F/Xu2/QMqJcrb8r8k7kzBHlfm38hQBgPZ/Fp6QYoE=; fh=K/8sz743ra7yO268ZvwOSBAjoyVRTHnc64MWyaZWw+A=; b=jY6v81dxATH73qOMQygIG+ZwcmNAgys2epYAh97SeCXglBFspz1IrJE/eGWr0fY4Vn jAPQK7SwWJWdieh2wRG/zq2Pih8Dkn8SldbOLeRY6BiLZNNevDbr0rkd3qTrYjQkAZ96 PE3qJJ0K3UM9nDf7Es3db+vGmyLA/KNNd3NVe0Bep3c4dPh7U5hMw4UquYi0a1aiQmks IX/kJ8Uez7g/Ox1vtaQFLn8jdQ2RQRHJ4hjnhiw2UV96yYLDHN59SeAF5QcrJFgDnrCY bpgGVnDxpPrm0Sbtm67RiGtHgePtoD7+yrNvYSbbbtzZA7C3ZI6d58bJROfxsIQmKm43 sZiQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eLirFQiR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073ca4cbcsm509704f8f.25.2025.04.24.15.22.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:22:27 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 15/21] hw/arm/virt: Register valid CPU types dynamically Date: Fri, 25 Apr 2025 00:21:06 +0200 Message-ID: <20250424222112.36194-16-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the static array returned as MachineClass::valid_cpu_types[] by a runtime one generated by MachineClass::get_valid_cpu_types() once the machine is created (its options being processed). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/arm/virt.c | 59 ++++++++++++++++++++++++++++----------------------- 1 file changed, 32 insertions(+), 27 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 6185ac1046f..f29f541ea93 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3126,36 +3126,41 @@ static int virt_hvf_get_physical_address_range(MachineState *ms) return requested_ipa_size; } +static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms) +{ + GPtrArray *vct = g_ptr_array_new_with_free_func(g_free); + +#ifdef CONFIG_TCG + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); +#ifdef TARGET_AARCH64 + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a55"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a72"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a76"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a710"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("a64fx"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); +#endif /* TARGET_AARCH64 */ +#endif /* CONFIG_TCG */ +#ifdef TARGET_AARCH64 + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57"))); +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("host"))); +#endif /* CONFIG_KVM || CONFIG_HVF */ +#endif /* TARGET_AARCH64 */ + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max"))); + + return vct; +} + static void virt_machine_class_init(ObjectClass *oc, const void *data) { MachineClass *mc = MACHINE_CLASS(oc); HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); - static const char * const valid_cpu_types[] = { -#ifdef CONFIG_TCG - ARM_CPU_TYPE_NAME("cortex-a7"), - ARM_CPU_TYPE_NAME("cortex-a15"), -#ifdef TARGET_AARCH64 - ARM_CPU_TYPE_NAME("cortex-a35"), - ARM_CPU_TYPE_NAME("cortex-a55"), - ARM_CPU_TYPE_NAME("cortex-a72"), - ARM_CPU_TYPE_NAME("cortex-a76"), - ARM_CPU_TYPE_NAME("cortex-a710"), - ARM_CPU_TYPE_NAME("a64fx"), - ARM_CPU_TYPE_NAME("neoverse-n1"), - ARM_CPU_TYPE_NAME("neoverse-v1"), - ARM_CPU_TYPE_NAME("neoverse-n2"), -#endif /* TARGET_AARCH64 */ -#endif /* CONFIG_TCG */ -#ifdef TARGET_AARCH64 - ARM_CPU_TYPE_NAME("cortex-a53"), - ARM_CPU_TYPE_NAME("cortex-a57"), -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) - ARM_CPU_TYPE_NAME("host"), -#endif /* CONFIG_KVM || CONFIG_HVF */ -#endif /* TARGET_AARCH64 */ - ARM_CPU_TYPE_NAME("max"), - NULL - }; mc->init = machvirt_init; /* Start with max_cpus set to 512, which is the maximum supported by KVM. @@ -3183,7 +3188,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data) #else mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); #endif - mc->valid_cpu_types = valid_cpu_types; + mc->get_valid_cpu_types = virt_get_valid_cpu_types; mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; mc->kvm_type = virt_kvm_type; mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range; From patchwork Thu Apr 24 22:21:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883989 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3672732wrs; Thu, 24 Apr 2025 15:23:20 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW0rFx8fMIID5l2PZmLrdayOT3Ac1vLGyo+mYEqJn4nsmsZyTsaWLvSkUzD/rImatuq9T2Kpw==@linaro.org X-Google-Smtp-Source: AGHT+IE0l17UPcifDIKdBFhE/KduCXJEgX7r2Z1V3Dan+msdHmbNR0nXJDDHMbCLSdbR3c3q7ugk X-Received: by 2002:a05:6214:f6b:b0:6e8:9170:9d06 with SMTP id 6a1803df08f44-6f4cba63842mr3156626d6.37.1745533399806; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4409d2a2386sm36668235e9.14.2025.04.24.15.22.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:22:32 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 16/21] hw/arm/virt: Check accelerator availability at runtime Date: Fri, 25 Apr 2025 00:21:07 +0200 Message-ID: <20250424222112.36194-17-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org It is not possible to call accelerator runtime helpers when QOM types are registered, because they depend on the parsing of the '-accel FOO' command line option, which happens after main(). Now than get_valid_cpu_types() is called after accelerator initializations, it is safe to call the accelerator helpers: main + configure_accelerators + qmp_x_exit_preconfig + qemu_init_board + machine_run_board_init + is_cpu_type_supported Replace compile-time check on CONFIG_{ACCEL} by runtime check on {accel}_enabled() helpers. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- hw/arm/virt.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index f29f541ea93..13aa2f34c6c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3130,7 +3130,7 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms) { GPtrArray *vct = g_ptr_array_new_with_free_func(g_free); -#ifdef CONFIG_TCG + if (tcg_enabled()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); #ifdef TARGET_AARCH64 @@ -3144,13 +3144,13 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms) g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); #endif /* TARGET_AARCH64 */ -#endif /* CONFIG_TCG */ + } #ifdef TARGET_AARCH64 g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57"))); -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) + if (kvm_enabled() || hvf_enabled()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("host"))); -#endif /* CONFIG_KVM || CONFIG_HVF */ + } #endif /* TARGET_AARCH64 */ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max"))); From patchwork Thu Apr 24 22:21:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883988 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3672706wrs; Thu, 24 Apr 2025 15:23:16 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWpjGxXkM9UWhYxcJJhYJcSvCLab18yJQ1hcnH/sQyOpiVKc0kw9NPq/9HWJVs2vTvIjlDnDQ==@linaro.org X-Google-Smtp-Source: AGHT+IEg0d7e1rQYNeyG80/8lcQyS8guMxCOs8e2Sf7iuSIdRT9N4s6fr3Y1f6HOJ6ecJXl86e1S X-Received: by 2002:a05:620a:460b:b0:7c5:3d60:7f88 with SMTP id af79cd13be357-7c9606de175mr34078185a.16.1745533396437; Thu, 24 Apr 2025 15:23:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745533396; cv=none; d=google.com; s=arc-20240605; b=d005/mQkF4rikPe7JoTBZPSppgIjx6MPyXnP6eynY32Bzhdsq/a+GSm4QvIKsd0Hzi 9eYnm9xJnQd309KZkwqtrLrk8RKoSbmmfBg9W03GXgVZOUafCoeFwB5qwmdna0uytvbB nakGqCrhZauhpoSLjFPPcvF1ORG5CpTZYWxMLlfvvte9Smey+tqVFD5OlsPo5Z0imfv2 hr7XkkSRslj3WmLJ/Q2KLXwJEc42pRMrqyg3Z7CwRcs1wQMadQ6Qyj6dbli9jYxmM3nZ RFisA/UNpRDjFDFnt1gXcVTkxh+VgVB0Lu6R4HNHiYCrNn03xkvQevA1FlliPSEg0q2H pXEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yyQnKU/Qb5MFlABzvGsbZVvBtDKdqhE3tTnhTcPso0Q=; fh=N/lBpjKCuvT6E7SMRk5pTv1WM6euM5RVe3usvrGRil8=; b=Szq64LUzZgWPrkfv1qdP5+8DnkX8dmns1evuH8Kb5z3RTdWNmXWJERNuewlq1JTgiD Ch6oqAkuclI+NRxUiVMi72JQUj6mIBjK1hIx3UjQXCgDQOiRxLRyvOuHGqknwPanhbJS +ngHkPlNI408Ac1ZzfHzrrQsyna/8k0tZj28hBTFFLD6UR1TU7Tdy06Lr+yzMwMH+Dfk xjc6uA3eTIlSR57AWDobPwCm6GfxdiOIPGCLxv52qciXv/zwnmhPJ9sfNaoLRrDtFCdE ttXLMh3GbozS87zt7aRJtHF5FnfGGharYQ2iy9ix5XQuNGGiT6jCn0fouw3lDkcvEIsD ETFA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g9dkEEVU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-440a536a1d1sm3101845e9.26.2025.04.24.15.22.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:22:37 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 17/21] qemu/target_info: Add %target_arch field to TargetInfo Date: Fri, 25 Apr 2025 00:21:08 +0200 Message-ID: <20250424222112.36194-18-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/qemu/target-info-impl.h | 3 +++ configs/targets/aarch64-softmmu.c | 1 + configs/targets/arm-softmmu.c | 1 + target-info-stub.c | 1 + 4 files changed, 6 insertions(+) diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h index d0e8c86176c..e5ef425f2dc 100644 --- a/include/qemu/target-info-impl.h +++ b/include/qemu/target-info-impl.h @@ -10,10 +10,13 @@ #define QEMU_TARGET_INFO_IMPL_H #include "qemu/target-info.h" +#include "qapi/qapi-types-machine.h" typedef struct TargetInfo { /* runtime equivalent of TARGET_NAME definition */ const char *target_name; + /* related to TARGET_ARCH definition */ + SysEmuTarget target_arch; /* QOM typename machines for this binary must implement */ const char *machine_typename; } TargetInfo; diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c index 375e6fa0b7b..ff89401ea34 100644 --- a/configs/targets/aarch64-softmmu.c +++ b/configs/targets/aarch64-softmmu.c @@ -13,6 +13,7 @@ static const TargetInfo target_info_aarch64_system = { .target_name = "aarch64", + .target_arch = SYS_EMU_TARGET_AARCH64, .machine_typename = TYPE_TARGET_AARCH64_MACHINE, }; diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c index d4acdae64f3..22ec9e4faa3 100644 --- a/configs/targets/arm-softmmu.c +++ b/configs/targets/arm-softmmu.c @@ -13,6 +13,7 @@ static const TargetInfo target_info_arm_system = { .target_name = "arm", + .target_arch = SYS_EMU_TARGET_ARM, .machine_typename = TYPE_TARGET_ARM_MACHINE, }; diff --git a/target-info-stub.c b/target-info-stub.c index 218e5898e7f..e573f5c1975 100644 --- a/target-info-stub.c +++ b/target-info-stub.c @@ -12,6 +12,7 @@ static const TargetInfo target_info_stub = { .target_name = TARGET_NAME, + .target_arch = -1, .machine_typename = TYPE_MACHINE, }; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073e46538sm471329f8f.64.2025.04.24.15.22.43 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:22:44 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 18/21] qemu/target_info: Add target_aarch64() helper Date: Fri, 25 Apr 2025 00:21:09 +0200 Message-ID: <20250424222112.36194-19-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a helper to distinct the binary is targetting Aarch64 or not. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/qemu/target-info.h | 7 +++++++ target-info.c | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 0224b35b166..395c009baf2 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -24,4 +24,11 @@ const char *target_name(void); */ const char *target_machine_typename(void); +/** + * target_aarch64: + * + * Returns whether the target architecture is Aarch64. + */ +bool target_aarch64(void); + #endif diff --git a/target-info.c b/target-info.c index 0042769e3a2..7f1758ae34f 100644 --- a/target-info.c +++ b/target-info.c @@ -19,3 +19,8 @@ const char *target_machine_typename(void) { return target_info()->machine_typename; } + +bool target_aarch64(void) +{ + return target_info()->target_arch == SYS_EMU_TARGET_AARCH64; +} From patchwork Thu Apr 24 22:21:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883994 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3672839wrs; Thu, 24 Apr 2025 15:23:43 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXD4+i+GwwEiC+Y8iUEth/nLyA+yxdTPZwsCJu/oaXB4+jKRD5nQ8aW1neUqq//Y5vsyra6CQ==@linaro.org X-Google-Smtp-Source: AGHT+IF/+krq9ME8iXujV0TSbTuWpJM/ntD9kc1JPcZ3OPwtyeNL/MjBD/wrwbb71a7IZlceCDY0 X-Received: by 2002:a05:622a:1c18:b0:476:98d6:141d with SMTP id d75a77b69052e-4801e2fb8f1mr2776531cf.32.1745533423229; Thu, 24 Apr 2025 15:23:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745533423; cv=none; d=google.com; s=arc-20240605; b=JvPNhW+vLYLqc5OJ5MWF3Yi7izULeC4wE7UVvDjqG2p/FY1ezFVmKg5ya91XY0Lzz7 TuTC+ACqEsQzS21hpzUSzLeZmqVv3GF2Zs82tLdvlLaAy7qi20BMk+L9+TOZWgF5WoL2 DEggg2ypvXz4osleAKMtlTOjNKhV7bc1ug8rJfWTaxxSnUo87KP91YRTs90hJE0UqC/n OurIo1Dvflfu6ExsJWBlW9H8/uh/ayyPL9Av9K+8FY/tOQncjF3zMTCg5J1uj/pjbtGN oDSa0ZrENzxtGQ8dxUidh9kCk16IFfVsVbTvL0bIiFbrvohlP72x6Ui/HGc0VIQhBZr4 FGJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TEEsp3WvcS1IZU1517HV/+srKi3TaTLqQjkTs9SQZOc=; fh=GesL+1h7kHHhaX1UnnJJQkHUiUPwrVqGhnWkOJOYAqY=; b=Jo/WtdBXbjdoKpSn73RClotzxGHHVMLIUkbMeK3jrbP9uBHTaut302durjjyydL/hK ufIsBYDYplT3yM/3J5AMSln7D1SppdtaHmsdhdWc1HhTjCSxZQfXID+FaU0Wuai2rVB8 jdxQiO5syEhJ7C93l5Zshwvxts/fUSI5GBTYMTPuF7txKSfj3YrJ+2hRdihR0GYBGBdH uoDfmJj0N5qsvgdNW10V6LbQ16PF2Z0kq/thwzNFFF+d/oZZWcyTPDK5a0USM04BAmpK GJm2T6wSOtEOpiMaiLq3m85J5YnsYB/dbgmhr0bswNA8Yxcx5AAPfM8trSwpBtHi7JX6 37dA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e+Ty8Y+e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073c8cd7fsm521991f8f.1.2025.04.24.15.22.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:22:48 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 19/21] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Date: Fri, 25 Apr 2025 00:21:10 +0200 Message-ID: <20250424222112.36194-20-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the target-specific TARGET_AARCH64 definition by a call to the generic target_aarch64() helper. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- hw/arm/virt.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 13aa2f34c6c..566afa4c978 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -32,6 +32,7 @@ #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/option.h" +#include "qemu/target-info.h" #include "monitor/qdev.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" @@ -3133,7 +3134,8 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms) if (tcg_enabled()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15"))); -#ifdef TARGET_AARCH64 + } + if (tcg_enabled() && target_aarch64()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a55"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a72"))); @@ -3143,15 +3145,14 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms) g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); -#endif /* TARGET_AARCH64 */ } -#ifdef TARGET_AARCH64 + if (target_aarch64()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57"))); if (kvm_enabled() || hvf_enabled()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("host"))); } -#endif /* TARGET_AARCH64 */ + } g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max"))); return vct; From patchwork Thu Apr 24 22:21:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883991 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3672766wrs; Thu, 24 Apr 2025 15:23:29 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXTipKVTxRo0/7rxkXjpq4EaoRd6uXMqclVlJ4i+z18RHVPVSnfPZxa3LbUR6lpeyp3vrSZ4w==@linaro.org X-Google-Smtp-Source: AGHT+IE1ZDu+z3Ia4ULewOCTYzy4Zhdyf14MgzY7DsvkFP2kVewyV75HIfpYnEcYR0kv/cQk6vuU X-Received: by 2002:a05:6214:1c07:b0:6e8:9535:b00 with SMTP id 6a1803df08f44-6f4cb9d29a1mr2478136d6.12.1745533408868; Thu, 24 Apr 2025 15:23:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745533408; cv=none; d=google.com; s=arc-20240605; b=k9Jpt1iAisr934jpSQmikkVaF7QiJYC7arPvGZKugqA/dX14xvkzS/TA6w2CHv9ne6 9FyuYJVEiirRNt5pmfi0CEtKAwICV/i4iXay/8ohgnusRyoKd76lYFXyeHMw74KZtBoz oYN+NAE5zKtVbZzKyOS0ENpBUjXtE/HsZKCD5G8bsdTp1K04fGwT5Ies3Q06gUpNd5Id bkmfP9wgGcUspCV+voSuFp2LlcRYL/e9NGC1R1PJClYSm9D9sWb7LW3ypimxYLTOCpj2 TGZIVV553inBez3MjPkiWPDs9fx8Cu9qWz21wbe5+dVYVyBNSWqOgPJxf+D53kwV6ZJy 33qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5OslDaHmml5vji5p+h0aO4Re5CvOPTyryghOTVR1940=; fh=fxYC0ZCoqAjQu6l5+GdvDuS0IkRFZ1VlrW9ie6uSwT0=; b=KXSt/G8HpkETRlMJ3g00pnH2erIS3Tae7/wHaSSH+LnToGdcWh5U+uQAq75vE54AVx 2r3/AiwZtydiTw26Xn5SXvrlSFS6ncBXiVfVys7k9rLFsN6SS/npUpfchzrCEqdAn4T8 bkA/YCrsBBaBAMiW352yxDHXhw5ijlpRp1A+NPbUlqerac/rUyF8N4+Hb0/FAgrP9qcG EfzznLjjinl51qs5tv6zZxBeaDUk14DmnA93krU/XfIAWtPlE6dq8KuxsBBeV4tKWYgJ /pYpZQR+6x0Mz1LUtbEO5flQhAE6rKFrr2+I5I1Hkngndd2L1tVlcOf9fLXcBH/q+xKF CvbQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iGr2VF6q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073ca5219sm511485f8f.27.2025.04.24.15.22.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:22:54 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 20/21] hw/core: Introduce MachineClass::get_default_cpu_type() helper Date: Fri, 25 Apr 2025 00:21:11 +0200 Message-ID: <20250424222112.36194-21-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org MachineClass::get_default_cpu_type() runs once the machine is created, being able to evaluate runtime checks; it returns the machine default CPU type. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/hw/boards.h | 6 ++++++ hw/core/machine.c | 10 ++++++++++ system/vl.c | 2 +- 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index 700e4f4ccf3..cc2f81cefeb 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -25,6 +25,11 @@ OBJECT_DECLARE_TYPE(MachineState, MachineClass, MACHINE) extern MachineState *current_machine; +/** + * machine_default_cpu_type: Return the machine default CPU type. + * @ms: Machine state + */ +const char *machine_default_cpu_type(const MachineState *ms); /** * machine_class_default_cpu_type: Return the machine default CPU type. * @mc: Machine class @@ -310,6 +315,7 @@ struct MachineClass { int numa_mem_align_shift; const char * const *valid_cpu_types; GPtrArray *(*get_valid_cpu_types)(const MachineState *ms); + const char *(*get_default_cpu_type)(const MachineState *ms); strList *allowed_dynamic_sysbus_devices; bool auto_enable_numa_with_memhp; bool auto_enable_numa_with_memdev; diff --git a/hw/core/machine.c b/hw/core/machine.c index 0901a92b32a..ba9ddf1b1f7 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1541,6 +1541,16 @@ const char *machine_class_default_cpu_type(MachineClass *mc) return mc->default_cpu_type; } +const char *machine_default_cpu_type(const MachineState *ms) +{ + MachineClass *mc = MACHINE_GET_CLASS(ms); + + if (mc->get_default_cpu_type) { + return mc->get_default_cpu_type(ms); + } + return machine_class_default_cpu_type(mc); +} + static bool is_cpu_type_supported(const MachineState *machine, Error **errp) { MachineClass *mc = MACHINE_GET_CLASS(machine); diff --git a/system/vl.c b/system/vl.c index e8706a9ce87..338f9d75289 100644 --- a/system/vl.c +++ b/system/vl.c @@ -3825,7 +3825,7 @@ void qemu_init(int argc, char **argv) migration_object_init(); /* parse features once if machine provides default cpu_type */ - current_machine->cpu_type = machine_class_default_cpu_type(machine_class); + current_machine->cpu_type = machine_default_cpu_type(current_machine); if (cpu_option) { current_machine->cpu_type = parse_cpu_option(cpu_option); } From patchwork Thu Apr 24 22:21:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 883992 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3672768wrs; Thu, 24 Apr 2025 15:23:29 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVZxoE7DhDkFdtvWms812rzxaCpiUkwzo/qKm0aFviYHxjcBHvVoRPqTYPLD0I6ssQDAG+2Sw==@linaro.org X-Google-Smtp-Source: AGHT+IH/c7TjSkhUh/x9EoNwitu+5xV+TJjp7VuX4hFbfjUzQJqnDOU5zZVIuRlmd7iDEqEGjxdN X-Received: by 2002:a05:622a:110b:b0:478:f69b:ac9 with SMTP id d75a77b69052e-47ec266ba2fmr66068961cf.11.1745533409067; Thu, 24 Apr 2025 15:23:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745533409; cv=none; d=google.com; s=arc-20240605; b=UdnYoFx7Zu7HvnmtVY4pKeBysLcQyEsIN67m30L+Z7bJgLlY9S1PIQTBZ6URFHUPZ1 E1sBfUIQEFtyvmDQsahPcG13A0uqvbxSlLkg8ITgkiS///TR8TPKv2Rtk6dXOW68UzsU XyXmaIdrAChB4owZNYQrG3AdSxz2lE912aSLvsJ/TNoxCnyTgs+p+M6oPfNRV91urkHT wG9m6+jTPhyGvdm6z9er/W6ntxWFwFZ2V5hMKZljTEEaAAa7bdPxxjfeVBEKsczhodU8 16pbuoM1Mf5svrEBkO5msdn0H7kHIF/FFEd6Ptc3gFM+MW5j+cYFXPgRZeCWod7aIw1S a5ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=uWC7ZUuhMJjjntdzJpmYnoIJKuGi0kxenHJ2eaOicnY=; fh=xBDGjMrCmtN2EfzM/Vp8N6QwWER4yVVcK/Wv9WxPqwQ=; b=d8ZDZDlQEIN4QO2W7hlXu68FmExkuQypJpt8i6WWhnsF6/mCdK5fytjqOwCXsbqHMn QU9r/EoUp3L5Pfcsp5H8wBes3NVQEUCp/iTPOk20OEufl+ZiFa5O5hLUzwqQwKz7qGvL jiENaW1mre399pWGPoeJeXLcspqvQ8DvFL13vPKipvFwy2RT2Ah98PWwWt8IC8L7aDyD DTngbSvALv438SHiN/PCNGjh5vuE2l2/Adwratq4U1dnpuUHEHY4IoSzdHUG0Iag62fi 9gB3MroWxjAsPYeu409qedOq0+QMxfoDU6iFjMWTk56iIUwBAAsfE8tk5HxTmS8W4H73 2TiA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="fZi/TxeA"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073c8cc74sm531999f8f.11.2025.04.24.15.22.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 15:22:58 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Pierrick Bouvier , Richard Henderson , qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v5 21/21] hw/arm/virt: Get default CPU type at runtime Date: Fri, 25 Apr 2025 00:21:12 +0200 Message-ID: <20250424222112.36194-22-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424222112.36194-1-philmd@linaro.org> References: <20250424222112.36194-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Prefer MachineClass::get_default_cpu_type() over MachineClass::default_cpu_type to get CPU type, evaluating TCG availability at runtime calling tcg_enabled(). It's worth noting that this is a behavior change: - Previously only ./configure --disable-tcg --enable-kvm ./qemu-system-aarch64 -M virt -accel kvm would default to 'max' and ./configure --enable-tcg --enable-kvm ./qemu-system-aarch64 -M virt -accel kvm would default to 'cortex-a15'. - Afterward, -accel kvm will always default to 'max'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/virt.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 566afa4c978..b59cc90bd36 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3127,6 +3127,12 @@ static int virt_hvf_get_physical_address_range(MachineState *ms) return requested_ipa_size; } +static const char *virt_get_default_cpu_type(const MachineState *ms) +{ + return tcg_enabled() ? ARM_CPU_TYPE_NAME("cortex-a15") + : ARM_CPU_TYPE_NAME("max"); +} + static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms) { GPtrArray *vct = g_ptr_array_new_with_free_func(g_free); @@ -3184,11 +3190,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data) mc->minimum_page_bits = 12; mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = virt_cpu_index_to_props; -#ifdef CONFIG_TCG - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); -#else - mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); -#endif + mc->get_default_cpu_type = virt_get_default_cpu_type; mc->get_valid_cpu_types = virt_get_valid_cpu_types; mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; mc->kvm_type = virt_kvm_type;