From patchwork Thu Apr 24 06:20:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 885122 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2CA91DE3B5; Thu, 24 Apr 2025 06:20:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745475657; cv=pass; b=lzNdx4Vd3xN/uqzXcdmWfQ5o8wpV/xcJZUhX9Rky1y0ROqniHQLyDOA+pZ4WjXGxcrmkOPAKvOR/XsZVznKxmEzz2YZ0aLxT3zjnJucmPtbUtcuGdBcYunLoxwniCIkfydmmKg2nHt3c8ri/gVvReAI4WK7Z4e1GYcsue9dEKGE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745475657; c=relaxed/simple; bh=//Yyo8IfmPE6LsmKMvdBpJlfkzrhUWHmpZ4E1fP/vUk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=P0Ns4cxN4vrFjbv+GLEnxCKT0sNtB0PcumuyGCm3By+u61kL2lgx+HxfrcUsdp1RbY7jqFJyUMLCeoA65rOwI8rOKXE/kPrebNYC1jDpkn5sIiWsyDXFqYUxDucDnPBD8nfJtkmBGEzoW4EeNl3E9+v6vAiUca6zoZ5y1wG2IlM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me; spf=pass smtp.mailfrom=icenowy.me; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b=hBO8klqu; arc=pass smtp.client-ip=136.143.188.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=icenowy.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b="hBO8klqu" ARC-Seal: i=1; a=rsa-sha256; t=1745475638; cv=none; d=zohomail.com; s=zohoarc; b=g4ZXJoPrb+24H0QzTpCpAXUjnh4cpDujKSrt+Vs8YSGt0cEwjqvcX8GP9qbW0fpuGqCr/f2tWKNlKyc1cfuhChuqWLmfKST7L8CtAm4LHobvigSLYDVCilhyUDSU0LGwRri/RBgG3gOTb4cpoEChHNksL4avR/pW5mc/DHWDro8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745475638; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=yCYzlAh9kSuErrhhEc/Udz9PQzNnvyNC+qUoV6xkhr0=; b=bFee/xfV9I3KZMtiVH+bjfRxCIsF5QbpMbmYLF+n0Xtcnwq5VaWjFdPbawdjkbCd4KDEHszr9B8QIzPIv3ouo1x9xXZvvIPDKw4jyiX7O5eG9HDdd8n0JNKVrlqh9O3oQu5YYSKB7CekLrJQwnrL//bX5ZqBOjhtHJBU4HEYBtg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1745475638; s=zmail2; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=yCYzlAh9kSuErrhhEc/Udz9PQzNnvyNC+qUoV6xkhr0=; b=hBO8klqu5eB5mxFUDI4u7WQ+8WEAO6x2lYfSG4Z8r9WG5or25HrG32lYBueq9pO4 3QzRhLBy3SM7RajujKttrCU7Vpa34ivPFT5w1mhQmdcO14ZpAEf1bu1PPIhp5GMNXKC HAJ18ab5Ww+5/WRtTj1emC20fnZiJYX1u6oNdhqVe1/8XXvIKbpOOt24pNByi8TD0i0 0R2dYg+RVDlx26XG48/dVQAD0IBXx0nuvY2Rg4WdKNkwAm+8a2Tm/ie9GpWh+ZnFMKL JwNj4Y0bop0lWt7vSWvYghb6/QFDFEMJl8kSg28OZNIls01+1Qutd+6LcvuzDIQDgCV /AotWYzZPA== Received: by mx.zohomail.com with SMTPS id 1745475636355491.3825414260032; Wed, 23 Apr 2025 23:20:36 -0700 (PDT) From: Icenowy Zheng To: Emil Renner Berthing , Jianlong Huang , Hal Feng , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng Subject: [PATCH v2 1/3] dt-bindings: pinctrl: starfive,jh7110: add PAD_INTERNAL_* virtual pins Date: Thu, 24 Apr 2025 14:20:15 +0800 Message-ID: <20250424062017.652969-2-uwu@icenowy.me> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250424062017.652969-1-uwu@icenowy.me> References: <20250424062017.652969-1-uwu@icenowy.me> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External The JH7110 SoC could support internal GPI signals to be routed to not external GPIO but internal low/high levels. Add two macros, PAD_INTERNAL_LOW and PAD_INTERNAL_HIGH, as two virtual "pads" to represent internal GPI sources with fixed low/high levels. Signed-off-by: Icenowy Zheng --- include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h b/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h index 3865f01396395..3cca874b2bef7 100644 --- a/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h +++ b/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h @@ -126,6 +126,10 @@ #define PAD_GMAC0_TXEN 18 #define PAD_GMAC0_TXC 19 +/* virtual pins for forcing GPI */ +#define PAD_INTERNAL_LOW 254 +#define PAD_INTERNAL_HIGH 255 + #define GPOUT_LOW 0 #define GPOUT_HIGH 1 From patchwork Thu Apr 24 06:20:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 884094 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13D8E1EB5D4; Thu, 24 Apr 2025 06:20:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745475661; cv=pass; b=flNMUw8sT6TuZMbqvkaR1gfio7DUUiwnUoyeDxvjpQH12Qjynlv5DXhhOnza97KqR2aiR0PkbNlngTl6lY9lF4OyaRboG3In/U2GUvOzRJJibQ1xiXEEMl2z4vXUdugpDzQKc8NO5sng5abC/ILEgItf07ZGiSJYoWIwmAKmJ58= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745475661; c=relaxed/simple; bh=vN7xR5GWyDc/8bfvleAm7zAUmZRyy+KJnQ6jPDHmxaw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZMky2CtVAqPVI/raKIdUkHONEmdZRyv1GSFVjeU2wKCyMmW88606slRxfUCZCcPe59QhMZk/jBzxsDXVt3mL+0nDw/AhjwPiMjMXHxFkNyzeaKPV5rpC4HrxtjR8sfzhbBCKdf6c6liiySCQiwcJjdNWkC8jY/mx4qzQgmB/mnc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me; spf=pass smtp.mailfrom=icenowy.me; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b=QXmvSEi3; arc=pass smtp.client-ip=136.143.188.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=icenowy.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b="QXmvSEi3" ARC-Seal: i=1; a=rsa-sha256; t=1745475644; cv=none; d=zohomail.com; s=zohoarc; b=oGwvTcG9MIW+fBY4Cgq7o37G3QIjlBY+wGR7kJDQftPVNQcdg2P23TeQq4my8AwwD7Pp+6IUvyFlsGZ9pZndu8XUMngi/9Cyvo7x1SfKLrHRAAqroZSDyzKmf1VmpYEye0JUZjxtfgqGyEYV6UPOjlnHLi7+uep3QwmXuFz94g4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745475644; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=4b8Iw4s/SYPaEv7/xDENn5gEin7xJfAzu3E1qui9INM=; b=F2rI7QNb7MtuLGaWXErPv6Z5Pp1bRF0J6NavZcagjKlEY821XfpSUW5jxRFuDDlZkrF04OcetpccVuUpgOgsJCEmFwj903eKya3UuS4At9JtyL21bUduc2weFwWq+GZDWQHtipy6JKw+8UZ7ZrJD/7LZ+utE5UZDwxm0bBPbPU0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1745475644; s=zmail2; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=4b8Iw4s/SYPaEv7/xDENn5gEin7xJfAzu3E1qui9INM=; b=QXmvSEi3S9d3purgYeNXHYF1ciARDcIhdB6aBBukpYQBzeWNeSoFMy99Sv7vB8di 0JsIunfO7rTQ3LIMZK+BOKqIImPMSsJl8Beud/8J9rtrn2MDQl9pUiTIKdj0na+Wg/P IsPcbOsZo6sJm1Gn3JjKdlmdLDJ/7dSUcTV0+WzQ1wVH5TKsgcVXBs7yzkusUXECCKs uuZLvoysybsB0exVCpdcgZJB2MD1dgaNPnEmQkbjkli3VDtLllRtd7DW3+dvT6TGAoR x2Xztbl+IFhY3kZYpPWCGIM0TSI82f/u099p45nKsTUg8Ez6jgGUjmo8BLbNXSQFfgq d+MWSiqDXQ== Received: by mx.zohomail.com with SMTPS id 1745475641388238.64234871132396; Wed, 23 Apr 2025 23:20:41 -0700 (PDT) From: Icenowy Zheng To: Emil Renner Berthing , Jianlong Huang , Hal Feng , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng Subject: [PATCH v2 2/3] pinctrl: starfive: jh7110: add support for PAD_INTERNAL_* for GPI Date: Thu, 24 Apr 2025 14:20:16 +0800 Message-ID: <20250424062017.652969-3-uwu@icenowy.me> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250424062017.652969-1-uwu@icenowy.me> References: <20250424062017.652969-1-uwu@icenowy.me> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External The JH7110 SoC's both pin controller support routing GPI signals to internal fixed low/high level. As we allocated two special "pin" numbers for these situations (PAD_INTERNAL_{LOW,HIGH}), add special handling code for these "pins". The DOEn/DOUT/FUNCTION fields are ignored and the internal input signal specified by the DIN field is routed to fixed low/high level. Signed-off-by: Icenowy Zheng --- .../starfive/pinctrl-starfive-jh7110.c | 41 +++++++++++++++---- 1 file changed, 34 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c index 1d0d6c224c104..fb18c7974ec86 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c @@ -291,6 +291,24 @@ void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin, } EXPORT_SYMBOL_GPL(jh7110_set_gpiomux); +static void jh7110_set_gpi(struct jh7110_pinctrl *sfp, u32 gpi, u32 val) +{ + u32 offset, shift; + u32 reg_val; + const struct jh7110_pinctrl_soc_info *info = sfp->info; + + offset = 4 * (gpi / 4); + shift = 8 * (gpi % 4); + + reg_val = readl_relaxed(sfp->base + + info->gpi_reg_base + offset); + reg_val &= info->gpi_mask << shift; + reg_val |= (val & info->gpi_mask) << shift; + + writel_relaxed(reg_val, sfp->base + + info->gpi_reg_base + offset); +} + static int jh7110_set_mux(struct pinctrl_dev *pctldev, unsigned int fsel, unsigned int gsel) { @@ -307,14 +325,23 @@ static int jh7110_set_mux(struct pinctrl_dev *pctldev, pinmux = group->data; for (i = 0; i < group->grp.npins; i++) { u32 v = pinmux[i]; + u32 pin = jh7110_pinmux_pin(v); - if (info->jh7110_set_one_pin_mux) - info->jh7110_set_one_pin_mux(sfp, - jh7110_pinmux_pin(v), - jh7110_pinmux_din(v), - jh7110_pinmux_dout(v), - jh7110_pinmux_doen(v), - jh7110_pinmux_function(v)); + switch (pin) { + case PAD_INTERNAL_LOW: + case PAD_INTERNAL_HIGH: + jh7110_set_gpi(sfp, jh7110_pinmux_din(v), + pin == PAD_INTERNAL_HIGH); + break; + default: + if (info->jh7110_set_one_pin_mux) + info->jh7110_set_one_pin_mux(sfp, + jh7110_pinmux_pin(v), + jh7110_pinmux_din(v), + jh7110_pinmux_dout(v), + jh7110_pinmux_doen(v), + jh7110_pinmux_function(v)); + } } return 0; From patchwork Thu Apr 24 06:21:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 885121 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58409207DFE; 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mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1745475729; s=zmail2; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=xVNOvXEvdW6leQE28c3jHe0aUAqH+GUjgXBsNd/0dtY=; b=aTmw7cA0A0R7yGwvidNysZ7lVbcK8j3iS0tYCpm6FjiTxXMnaR9ptnsGRb1kzUMC V3JtyIIZ1XuzwEuN7Gz0sHdJYzzGQb5T65nideQk+BM00P1mp292UrO9bVXvF9cwB5y Ihuc7dxMXSGibLBQJZpmBEV/2bXLS487kXHyYbj9P03roC7UYmkuxzU8Ji3dJsz9MCl uRogeAoqAEEvn6mBfxWIJTIgH3wm3VpcZakcs6QmT6gvhqVAlgalOYQy+EVWwCTELyI HhCyx1COuaqz6odjBcY9ScWA0CZEMssyVF1ylHqaI/Jf5TYtrqwKSgezprny/F0I7Qh bdIfjBFarA== Received: by mx.zohomail.com with SMTPS id 1745475727228758.2441586398901; Wed, 23 Apr 2025 23:22:07 -0700 (PDT) From: Icenowy Zheng To: Emil Renner Berthing , Jianlong Huang , Hal Feng , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng Subject: [PATCH v2 3/3] riscv: dts: starfive: jh7110-pine64-star64: force no USB overcurrent Date: Thu, 24 Apr 2025 14:21:54 +0800 Message-ID: <20250424062154.655128-1-uwu@icenowy.me> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250424062017.652969-1-uwu@icenowy.me> References: <20250424062017.652969-1-uwu@icenowy.me> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External The Star64 board has no GPIOs to indicate USB overcurrent, however the USB controller would stop to work if the overcurrent_n signal it gets is low (which means overcurrent situations happening because of the _n). Use the pin controller to force the overcurrent_n signal to be high in order to ensure stable behavior of the USB controller. Signed-off-by: Icenowy Zheng --- This patch depends on [1] for including the necessary header file. [1] https://lore.kernel.org/linux-riscv/20250424060605.638678-1-uwu@icenowy.me/T/#u arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts index 31e825be2065a..4fb522d127e21 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts @@ -91,6 +91,13 @@ GPOEN_ENABLE, input-schmitt-disable; slew-rate = <0>; }; + + overcurrent-pins { + pinmux = ; + }; }; };