From patchwork Fri Apr 25 08:53:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrie Wu X-Patchwork-Id: 884689 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C03C24B34; Fri, 25 Apr 2025 08:53:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745571223; cv=none; b=rXbX2V3Mpt4FXkqFc2FGCtnlonFdu4CNyMTgI0BQa3j7xGgng+3kQTBO8/nhBTPrP+ENUv4PjC9ro36UUZ/OBRo1M8fQvScrWbKByg42KXl4/CCekLX5XzoHxdwtgkPcf/mO3xG8mmOgJ7Rey0/g58PL0/GCQoftEgAVXlTm9FU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745571223; c=relaxed/simple; bh=PQCeAd7pZM4vVuI0Mcbmjv8uHncBoyYxVa1Kaamv474=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ISgqqLSwsH7wZI6izrUNJZ7lvY03Iu/GheewjPf98NLUsk1gD+urNb8LGtLXAP/DSPUUh7vfb32p0u7xsnuK93Ni/1WvtjVuPnlsAMHPxQh+bCApNekw112HlKEoEPyX9Euh1GWozPWfYuzNYUIVWP4Yl3y7LJz1EDdCBLGrCQk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=hYqJ4ZcH; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="hYqJ4ZcH" X-UUID: c537acc221b211f09b6713c7f6bde12e-20250425 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=GuK68BmzHZP33GSN5Zs/I6BAYEMPbqZMTM2A0yTHWuk=; b=hYqJ4ZcH5LE2k5sQI/lQBM/KZRQo9LpzfzqHLxku4rCIqDr+JaWZIaPDRCxsBuMlKdlNhrFZAxeCahHYfFj28rtfTySTWl5XlAoulzxyo8LdfXublFJyzlaqqWm09l5ONo8SueswVBHa2nv5E4qNIfkpWHIth0zNW6MR5PcaFJM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1, REQID:4dde0a50-d657-4bf6-82c7-6f53e0356fe6, IP:0, UR L:0,TC:0,Content:0,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-30 X-CID-META: VersionHash:0ef645f, CLOUDID:6c290a07-829c-41bc-b3dd-83387f72f90e, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:2, IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV: 0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 5,DFT X-CID-BAS: 5,DFT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c537acc221b211f09b6713c7f6bde12e-20250425 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1227368384; Fri, 25 Apr 2025 16:53:34 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 25 Apr 2025 16:53:33 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 25 Apr 2025 16:53:32 +0800 From: Kyrie Wu To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , kyrie wu , , , , , CC: Kyrie Wu Subject: [PATCH v3 01/12] dt-bindings: media: mediatek,jpeg: Add mediatek, mt8196-jpgdec compatible Date: Fri, 25 Apr 2025 16:53:17 +0800 Message-ID: <20250425085328.16929-2-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250425085328.16929-1-kyrie.wu@mediatek.com> References: <20250425085328.16929-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Compared to the previous generation IC, the MT8196 uses SMMU instead of IOMMU and supports features such as dynamic voltage and frequency scaling. Therefore, add "mediatek,mt8196-jpgdec" compatible to the binding document. Signed-off-by: Kyrie Wu --- .../bindings/media/mediatek,mt8195-jpegdec.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml index e5448c60e3eb..28a9a9bfdbf8 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml @@ -14,7 +14,9 @@ description: properties: compatible: - const: mediatek,mt8195-jpgdec + enum: + - mediatek,mt8195-jpgdec + - mediatek,mt8196-jpgdec power-domains: maxItems: 1 @@ -44,7 +46,9 @@ patternProperties: properties: compatible: - const: mediatek,mt8195-jpgdec-hw + enum: + - mediatek,mt8195-jpgdec-hw + - mediatek,mt8196-jpgdec-hw reg: maxItems: 1 From patchwork Fri Apr 25 08:53:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrie Wu X-Patchwork-Id: 884688 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 268B61EB5F1; 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Fri, 25 Apr 2025 16:53:35 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 25 Apr 2025 16:53:34 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 25 Apr 2025 16:53:33 +0800 From: Kyrie Wu To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , kyrie wu , , , , , CC: Kyrie Wu Subject: [PATCH v3 02/12] dt-bindings: media: mediatek,jpeg: Add mediatek, mt8196-jpgenc compatible Date: Fri, 25 Apr 2025 16:53:18 +0800 Message-ID: <20250425085328.16929-3-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250425085328.16929-1-kyrie.wu@mediatek.com> References: <20250425085328.16929-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Compared to the previous generation IC, the MT8196 uses SMMU instead of IOMMU and supports features such as dynamic voltage and frequency scaling. Therefore, add "mediatek,mt8196-jpgenc" compatible to the binding document. Signed-off-by: Kyrie Wu --- .../bindings/media/mediatek,mt8195-jpegenc.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml index 596186497b68..e2d772ea0fb0 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml @@ -14,7 +14,9 @@ description: properties: compatible: - const: mediatek,mt8195-jpgenc + enum: + - mediatek,mt8195-jpgenc + - mediatek,mt8196-jpgenc power-domains: maxItems: 1 @@ -44,7 +46,9 @@ patternProperties: properties: compatible: - const: mediatek,mt8195-jpgenc-hw + enum: + - mediatek,mt8195-jpgenc-hw + - mediatek,mt8196-jpgenc-hw reg: maxItems: 1 From patchwork Fri Apr 25 08:53:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrie Wu X-Patchwork-Id: 884686 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 401B2207DFF; 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Fri, 25 Apr 2025 16:53:37 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 25 Apr 2025 16:53:35 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 25 Apr 2025 16:53:35 +0800 From: Kyrie Wu To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , kyrie wu , , , , , CC: Kyrie Wu Subject: [PATCH v3 04/12] media: mediatek: jpeg: add jpeg smmu sid setting Date: Fri, 25 Apr 2025 16:53:20 +0800 Message-ID: <20250425085328.16929-5-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250425085328.16929-1-kyrie.wu@mediatek.com> References: <20250425085328.16929-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Add a configuration to set jpeg dec & enc smmu sid Change-Id: Id753ce17138c363bcb597e7023d79e3c39b240da Signed-off-by: Kyrie Wu --- .../platform/mediatek/jpeg/mtk_jpeg_core.c | 37 +++++++++++++++++++ .../platform/mediatek/jpeg/mtk_jpeg_core.h | 15 ++++++++ .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 23 ++++++++++++ .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 23 ++++++++++++ 4 files changed, 98 insertions(+) diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c index e89ccb8c904c..ea890f01fa9e 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -1584,6 +1585,20 @@ static irqreturn_t mtk_jpeg_enc_done(struct mtk_jpeg_dev *jpeg) return IRQ_HANDLED; } +static void mtk_jpeg_enc_set_smmu_sid(struct mtk_jpegenc_comp_dev *jpeg) +{ + struct mtk_jpeg_dev *mjpeg = jpeg->master_dev; + + if (!mjpeg->variant->support_smmu || !jpeg->smmu_regmap) + return; + + regmap_update_bits(jpeg->smmu_regmap, JPEG_ENC_SMMU_SID, + JPG_REG_GUSER_ID_MASK << + JPG_REG_ENC_GUSER_ID_SHIFT, + JPG_REG_GUSER_ID_ENC_SID << + JPG_REG_ENC_GUSER_ID_SHIFT); +} + static void mtk_jpegenc_worker(struct work_struct *work) { struct mtk_jpegenc_comp_dev *comp_jpeg[MTK_JPEGENC_HW_MAX]; @@ -1655,6 +1670,9 @@ static void mtk_jpegenc_worker(struct work_struct *work) jpeg_dst_buf->frame_num = ctx->total_frame_num; ctx->total_frame_num++; mtk_jpeg_enc_reset(comp_jpeg[hw_id]->reg_base); + + mtk_jpeg_enc_set_smmu_sid(comp_jpeg[hw_id]); + mtk_jpeg_set_enc_dst(ctx, comp_jpeg[hw_id]->reg_base, &dst_buf->vb2_buf); @@ -1679,6 +1697,20 @@ static void mtk_jpegenc_worker(struct work_struct *work) v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); } +static void mtk_jpeg_dec_set_smmu_sid(struct mtk_jpegdec_comp_dev *jpeg) +{ + struct mtk_jpeg_dev *mjpeg = jpeg->master_dev; + + if (!mjpeg->variant->support_smmu || !jpeg->smmu_regmap) + return; + + regmap_update_bits(jpeg->smmu_regmap, JPEG_DEC_SMMU_SID, + JPG_REG_GUSER_ID_MASK << + JPG_REG_DEC_GUSER_ID_SHIFT, + JPG_REG_GUSER_ID_DEC_SID << + JPG_REG_DEC_GUSER_ID_SHIFT); +} + static void mtk_jpegdec_worker(struct work_struct *work) { struct mtk_jpeg_ctx *ctx = container_of(work, struct mtk_jpeg_ctx, @@ -1771,6 +1803,9 @@ static void mtk_jpegdec_worker(struct work_struct *work) spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags); ctx->total_frame_num++; mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base); + + mtk_jpeg_dec_set_smmu_sid(comp_jpeg[hw_id]); + mtk_jpeg_dec_set_config(comp_jpeg[hw_id]->reg_base, jpeg->variant->support_34bit, &jpeg_src_buf->dec_param, @@ -1929,6 +1964,7 @@ static struct mtk_jpeg_variant mtk8196_jpegenc_drvdata = { .cap_q_default_fourcc = V4L2_PIX_FMT_JPEG, .multi_core = true, .jpeg_worker = mtk_jpegenc_worker, + .support_smmu = true, }; static const struct mtk_jpeg_variant mtk8195_jpegdec_drvdata = { @@ -1955,6 +1991,7 @@ static const struct mtk_jpeg_variant mtk8196_jpegdec_drvdata = { .cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M, .multi_core = true, .jpeg_worker = mtk_jpegdec_worker, + .support_smmu = true, }; static const struct of_device_id mtk_jpeg_match[] = { diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h index 02ed0ed5b736..46899512a5e6 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -34,6 +35,14 @@ #define MTK_JPEG_MAX_EXIF_SIZE (64 * 1024) +#define JPEG_DEC_SMMU_SID 0 +#define JPEG_ENC_SMMU_SID 0 +#define JPG_REG_GUSER_ID_MASK 0x7 +#define JPG_REG_GUSER_ID_DEC_SID 0x4 +#define JPG_REG_GUSER_ID_ENC_SID 0x5 +#define JPG_REG_DEC_GUSER_ID_SHIFT 8 +#define JPG_REG_ENC_GUSER_ID_SHIFT 4 + #define MTK_JPEG_ADDR_MASK GENMASK(1, 0) /** @@ -65,6 +74,7 @@ enum mtk_jpeg_ctx_state { * @multi_core: mark jpeg hw is multi_core or not * @jpeg_worker: jpeg dec or enc worker * @support_34bit: flag to check support for 34-bit DMA address + * @support_smmu: flag to check if support smmu */ struct mtk_jpeg_variant { struct clk_bulk_data *clks; @@ -82,6 +92,7 @@ struct mtk_jpeg_variant { bool multi_core; void (*jpeg_worker)(struct work_struct *work); bool support_34bit; + bool support_smmu; }; struct mtk_jpeg_src_buf { @@ -150,6 +161,7 @@ struct mtk_jpegdec_clk { * @hw_param: jpeg encode hw parameters * @hw_state: record hw state * @hw_lock: spinlock protecting the hw device resource + * @smmu_regmap: SMMU registers mapping */ struct mtk_jpegenc_comp_dev { struct device *dev; @@ -163,6 +175,7 @@ struct mtk_jpegenc_comp_dev { enum mtk_jpeg_hw_state hw_state; /* spinlock protecting the hw device resource */ spinlock_t hw_lock; + struct regmap *smmu_regmap; }; /** @@ -177,6 +190,7 @@ struct mtk_jpegenc_comp_dev { * @hw_param: jpeg decode hw parameters * @hw_state: record hw state * @hw_lock: spinlock protecting hw + * @smmu_regmap: SMMU registers mapping */ struct mtk_jpegdec_comp_dev { struct device *dev; @@ -190,6 +204,7 @@ struct mtk_jpegdec_comp_dev { enum mtk_jpeg_hw_state hw_state; /* spinlock protecting the hw device resource */ spinlock_t hw_lock; + struct regmap *smmu_regmap; }; /** diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c index 20553bf541df..059377805706 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c @@ -616,6 +616,25 @@ static int mtk_jpegdec_hw_init_irq(struct mtk_jpegdec_comp_dev *dev) return 0; } +static int mtk_jpegdec_smmu_init(struct mtk_jpegdec_comp_dev *dev) +{ + struct mtk_jpeg_dev *master_dev = dev->master_dev; + + if (!master_dev->variant->support_smmu) + return 0; + + dev->smmu_regmap = + syscon_regmap_lookup_by_phandle(dev->plat_dev->dev.of_node, + "mediatek,smmu-config"); + if (IS_ERR(dev->smmu_regmap)) { + return dev_err_probe(dev->dev, dev->smmu_regmap, + "mmap smmu_base failed(%ld)\n", + PTR_ERR(dev->smmu_regmap)); + } + + return 0; +} + static int mtk_jpegdec_hw_probe(struct platform_device *pdev) { struct mtk_jpegdec_clk *jpegdec_clk; @@ -668,6 +687,10 @@ static int mtk_jpegdec_hw_probe(struct platform_device *pdev) master_dev->reg_decbase[i] = dev->reg_base; dev->master_dev = master_dev; + ret = mtk_jpegdec_smmu_init(dev); + if (ret) + return ret; + platform_set_drvdata(pdev, dev); pm_runtime_enable(&pdev->dev); diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c index 69c95113f205..73c55e1546aa 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c @@ -340,6 +340,25 @@ static int mtk_jpegenc_hw_init_irq(struct mtk_jpegenc_comp_dev *dev) return 0; } +static int mtk_jpegenc_smmu_init(struct mtk_jpegenc_comp_dev *dev) +{ + struct mtk_jpeg_dev *master_dev = dev->master_dev; + + if (!master_dev->variant->support_smmu) + return 0; + + dev->smmu_regmap = + syscon_regmap_lookup_by_phandle(dev->plat_dev->dev.of_node, + "mediatek,smmu-config"); + if (IS_ERR(dev->smmu_regmap)) { + return dev_err_probe(dev->dev, dev->smmu_regmap, + "mmap smmu_base failed(%ld)\n", + PTR_ERR(dev->smmu_regmap)); + } + + return 0; +} + static int mtk_jpegenc_hw_probe(struct platform_device *pdev) { struct mtk_jpegenc_clk *jpegenc_clk; @@ -390,6 +409,10 @@ static int mtk_jpegenc_hw_probe(struct platform_device *pdev) master_dev->reg_encbase[i] = dev->reg_base; dev->master_dev = master_dev; + ret = mtk_jpegenc_smmu_init(dev); + if (ret) + return ret; + platform_set_drvdata(pdev, dev); pm_runtime_enable(&pdev->dev); From patchwork Fri Apr 25 08:53:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrie Wu X-Patchwork-Id: 884687 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 127A3230278; Fri, 25 Apr 2025 08:53:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Fri, 25 Apr 2025 16:53:38 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 25 Apr 2025 16:53:37 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 25 Apr 2025 16:53:36 +0800 From: Kyrie Wu To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , kyrie wu , , , , , CC: Kyrie Wu Subject: [PATCH v3 06/12] media: mediatek: jpeg: refactor jpeg buffer payload setting Date: Fri, 25 Apr 2025 16:53:22 +0800 Message-ID: <20250425085328.16929-7-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250425085328.16929-1-kyrie.wu@mediatek.com> References: <20250425085328.16929-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N 1. for multi-core jpegdec: core0: |<-------- decoding buffer0 and resolution changed to smaller core1: |<-------- decoding buffer1 core0: |<- handling resolution changing core0: |<- vb2_set_plane_payload 2. the payload size is changed on the step of set format. Because core1 is running and streaming has not been stopped, the format cannot be set again, resulting in no change in the payload size. 3. at this time, the payload size is bigger than buffer length, it will print a warnning call trace 4. set payload size must less than buffer length Signed-off-by: Kyrie Wu --- .../platform/mediatek/jpeg/mtk_jpeg_core.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c index 0074d1edb534..52d59bb5c9ad 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -720,10 +720,22 @@ static int mtk_jpeg_buf_prepare(struct vb2_buffer *vb) plane_fmt = q_data->pix_mp.plane_fmt[i]; if (ctx->enable_exif && q_data->fmt->fourcc == V4L2_PIX_FMT_JPEG) - vb2_set_plane_payload(vb, i, plane_fmt.sizeimage + - MTK_JPEG_MAX_EXIF_SIZE); + if (vb->planes[i].length > (plane_fmt.sizeimage + + MTK_JPEG_MAX_EXIF_SIZE)) + vb2_set_plane_payload(vb, i, + plane_fmt.sizeimage + + MTK_JPEG_MAX_EXIF_SIZE); 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Fri, 25 Apr 2025 16:53:40 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 25 Apr 2025 16:53:39 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 25 Apr 2025 16:53:38 +0800 From: Kyrie Wu To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , kyrie wu , , , , , CC: Kyrie Wu Subject: [PATCH v3 08/12] media: mediatek: jpeg: fix stop streaming flow for multi-core Date: Fri, 25 Apr 2025 16:53:24 +0800 Message-ID: <20250425085328.16929-9-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250425085328.16929-1-kyrie.wu@mediatek.com> References: <20250425085328.16929-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N 1. For multi-core jpegdec, the all hws may run at the same time, if one hw decoded firstly, the function of mtk_jpeg_dec_stop_streaming would be called, but others input buffers are decoding, this will cause some running buffers to be buffer done, causing errors; 2. add a parameter to calculate the decoding buffer counts, it wil decrease to 0 until the all buffers decoded and the mtk_jpeg_dec_stop_streaming could continue to be executed. Signed-off-by: Kyrie Wu --- .../media/platform/mediatek/jpeg/mtk_jpeg_core.c | 16 ++++++++++++++++ .../media/platform/mediatek/jpeg/mtk_jpeg_core.h | 2 ++ .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 9 +++++++++ .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 9 +++++++++ 4 files changed, 36 insertions(+) diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c index 7e3509be6f69..1d3df1230191 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -861,8 +861,12 @@ static struct vb2_v4l2_buffer *mtk_jpeg_buf_remove(struct mtk_jpeg_ctx *ctx, static void mtk_jpeg_enc_stop_streaming(struct vb2_queue *q) { struct mtk_jpeg_ctx *ctx = vb2_get_drv_priv(q); + struct mtk_jpeg_dev *jpeg = ctx->jpeg; struct vb2_v4l2_buffer *vb; + if (jpeg->variant->multi_core) + wait_event(jpeg->hw_wq, (atomic_read(&ctx->buf_list_cnt) == 0)); + while ((vb = mtk_jpeg_buf_remove(ctx, q->type))) v4l2_m2m_buf_done(vb, VB2_BUF_STATE_ERROR); } @@ -870,6 +874,7 @@ static void mtk_jpeg_enc_stop_streaming(struct vb2_queue *q) static void mtk_jpeg_dec_stop_streaming(struct vb2_queue *q) { struct mtk_jpeg_ctx *ctx = vb2_get_drv_priv(q); + struct mtk_jpeg_dev *jpeg = ctx->jpeg; struct vb2_v4l2_buffer *vb; /* @@ -877,6 +882,9 @@ static void mtk_jpeg_dec_stop_streaming(struct vb2_queue *q) * Before STREAMOFF, we still have to return the old resolution and * subsampling. Update capture queue when the stream is off. */ + if (jpeg->variant->multi_core) + wait_event(jpeg->hw_wq, (atomic_read(&ctx->buf_list_cnt) == 0)); + if (ctx->state == MTK_JPEG_SOURCE_CHANGE && V4L2_TYPE_IS_CAPTURE(q->type)) { struct mtk_jpeg_src_buf *src_buf; @@ -1186,6 +1194,7 @@ static int mtk_jpeg_open(struct file *file) v4l2_fh_init(&ctx->fh, vfd); file->private_data = &ctx->fh; v4l2_fh_add(&ctx->fh); + atomic_set(&ctx->buf_list_cnt, 0); ctx->jpeg = jpeg; ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(jpeg->m2m_dev, ctx, @@ -1568,6 +1577,11 @@ static int mtk_jpegdec_set_hw_param(struct mtk_jpeg_ctx *ctx, return 0; } +static void jpeg_buf_queue_inc(struct mtk_jpeg_ctx *ctx) +{ + atomic_inc(&ctx->buf_list_cnt); +} + static irqreturn_t mtk_jpeg_enc_done(struct mtk_jpeg_dev *jpeg) { struct mtk_jpeg_ctx *ctx; @@ -1693,6 +1707,7 @@ static void mtk_jpegenc_worker(struct work_struct *work) &src_buf->vb2_buf); mtk_jpeg_set_enc_params(ctx, comp_jpeg[hw_id]->reg_base); mtk_jpeg_enc_start(comp_jpeg[hw_id]->reg_base); + jpeg_buf_queue_inc(ctx); v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags); @@ -1825,6 +1840,7 @@ static void mtk_jpegdec_worker(struct work_struct *work) &bs, &fb); mtk_jpeg_dec_start(comp_jpeg[hw_id]->reg_base); + jpeg_buf_queue_inc(ctx); v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags); diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h index 186cd1862028..6e8304680393 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h @@ -303,6 +303,7 @@ struct mtk_jpeg_q_data { * @dst_done_queue: encoded frame buffer queue * @done_queue_lock: encoded frame operation spinlock * @last_done_frame_num: the last encoded frame number + * @buf_list_cnt: the frame buffer count own by jpeg driver */ struct mtk_jpeg_ctx { struct mtk_jpeg_dev *jpeg; @@ -321,6 +322,7 @@ struct mtk_jpeg_ctx { /* spinlock protecting the encode done buffer */ spinlock_t done_queue_lock; u32 last_done_frame_num; + atomic_t buf_list_cnt; }; #endif /* _MTK_JPEG_CORE_H */ diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c index e913f0f899b8..c1e10af2086b 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c @@ -522,6 +522,11 @@ static void mtk_jpegdec_put_buf(struct mtk_jpegdec_comp_dev *jpeg) spin_unlock_irqrestore(&ctx->done_queue_lock, flags); } +static void jpeg_buf_queue_dec(struct mtk_jpeg_ctx *ctx) +{ + atomic_dec(&ctx->buf_list_cnt); +} + static void mtk_jpegdec_timeout_work(struct work_struct *work) { enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR; @@ -530,9 +535,11 @@ static void mtk_jpegdec_timeout_work(struct work_struct *work) job_timeout_work.work); struct mtk_jpeg_dev *master_jpeg = cjpeg->master_dev; struct vb2_v4l2_buffer *src_buf, *dst_buf; + struct mtk_jpeg_ctx *ctx; src_buf = cjpeg->hw_param.src_buffer; dst_buf = cjpeg->hw_param.dst_buffer; + ctx = cjpeg->hw_param.curr_ctx; v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true); mtk_jpeg_dec_reset(cjpeg->reg_base); @@ -543,6 +550,7 @@ static void mtk_jpegdec_timeout_work(struct work_struct *work) wake_up(&master_jpeg->hw_wq); v4l2_m2m_buf_done(src_buf, buf_state); mtk_jpegdec_put_buf(cjpeg); + jpeg_buf_queue_dec(ctx); } static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv) @@ -583,6 +591,7 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv) buf_state = VB2_BUF_STATE_DONE; v4l2_m2m_buf_done(src_buf, buf_state); mtk_jpegdec_put_buf(jpeg); + jpeg_buf_queue_dec(ctx); pm_runtime_put(ctx->jpeg->dev); clk_disable_unprepare(jpeg->jdec_clk.clks->clk); diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c index b92f677359c9..2d7e72a424c5 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c @@ -251,6 +251,11 @@ static void mtk_jpegenc_put_buf(struct mtk_jpegenc_comp_dev *jpeg) spin_unlock_irqrestore(&ctx->done_queue_lock, flags); } +static void jpeg_buf_queue_dec(struct mtk_jpeg_ctx *ctx) +{ + atomic_dec(&ctx->buf_list_cnt); +} + static void mtk_jpegenc_timeout_work(struct work_struct *work) { struct delayed_work *dly_work = to_delayed_work(work); @@ -261,9 +266,11 @@ static void mtk_jpegenc_timeout_work(struct work_struct *work) struct mtk_jpeg_dev *master_jpeg = cjpeg->master_dev; enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR; struct vb2_v4l2_buffer *src_buf, *dst_buf; + struct mtk_jpeg_ctx *ctx; src_buf = cjpeg->hw_param.src_buffer; dst_buf = cjpeg->hw_param.dst_buffer; + ctx = cjpeg->hw_param.curr_ctx; v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true); mtk_jpeg_enc_reset(cjpeg->reg_base); @@ -274,6 +281,7 @@ static void mtk_jpegenc_timeout_work(struct work_struct *work) wake_up(&master_jpeg->hw_wq); v4l2_m2m_buf_done(src_buf, buf_state); mtk_jpegenc_put_buf(cjpeg); + jpeg_buf_queue_dec(ctx); } static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv) @@ -307,6 +315,7 @@ static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv) buf_state = VB2_BUF_STATE_DONE; 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Fri, 25 Apr 2025 16:53:41 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 25 Apr 2025 16:53:40 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 25 Apr 2025 16:53:39 +0800 From: Kyrie Wu To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , kyrie wu , , , , , CC: Kyrie Wu Subject: [PATCH v3 09/12] media: mediatek: jpeg: refactor multi-core clk suspend and resume setting Date: Fri, 25 Apr 2025 16:53:25 +0800 Message-ID: <20250425085328.16929-10-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250425085328.16929-1-kyrie.wu@mediatek.com> References: <20250425085328.16929-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N refactor jpeg clk suspend and resume setting for multi-core Signed-off-by: Kyrie Wu --- .../platform/mediatek/jpeg/mtk_jpeg_core.c | 28 +++---- .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 75 ++++++++++++++++++- .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 75 ++++++++++++++++++- 3 files changed, 151 insertions(+), 27 deletions(-) diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c index 1d3df1230191..c1d2de92f125 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -1126,6 +1126,9 @@ static void mtk_jpeg_clk_on(struct mtk_jpeg_dev *jpeg) { int ret; + if (jpeg->variant->multi_core) + return; + ret = clk_bulk_prepare_enable(jpeg->variant->num_clks, jpeg->variant->clks); if (ret) @@ -1134,6 +1137,9 @@ static void mtk_jpeg_clk_on(struct mtk_jpeg_dev *jpeg) static void mtk_jpeg_clk_off(struct mtk_jpeg_dev *jpeg) { + if (jpeg->variant->multi_core) + return; + clk_bulk_disable_unprepare(jpeg->variant->num_clks, jpeg->variant->clks); } @@ -1677,13 +1683,6 @@ static void mtk_jpegenc_worker(struct work_struct *work) goto enc_end; } - ret = clk_prepare_enable(comp_jpeg[hw_id]->venc_clk.clks->clk); - if (ret) { - dev_err(jpeg->dev, "%s : %d, jpegenc clk_prepare_enable fail\n", - __func__, __LINE__); - goto enc_end; - } - v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); @@ -1798,20 +1797,13 @@ static void mtk_jpegdec_worker(struct work_struct *work) jpeg_dst_buf->frame_num = ctx->total_frame_num; mtk_jpegdec_set_hw_param(ctx, hw_id, src_buf, dst_buf); - ret = pm_runtime_get_sync(comp_jpeg[hw_id]->dev); + ret = pm_runtime_resume_and_get(comp_jpeg[hw_id]->dev); if (ret < 0) { dev_err(jpeg->dev, "%s : %d, pm_runtime_get_sync fail !!!\n", __func__, __LINE__); goto dec_end; } - ret = clk_prepare_enable(comp_jpeg[hw_id]->jdec_clk.clks->clk); - if (ret) { - dev_err(jpeg->dev, "%s : %d, jpegdec clk_prepare_enable fail\n", - __func__, __LINE__); - goto clk_end; - } - v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); @@ -1821,7 +1813,7 @@ static void mtk_jpegdec_worker(struct work_struct *work) &dst_buf->vb2_buf, &fb)) { dev_err(jpeg->dev, "%s : %d, mtk_jpeg_set_dec_dst fail\n", __func__, __LINE__); - goto setdst_end; + goto set_dst_fail; } schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work, @@ -1846,9 +1838,7 @@ static void mtk_jpegdec_worker(struct work_struct *work) return; -setdst_end: - clk_disable_unprepare(comp_jpeg[hw_id]->jdec_clk.clks->clk); -clk_end: +set_dst_fail: pm_runtime_put(comp_jpeg[hw_id]->dev); dec_end: v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c index c1e10af2086b..5d9a247f0360 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c @@ -543,14 +543,13 @@ static void mtk_jpegdec_timeout_work(struct work_struct *work) v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true); mtk_jpeg_dec_reset(cjpeg->reg_base); - clk_disable_unprepare(cjpeg->jdec_clk.clks->clk); - pm_runtime_put(cjpeg->dev); cjpeg->hw_state = MTK_JPEG_HW_IDLE; atomic_inc(&master_jpeg->hw_rdy); wake_up(&master_jpeg->hw_wq); v4l2_m2m_buf_done(src_buf, buf_state); mtk_jpegdec_put_buf(cjpeg); jpeg_buf_queue_dec(ctx); + pm_runtime_put(cjpeg->dev); } static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv) @@ -592,12 +591,11 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv) v4l2_m2m_buf_done(src_buf, buf_state); mtk_jpegdec_put_buf(jpeg); jpeg_buf_queue_dec(ctx); - pm_runtime_put(ctx->jpeg->dev); - clk_disable_unprepare(jpeg->jdec_clk.clks->clk); jpeg->hw_state = MTK_JPEG_HW_IDLE; wake_up(&master_jpeg->hw_wq); atomic_inc(&master_jpeg->hw_rdy); + pm_runtime_put(jpeg->dev); return IRQ_HANDLED; } @@ -703,15 +701,84 @@ static int mtk_jpegdec_hw_probe(struct platform_device *pdev) platform_set_drvdata(pdev, dev); pm_runtime_enable(&pdev->dev); + ret = devm_clk_bulk_get(dev->dev, + jpegdec_clk->clk_num, + jpegdec_clk->clks); + if (ret) { + dev_err(&pdev->dev, "Failed to init clk\n"); + return ret; + } + + return 0; +} + +static void mtk_jpeg_clk_on(struct mtk_jpegdec_comp_dev *jpeg) +{ + int ret; + + ret = clk_bulk_prepare_enable(jpeg->jdec_clk.clk_num, + jpeg->jdec_clk.clks); + if (ret) + dev_err(jpeg->dev, "%s : %d, jpegdec clk_prepare_enable fail\n", + __func__, __LINE__); +} + +static void mtk_jpeg_clk_off(struct mtk_jpegdec_comp_dev *jpeg) +{ + clk_bulk_disable_unprepare(jpeg->jdec_clk.clk_num, + jpeg->jdec_clk.clks); +} + +static __maybe_unused int mtk_jpegdec_pm_suspend(struct device *dev) +{ + struct mtk_jpegdec_comp_dev *jpeg = dev_get_drvdata(dev); + + mtk_jpeg_clk_off(jpeg); return 0; } +static __maybe_unused int mtk_jpegdec_pm_resume(struct device *dev) +{ + struct mtk_jpegdec_comp_dev *jpeg = dev_get_drvdata(dev); + + mtk_jpeg_clk_on(jpeg); + + return 0; +} + +static __maybe_unused int mtk_jpegdec_suspend(struct device *dev) +{ + struct mtk_jpegdec_comp_dev *jpeg = dev_get_drvdata(dev); + + v4l2_m2m_suspend(jpeg->master_dev->m2m_dev); + return pm_runtime_force_suspend(dev); +} + +static __maybe_unused int mtk_jpegdec_resume(struct device *dev) +{ + struct mtk_jpegdec_comp_dev *jpeg = dev_get_drvdata(dev); + int ret; + + ret = pm_runtime_force_resume(dev); + if (ret < 0) + return ret; + + v4l2_m2m_resume(jpeg->master_dev->m2m_dev); + return ret; +} + +static const struct dev_pm_ops mtk_jpegdec_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(mtk_jpegdec_suspend, mtk_jpegdec_resume) + SET_RUNTIME_PM_OPS(mtk_jpegdec_pm_suspend, mtk_jpegdec_pm_resume, NULL) +}; + static struct platform_driver mtk_jpegdec_hw_driver = { .probe = mtk_jpegdec_hw_probe, .driver = { .name = "mtk-jpegdec-hw", .of_match_table = mtk_jpegdec_hw_ids, + .pm = &mtk_jpegdec_pm_ops, }, }; diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c index 2d7e72a424c5..75cd3627c5ae 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c @@ -274,14 +274,13 @@ static void mtk_jpegenc_timeout_work(struct work_struct *work) v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true); mtk_jpeg_enc_reset(cjpeg->reg_base); - clk_disable_unprepare(cjpeg->venc_clk.clks->clk); - pm_runtime_put(cjpeg->dev); cjpeg->hw_state = MTK_JPEG_HW_IDLE; atomic_inc(&master_jpeg->hw_rdy); wake_up(&master_jpeg->hw_wq); v4l2_m2m_buf_done(src_buf, buf_state); mtk_jpegenc_put_buf(cjpeg); jpeg_buf_queue_dec(ctx); + pm_runtime_put(cjpeg->dev); } static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv) @@ -316,12 +315,11 @@ static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv) v4l2_m2m_buf_done(src_buf, buf_state); mtk_jpegenc_put_buf(jpeg); jpeg_buf_queue_dec(ctx); - pm_runtime_put(ctx->jpeg->dev); - clk_disable_unprepare(jpeg->venc_clk.clks->clk); jpeg->hw_state = MTK_JPEG_HW_IDLE; wake_up(&master_jpeg->hw_wq); atomic_inc(&master_jpeg->hw_rdy); + pm_runtime_put(jpeg->dev); return IRQ_HANDLED; } @@ -425,15 +423,84 @@ static int mtk_jpegenc_hw_probe(struct platform_device *pdev) platform_set_drvdata(pdev, dev); pm_runtime_enable(&pdev->dev); + ret = devm_clk_bulk_get(dev->dev, + jpegenc_clk->clk_num, + jpegenc_clk->clks); + if (ret) { + dev_err(&pdev->dev, "Failed to init clk\n"); + return ret; + } + + return 0; +} + +static void mtk_jpeg_clk_on(struct mtk_jpegenc_comp_dev *jpeg) +{ + int ret; + + ret = clk_bulk_prepare_enable(jpeg->venc_clk.clk_num, + jpeg->venc_clk.clks); + if (ret) + dev_err(jpeg->dev, "%s : %d, jpegenc clk_prepare_enable fail\n", + __func__, __LINE__); +} + +static void mtk_jpeg_clk_off(struct mtk_jpegenc_comp_dev *jpeg) +{ + clk_bulk_disable_unprepare(jpeg->venc_clk.clk_num, + jpeg->venc_clk.clks); +} + +static __maybe_unused int mtk_jpegenc_pm_suspend(struct device *dev) +{ + struct mtk_jpegenc_comp_dev *jpeg = dev_get_drvdata(dev); + + mtk_jpeg_clk_off(jpeg); return 0; } +static __maybe_unused int mtk_jpegenc_pm_resume(struct device *dev) +{ + struct mtk_jpegenc_comp_dev *jpeg = dev_get_drvdata(dev); + + mtk_jpeg_clk_on(jpeg); + + return 0; +} + +static __maybe_unused int mtk_jpegenc_suspend(struct device *dev) +{ + struct mtk_jpegenc_comp_dev *jpeg = dev_get_drvdata(dev); + + v4l2_m2m_suspend(jpeg->master_dev->m2m_dev); + return pm_runtime_force_suspend(dev); +} + +static __maybe_unused int mtk_jpegenc_resume(struct device *dev) +{ + struct mtk_jpegenc_comp_dev *jpeg = dev_get_drvdata(dev); + int ret; + + ret = pm_runtime_force_resume(dev); + if (ret < 0) + return ret; + + v4l2_m2m_resume(jpeg->master_dev->m2m_dev); + return ret; +} + +static const struct dev_pm_ops mtk_jpegenc_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(mtk_jpegenc_suspend, mtk_jpegenc_resume) + SET_RUNTIME_PM_OPS(mtk_jpegenc_pm_suspend, mtk_jpegenc_pm_resume, NULL) +}; + static struct platform_driver mtk_jpegenc_hw_driver = { .probe = mtk_jpegenc_hw_probe, .driver = { .name = "mtk-jpegenc-hw", .of_match_table = mtk_jpegenc_drv_ids, + .pm = &mtk_jpegenc_pm_ops, }, }; From patchwork Fri Apr 25 08:53:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrie Wu X-Patchwork-Id: 884683 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8933923D28C; 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Fri, 25 Apr 2025 16:53:44 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 25 Apr 2025 16:53:42 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 25 Apr 2025 16:53:42 +0800 From: Kyrie Wu To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , kyrie wu , , , , , CC: Kyrie Wu Subject: [PATCH v3 12/12] media: mediatek: jpeg: fix remove buffer operation for multi-core Date: Fri, 25 Apr 2025 16:53:28 +0800 Message-ID: <20250425085328.16929-13-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250425085328.16929-1-kyrie.wu@mediatek.com> References: <20250425085328.16929-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N move remove buffer code to spinlock protect area for multi-core Signed-off-by: Kyrie Wu --- drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c index eba9f58b9198..34fa03bcfdd3 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -1684,9 +1684,6 @@ static void mtk_jpegenc_worker(struct work_struct *work) goto enc_end; } - v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); - v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); - schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work, msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC)); @@ -1707,6 +1704,8 @@ static void mtk_jpegenc_worker(struct work_struct *work) &src_buf->vb2_buf); mtk_jpeg_set_enc_params(ctx, comp_jpeg[hw_id]->reg_base); mtk_jpeg_enc_start(comp_jpeg[hw_id]->reg_base); + v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); jpeg_buf_queue_inc(ctx); v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags); @@ -1803,9 +1802,6 @@ static void mtk_jpegdec_worker(struct work_struct *work) goto dec_end; } - v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); - v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); - mtk_jpeg_set_dec_src(ctx, &src_buf->vb2_buf, &bs); if (mtk_jpeg_set_dec_dst(ctx, &jpeg_src_buf->dec_param, @@ -1833,6 +1829,8 @@ static void mtk_jpegdec_worker(struct work_struct *work) jpeg_src_buf->bs_size, &bs, &fb); + v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); mtk_jpeg_dec_start(comp_jpeg[hw_id]->reg_base); jpeg_buf_queue_inc(ctx); v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);