From patchwork Tue Apr 29 08:19:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 887109 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 00C71279780; Tue, 29 Apr 2025 08:20:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745914817; cv=none; b=Zffvx8F2Jt0XDacpNHRx37MuFen1vYdtUBcJQsV/qsQfXIePyic0xm0RPOmF0aoz7F3ga/WPAmZZx5ST4AmTYs2CdYNnIVAYKme/N6Cw3RJkSRGBQ1KYY6VJV2dhxdo+64ofvOWvIO9dQXPaH3w28PUggouN14Lj7kWBy51Naqs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745914817; c=relaxed/simple; bh=73zA2CLYL9Mn6PX0DxYR0lMBD9A44hRDhGJfPS6gdrI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bA2qgtB9ny1ZkcevwOA4d6iudBqPHz7g+eVsoHxzPUsh+IbdSOh+iKvD5kJ8lcK7QiCONlld4hSVEHtrPxdjVn0baOxaRkPdETBVBSUFW7JFl+xzKJu83LUPi3l1RXW0+ylP1jjR3n/8ycFln4arzPmgBuf59Ghsxvc/bO610Kg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: +jeovNkORJK8jxGD8ggfVA== X-CSE-MsgGUID: iFUeV+J8QuesaRFIvVTfjA== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 29 Apr 2025 17:20:06 +0900 Received: from superbuilder.administration.lan (unknown [10.226.93.118]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 2764A4007F4D; Tue, 29 Apr 2025 17:20:02 +0900 (JST) From: Thierry Bultel To: thierry.bultel@linatsea.fr Cc: linux-renesas-soc@vger.kernel.org, geert@linux-m68k.org, paul.barker.ct@bp.renesas.com, Thierry Bultel , Geert Uytterhoeven , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 01/11] dt-bindings: serial: Added secondary clock for RZ/T2H RSCI Date: Tue, 29 Apr 2025 10:19:43 +0200 Message-ID: <20250429081956.3804621-2-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429081956.3804621-1-thierry.bultel.yh@bp.renesas.com> References: <20250429081956.3804621-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 At boot, the default clock is the PCLKM core lock (synchronous clock, which is enabled by the bootloader). For different baudrates, the asynchronous clock input must be used. Clock selection is made by an internal register of RCSI. Signed-off-by: Thierry Bultel --- .../bindings/serial/renesas,rsci.yaml | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml index ea879db5f485..aa2428837a2f 100644 --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml @@ -35,10 +35,14 @@ properties: - const: tei clocks: - maxItems: 1 + items: + - description: serial functional clock + - description: default core clock clock-names: - const: fck # UART functional clock + items: + - const: async + - const: bus power-domains: maxItems: 1 @@ -58,11 +62,7 @@ unevaluatedProperties: false examples: - | #include - #include - - aliases { - serial0 = &sci0; - }; + #include sci0: serial@80005000 { compatible = "renesas,r9a09g077-rsci"; @@ -72,7 +72,7 @@ examples: , ; interrupt-names = "eri", "rxi", "txi", "tei"; - clocks = <&cpg CPG_MOD 108>; - clock-names = "fck"; + clocks = <&cpg CPG_MOD 108>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "async", "bus"; power-domains = <&cpg>; }; From patchwork Tue Apr 29 08:19:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 886011 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 032B229DB8A; Tue, 29 Apr 2025 08:20:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745914832; cv=none; b=fk+r4laxaaT7fjwgZTWiej5DHhUL24lv0X2h1AjuHk0evemoeeospTZKGN6Pfb1JRlEx7h6p/sd5lS/NbgaH/9KlTW4KxIqzsbjV7WSLzJs4DSq/TvjwlEM9nosSRSPP/T1wOz9j+ltsleznQu3cxJp//V9TyYc9UaJUL9i8tDA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745914832; c=relaxed/simple; bh=+BwwaZP7mKUUGqzq+enoHtnpMa8fH5lKLi77eqlQmro=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KY67Of+hOBwOG2RsKKu8YI6rckCTJ/coKTjctNhkJE9JmTow6XVSdWrqaaH/BA3RAXGoanO8IzSl9pLQ7kEYQ5/DQIsBRgZ46Yu+FvGK1t2xMkO8uui0YXEyA59JOpEgabPi5FJdTA9pdCFt8JNAa6Gg+Ax36emKbH2aC9jkUMU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: bkfLIwFNREavsEYMCh1ABw== X-CSE-MsgGUID: bUF+ERATSmiuO/ILdBAoSg== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 29 Apr 2025 17:20:29 +0900 Received: from superbuilder.administration.lan (unknown [10.226.93.118]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id E4426402F378; Tue, 29 Apr 2025 17:20:26 +0900 (JST) From: Thierry Bultel To: thierry.bultel@linatsea.fr Cc: linux-renesas-soc@vger.kernel.org, geert@linux-m68k.org, paul.barker.ct@bp.renesas.com, Thierry Bultel , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v8 07/11] serial: sh-sci: Use private port ID Date: Tue, 29 Apr 2025 10:19:49 +0200 Message-ID: <20250429081956.3804621-8-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429081956.3804621-1-thierry.bultel.yh@bp.renesas.com> References: <20250429081956.3804621-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Thierry Bultel New port types cannot be added in serial_core.h, which is shared with userspace. In order to support new port types, the coming new ones will have BIT(15) set in the id value, and in this case, uartport->type is set to PORT_GENERIC. This commit therefore changes all the places where the port type is read, by not relying on uartport->type but on the private value stored in struct sci_port. Signed-off-by: Thierry Bultel --- drivers/tty/serial/sh-sci-common.h | 3 + drivers/tty/serial/sh-sci.c | 157 ++++++++++++++++------------- 2 files changed, 90 insertions(+), 70 deletions(-) diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci-common.h index bd9d9cfac1c8..de9796595cfd 100644 --- a/drivers/tty/serial/sh-sci-common.h +++ b/drivers/tty/serial/sh-sci-common.h @@ -142,6 +142,9 @@ struct sci_port { int rx_fifo_timeout; u16 hscif_tot; + unsigned int type; + unsigned int regtype; + const struct sci_port_ops *ops; bool has_rtscts; diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index ff1986dc6af3..2abf80230a77 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -75,6 +75,8 @@ #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS +#define SCI_PUBLIC_PORT_ID(port) (!((port) & BIT(15)) ? (port) : PORT_GENERIC) + static struct sci_port sci_ports[SCI_NPORTS]; static unsigned long sci_ports_in_use; static struct uart_driver sci_uart_driver; @@ -580,7 +582,7 @@ static void sci_start_tx(struct uart_port *port) unsigned short ctrl; #ifdef CONFIG_SERIAL_SH_SCI_DMA - if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { + if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { u16 new, scr = sci_serial_in(port, SCSCR); if (s->chan_tx) new = scr | SCSCR_TDRQE; @@ -592,7 +594,7 @@ static void sci_start_tx(struct uart_port *port) if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) && dma_submit_error(s->cookie_tx)) { - if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) + if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) /* Switch irq from SCIF to DMA */ disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]); @@ -601,8 +603,8 @@ static void sci_start_tx(struct uart_port *port) } #endif - if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE || - port->type == PORT_SCIFA || port->type == PORT_SCIFB) { + if (!s->chan_tx || s->regtype == SCIx_RZ_SCIFA_REGTYPE || + s->type == PORT_SCIFA || s->type == PORT_SCIFB) { /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ ctrl = sci_serial_in(port, SCSCR); @@ -611,7 +613,7 @@ static void sci_start_tx(struct uart_port *port) * (transmit interrupt enable) or in the same instruction to start * the transmit process. */ - if (port->type == PORT_SCI) + if (s->type == PORT_SCI) ctrl |= SCSCR_TE; sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE); @@ -620,12 +622,13 @@ static void sci_start_tx(struct uart_port *port) static void sci_stop_tx(struct uart_port *port) { + struct sci_port *s = to_sci_port(port); unsigned short ctrl; /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ ctrl = sci_serial_in(port, SCSCR); - if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) + if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) ctrl &= ~SCSCR_TDRQE; ctrl &= ~SCSCR_TIE; @@ -633,21 +636,22 @@ static void sci_stop_tx(struct uart_port *port) sci_serial_out(port, SCSCR, ctrl); #ifdef CONFIG_SERIAL_SH_SCI_DMA - if (to_sci_port(port)->chan_tx && - !dma_submit_error(to_sci_port(port)->cookie_tx)) { - dmaengine_terminate_async(to_sci_port(port)->chan_tx); - to_sci_port(port)->cookie_tx = -EINVAL; + if (s->chan_tx && + !dma_submit_error(s->cookie_tx)) { + dmaengine_terminate_async(s->chan_tx); + s->cookie_tx = -EINVAL; } #endif } static void sci_start_rx(struct uart_port *port) { + struct sci_port *s = to_sci_port(port); unsigned short ctrl; ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port); - if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) + if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) ctrl &= ~SCSCR_RDRQE; sci_serial_out(port, SCSCR, ctrl); @@ -655,11 +659,12 @@ static void sci_start_rx(struct uart_port *port) static void sci_stop_rx(struct uart_port *port) { + struct sci_port *s = to_sci_port(port); unsigned short ctrl; ctrl = sci_serial_in(port, SCSCR); - if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) + if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) ctrl &= ~SCSCR_RDRQE; ctrl &= ~port_rx_irq_mask(port); @@ -669,10 +674,12 @@ static void sci_stop_rx(struct uart_port *port) static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) { - if (port->type == PORT_SCI) { + struct sci_port *s = to_sci_port(port); + + if (s->type == PORT_SCI) { /* Just store the mask */ sci_serial_out(port, SCxSR, mask); - } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { + } else if (s->params->overrun_mask == SCIFA_ORER) { /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ /* Only clear the status bits we want to clear */ sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask); @@ -742,13 +749,13 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag) return; } - if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { + if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { u16 data = sci_serial_in(port, SCPDR); u16 ctrl = sci_serial_in(port, SCPCR); /* Enable RXD and TXD pin functions */ ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); - if (to_sci_port(port)->has_rtscts) { + if (s->has_rtscts) { /* RTS# is output, active low, unless autorts */ if (!(port->mctrl & TIOCM_RTS)) { ctrl |= SCPCR_RTSC; @@ -765,7 +772,7 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag) } sci_serial_out(port, SCPDR, data); sci_serial_out(port, SCPCR, ctrl); - } else if (sci_getreg(port, SCSPTR)->size && s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) { + } else if (sci_getreg(port, SCSPTR)->size && s->regtype != SCIx_RZV2H_SCIF_REGTYPE) { u16 status = sci_serial_in(port, SCSPTR); /* RTS# is always output; and active low, unless autorts */ @@ -852,7 +859,7 @@ static void sci_transmit_chars(struct uart_port *port) c = port->x_char; port->x_char = 0; } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) { - if (port->type == PORT_SCI && + if (s->type == PORT_SCI && kfifo_is_empty(&tport->xmit_fifo)) { ctrl = sci_serial_in(port, SCSCR); ctrl &= ~SCSCR_TE; @@ -873,7 +880,7 @@ static void sci_transmit_chars(struct uart_port *port) if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) uart_write_wakeup(port); if (kfifo_is_empty(&tport->xmit_fifo)) { - if (port->type == PORT_SCI) { + if (s->type == PORT_SCI) { ctrl = sci_serial_in(port, SCSCR); ctrl &= ~SCSCR_TIE; ctrl |= SCSCR_TEIE; @@ -904,7 +911,7 @@ static void sci_receive_chars(struct uart_port *port) if (count == 0) break; - if (port->type == PORT_SCI) { + if (s->type == PORT_SCI) { char c = sci_serial_in(port, SCxRDR); if (uart_handle_sysrq_char(port, c)) count = 0; @@ -914,8 +921,8 @@ static void sci_receive_chars(struct uart_port *port) for (i = 0; i < count; i++) { char c; - if (port->type == PORT_SCIF || - port->type == PORT_HSCIF) { + if (s->type == PORT_SCIF || + s->type == PORT_HSCIF) { status = sci_serial_in(port, SCxSR); c = sci_serial_in(port, SCxRDR); } else { @@ -1052,6 +1059,7 @@ static int sci_handle_breaks(struct uart_port *port) static int scif_set_rtrg(struct uart_port *port, int rx_trig) { + struct sci_port *s = to_sci_port(port); unsigned int bits; if (rx_trig >= port->fifosize) @@ -1065,7 +1073,7 @@ static int scif_set_rtrg(struct uart_port *port, int rx_trig) return rx_trig; } - switch (port->type) { + switch (s->type) { case PORT_SCIF: if (rx_trig < 4) { bits = 0; @@ -1150,7 +1158,7 @@ static ssize_t rx_fifo_trigger_store(struct device *dev, return ret; sci->rx_trigger = sci->ops->set_rtrg(port, r); - if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) + if (sci->type == PORT_SCIFA || sci->type == PORT_SCIFB) sci->ops->set_rtrg(port, 1); return count; @@ -1166,7 +1174,7 @@ static ssize_t rx_fifo_timeout_show(struct device *dev, struct sci_port *sci = to_sci_port(port); int v; - if (port->type == PORT_HSCIF) + if (sci->type == PORT_HSCIF) v = sci->hscif_tot >> HSSCR_TOT_SHIFT; else v = sci->rx_fifo_timeout; @@ -1188,7 +1196,7 @@ static ssize_t rx_fifo_timeout_store(struct device *dev, if (ret) return ret; - if (port->type == PORT_HSCIF) { + if (sci->type == PORT_HSCIF) { if (r < 0 || r > 3) return -EINVAL; sci->hscif_tot = r << HSSCR_TOT_SHIFT; @@ -1229,11 +1237,11 @@ static void sci_dma_tx_complete(void *arg) schedule_work(&s->work_tx); } else { s->cookie_tx = -EINVAL; - if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || - s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { + if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || + s->regtype == SCIx_RZ_SCIFA_REGTYPE) { u16 ctrl = sci_serial_in(port, SCSCR); sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE); - if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { + if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) { /* Switch irq from DMA to SCIF */ dmaengine_pause(s->chan_tx_saved); enable_irq(s->irqs[SCIx_TXI_IRQ]); @@ -1315,10 +1323,10 @@ static void sci_dma_rx_reenable_irq(struct sci_port *s) /* Direct new serial port interrupts back to CPU */ scr = sci_serial_in(port, SCSCR); - if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || - s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { + if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || + s->regtype == SCIx_RZ_SCIFA_REGTYPE) { enable_irq(s->irqs[SCIx_RXI_IRQ]); - if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) + if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) s->ops->set_rtrg(port, s->rx_trigger); else scr &= ~SCSCR_RDRQE; @@ -1558,8 +1566,8 @@ static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) tty_flip_buffer_push(&port->state->port); } - if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || - s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) + if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || + s->regtype == SCIx_RZ_SCIFA_REGTYPE) sci_dma_rx_submit(s, true); sci_dma_rx_reenable_irq(s); @@ -1682,8 +1690,8 @@ static void sci_request_dma(struct uart_port *port) s->chan_rx_saved = s->chan_rx = chan; - if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || - s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) + if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || + s->regtype == SCIx_RZ_SCIFA_REGTYPE) sci_dma_rx_submit(s, false); } } @@ -1753,10 +1761,10 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr) u16 ssr = sci_serial_in(port, SCxSR); /* Disable future Rx interrupts */ - if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || - s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { + if (s->type == PORT_SCIFA || s->type == PORT_SCIFB || + s->regtype == SCIx_RZ_SCIFA_REGTYPE) { disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); - if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { + if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) { s->ops->set_rtrg(port, 1); scr |= SCSCR_RIE; } else { @@ -1820,7 +1828,7 @@ static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr) unsigned long flags; u32 ctrl; - if (port->type != PORT_SCI) + if (s->type != PORT_SCI) return sci_tx_interrupt(irq, ptr); uart_port_lock_irqsave(port, &flags); @@ -1867,7 +1875,7 @@ static irqreturn_t sci_er_interrupt(int irq, void *ptr) } /* Handle errors */ - if (port->type == PORT_SCI) { + if (s->type == PORT_SCI) { if (sci_handle_errors(port)) { /* discard character in rx buffer */ sci_serial_in(port, SCxSR); @@ -2091,7 +2099,9 @@ static unsigned int sci_tx_empty(struct uart_port *port) static void sci_set_rts(struct uart_port *port, bool state) { - if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { + struct sci_port *s = to_sci_port(port); + + if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { u16 data = sci_serial_in(port, SCPDR); /* Active low */ @@ -2118,7 +2128,9 @@ static void sci_set_rts(struct uart_port *port, bool state) static bool sci_get_cts(struct uart_port *port) { - if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { + struct sci_port *s = to_sci_port(port); + + if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { /* Active low */ return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD); } else if (sci_getreg(port, SCSPTR)->size) { @@ -2164,21 +2176,21 @@ static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) if (!(mctrl & TIOCM_RTS)) { /* Disable Auto RTS */ - if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) + if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE) sci_serial_out(port, SCFCR, sci_serial_in(port, SCFCR) & ~SCFCR_MCE); /* Clear RTS */ sci_set_rts(port, 0); } else if (s->autorts) { - if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { + if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) { /* Enable RTS# pin function */ sci_serial_out(port, SCPCR, sci_serial_in(port, SCPCR) & ~SCPCR_RTSC); } /* Enable Auto RTS */ - if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) + if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE) sci_serial_out(port, SCFCR, sci_serial_in(port, SCFCR) | SCFCR_MCE); } else { @@ -2315,7 +2327,7 @@ static int sci_sck_calc(struct sci_port *s, unsigned int bps, int err, min_err = INT_MAX; unsigned int sr; - if (s->port.type != PORT_HSCIF) + if (s->type != PORT_HSCIF) freq *= 2; for_each_sr(sr, s) { @@ -2342,7 +2354,7 @@ static int sci_brg_calc(struct sci_port *s, unsigned int bps, int err, min_err = INT_MAX; unsigned int sr, dl; - if (s->port.type != PORT_HSCIF) + if (s->type != PORT_HSCIF) freq *= 2; for_each_sr(sr, s) { @@ -2375,7 +2387,7 @@ static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, unsigned int sr, br, prediv, scrate, c; int err, min_err = INT_MAX; - if (s->port.type != PORT_HSCIF) + if (s->type != PORT_HSCIF) freq *= 2; /* @@ -2460,8 +2472,8 @@ static void sci_reset(struct uart_port *port) s->ops->set_rtrg(port, 1); timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); } else { - if (port->type == PORT_SCIFA || - port->type == PORT_SCIFB) + if (s->type == PORT_SCIFA || + s->type == PORT_SCIFB) s->ops->set_rtrg(port, 1); else s->ops->set_rtrg(port, s->rx_trigger); @@ -2521,8 +2533,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, */ /* Optional Undivided External Clock */ - if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && - port->type != PORT_SCIFB) { + if (s->clk_rates[SCI_SCK] && s->type != PORT_SCIFA && + s->type != PORT_SCIFB) { err = sci_sck_calc(s, baud, &srr1); if (abs(err) < abs(min_err)) { best_clk = SCI_SCK; @@ -2607,7 +2619,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, sci_serial_out(port, SEMR, 0); if (best_clk >= 0) { - if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) + if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) switch (srr + 1) { case 5: smr_val |= SCSMR_SRC_5; break; case 7: smr_val |= SCSMR_SRC_7; break; @@ -2692,12 +2704,12 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, * (transmit interrupt enable) or in the same instruction to * start the transmitting process. So skip setting TE here for SCI. */ - if (port->type != PORT_SCI) + if (s->type != PORT_SCI) scr_val |= SCSCR_TE; scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); if ((srr + 1 == 5) && - (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { + (s->type == PORT_SCIFA || s->type == PORT_SCIFB)) { /* * In asynchronous mode, when the sampling rate is 1/5, first * received data may become invalid on some SCIFA and SCIFB. @@ -2741,7 +2753,9 @@ void sci_pm(struct uart_port *port, unsigned int state, static const char *sci_type(struct uart_port *port) { - switch (port->type) { + struct sci_port *s = to_sci_port(port); + + switch (s->type) { case PORT_IRDA: return "irda"; case PORT_SCI: @@ -2825,8 +2839,7 @@ void sci_config_port(struct uart_port *port, int flags) { if (flags & UART_CONFIG_TYPE) { struct sci_port *sport = to_sci_port(port); - - port->type = sport->cfg->type; + port->type = SCI_PUBLIC_PORT_ID(sport->type); sci_request_port(port); } } @@ -2964,7 +2977,7 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) struct clk *clk; unsigned int i; - if (sci_port->cfg->type == PORT_HSCIF) + if (sci_port->type == PORT_HSCIF) clk_names[SCI_SCK] = "hsck"; for (i = 0; i < SCI_NUM_CLKS; i++) { @@ -3050,6 +3063,9 @@ static int sci_init_single(struct platform_device *dev, sci_port->cfg = p; + sci_port->type = p->type; + sci_port->regtype = p->regtype; + port->iotype = UPIO_MEM; port->line = index; port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); @@ -3128,11 +3144,11 @@ static int sci_init_single(struct platform_device *dev, return ret; } - port->type = p->type; + port->type = SCI_PUBLIC_PORT_ID(p->type); port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; port->fifosize = sci_port->params->fifosize; - if (port->type == PORT_SCI && !dev->dev.of_node) { + if (p->type == PORT_SCI && !dev->dev.of_node) { if (sci_port->reg_size >= 0x20) port->regshift = 2; else @@ -3322,13 +3338,13 @@ static struct uart_driver sci_uart_driver = { static void sci_remove(struct platform_device *dev) { - struct sci_port *port = platform_get_drvdata(dev); - unsigned int type = port->port.type; /* uart_remove_... clears it */ + struct sci_port *s = platform_get_drvdata(dev); + unsigned int type = s->type; /* uart_remove_... clears it */ - sci_ports_in_use &= ~BIT(port->port.line); - uart_remove_one_port(&sci_uart_driver, &port->port); + sci_ports_in_use &= ~BIT(s->port.line); + uart_remove_one_port(&sci_uart_driver, &s->port); - if (port->port.fifosize > 1) + if (s->port.fifosize > 1) device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); @@ -3682,8 +3698,8 @@ static int sci_probe(struct platform_device *dev) if (ret) return ret; } - if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || - sp->port.type == PORT_HSCIF) { + if (sp->type == PORT_SCIFA || sp->type == PORT_SCIFB || + sp->type == PORT_HSCIF) { ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); if (ret) { if (sp->port.fifosize > 1) { @@ -3799,7 +3815,8 @@ int __init scix_early_console_setup(struct earlycon_device *device, if (!device->port.membase) return -ENODEV; - device->port.type = data->type; + device->port.type = SCI_PUBLIC_PORT_ID(data->type); + sci_ports[0].port = device->port; port_cfg.type = data->type; From patchwork Tue Apr 29 08:19:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 887108 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1938E29E056; Tue, 29 Apr 2025 08:20:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745914837; cv=none; b=XbC8OBR0iNeHfIh4po7/lftm0fBmDG+6DsPBremzyuhFXeXIUvc/DjxS6sauEM2SVwHycDfvirRx/XEwefd87Eh6dboOAOtrI/q9GtYf7hlYFvUVtpsAOpYIjKTdaNCe5O2a3wnaYX7Z0XtzI1biiHnUVlw5PK+x0b4pFUOfI6o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745914837; c=relaxed/simple; bh=yEyrbPgk7s3efGAdHAySOqF6o8qJbfCxuUamvayjufs=; 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Tue, 29 Apr 2025 17:20:30 +0900 (JST) From: Thierry Bultel To: thierry.bultel@linatsea.fr Cc: linux-renesas-soc@vger.kernel.org, geert@linux-m68k.org, paul.barker.ct@bp.renesas.com, Thierry Bultel , Wolfram Sang , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v8 08/11] serial: sh-sci: Add support for RZ/T2H SCI Date: Tue, 29 Apr 2025 10:19:50 +0200 Message-ID: <20250429081956.3804621-9-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429081956.3804621-1-thierry.bultel.yh@bp.renesas.com> References: <20250429081956.3804621-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Define a new RSCI port type, and the RSCI 32 bits registers set. The RZ/T2H SCI has a a fifo, and a quite different set of registers from the orginal SH SCI ones. DMA is not supported yet. Reviewed-by: Wolfram Sang Signed-off-by: Thierry Bultel --- Changes v7->v8: - s/rzsci/rsci/g - declared SCI_PORT_RSCI as private port ID - look for secondary clock - report error when rsci clocks are not found Changes v6->v7: - Renamed compatible string to r9a09g077-rsci Changes v5->v6: - Rename SERIAL_RZ_SCI_T2 to CONFIG_SERIAL_RSCI - Rename rz-sci-t2.{c,h} to rsci.{c,h} - Rename port type to PORT_RSCI - Rename sci_r9a09g077_data to of_sci_r9a09g077_data for consistency Changes v4->v5: - Rename SERIAL_RZ_SCI to SERIAL_RZ_SCI_T2 - Rename rzsci.{c,h} to rz-sci-t2.{c,h} - Rename port type to PORT_RZ_SCI_T2 - Set sci_shutdown ops pointer (needed by systemd for having a console) Changes v3->v4: - Added missing #include - Fix christmas tree code style in rzsci_transmit_chars. --- drivers/tty/serial/Kconfig | 7 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/rsci.c | 466 +++++++++++++++++++++++++++++ drivers/tty/serial/rsci.h | 12 + drivers/tty/serial/sh-sci-common.h | 5 + drivers/tty/serial/sh-sci.c | 43 ++- 6 files changed, 524 insertions(+), 10 deletions(-) create mode 100644 drivers/tty/serial/rsci.c create mode 100644 drivers/tty/serial/rsci.h diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 79a8186d3361..44427415a80d 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -675,6 +675,13 @@ config SERIAL_SH_SCI_DMA depends on SERIAL_SH_SCI && DMA_ENGINE default ARCH_RENESAS +config SERIAL_RSCI + tristate "Support for Renesas RZ/T2H SCI variant" + depends on SERIAL_SH_SCI + help + Support for the RZ/T2H SCI variant with fifo. + Say Y if you want to be able to use the RZ/T2H SCI serial port. + config SERIAL_HS_LPC32XX tristate "LPC32XX high speed serial port support" depends on ARCH_LPC32XX || COMPILE_TEST diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index d58d9f719889..a2ccbc508ec5 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_SERIAL_QCOM_GENI) += qcom_geni_serial.o obj-$(CONFIG_SERIAL_QE) += ucc_uart.o obj-$(CONFIG_SERIAL_RDA) += rda-uart.o obj-$(CONFIG_SERIAL_RP2) += rp2.o +obj-$(CONFIG_SERIAL_RSCI) += rsci.o obj-$(CONFIG_SERIAL_SA1100) += sa1100.o obj-$(CONFIG_SERIAL_SAMSUNG) += samsung_tty.o obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c new file mode 100644 index 000000000000..6a71bcffcc98 --- /dev/null +++ b/drivers/tty/serial/rsci.c @@ -0,0 +1,466 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "rsci.h" + +/* RSCI registers */ +#define RDR 0x00 +#define TDR 0x04 +#define CCR0 0x08 +#define CCR1 0x0C +#define CCR2 0x10 +#define CCR3 0x14 +#define CCR4 0x18 +#define FCR 0x24 +#define DCR 0x30 +#define CSR 0x48 +#define FRSR 0x50 +#define FTSR 0x54 +#define CFCLR 0x68 +#define FFCLR 0x70 + +/* RDR (Receive Data Register) */ +#define RDR_FFER BIT(12) /* FIFO Framing Error */ +#define RDR_FPER BIT(11) /* FIFO Parity Error */ +#define RDR_RDAT_MSK GENMASK(8, 0) + +/* TDR (Transmit Data Register) */ +#define TDR_MPBT BIT(9) /* Multiprocessor Transfer */ +#define TDR_TDAT_9BIT_LSHIFT 0 +#define TDR_TDAT_9BIT_VAL 0x1FF +#define TDR_TDAT_9BIT_MSK (TDR_TDAT_9BIT_VAL << TDR_TDAT_9BIT_LSHIFT) + +/* CCR0 (Common Control Register 0) */ +#define CCR0_SSE BIT(24) /* SSn# Pin Function Enable */ +#define CCR0_TEIE BIT(21) /* Transmit End Interrupt Enable */ +#define CCR0_TIE BIT(20) /* Transmit Interrupt Enable */ +#define CCR0_RIE BIT(16) /* Receive Interrupt Enable */ +#define CCR0_IDSEL BIT(10) /* ID Frame Select */ +#define CCR0_DCME BIT(9) /* Data Compare Match Enable */ +#define CCR0_MPIE BIT(8) /* Multiprocessor Interrupt Enable */ +#define CCR0_TE BIT(4) /* Transmit Enable */ +#define CCR0_RE BIT(0) /* Receive Enable */ + +/* CCR1 (Common Control Register 1) */ +#define CCR1_NFEN BIT(28) /* Digital Noise Filter Function */ +#define CCR1_SHARPS BIT(20) /* Half -duplex Communication Select */ +#define CCR1_SPLP BIT(16) /* Loopback Control */ +#define CCR1_RINV BIT(13) /* RxD invert */ +#define CCR1_TINV BIT(12) /* TxD invert */ +#define CCR1_PM BIT(9) /* Parity Mode */ +#define CCR1_PE BIT(8) /* Parity Enable */ +#define CCR1_SPB2IO BIT(5) /* Serial Port Break I/O */ +#define CCR1_SPB2DT BIT(4) /* Serial Port Break Data Select */ +#define CCR1_CTSPEN BIT(1) /* CTS External Pin Enable */ +#define CCR1_CTSE BIT(0) /* CTS Enable */ + +/* FCR (FIFO Control Register) */ +#define FCR_RFRST BIT(23) /* Receive FIFO Data Register Reset */ +#define FCR_TFRST BIT(15) /* Transmit FIFO Data Register Reset */ +#define FCR_DRES BIT(0) /* Incoming Data Ready Error Select */ +#define FCR_RTRG4_0 GENMASK(20, 16) +#define FCR_TTRG GENMASK(12, 8) + +/* CSR (Common Status Register) */ +#define CSR_RDRF BIT(31) /* Receive Data Full */ +#define CSR_TEND BIT(30) /* Transmit End Flag */ +#define CSR_TDRE BIT(29) /* Transmit Data Empty */ +#define CSR_FER BIT(28) /* Framing Error */ +#define CSR_PER BIT(27) /* Parity Error */ +#define CSR_MFF BIT(26) /* Mode Fault Error */ +#define CSR_ORER BIT(24) /* Overrun Error */ +#define CSR_DFER BIT(18) /* Data Compare Match Framing Error */ +#define CSR_DPER BIT(17) /* Data Compare Match Parity Error */ +#define CSR_DCMF BIT(16) /* Data Compare Match */ +#define CSR_RXDMON BIT(15) /* Serial Input Data Monitor */ +#define CSR_ERS BIT(4) /* Error Signal Status */ + +#define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask) +#define SCxSR_ERROR_CLEAR(port) (to_sci_port(port)->params->error_clear) + +#define RSCI_DEFAULT_ERROR_MASK (CSR_PER | CSR_FER) + +#define RSCI_RDxF_CLEAR (CFCLR_RDRFC) +#define RSCI_ERROR_CLEAR (CFCLR_PERC | CFCLR_FERC) +#define RSCI_TDxE_CLEAR (CFCLR_TDREC) +#define RSCI_BREAK_CLEAR (CFCLR_PERC | CFCLR_FERC | CFCLR_ORERC) + +/* FRSR (FIFO Receive Status Register) */ +#define FRSR_R5_0 GENMASK(13, 8) /* Receive FIFO Data Count */ +#define FRSR_DR BIT(0) /* Receive Data Ready */ + +/* CFCLR (Common Flag CLear Register) */ +#define CFCLR_RDRFC BIT(31) /* RDRF Clear */ +#define CFCLR_TDREC BIT(29) /* TDRE Clear */ +#define CFCLR_FERC BIT(28) /* FER Clear */ +#define CFCLR_PERC BIT(27) /* PER Clear */ +#define CFCLR_MFFC BIT(26) /* MFF Clear */ +#define CFCLR_ORERC BIT(24) /* ORER Clear */ +#define CFCLR_DFERC BIT(18) /* DFER Clear */ +#define CFCLR_DPERC BIT(17) /* DPER Clear */ +#define CFCLR_DCMFC BIT(16) /* DCMF Clear */ +#define CFCLR_ERSC BIT(4) /* ERS Clear */ +#define CFCLR_CLRFLAG (CFCLR_RDRFC | CFCLR_FERC | CFCLR_PERC | \ + CFCLR_MFFC | CFCLR_ORERC | CFCLR_DFERC | \ + CFCLR_DPERC | CFCLR_DCMFC | CFCLR_ERSC) + +/* FFCLR (FIFO Flag CLear Register) */ +#define FFCLR_DRC BIT(0) /* DR Clear */ + +#define DCR_DEPOL BIT(0) + +static u32 rsci_serial_in(struct uart_port *p, int offset) +{ + return readl(p->membase + offset); +} + +static void rsci_serial_out(struct uart_port *p, int offset, int value) +{ + writel(value, p->membase + offset); +} + +static void rsci_clear_DRxC(struct uart_port *port) +{ + rsci_serial_out(port, CFCLR, CFCLR_RDRFC); + rsci_serial_out(port, FFCLR, FFCLR_DRC); +} + +static void rsci_clear_SCxSR(struct uart_port *port, unsigned int mask) +{ + rsci_serial_out(port, CFCLR, mask); +} + +static void rsci_start_rx(struct uart_port *port) +{ + unsigned int ctrl; + + ctrl = rsci_serial_in(port, CCR0); + ctrl |= CCR0_RIE; + rsci_serial_out(port, CCR0, ctrl); +} + +static void rsci_set_termios(struct uart_port *port, struct ktermios *termios, + const struct ktermios *old) +{ + struct sci_port *s = to_sci_port(port); + unsigned long flags; + + sci_port_enable(s); + uart_port_lock_irqsave(port, &flags); + + /* For now, only RX enabling is supported */ + if (termios->c_cflag & CREAD) + rsci_start_rx(port); + + uart_port_unlock_irqrestore(port, flags); + sci_port_disable(s); +} + +static int rsci_txfill(struct uart_port *port) +{ + return rsci_serial_in(port, FTSR); +} + +static int rsci_rxfill(struct uart_port *port) +{ + u32 val = rsci_serial_in(port, FRSR); + + return FIELD_GET(FRSR_R5_0, val); +} + +static unsigned int rsci_tx_empty(struct uart_port *port) +{ + unsigned int status = rsci_serial_in(port, CSR); + unsigned int in_tx_fifo = rsci_txfill(port); + + return (status & CSR_TEND) && !in_tx_fifo ? TIOCSER_TEMT : 0; +} + +static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + /* Not supported yet */ +} + +static unsigned int rsci_get_mctrl(struct uart_port *port) +{ + /* Not supported yet */ + return 0; +} + +static void rsci_clear_CFC(struct uart_port *port, unsigned int mask) +{ + rsci_serial_out(port, CFCLR, mask); +} + +static void rsci_start_tx(struct uart_port *port) +{ + struct sci_port *sp = to_sci_port(port); + u32 ctrl; + + if (sp->chan_tx) + return; + + /* + * TE (Transmit Enable) must be set after setting TIE + * (Transmit Interrupt Enable) or in the same instruction + * to start the transmit process. + */ + ctrl = rsci_serial_in(port, CCR0); + ctrl |= CCR0_TIE | CCR0_TE; + rsci_serial_out(port, CCR0, ctrl); +} + +static void rsci_stop_tx(struct uart_port *port) +{ + u32 ctrl; + + ctrl = rsci_serial_in(port, CCR0); + ctrl &= ~CCR0_TIE; + rsci_serial_out(port, CCR0, ctrl); +} + +static void rsci_stop_rx(struct uart_port *port) +{ + u32 ctrl; + + ctrl = rsci_serial_in(port, CCR0); + ctrl &= ~CCR0_RIE; + rsci_serial_out(port, CCR0, ctrl); +} + +static int rsci_txroom(struct uart_port *port) +{ + return port->fifosize - rsci_txfill(port); +} + +static void rsci_transmit_chars(struct uart_port *port) +{ + unsigned int stopped = uart_tx_stopped(port); + struct tty_port *tport = &port->state->port; + u32 status, ctrl; + int count; + + status = rsci_serial_in(port, CSR); + if (!(status & CSR_TDRE)) { + ctrl = rsci_serial_in(port, CCR0); + if (kfifo_is_empty(&tport->xmit_fifo)) + ctrl &= ~CCR0_TIE; + else + ctrl |= CCR0_TIE; + rsci_serial_out(port, CCR0, ctrl); + return; + } + + count = rsci_txroom(port); + + do { + unsigned char c; + + if (port->x_char) { + c = port->x_char; + port->x_char = 0; + } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) { + break; + } + + rsci_clear_CFC(port, CFCLR_TDREC); + rsci_serial_out(port, TDR, c); + + port->icount.tx++; + } while (--count > 0); + + if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) + uart_write_wakeup(port); + + if (kfifo_is_empty(&tport->xmit_fifo)) { + ctrl = rsci_serial_in(port, CCR0); + ctrl &= ~CCR0_TIE; + ctrl |= CCR0_TEIE; + rsci_serial_out(port, CCR0, ctrl); + } +} + +static void rsci_receive_chars(struct uart_port *port) +{ + struct tty_port *tport = &port->state->port; + u32 rdat, status, frsr_status = 0; + int i, count, copied = 0; + unsigned char flag; + + status = rsci_serial_in(port, CSR); + frsr_status = rsci_serial_in(port, FRSR); + + if (!(status & CSR_RDRF) && !(frsr_status & FRSR_DR)) + return; + + while (1) { + /* Don't copy more bytes than there is room for in the buffer */ + count = tty_buffer_request_room(tport, rsci_rxfill(port)); + + /* If for any reason we can't copy more data, we're done! */ + if (count == 0) + break; + + for (i = 0; i < count; i++) { + char c; + + rdat = rsci_serial_in(port, RDR); + /* 9-bits data is not supported yet */ + c = rdat & RDR_RDAT_MSK; + + if (uart_handle_sysrq_char(port, c)) { + count--; + i--; + continue; + } + + /* Store data and status. + * Non FIFO mode is not supported + */ + if (rdat & RDR_FFER) { + flag = TTY_FRAME; + port->icount.frame++; + } else if (rdat & RDR_FPER) { + flag = TTY_PARITY; + port->icount.parity++; + } else { + flag = TTY_NORMAL; + } + + tty_insert_flip_char(tport, c, flag); + } + + rsci_serial_in(port, CSR); /* dummy read */ + rsci_clear_DRxC(port); + + copied += count; + port->icount.rx += count; + } + + if (copied) { + /* Tell the rest of the system the news. New characters! */ + tty_flip_buffer_push(tport); + } else { + /* TTY buffers full; read from RX reg to prevent lockup */ + rsci_serial_in(port, RDR); + rsci_serial_in(port, CSR); /* dummy read */ + rsci_clear_DRxC(port); + } +} + +static void rsci_poll_put_char(struct uart_port *port, unsigned char c) +{ + u32 status; + int ret; + + ret = readl_relaxed_poll_timeout_atomic(port->membase + CSR, status, + (status & CSR_TDRE), 100, + USEC_PER_SEC); + if (ret != 0) { + dev_err(port->dev, + "Error while sending data in UART TX : %d\n", ret); + goto done; + } + rsci_serial_out(port, TDR, c); +done: + rsci_clear_SCxSR(port, CFCLR_TDREC); +} + +static void rsci_prepare_console_write(struct uart_port *port, u32 ctrl) +{ + struct sci_port *s = to_sci_port(port); + u32 ctrl_temp = + s->params->param_bits->rxtx_enable | + CCR0_TIE | + s->hscif_tot; + rsci_serial_out(port, CCR0, ctrl_temp); +} + +static const char *rsci_type(struct uart_port *port) +{ + return "rsci"; +} + +static size_t rsci_suspend_regs_size(void) +{ + return 0; +} + +static const struct sci_common_regs rsci_common_regs = { + .status = CSR, + .control = CCR0, +}; + +static const struct sci_port_params_bits rsci_port_param_bits = { + .rxtx_enable = CCR0_RE | CCR0_TE, + .te_clear = CCR0_TE | CCR0_TEIE, + .poll_sent_bits = CSR_TDRE | CSR_TEND, +}; + +static const struct sci_port_params rsci_port_params = { + .fifosize = 16, + .overrun_reg = CSR, + .overrun_mask = CSR_ORER, + .sampling_rate_mask = SCI_SR(32), + .error_mask = RSCI_DEFAULT_ERROR_MASK, + .error_clear = RSCI_ERROR_CLEAR, + .param_bits = &rsci_port_param_bits, + .common_regs = &rsci_common_regs, +}; + +static const struct uart_ops rzt2_sci_uart_ops = { + .tx_empty = rsci_tx_empty, + .set_mctrl = rsci_set_mctrl, + .get_mctrl = rsci_get_mctrl, + .start_tx = rsci_start_tx, + .stop_tx = rsci_stop_tx, + .stop_rx = rsci_stop_rx, + .startup = sci_startup, + .shutdown = sci_shutdown, + .set_termios = rsci_set_termios, + .pm = sci_pm, + .type = rsci_type, + .release_port = sci_release_port, + .request_port = sci_request_port, + .config_port = sci_config_port, + .verify_port = sci_verify_port, +}; + +static const struct sci_port_ops rsci_port_ops = { + .read_reg = rsci_serial_in, + .write_reg = rsci_serial_out, + .clear_SCxSR = rsci_clear_SCxSR, + .transmit_chars = rsci_transmit_chars, + .receive_chars = rsci_receive_chars, + .poll_put_char = rsci_poll_put_char, + .prepare_console_write = rsci_prepare_console_write, + .suspend_regs_size = rsci_suspend_regs_size, +}; + +struct sci_of_data of_sci_r9a09g077_data = { + .type = SCI_PORT_RSCI, + .ops = &rsci_port_ops, + .uart_ops = &rzt2_sci_uart_ops, + .params = &rsci_port_params, +}; + +#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON + +static int __init rzt2hsci_early_console_setup(struct earlycon_device *device, + const char *opt) +{ + return scix_early_console_setup(device, &of_sci_r9a09g077_data); +} + +OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rzt2hsci_early_console_setup); + +#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ diff --git a/drivers/tty/serial/rsci.h b/drivers/tty/serial/rsci.h new file mode 100644 index 000000000000..0a037af26267 --- /dev/null +++ b/drivers/tty/serial/rsci.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __RSCI_H__ +#define __RSCI_H__ + +#include "sh-sci-common.h" + +#ifdef CONFIG_SERIAL_RSCI +extern struct sci_of_data of_sci_r9a09g077_data; +#endif + +#endif /* __RSCI_H__ */ diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci-common.h index de9796595cfd..f172715621ae 100644 --- a/drivers/tty/serial/sh-sci-common.h +++ b/drivers/tty/serial/sh-sci-common.h @@ -5,6 +5,11 @@ #include +/* Private port IDs */ +enum SCI_PORT_TYPE { + SCI_PORT_RSCI = BIT(15)|0, +}; + enum SCI_CLKS { SCI_FCK, /* Functional Clock */ SCI_SCK, /* Optional External Clock */ diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 2abf80230a77..44066cd53e5e 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -54,6 +54,7 @@ #include #endif +#include "rsci.h" #include "serial_mctrl_gpio.h" #include "sh-sci.h" #include "sh-sci-common.h" @@ -1828,7 +1829,7 @@ static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr) unsigned long flags; u32 ctrl; - if (s->type != PORT_SCI) + if (s->type != PORT_SCI && s->type != SCI_PORT_RSCI) return sci_tx_interrupt(irq, ptr); uart_port_lock_irqsave(port, &flags); @@ -2977,14 +2978,26 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) struct clk *clk; unsigned int i; - if (sci_port->type == PORT_HSCIF) + if (sci_port->type == PORT_HSCIF) { clk_names[SCI_SCK] = "hsck"; + } else if (sci_port->type == SCI_PORT_RSCI) { + clk_names[SCI_FCK] = "async"; + clk_names[SCI_SCK] = "bus"; + } for (i = 0; i < SCI_NUM_CLKS; i++) { - clk = devm_clk_get_optional(dev, clk_names[i]); + const char *name = clk_names[i]; + + clk = devm_clk_get_optional(dev, name); if (IS_ERR(clk)) return PTR_ERR(clk); + if (!clk && i <= SCI_SCK && sci_port->type == SCI_PORT_RSCI) { + return dev_err_probe(dev, -ENODEV, + "failed to get %s\n", + name); + } + if (!clk && i == SCI_FCK) { /* * Not all SH platforms declare a clock lookup entry @@ -2995,13 +3008,13 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) if (IS_ERR(clk)) return dev_err_probe(dev, PTR_ERR(clk), "failed to get %s\n", - clk_names[i]); + name); } if (!clk) - dev_dbg(dev, "failed to get %s\n", clk_names[i]); + dev_dbg(dev, "failed to get %s\n", name); else - dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], + dev_dbg(dev, "clk %s is %pC rate %lu\n", name, clk, clk_get_rate(clk)); sci_port->clks[i] = clk; } @@ -3085,10 +3098,10 @@ static int sci_init_single(struct platform_device *dev, } /* - * The fourth interrupt on SCI port is transmit end interrupt, so + * The fourth interrupt on SCI and RSCI port is transmit end interrupt, so * shuffle the interrupts. */ - if (p->type == PORT_SCI) + if (p->type == PORT_SCI || p->type == SCI_PORT_RSCI) swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); /* The SCI generates several interrupts. They can be muxed together or @@ -3122,6 +3135,9 @@ static int sci_init_single(struct platform_device *dev, else sci_port->rx_trigger = 8; break; + case SCI_PORT_RSCI: + sci_port->rx_trigger = 15; + break; default: sci_port->rx_trigger = 1; break; @@ -3346,7 +3362,8 @@ static void sci_remove(struct platform_device *dev) if (s->port.fifosize > 1) device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); - if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) + if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF || + type == SCI_PORT_RSCI) device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); } @@ -3440,6 +3457,12 @@ static const struct of_device_id of_sci_match[] __maybe_unused = { .compatible = "renesas,scif-r9a09g057", .data = &of_sci_scif_rzv2h, }, +#ifdef CONFIG_SERIAL_RSCI + { + .compatible = "renesas,r9a09g077-rsci", + .data = &of_sci_r9a09g077_data, + }, +#endif /* CONFIG_SERIAL_RSCI */ /* Family-specific types */ { .compatible = "renesas,rcar-gen1-scif", @@ -3699,7 +3722,7 @@ static int sci_probe(struct platform_device *dev) return ret; } if (sp->type == PORT_SCIFA || sp->type == PORT_SCIFB || - sp->type == PORT_HSCIF) { + sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI) { ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); if (ret) { if (sp->port.fifosize > 1) {