From patchwork Wed Apr 30 11:34:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 886117 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A316E1DF25A; Wed, 30 Apr 2025 11:34:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746012891; cv=none; b=pvnWXCUtp7y+FO8lZttsAqSQT8Fhzb7Y1xGX2UurFJPYPFV5O2RXZty20tUQ4Wiu95fW+F/nfG+dx2r9x1BZUfbOV7g7XQCWgN3pw80f057IGl74KvYLKSzVKPyR/S6znMiQqIfoQJ5L3McfLDA4l2lpI1A33fDqK+t0x3GuUCo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746012891; c=relaxed/simple; bh=O8M7WlTxn8semPE2JzxaHompKC+iZ1DAro1Zycg0m6Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Vhb/Ph0Iy+QencJH2px1Nc3uyW3b81hKiSJ5fQ1j26grNvO37NkPSyUi5GfELWjN26iaazn0FZQfmXEorWdbUOlhy06ff0HdW41F/Y8c8aZ/b/4UP46IJ+NPqT2hYQRGHcEKFe153+Mi2vFv48J1eONW4arA7Izj6iBpY1mf/0U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KEHBdKra; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KEHBdKra" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 08411C4CEEA; Wed, 30 Apr 2025 11:34:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746012891; bh=O8M7WlTxn8semPE2JzxaHompKC+iZ1DAro1Zycg0m6Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=KEHBdKra2mXdkiVsTHlLO7tdShMTACqejTsHXrwqcP5ys+6FB9aWLs8Ns+VeiPNjV ZHPs4mKqI8wvJQZY7xhgE/ujmIdOBs04XGTxJv7mkCvgsiKeWLwERtKsChGhXSInUj TUFgNR2gUZ1alNWRC9f9RqmBJUHee3rdsgM5KEET6h+UdotVIQx8MssgPfDa6LV3cX gPU2orswpX6qGZqPV6qPk7xIVoqKFeb1Tf+PBUwMQzWGkkD29i9Uk+7789cHDH4Qos uEDTvah1XEL8kGppLKshZ3D72/3SqR0cebpudd5iwBeU1m4rCX05pY+F62OSbA7AuP CWBl/QjhWgzjg== From: Konrad Dybcio Date: Wed, 30 Apr 2025 13:34:35 +0200 Subject: [PATCH RFT v6 1/5] drm/msm/adreno: Implement SMEM-based speed bin Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250430-topic-smem_speedbin_respin-v6-1-954ff66061cf@oss.qualcomm.com> References: <20250430-topic-smem_speedbin_respin-v6-0-954ff66061cf@oss.qualcomm.com> In-Reply-To: <20250430-topic-smem_speedbin_respin-v6-0-954ff66061cf@oss.qualcomm.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746012880; l=6308; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=GTpsvdnL6p2ILmZWjIPbAA6NC+j9tLy6m3UjKescP3A=; b=ha8FpMoq9T4mmX3m9HNKeBMSSrWb2DbWZKxgNjfPFD2AdchprDESj6sTh8GT1F3XWPNmyxAxM JUM1GosfsezA1X2HZX1p+3kx3ceU5WAy9Z3e+VJAMkF1e0rdmCNBuBk X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is abstracted through SMEM, instead of being directly available in a fuse. Add support for SMEM-based speed binning, which includes getting "feature code" and "product code" from said source and parsing them to form something that lets us match OPPs against. Due to the product code being ignored in the context of Adreno on production parts (as of SM8650), hardcode it to SOCINFO_PC_UNKNOWN. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 +++++----- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 42 +++++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++++- 4 files changed, 54 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 242d02d48c0cd0972bb96a960872b73384fe043b..0db57e4b7596b01c091ed82510cf14cf2a8e0d03 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2328,18 +2328,20 @@ static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) return UINT_MAX; } -static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info) +static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu, + struct device *dev, + const struct adreno_info *info) { u32 supp_hw; u32 speedbin; int ret; - ret = adreno_read_speedbin(dev, &speedbin); + ret = adreno_read_speedbin(adreno_gpu, dev, &speedbin); /* - * -ENOENT means that the platform doesn't support speedbin which is - * fine + * -ENOENT/EOPNOTSUPP means that the platform doesn't support speedbin + * which is fine */ - if (ret == -ENOENT) { + if (ret == -ENOENT || ret == -EOPNOTSUPP) { return 0; } else if (ret) { dev_err_probe(dev, ret, @@ -2495,7 +2497,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); - ret = a6xx_set_supported_hw(&pdev->dev, config->info); + ret = a6xx_set_supported_hw(adreno_gpu, &pdev->dev, config->info); if (ret) { a6xx_llc_slices_destroy(a6xx_gpu); kfree(a6xx_gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 236b25c094cd5d462f4b6653de7b7910985cccb6..a8376574381abff90d4a56e86f3f05735027ca9f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -6,6 +6,8 @@ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. */ +#include + #include "adreno_gpu.h" bool hang_debug = false; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 26db1f4b5fb90930bdbd2f17682bf47e35870936..b0ec64e9a35591507f26e16b4ef60ec874dafe12 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -21,6 +21,9 @@ #include "msm_gem.h" #include "msm_mmu.h" +#include +#include + static u64 address_space_size = 0; MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space"); module_param(address_space_size, ullong, 0600); @@ -1090,9 +1093,40 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) adreno_ocmem->hdl); } -int adreno_read_speedbin(struct device *dev, u32 *speedbin) +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *fuse) { - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); + int ret; + + /* + * Try reading the speedbin via a nvmem cell first + * -ENOENT means "no nvmem-cells" and essentially means "old DT" or + * "nvmem fuse is irrelevant", simply assume it's fine. + */ + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", fuse); + if (!ret) + return 0; + else if (ret != -ENOENT) + return dev_err_probe(dev, ret, "Couldn't read the speed bin fuse value\n"); + +#ifdef CONFIG_QCOM_SMEM + u32 fcode; + + /* + * Only check the feature code - the product code only matters for + * proto SoCs unavailable outside Qualcomm labs, as far as GPU bin + * matching is concerned. + * + * Ignore EOPNOTSUPP, as not all SoCs expose this info through SMEM. + */ + ret = qcom_smem_get_feature_code(&fcode); + if (!ret) + *fuse = ADRENO_SKU_ID(fcode); + else if (ret != -EOPNOTSUPP) + return dev_err_probe(dev, ret, "Couldn't get feature code from SMEM\n"); +#endif + + return ret; } int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, @@ -1132,9 +1166,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) + if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin) speedbin = 0xffff; - adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); + adreno_gpu->speedbin = speedbin; gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 92caba3584da0400b44a903e465814af165d40a3..3946b9e992b9a8e2fd81f3e03354f9f83717b270 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -80,6 +80,10 @@ struct adreno_reglist { struct adreno_speedbin { uint16_t fuse; +/* As of SM8650, PCODE on production SoCs is meaningless wrt the GPU bin */ +#define ADRENO_SKU_ID_FCODE GENMASK(15, 0) +#define ADRENO_SKU_ID(fcode) (fcode) + uint16_t speedbin; }; @@ -634,7 +638,8 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, struct adreno_smmu_fault_info *info, const char *block, u32 scratch[4]); -int adreno_read_speedbin(struct device *dev, u32 *speedbin); +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *speedbin); /* * For a5xx and a6xx targets load the zap shader that is used to pull the GPU From patchwork Wed Apr 30 11:34:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 886519 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8F7D231829; Wed, 30 Apr 2025 11:34:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746012897; cv=none; b=a63E8R74Ls6yJCeZdRghqKmA1MK/VIE1F2gL1aZ+3FKXQzG7cmRmxPDq+2p+HxwRfa7uEMoFxJH3Fj1rEs2V+ldpP/cQam5J7DjcFyegj1aWAGdbQA+wGzMobx5loReIGnPD0ZoTeqvVRE0LZHaJm591GW4MQUfBVGSg+TFx+fk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746012897; c=relaxed/simple; bh=nvHCaF8qd9Kc8urkFp5so4scjDxpMQByuGnGWBLb67k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MgAPgS16ERnlsFzJMwIe+jOJT4vNBDmahwEjfJ4JSDjgPoTQhbytmU3TlOPa4z0ylxe1Ao1DRQem5+yLlzFp/NITVVuDlxP5vR7vEMZjpO9TBMmpPVS5nk0hBxqeQ5yvB6+B5MH1CFITBFIS30rv2zMq1nZkATBgLvk/IQHQ8EU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l2uojk/Q; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l2uojk/Q" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A987BC4CEE9; Wed, 30 Apr 2025 11:34:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746012896; bh=nvHCaF8qd9Kc8urkFp5so4scjDxpMQByuGnGWBLb67k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=l2uojk/Q7MsywuGQVGi82QAaos+ZqzmRniiGEdY0lUTIZ1DYWGiOlgO/ZhG6XPD1y WETk+G3QTw+NSC8kPH20jlxWQORBqk6Tj7awrCbevWXx1NZdBU3oUnu2KQMqRagty8 jHHC9bf66hGPvvZq6K7LuVMj0kAWrOkx6+O9a1IU+iFIxB4p4GkWus9SnRG7+G4VlT kmB8PZqicZGWW2U5TJyXifRH/kp7LkJSPpM3MKvoT/YnOCnQwnvwoV84FZ2ea6FP5r nKc09AQm/dbR4VJhDlW1AkHSkErpM9JhKzoCzDpjF9acKOxnGi6uUe5GuFUV6Dopyr SbJCqv4R/bUeA== From: Konrad Dybcio Date: Wed, 30 Apr 2025 13:34:36 +0200 Subject: [PATCH RFT v6 2/5] drm/msm/adreno: Add speedbin data for SM8550 / A740 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250430-topic-smem_speedbin_respin-v6-2-954ff66061cf@oss.qualcomm.com> References: <20250430-topic-smem_speedbin_respin-v6-0-954ff66061cf@oss.qualcomm.com> In-Reply-To: <20250430-topic-smem_speedbin_respin-v6-0-954ff66061cf@oss.qualcomm.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746012880; l=1547; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=s8amPV021nvmCFk5BsbFzQEAO5l0wK8PePLGYxCymEg=; b=M20YHKO9vKas3G0+FGjEatcTaoRgXamQ47q1mgVoAIrR1hBspD5dxyYSRUOY7LHw/IwqxcR1Q BEc6YmTSBfYDyTIpfQOZaoZ+Yh7h5YNXLdR3awkflU6Ix2++3c1mdih X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Add speebin data for A740, as found on SM8550 and derivative SoCs. For non-development SoCs it seems that "everything except FC_AC, FC_AF should be speedbin 1", but what the values are for said "everything" are not known, so that's an exercise left to the user.. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 53e2ff4406d8f0afe474aaafbf0e459ef8f4577d..61daa331567925e529deae5e25d6fb63a8ba8375 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -11,6 +11,9 @@ #include "a6xx.xml.h" #include "a6xx_gmu.xml.h" +#include +#include + static const struct adreno_reglist a612_hwcg[] = { {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, @@ -1431,6 +1434,11 @@ static const struct adreno_info a7xx_gpus[] = { }, .address_space_size = SZ_16G, .preempt_record_size = 4192 * SZ_1K, + .speedbins = ADRENO_SPEEDBINS( + { ADRENO_SKU_ID(SOCINFO_FC_AC), 0 }, + { ADRENO_SKU_ID(SOCINFO_FC_AF), 0 }, + /* Other feature codes (on prod SoCs) should match to speedbin 1 */ + ), }, { .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ .family = ADRENO_7XX_GEN2, From patchwork Wed Apr 30 11:34:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 886116 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09975231829; Wed, 30 Apr 2025 11:35:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746012902; cv=none; b=iF4nVJceBLW05gG6EQX0vJApgrdx1Hhyc67jQSv3mM7GlFTFBk0sN9DrmQorwpWrfWFV1ogcTcxj+1pwpNqZMbvFTxll25Llh4LABQmDSsn6M1XuGcgbTGq4t58A/OduWH6eXivNURbYvsxsbZMEGYPa1dlb1uN9PZolVTfjRc4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746012902; c=relaxed/simple; bh=yyD1cbb+bkMR/9YU0BHBwauoxKa4CcRYXmN3iuWr+yM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TagKUtXs3EjoqphZ9OQnEjDDivQnDgKAaNVRvh8cM9snnEjXcXHfWhMgWBmHkIFF/gzBXG+Ss3Ad2RLMQieaurR7mt/OynmXB7dUidkIf1ntiSdqFMnJWEKsRaVQjQHywSR7KYu82DxTHPhjb6DuizLSwRdlpFqzFy938QfZJF4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qebHaRJ7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qebHaRJ7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 04A3BC4CEED; Wed, 30 Apr 2025 11:34:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746012901; bh=yyD1cbb+bkMR/9YU0BHBwauoxKa4CcRYXmN3iuWr+yM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qebHaRJ7B3N2Wk6Z3WdDcWwCYaytcEDoHEg5eamGne/foQKk3GWCOSkrmk6wv5wt4 pEtQEyz/F5rahR+lkuO6+K2QwVRoXThlSBzIj86ysnsjE+it1sTJYyo9M9PF6ak11f Mz+5UpIYPNwoUcbtoS05GcGLciOEL6Ntd927LZP+MNQ2YNlWfGBbRwqQsxY+5zlfzo Q8VD+eFikcPlLNHtuM56W+77zqjYbydtJEEAbFLB5DUUGwsb+wgXMQcPz381Fuz9NC 1lw1BPkCJsO7ZhDlrlwZmhIrUgr+7VtHM+Wj6S07ScemXpyfk7/njcuSQZgldjOjJg 1cy2rGy2cxTZg== From: Konrad Dybcio Date: Wed, 30 Apr 2025 13:34:37 +0200 Subject: [PATCH RFT v6 3/5] drm/msm/adreno: Define A530 speed bins explicitly Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250430-topic-smem_speedbin_respin-v6-3-954ff66061cf@oss.qualcomm.com> References: <20250430-topic-smem_speedbin_respin-v6-0-954ff66061cf@oss.qualcomm.com> In-Reply-To: <20250430-topic-smem_speedbin_respin-v6-0-954ff66061cf@oss.qualcomm.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746012880; l=930; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=vdqNF+6quxj2StOOTX7jH5Xg/VFIUIIQYh+43Msf0f4=; b=yj0jAj72kXnPsZI/W9i3P4rFmZ/2Sk6iFwiOZV6jRdaNjCicAgyvTKpUA9rCQpPi9PvfP29H1 Iq85Tsqq16qAsw2qhb5cjXD4gVVrspx6gKwKmTlbLO0JPif9GxF3ZdA X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio In preparation for commonizing the speedbin handling code. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c index 633f3153916277b34f90acc046ed2ee04a761727..105b3d14bd7592c784863346cfbcc28f000c2e8f 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c @@ -129,6 +129,12 @@ static const struct adreno_info a5xx_gpus[] = { ADRENO_QUIRK_FAULT_DETECT_MASK, .init = a5xx_gpu_init, .zapfw = "a530_zap.mdt", + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 1, 1 }, + { 2, 2 }, + { 3, 3 }, + ), }, { .chip_ids = ADRENO_CHIP_IDS(0x05040001), .family = ADRENO_5XX, From patchwork Wed Apr 30 11:34:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 886518 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC5E3254859; Wed, 30 Apr 2025 11:35:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746012906; cv=none; b=aYuGqn86Du7uqZFuDanb9g709gyQXk3/tuMe7N5TYUSakqZI153cUfq9U766A9STFfasAT57Pvufdrubv/g2TpahplZA0ikatJLn8jzxYMMDGdakw7Fpv/OZJQGKiORzFI0/GQOlOmqEtftxI5beXGeIz/kpJPilfuvd1c2Wugo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746012906; c=relaxed/simple; bh=LHZnKYex6dp3WNbtjSac96l2EBFyL8TSY4xUGq1SAvE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ckeveaFQHXExxoLfywGdxj+sBDX8DEXYgfO276v4cV0O9C25KTvrH2PBDiMas3KoELtZSBS3SkgCPPwRohtrD8LvAV+A0XgNP/t0XDpMcILYroFAhDO/J51DTHnS1YpMHeLenLlMSnUAMzln1oTyPi2k+DV4mnm+ScoXT71tZAI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XRG4QgrY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XRG4QgrY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EFBD7C4CEE9; Wed, 30 Apr 2025 11:35:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746012906; bh=LHZnKYex6dp3WNbtjSac96l2EBFyL8TSY4xUGq1SAvE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=XRG4QgrYDDqy2pyDvrZxUwkD2x99Mj+xkFm1HRm0bmEc6G35MIYIz24JTtRezUGIi id0/QZUCUlucs5RyR+S4U37jeIAG5nS8d98xxXjXANsGxNhQXKw2B7EU1ydlQINj3D opfrK7uzyZ4UuewCMOiqnzp0q+hTtMbuFLuhO6tunU/ElLwbIbNEmVAZ+tddKWAUSo F20k4Nosu9pQR+4Qry4JtBqUbzF/Sh8315BU42CuLoWcCFc42yH+eGA8pWVy/Bb8eh bmFYDNfJ9aTifXXoEb+EGYj1P53OpBc8MgDvKzLqrUWJ5TER6k7Cxkp81ZqLaVzToI BxWv/nNE946vQ== From: Konrad Dybcio Date: Wed, 30 Apr 2025 13:34:38 +0200 Subject: [PATCH RFT v6 4/5] drm/msm/adreno: Redo the speedbin assignment Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250430-topic-smem_speedbin_respin-v6-4-954ff66061cf@oss.qualcomm.com> References: <20250430-topic-smem_speedbin_respin-v6-0-954ff66061cf@oss.qualcomm.com> In-Reply-To: <20250430-topic-smem_speedbin_respin-v6-0-954ff66061cf@oss.qualcomm.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746012880; l=9709; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=MXMEfrafFdHw21/4rMFRCNuIKP/bMWP/Sji0DMRotDc=; b=pjpXsv2BUAU2H/AP19P8nny7lZqF5RVQ0EZQ6U2rswYLsvgGs8SAXFqcR8+nzR7T9CgKjlrhE FENSo/J/LbqAcOxQGmDRbwM+0cb9RogKH3cljoCqLl+OVFngF0N1ns3 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio There is no need to reinvent the wheel for simple read-match-set logic. Make speedbin discovery and assignment generation independent. This implicitly removes the bogus 0x80 / BIT(7) speed bin on A5xx, which has no representation in hardware whatshowever. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 34 -------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 56 ----------------------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 81 +++++++++++++++++++++++++++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 -- 4 files changed, 71 insertions(+), 103 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 650e5bac225f372e819130b891f1d020b464f17f..7b9e4292ff53aa608244525063577baae0314abd 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1717,38 +1717,6 @@ static const struct adreno_gpu_funcs funcs = { .get_timestamp = a5xx_get_timestamp, }; -static void check_speed_bin(struct device *dev) -{ - struct nvmem_cell *cell; - u32 val; - - /* - * If the OPP table specifies a opp-supported-hw property then we have - * to set something with dev_pm_opp_set_supported_hw() or the table - * doesn't get populated so pick an arbitrary value that should - * ensure the default frequencies are selected but not conflict with any - * actual bins - */ - val = 0x80; - - cell = nvmem_cell_get(dev, "speed_bin"); - - if (!IS_ERR(cell)) { - void *buf = nvmem_cell_read(cell, NULL); - - if (!IS_ERR(buf)) { - u8 bin = *((u8 *) buf); - - val = (1 << bin); - kfree(buf); - } - - nvmem_cell_put(cell); - } - - devm_pm_opp_set_supported_hw(dev, &val, 1); -} - struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) { struct msm_drm_private *priv = dev->dev_private; @@ -1771,8 +1739,6 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) a5xx_gpu->lm_leakage = 0x4E001A; - check_speed_bin(&pdev->dev); - nr_rings = 4; if (config->info->revn == 510) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 0db57e4b7596b01c091ed82510cf14cf2a8e0d03..ac6a8acceffc5b5ea0262c8ba49d5774f03894d8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2316,55 +2316,6 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return progress; } -static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) -{ - if (!info->speedbins) - return UINT_MAX; - - for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) - if (info->speedbins[i].fuse == fuse) - return BIT(info->speedbins[i].speedbin); - - return UINT_MAX; -} - -static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu, - struct device *dev, - const struct adreno_info *info) -{ - u32 supp_hw; - u32 speedbin; - int ret; - - ret = adreno_read_speedbin(adreno_gpu, dev, &speedbin); - /* - * -ENOENT/EOPNOTSUPP means that the platform doesn't support speedbin - * which is fine - */ - if (ret == -ENOENT || ret == -EOPNOTSUPP) { - return 0; - } else if (ret) { - dev_err_probe(dev, ret, - "failed to read speed-bin. Some OPPs may not be supported by hardware\n"); - return ret; - } - - supp_hw = fuse_to_supp_hw(info, speedbin); - - if (supp_hw == UINT_MAX) { - DRM_DEV_ERROR(dev, - "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", - speedbin); - supp_hw = BIT(0); /* Default */ - } - - ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); - if (ret) - return ret; - - return 0; -} - static const struct adreno_gpu_funcs funcs = { .base = { .get_param = adreno_get_param, @@ -2497,13 +2448,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); - ret = a6xx_set_supported_hw(adreno_gpu, &pdev->dev, config->info); - if (ret) { - a6xx_llc_slices_destroy(a6xx_gpu); - kfree(a6xx_gpu); - return ERR_PTR(ret); - } - if ((enable_preemption == 1) || (enable_preemption == -1 && (config->info->quirks & ADRENO_QUIRK_PREEMPTION))) ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index b0ec64e9a35591507f26e16b4ef60ec874dafe12..339e210db06398eae88f425574e684ea5b5ad68b 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1093,13 +1093,13 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) adreno_ocmem->hdl); } -int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, - struct device *dev, u32 *fuse) +static int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *fuse) { int ret; /* - * Try reading the speedbin via a nvmem cell first + * Try reading the speedbin via a nvmem cell first. * -ENOENT means "no nvmem-cells" and essentially means "old DT" or * "nvmem fuse is irrelevant", simply assume it's fine. */ @@ -1114,8 +1114,7 @@ int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, /* * Only check the feature code - the product code only matters for - * proto SoCs unavailable outside Qualcomm labs, as far as GPU bin - * matching is concerned. + * prototype SoCs, as far as GPU bin matching is concerned. * * Ignore EOPNOTSUPP, as not all SoCs expose this info through SMEM. */ @@ -1126,7 +1125,70 @@ int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, return dev_err_probe(dev, ret, "Couldn't get feature code from SMEM\n"); #endif - return ret; + return 0; +} + +#define ADRENO_SPEEDBIN_FUSE_NODATA 0xFFFF /* Made-up large value, expected by mesa */ +static int adreno_set_speedbin(struct adreno_gpu *adreno_gpu, struct device *dev) +{ + const struct adreno_info *info = adreno_gpu->info; + u32 fuse = ADRENO_SPEEDBIN_FUSE_NODATA; + u32 supp_hw = UINT_MAX; + int ret; + + /* No speedbins defined for this GPU SKU => allow all defined OPPs. */ + if (!info->speedbins) { + /* + * Due to OPP framework's safety assumptions, the speedbin data + * must be defined either in both the driver catalog and DT, or + * in neither. + * + * This means that having a too old DT (with no opp-supported-hw) + * or a "too new" one (with opp-supported-hw, but the kernel not + * having the fuse matching tables) becomes a problem. + * + * We can only work around one of these at a time, so choose the + * more real issue of outdated DT and skip setting compatibility + * constraints so as not to trip off any alarms in _opp_is_supported() + */ + adreno_gpu->speedbin = ADRENO_SPEEDBIN_FUSE_NODATA; + + return 0; + } + + /* + * If a real error (not counting older devicetrees having no nvmem references) + * occurs when trying to get the fuse value, bail out. + */ + ret = adreno_read_speedbin(adreno_gpu, dev, &fuse); + if (ret) { + return ret; + } else if (fuse == ADRENO_SPEEDBIN_FUSE_NODATA) { + /* The info struct has speedbin data, but the DT doesn't => allow all OPPs */ + DRM_DEV_INFO(dev, "No GPU speed bin fuse, please update your device tree\n"); + + /* + * In this case, the DT doesn't point us to speedbin info. + * We can then assume the opp-supported-hw properties are missing as well, + * as having one in place but not the other would be rather invalid anyway. + * + * We're not calling set_supported_hw(ALLOW_ALL_OPPS) here, as OPP APIs + * would then still expect opp-supported-hw, which we may lack + */ + return 0; + } + + adreno_gpu->speedbin = fuse; + + /* Traverse the known speedbins */ + for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) { + if (info->speedbins[i].fuse == fuse) { + supp_hw = BIT(info->speedbins[i].speedbin); + return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + } + } + + return dev_err_probe(dev, -EINVAL, "Unknown speed bin fuse value: 0x%x\n", fuse); } int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, @@ -1138,7 +1200,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct msm_gpu_config adreno_gpu_config = { 0 }; struct msm_gpu *gpu = &adreno_gpu->base; const char *gpu_name; - u32 speedbin; int ret; adreno_gpu->funcs = funcs; @@ -1166,9 +1227,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } - if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin) - speedbin = 0xffff; - adreno_gpu->speedbin = speedbin; + ret = adreno_set_speedbin(adreno_gpu, dev); + if (ret) + return ret; gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 3946b9e992b9a8e2fd81f3e03354f9f83717b270..bc46ed5608cd3f5c05142826a03b97d5cdab9eff 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -638,9 +638,6 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, struct adreno_smmu_fault_info *info, const char *block, u32 scratch[4]); -int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, - struct device *dev, u32 *speedbin); - /* * For a5xx and a6xx targets load the zap shader that is used to pull the GPU * out of secure mode From patchwork Wed Apr 30 11:34:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 886115 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51F0F254859; Wed, 30 Apr 2025 11:35:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746012911; cv=none; b=IiNVRL5Sk8pCO4XzRIPvprWAy8cyf/FFJjF1zecLuUyb34mB11RLyb4Uj5vZyC5CjdLhJfa1iqrdjXFUa4oqH+a2Xgbd3j/xsVI5J6X3CVZQU3lCK8GRJZzfOP8MuG5/0ESGGwQBAvaurJnm1kkF7Na0OB2JIbaBbwGh1S6YpU4= ARC-Message-Signature: i=1; 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b=uOC5hoDdv1oVbIrUlBwvXtLsNiQP1ThurUJnZMx16hFnXEtarn3vRcpJ0PcoRqwk8 eh98LgxlcGp++SDJAbfVMrNzuBnivlni8I1EF49ma+Dk2+Pilywj+qv8Ml/ekHzyqy 4/i67Mz4SAO2YclNxltUEYXW7S0/s5HxNlMr/5VP3XokpFmsiSnrYtt4OVY5x+g/f4 C6LXW39rb1Il8U+GUTHIjKTCCfaVRB4VeMC3nVDQXXPSAcnCshRyp7Nq1CkEozzfkU wOdJJ5XeEb8gmyiX46/FCxXf9oESN5SoLcUj49S2kIXRdqeqqNsQAlElLUY7z3smGJ YIuLk5HbndeUg== From: Konrad Dybcio Date: Wed, 30 Apr 2025 13:34:39 +0200 Subject: [PATCH RFT v6 5/5] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250430-topic-smem_speedbin_respin-v6-5-954ff66061cf@oss.qualcomm.com> References: <20250430-topic-smem_speedbin_respin-v6-0-954ff66061cf@oss.qualcomm.com> In-Reply-To: <20250430-topic-smem_speedbin_respin-v6-0-954ff66061cf@oss.qualcomm.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746012880; l=2805; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=V5Mdu0t8s6038X7jL5bKI4EfIFMP3ptl8Yd+DlwLKYE=; b=qQPJUvYTMPHisX1M2G+D+OwLnJrCPingfSYcdKAquSYG4Dk0Pxh4UMXz1M4HdBGf040+bv+JQ ioqGLG89BISDiC0IpLS48BEOQOLHyImC2YQYk4dNcQhxtkjRB63FJxh X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Add the speedbin masks to ensure only the desired OPPs are available on chips of a given bin. Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 82cabf777cd2c1dc87457aeede913873e7322ec2..1c006879bbfe01d7b20e6fab620affb61e31ecec 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2460,56 +2460,75 @@ zap-shader { memory-region = <&gpu_micro_code_mem>; }; - /* Speedbin needs more work on A740+, keep only lower freqs */ gpu_opp_table: opp-table { compatible = "operating-points-v2"; + opp-719000000 { + opp-hz = /bits/ 64 <719000000>; + opp-level = ; + opp-supported-hw = <0x1>; + }; + opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; opp-peak-kBps = <16500000>; + opp-supported-hw = <0x3>; }; opp-615000000 { opp-hz = /bits/ 64 <615000000>; opp-level = ; opp-peak-kBps = <12449218>; + opp-supported-hw = <0x3>; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-level = ; opp-peak-kBps = <10687500>; + opp-supported-hw = <0x3>; }; opp-475000000 { opp-hz = /bits/ 64 <475000000>; opp-level = ; opp-peak-kBps = <6074218>; + opp-supported-hw = <0x3>; }; opp-401000000 { opp-hz = /bits/ 64 <401000000>; opp-level = ; opp-peak-kBps = <6074218>; + opp-supported-hw = <0x3>; }; opp-348000000 { opp-hz = /bits/ 64 <348000000>; opp-level = ; opp-peak-kBps = <6074218>; + opp-supported-hw = <0x3>; }; opp-295000000 { opp-hz = /bits/ 64 <295000000>; opp-level = ; opp-peak-kBps = <6074218>; + opp-supported-hw = <0x3>; }; opp-220000000 { opp-hz = /bits/ 64 <220000000>; opp-level = ; opp-peak-kBps = <2136718>; + opp-supported-hw = <0x3>; + }; + + opp-124800000 { + opp-hz = /bits/ 64 <124800000>; + opp-level = ; + opp-supported-hw = <0x3>; }; }; };