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Fri, 2 May 2025 17:14:47 GMT Received: from hu-ptalari-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 2 May 2025 10:14:41 -0700 From: Praveen Talari To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , "Praveen Talari" , , , , CC: , , , , , , , Nikunj Kela Subject: [PATCH v4 1/8] dt-bindings: serial: describe SA8255p Date: Fri, 2 May 2025 22:44:10 +0530 Message-ID: <20250502171417.28856-2-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502171417.28856-1-quic_ptalari@quicinc.com> References: <20250502171417.28856-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=B7i50PtM c=1 sm=1 tr=0 ts=6814fd88 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=gEfo2CItAAAA:8 a=COk6AnOGAAAA:8 a=rjx3OjMNV77wTL7fGyAA:9 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: qEr_DxgS4bC3VoQJcMpR2Njni7V0Rs5V X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDEzNyBTYWx0ZWRfX8sOQA38KLIcJ k3oWqSGM98JXlO3DsicTiNDMVmw1lseQqg0QjqokRfRW87QCpdQRi9cpnCMSwQerhm4WXsfOp4o /c9CsPEG91oTIMCjn+hdH7uK3IyQLbzMAQOuEGUpWjfpCKlsRCf9i4nJpoh9xssJJ/l7h3QR5Rj O9zmWcsmsn4bHk430DNnKW1ZtIKhUjj6mgKo7woD0Y8IYEfOCaMYLVztaTyt6zozIs/e9su1Lbu JU9kriD9NY0Xaa2K6lgGL4uCphynkLxXUkBvr5P61qwzdQFe4bxQdkc0Qt1B7OkXJ0I+kwAz4vF 3OzCB/nAKAtQD8oCp+3E+g6Lsipb2Bgw7lvojTBVB8X0vSNHhsWiBYI1VLCKAJ4AzX+/CzgX4F5 /TpAMVHpY/2epRmPDMBJTTKPr5PauLL3VhAl8URIh4eF1fEdkLIQkDXUg6jYF9z0fvyJFsuX X-Proofpoint-ORIG-GUID: qEr_DxgS4bC3VoQJcMpR2Njni7V0Rs5V X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-02_03,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 spamscore=0 clxscore=1015 mlxscore=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020137 From: Nikunj Kela SA8255p platform abstracts resources such as clocks, interconnect and GPIO pins configuration in Firmware. SCMI power and perf protocols are used to send request for resource configurations. Add DT bindings for the QUP GENI UART controller on sa8255p platform. Signed-off-by: Nikunj Kela Co-developed-by: Praveen Talari Signed-off-by: Praveen Talari --- v3 -> v4 - added version log after --- v2 -> v3 - dropped description for interrupt-names - rebased reg property order in required option v1 -> v2 - reorder sequence of tags in commit text - moved reg property after compatible field - added interrupt-names property --- .../serial/qcom,sa8255p-geni-uart.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml diff --git a/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml b/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml new file mode 100644 index 000000000000..85b1d7c05079 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/qcom,sa8255p-geni-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Geni based QUP UART interface + +maintainers: + - Praveen Talari + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + enum: + - qcom,sa8255p-geni-uart + - qcom,sa8255p-geni-debug-uart + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + items: + - description: UART core irq + - description: Wakeup irq (RX GPIO) + + interrupt-names: + items: + - const: uart + - const: wakeup + + power-domains: + minItems: 2 + maxItems: 2 + + power-domain-names: + items: + - const: power + - const: perf + +required: + - compatible + - reg + - interrupts + - power-domains + - power-domain-names + +unevaluatedProperties: false + +examples: + - | + #include + + serial@990000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x990000 0x4000>; + interrupts = ; + power-domains = <&scmi0_pd 0>, <&scmi0_dvfs 0>; + power-domain-names = "power", "perf"; + }; +... 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Fri, 2 May 2025 17:14:54 GMT Received: from hu-ptalari-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 2 May 2025 10:14:48 -0700 From: Praveen Talari To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , "Praveen Talari" , , , , CC: , , , , , , , Nikunj Kela Subject: [PATCH v4 2/8] dt-bindings: qcom: geni-se: describe SA8255p Date: Fri, 2 May 2025 22:44:11 +0530 Message-ID: <20250502171417.28856-3-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502171417.28856-1-quic_ptalari@quicinc.com> References: <20250502171417.28856-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=B7i50PtM c=1 sm=1 tr=0 ts=6814fd8e cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=gEfo2CItAAAA:8 a=COk6AnOGAAAA:8 a=v7CWcBsnNxNFVLN3aFYA:9 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: llfo7IG0QeNlvBj24nDnV2wxLsZWhVMy X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDEzNyBTYWx0ZWRfX0mi+qGDDJpdv LeY+yt4cE93+4qyGK8+x7tV3l0fO+QsouoLPJ5PLu7E3V0M4RHaqaVUpI6Ogxp6wK+jADazKGEj iOrxJNNxdgXH0DnT9HQxlWlV/FgYBRcIvWgJ3Q0xJMzgx7Wmqpt0LQmIxX8aeii0EERIqXWSVsB KpNLRYQ3KNjd2KmvsWn3A6ZXX3/gkUz6B56T2viculp4bWaOzGlPlqxmpABc/qUuiCrtZLmNUZg v0pWtE8R19I4t5WKbKj06HicbIiT9zjfNYc10oHKJ6OOsu0L0VrE6jYugnGuJHO7rbUKAW4470p NxNNHnMmIUYdF51UNd1uQ/E8kJYd1Dc4c8dNDMGgDtqH1yyKW3VqaU1VDfgJBcRiNbM4XkpJQkx yGrY4hd6oe0NmawbJKJpP7UqmX9cp6bBU/dpKH0jl8KHZmrLsZLYoCnUzGDI/UaMNM5UyqQ7 X-Proofpoint-ORIG-GUID: llfo7IG0QeNlvBj24nDnV2wxLsZWhVMy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-02_03,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 spamscore=0 clxscore=1015 mlxscore=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020137 From: Nikunj Kela SA8255p platform abstracts resources such as clocks, interconnect configuration in Firmware. Add DT bindings for the QUP Wrapper on sa8255p platform. Signed-off-by: Nikunj Kela Co-developed-by: Praveen Talari Signed-off-by: Praveen Talari Reviewed-by: Krzysztof Kozlowski --- v3 -> v4 - reordered required: after properties and patternproperties - added version log after --- v2 -> v3 - reordered required option v1 -> v2 - reorder sequence of tags in commit text - resolved waring errors while encountered in dt binding and dtb check. --- .../soc/qcom/qcom,sa8255p-geni-se-qup.yaml | 107 ++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml new file mode 100644 index 000000000000..352af3426d34 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,sa8255p-geni-se-qup.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GENI Serial Engine QUP Wrapper Controller + +maintainers: + - Praveen Talari + +description: + Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper + is a programmable module for supporting a wide range of serial interfaces + like UART, SPI, I2C, I3C, etc. A single QUP module can provide up to 8 Serial + Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP + Wrapper controller is modeled as a node with zero or more child nodes each + representing a serial engine. + +properties: + compatible: + const: qcom,sa8255p-geni-se-qup + + reg: + description: QUP wrapper common register address and length. + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + iommus: + maxItems: 1 + + dma-coherent: true + +patternProperties: + "spi@[0-9a-f]+$": + type: object + description: GENI serial engine based SPI controller. SPI in master mode + supports up to 50MHz, up to four chip selects, programmable + data path from 4 bits to 32 bits and numerous protocol + variants. + additionalProperties: true + + properties: + compatible: + const: qcom,sa8255p-geni-spi + + "i2c@[0-9a-f]+$": + type: object + description: GENI serial engine based I2C controller. + additionalProperties: true + + properties: + compatible: + const: qcom,sa8255p-geni-i2c + + "serial@[0-9a-f]+$": + type: object + description: GENI Serial Engine based UART Controller. + additionalProperties: true + + properties: + compatible: + enum: + - qcom,sa8255p-geni-uart + - qcom,sa8255p-geni-debug-uart + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + geniqup@9c0000 { + compatible = "qcom,sa8255p-geni-se-qup"; + reg = <0 0x9c0000 0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + serial@990000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0 0x990000 0 0x4000>; + interrupts = ; + power-domains = <&scmi0_pd 0>, <&scmi0_dvfs 0>; + power-domain-names = "power", "perf"; + }; + }; + }; +... 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Fri, 2 May 2025 17:15:00 GMT Received: from hu-ptalari-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 2 May 2025 10:14:55 -0700 From: Praveen Talari To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , "Praveen Talari" , , , , CC: , , , , , , Subject: [PATCH v4 3/8] soc: qcom: geni-se: Enable QUPs on SA8255p Qualcomm platforms Date: Fri, 2 May 2025 22:44:12 +0530 Message-ID: <20250502171417.28856-4-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502171417.28856-1-quic_ptalari@quicinc.com> References: <20250502171417.28856-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: g3Sq3OYFDHJCsgnk28FLNb8vvkxdPgqT X-Authority-Analysis: v=2.4 cv=bsxMBFai c=1 sm=1 tr=0 ts=6814fd95 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=-8ewQQW4l5uToJikuzQA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDEzNyBTYWx0ZWRfX6CzH+WMwB21q MpsyiXPS8KpKUP1UloG6IPPvy3RNxONTBxaxWuk2OnkP63DhH9Ys10zc/PlJx9JpaNXss5hydzr iww3/b0KC5WbhIi3W/I4DhWs/ylty/mYuRbaq4l7FNRJFdS9CVK5bGi/9Hu+L3p8CcKu3Ycp13K /tVzhOtpLevxZy9zKTyPlC3S+hGDcQhOjGxkgV9yRhYI2mvZZwAv8GzpEGm6RiAMXDeydj3rqhx W6gT0rGsPNSI0+h+iYW5Ru0GTPmqAPNaDL3FQL7Oj7IXL6dQ4+hGZy8kW3KxN3Pm3SlfD24duGL c2JqeajTBAM8Q0ZP1l8z94y6aZXvPC3frmUyCCHl0DfVXG6uFzjLNaAdBOXXaqsVjdS617Bj/P/ CK9BsH4FKdiMqWU5M02SjYh7q/bC0KLkZBHVE0bGuQ6usae5FdYXrDUjyhYtLPsNsvpRM0Fy X-Proofpoint-ORIG-GUID: g3Sq3OYFDHJCsgnk28FLNb8vvkxdPgqT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-02_03,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 bulkscore=0 suspectscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020137 On the sa8255p platform, resources such as clocks,interconnects and TLMM (GPIO) configurations are managed by firmware. Introduce a platform data function callback to distinguish whether resource control is performed by firmware or directly by the driver in linux. The refactor ensures clear differentiation of resource management mechanisms, improving maintainability and flexibility in handling platform-specific configurations. Signed-off-by: Praveen Talari --- v3 -> v4 - declared an empty struct for sa8255p and added check as num clks. - Added version log after --- v1 -> v2 - changed datatype of i from int to unsigned int as per comment. --- drivers/soc/qcom/qcom-geni-se.c | 73 ++++++++++++++++++++------------- 1 file changed, 45 insertions(+), 28 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 4cb959106efa..b6e90bac55fe 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -105,6 +105,8 @@ struct geni_wrapper { struct geni_se_desc { unsigned int num_clks; const char * const *clks; + int (*geni_se_rsc_init)(struct geni_wrapper *wrapper, + const struct geni_se_desc *desc); }; static const char * const icc_path_names[] = {"qup-core", "qup-config", @@ -891,10 +893,44 @@ int geni_icc_disable(struct geni_se *se) } EXPORT_SYMBOL_GPL(geni_icc_disable); +static int geni_se_resource_init(struct geni_wrapper *wrapper, + const struct geni_se_desc *desc) +{ + struct device *dev = wrapper->dev; + int ret; + unsigned int i; + + wrapper->num_clks = min_t(unsigned int, desc->num_clks, MAX_CLKS); + + for (i = 0; i < wrapper->num_clks; ++i) + wrapper->clks[i].id = desc->clks[i]; + + ret = of_count_phandle_with_args(dev->of_node, "clocks", "#clock-cells"); + if (ret < 0) { + dev_err(dev, "invalid clocks property at %pOF\n", dev->of_node); + return ret; + } + + if (ret < wrapper->num_clks) { + dev_err(dev, "invalid clocks count at %pOF, expected %d entries\n", + dev->of_node, wrapper->num_clks); + return -EINVAL; + } + + ret = devm_clk_bulk_get(dev, wrapper->num_clks, wrapper->clks); + if (ret) { + dev_err(dev, "Err getting clks %d\n", ret); + return ret; + } + + return ret; +} + static int geni_se_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct geni_wrapper *wrapper; + const struct geni_se_desc *desc; int ret; wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL); @@ -906,36 +942,12 @@ static int geni_se_probe(struct platform_device *pdev) if (IS_ERR(wrapper->base)) return PTR_ERR(wrapper->base); - if (!has_acpi_companion(&pdev->dev)) { - const struct geni_se_desc *desc; - int i; + desc = device_get_match_data(&pdev->dev); - desc = device_get_match_data(&pdev->dev); - if (!desc) + if (!has_acpi_companion(&pdev->dev) && desc->num_clks) { + ret = desc->geni_se_rsc_init(wrapper, desc); + if (ret) return -EINVAL; - - wrapper->num_clks = min_t(unsigned int, desc->num_clks, MAX_CLKS); - - for (i = 0; i < wrapper->num_clks; ++i) - wrapper->clks[i].id = desc->clks[i]; - - ret = of_count_phandle_with_args(dev->of_node, "clocks", "#clock-cells"); - if (ret < 0) { - dev_err(dev, "invalid clocks property at %pOF\n", dev->of_node); - return ret; - } - - if (ret < wrapper->num_clks) { - dev_err(dev, "invalid clocks count at %pOF, expected %d entries\n", - dev->of_node, wrapper->num_clks); - return -EINVAL; - } - - ret = devm_clk_bulk_get(dev, wrapper->num_clks, wrapper->clks); - if (ret) { - dev_err(dev, "Err getting clks %d\n", ret); - return ret; - } } dev_set_drvdata(dev, wrapper); @@ -951,8 +963,11 @@ static const char * const qup_clks[] = { static const struct geni_se_desc qup_desc = { .clks = qup_clks, .num_clks = ARRAY_SIZE(qup_clks), + .geni_se_rsc_init = geni_se_resource_init, }; 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Fri, 02 May 2025 17:15:07 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 542HF6CO011760 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 2 May 2025 17:15:06 GMT Received: from hu-ptalari-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 2 May 2025 10:15:01 -0700 From: Praveen Talari To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , "Praveen Talari" , , , , CC: , , , , , , Subject: [PATCH v4 4/8] serial: qcom-geni: move resource initialization to separate function Date: Fri, 2 May 2025 22:44:13 +0530 Message-ID: <20250502171417.28856-5-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502171417.28856-1-quic_ptalari@quicinc.com> References: <20250502171417.28856-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=Ldc86ifi c=1 sm=1 tr=0 ts=6814fd9b cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=0DDkC8yEFXPSaA7UoRYA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: AE5qOq9Hvlo8Se6LbfCH3iXadjVpM6Bj X-Proofpoint-ORIG-GUID: AE5qOq9Hvlo8Se6LbfCH3iXadjVpM6Bj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDEzNyBTYWx0ZWRfX2vALYNgm+VU3 E/Pv6uVkk9A0OOUdXsKDQMlIXeeRy0uTsZvLHEkKqxHjU/K6TUtYToj0tUKNGA2vYyCptx9/cdM gWtWbxFhDcEEsJ9QwGzpk+Y6Uo/xpzCZ/BfJdHNm+YDF+ZvcuxOruM+FxRxDtAiOlPyUj2eebWK FgjtmdcIT/C1bNq3PEDt/G22+VAau+JltqPLfHwloE7FZ/u2S/WunaiMgLuRTjEX8dRr7JnytlN NDQ3AdmIAVCTBuXaxGCQeK0HcYIYtoD20hRSg2kTlcFOUjTfx8gOHtgyuT0YDj+Q6kFPvVE9oBi qM9x50Tr889ZDGWdJlH20HT2h3+tdBV2sywOROXjyhR6sFM50Ec7qTdc9hUnfKrrf6yklrPwxY5 Cc0dzNmCdKOgarS2pUo9GLVeieU8CBhnQkUJ8VV+9teEdprBMQQr+rMJ8wLgd9bbHrSpR3/+ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-02_03,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 impostorscore=0 clxscore=1015 spamscore=0 bulkscore=0 mlxlogscore=999 malwarescore=0 mlxscore=0 suspectscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020137 Enhances code readability and future modifications within the new API. Move the code that handles the actual initialization of resources like clock and ICC paths to a separate function, making the probe function cleaner. Signed-off-by: Praveen Talari --- v3 -> v4 - added version log after --- v1 -> v2 - updated subject description. - added a new line after function end --- drivers/tty/serial/qcom_geni_serial.c | 66 ++++++++++++++++----------- 1 file changed, 40 insertions(+), 26 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 0293b6210aa6..6ad759146f71 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1588,6 +1588,43 @@ static struct uart_driver qcom_geni_uart_driver = { .nr = GENI_UART_PORTS, }; +static int geni_serial_resource_init(struct qcom_geni_serial_port *port) +{ + int ret; + + port->se.clk = devm_clk_get(port->se.dev, "se"); + if (IS_ERR(port->se.clk)) { + ret = PTR_ERR(port->se.clk); + dev_err(port->se.dev, "Err getting SE Core clk %d\n", ret); + return ret; + } + + ret = geni_icc_get(&port->se, NULL); + if (ret) + return ret; + + port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; + port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; + + /* Set BW for register access */ + ret = geni_icc_set_bw(&port->se); + if (ret) + return ret; + + ret = devm_pm_opp_set_clkname(port->se.dev, "se"); + if (ret) + return ret; + + /* OPP table is optional */ + ret = devm_pm_opp_of_add_table(port->se.dev); + if (ret && ret != -ENODEV) { + dev_err(port->se.dev, "invalid OPP table in device tree\n"); + return ret; + } + + return 0; +} + static void qcom_geni_serial_pm(struct uart_port *uport, unsigned int new_state, unsigned int old_state) { @@ -1690,12 +1727,10 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) port->dev_data = data; port->se.dev = &pdev->dev; port->se.wrapper = dev_get_drvdata(pdev->dev.parent); - port->se.clk = devm_clk_get(&pdev->dev, "se"); - if (IS_ERR(port->se.clk)) { - ret = PTR_ERR(port->se.clk); - dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); + + ret = geni_serial_resource_init(port); + if (ret) return ret; - } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) @@ -1713,17 +1748,6 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) return -ENOMEM; } - ret = geni_icc_get(&port->se, NULL); - if (ret) - return ret; - port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; - port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; - - /* Set BW for register access */ - ret = geni_icc_set_bw(&port->se); - if (ret) - return ret; - port->name = devm_kasprintf(uport->dev, GFP_KERNEL, "qcom_geni_serial_%s%d", uart_console(uport) ? "console" : "uart", uport->line); @@ -1745,16 +1769,6 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) port->cts_rts_swap = true; - ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); - if (ret) - return ret; - /* OPP table is optional */ - ret = devm_pm_opp_of_add_table(&pdev->dev); - if (ret && ret != -ENODEV) { - dev_err(&pdev->dev, "invalid OPP table in device tree\n"); - return ret; - } - port->private_data.drv = drv; uport->private_data = &port->private_data; platform_set_drvdata(pdev, port); From patchwork Fri May 2 17:14:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Talari X-Patchwork-Id: 886886 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34FFA1ACED3; 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Fri, 02 May 2025 17:15:13 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 542HFDB8024270 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 2 May 2025 17:15:13 GMT Received: from hu-ptalari-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 2 May 2025 10:15:07 -0700 From: Praveen Talari To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , "Praveen Talari" , , , , CC: , , , , , , Subject: [PATCH v4 5/8] serial: qcom-geni: move resource control logic to separate functions Date: Fri, 2 May 2025 22:44:14 +0530 Message-ID: <20250502171417.28856-6-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502171417.28856-1-quic_ptalari@quicinc.com> References: <20250502171417.28856-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=BNizrEQG c=1 sm=1 tr=0 ts=6814fda1 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=HYIVWE9JnHk2aDURxZAA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDEzNyBTYWx0ZWRfX3wI20L4XawgW gEU5qUoWFF11pH5EIg06s3Qu0fEHjFDMOCLRSavdqDnLdvhPb6hGU9rQENKxkzOIv8TkZPG598i PVTUmApJoe8Mgm0EDV4SsRh1GwNJU42tlQ2FXMe3IyfnDYN50yRcN3ED7wvRtyAWOZd8mJt65f5 kWjcItZ2fa+6B70GxNQU5dkegXtGzOa9jm1cC5n0AQTM9mIKshcklhRxdhMQZxFKHU/tG5Mf+Rn AJk2OLcCIsS+agYDkKWJ/RzQGSnm75NCcBVioieUrBAYdRzCXqODPgoRupHw3JvQAB4wGhF3O3b nW8fmGVhlj1/vN3O6CTQQJGwzkORWaLpVfCXfnYdvxU8lsh+yLuyiVVKvodYL0yZHrXSRviOIW6 BQDgU+KJnQQ3SgHI9VC2neaUnarqBknZbZTVbfTY5LFrPT8cTjwtjUpxuCSZ7CtgD6kZgqUZ X-Proofpoint-GUID: 6ADCNu5O8sOicPWIfNNr-BvyjCGIrDV6 X-Proofpoint-ORIG-GUID: 6ADCNu5O8sOicPWIfNNr-BvyjCGIrDV6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-02_03,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 bulkscore=0 clxscore=1015 spamscore=0 adultscore=0 phishscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020137 Supports use in PM system/runtime frameworks, helping to distinguish new resource control mechanisms and facilitate future modifications within the new API. The code that handles the actual enable or disable of resources like clock and ICC paths to a separate function (geni_serial_resources_on() and geni_serial_resources_off()) which enhances code readability. Signed-off-by: Praveen Talari --- v3 -> v4 - added version log after --- v1 -> v2 - returned 0 instead of ret variable --- drivers/tty/serial/qcom_geni_serial.c | 54 +++++++++++++++++++++------ 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 6ad759146f71..2cd2085473f3 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1588,6 +1588,42 @@ static struct uart_driver qcom_geni_uart_driver = { .nr = GENI_UART_PORTS, }; +static int geni_serial_resources_off(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + int ret; + + dev_pm_opp_set_rate(uport->dev, 0); + ret = geni_se_resources_off(&port->se); + if (ret) + return ret; + + geni_icc_disable(&port->se); + + return 0; +} + +static int geni_serial_resources_on(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + int ret; + + ret = geni_icc_enable(&port->se); + if (ret) + return ret; + + ret = geni_se_resources_on(&port->se); + if (ret) { + geni_icc_disable(&port->se); + return ret; + } + + if (port->clk_rate) + dev_pm_opp_set_rate(uport->dev, port->clk_rate); + + return 0; +} + static int geni_serial_resource_init(struct qcom_geni_serial_port *port) { int ret; @@ -1628,23 +1664,17 @@ static int geni_serial_resource_init(struct qcom_geni_serial_port *port) static void qcom_geni_serial_pm(struct uart_port *uport, unsigned int new_state, unsigned int old_state) { - struct qcom_geni_serial_port *port = to_dev_port(uport); /* If we've never been called, treat it as off */ if (old_state == UART_PM_STATE_UNDEFINED) old_state = UART_PM_STATE_OFF; - if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { - geni_icc_enable(&port->se); - if (port->clk_rate) - dev_pm_opp_set_rate(uport->dev, port->clk_rate); - geni_se_resources_on(&port->se); - } else if (new_state == UART_PM_STATE_OFF && - old_state == UART_PM_STATE_ON) { - geni_se_resources_off(&port->se); - dev_pm_opp_set_rate(uport->dev, 0); - geni_icc_disable(&port->se); - } + if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) + geni_serial_resources_on(uport); + else if (new_state == UART_PM_STATE_OFF && + old_state == UART_PM_STATE_ON) + geni_serial_resources_off(uport); + } static const struct uart_ops qcom_geni_console_pops = { From patchwork Fri May 2 17:14:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Talari X-Patchwork-Id: 887093 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B52611A0BFA; Fri, 2 May 2025 17:15:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Fri, 02 May 2025 17:15:20 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 542HFJc9006045 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 2 May 2025 17:15:19 GMT Received: from hu-ptalari-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 2 May 2025 10:15:14 -0700 From: Praveen Talari To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , "Praveen Talari" , , , , CC: , , , , , , Subject: [PATCH v4 6/8] serial: qcom-geni: move clock-rate logic to separate function Date: Fri, 2 May 2025 22:44:15 +0530 Message-ID: <20250502171417.28856-7-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502171417.28856-1-quic_ptalari@quicinc.com> References: <20250502171417.28856-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: e2qnMQqnBYPyKkVzK4JHiHpVATSPnGB8 X-Authority-Analysis: v=2.4 cv=bsxMBFai c=1 sm=1 tr=0 ts=6814fda8 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=X08zvMDfRsL5Z2rP0xYA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDEzNyBTYWx0ZWRfXzb0KFok/wP0V 9ID5Z5rK7ub5mQTjrlqiQZOLxO1dPwvbtQ9FhjtGaZ76lVPJ83pEr4azGO38E3w+5vAh/QAZAL2 krAA6a/MA8a39Aa/M1iK7IFK8x+G6nkR7jT0/F6YTA4UHPSwMC6luA0iEuKkYl7qIDNLzZ3Cgyd ZkCj1OvwydOd8UhHpYobKTWRc3kKtAe6CToYM/2ccEtfaT8ulepkyKLQEWTz50HeJjWkJ3djuHX ULmDa7TTOPg7MEUrWwPyAlhPYu6vTxuUb77+j8Z01tIe0BlVx+CdntrkyQwTi7xRoCLGWs9vtk+ uXHy4696ZPiCHat95U4CXbzybdoXfVkkuKDe4rj4OcbCbp+NUavayK8MryF4LSHkDwmRNXgouMa fEC5zoYxHro1uRgH8PLLmLd6GoY6gH497mRyTVcjpeq0nfcgLw+vzFIKf3U4G1RhnjMUOf9m X-Proofpoint-ORIG-GUID: e2qnMQqnBYPyKkVzK4JHiHpVATSPnGB8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-02_03,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 bulkscore=0 suspectscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020137 Facilitates future modifications within the new function, leading to better readability and maintainability of the code. Move the code that handles the actual logic of clock-rate calculations to a separate function geni_serial_set_rate() which enhances code readability. Signed-off-by: Praveen Talari --- v3 -> v4 - added version log after --- v1 -> v2 - resolved build warnings for datatype format specifiers - removed double spaces in log --- drivers/tty/serial/qcom_geni_serial.c | 62 +++++++++++++++++---------- 1 file changed, 39 insertions(+), 23 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 2cd2085473f3..60afee3884a6 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1283,27 +1283,14 @@ static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud, return ser_clk; } -static void qcom_geni_serial_set_termios(struct uart_port *uport, - struct ktermios *termios, - const struct ktermios *old) +static int geni_serial_set_rate(struct uart_port *uport, unsigned long baud) { - unsigned int baud; - u32 bits_per_char; - u32 tx_trans_cfg; - u32 tx_parity_cfg; - u32 rx_trans_cfg; - u32 rx_parity_cfg; - u32 stop_bit_len; - unsigned int clk_div; - u32 ser_clk_cfg; struct qcom_geni_serial_port *port = to_dev_port(uport); unsigned long clk_rate; - u32 ver, sampling_rate; unsigned int avg_bw_core; - unsigned long timeout; - - /* baud rate */ - baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); + unsigned int clk_div; + u32 ver, sampling_rate; + u32 ser_clk_cfg; sampling_rate = UART_OVERSAMPLING; /* Sampling rate is halved for IP versions >= 2.5 */ @@ -1315,13 +1302,13 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, sampling_rate, &clk_div); if (!clk_rate) { dev_err(port->se.dev, - "Couldn't find suitable clock rate for %u\n", + "Couldn't find suitable clock rate for %lu\n", baud * sampling_rate); - return; + return -EINVAL; } - dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n", - baud * sampling_rate, clk_rate, clk_div); + dev_dbg(port->se.dev, "desired_rate = %lu, clk_rate = %lu, clk_div = %u\n", + baud * sampling_rate, clk_rate, clk_div); uport->uartclk = clk_rate; port->clk_rate = clk_rate; @@ -1339,6 +1326,37 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); geni_icc_set_bw(&port->se); + writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); + writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); + return 0; +} + +static void qcom_geni_serial_set_termios(struct uart_port *uport, + struct ktermios *termios, + const struct ktermios *old) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + unsigned int baud; + unsigned long timeout; + u32 bits_per_char; + u32 tx_trans_cfg; + u32 tx_parity_cfg; + u32 rx_trans_cfg; + u32 rx_parity_cfg; + u32 stop_bit_len; + int ret = 0; + + /* baud rate */ + baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); + + ret = geni_serial_set_rate(uport, baud); + if (ret) { + dev_err(port->se.dev, + "%s: Failed to set baud:%u ret:%d\n", + __func__, baud, ret); + return; + } + /* parity */ tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); @@ -1406,8 +1424,6 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); - writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); - writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); } #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE From patchwork Fri May 2 17:14:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Talari X-Patchwork-Id: 886885 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 063511A0BFA; Fri, 2 May 2025 17:15:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Introduce necessary callbacks and updates to ensure seamless transitions between power states, enhancing overall power efficiency. Signed-off-by: Praveen Talari --- drivers/tty/serial/qcom_geni_serial.c | 33 +++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 60afee3884a6..9d698c354510 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1686,10 +1686,10 @@ static void qcom_geni_serial_pm(struct uart_port *uport, old_state = UART_PM_STATE_OFF; if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) - geni_serial_resources_on(uport); + pm_runtime_resume_and_get(uport->dev); else if (new_state == UART_PM_STATE_OFF && old_state == UART_PM_STATE_ON) - geni_serial_resources_off(uport); + pm_runtime_put_sync(uport->dev); } @@ -1827,9 +1827,11 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) return ret; } + pm_runtime_enable(port->se.dev); + ret = uart_add_one_port(drv, uport); if (ret) - return ret; + goto error; if (port->wakeup_irq > 0) { device_init_wakeup(&pdev->dev, true); @@ -1839,11 +1841,15 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) device_init_wakeup(&pdev->dev, false); ida_free(&port_ida, uport->line); uart_remove_one_port(drv, uport); - return ret; + goto error; } } return 0; + +error: + pm_runtime_disable(port->se.dev); + return ret; } static void qcom_geni_serial_remove(struct platform_device *pdev) @@ -1855,9 +1861,26 @@ static void qcom_geni_serial_remove(struct platform_device *pdev) dev_pm_clear_wake_irq(&pdev->dev); device_init_wakeup(&pdev->dev, false); ida_free(&port_ida, uport->line); + pm_runtime_disable(port->se.dev); uart_remove_one_port(drv, &port->uport); } +static int qcom_geni_serial_runtime_suspend(struct device *dev) +{ + struct qcom_geni_serial_port *port = dev_get_drvdata(dev); + struct uart_port *uport = &port->uport; + + return geni_serial_resources_off(uport); +}; + +static int qcom_geni_serial_runtime_resume(struct device *dev) +{ + struct qcom_geni_serial_port *port = dev_get_drvdata(dev); + struct uart_port *uport = &port->uport; + + return geni_serial_resources_on(uport); +}; + static int qcom_geni_serial_suspend(struct device *dev) { struct qcom_geni_serial_port *port = dev_get_drvdata(dev); @@ -1901,6 +1924,8 @@ static const struct qcom_geni_device_data qcom_geni_uart_data = { }; static const struct dev_pm_ops qcom_geni_serial_pm_ops = { + SET_RUNTIME_PM_OPS(qcom_geni_serial_runtime_suspend, + qcom_geni_serial_runtime_resume, NULL) SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_suspend, qcom_geni_serial_resume) }; From patchwork Fri May 2 17:14:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Talari X-Patchwork-Id: 887092 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 932161AB531; Fri, 2 May 2025 17:15:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 02 May 2025 17:15:46 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 542HFWU0022943 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 2 May 2025 17:15:32 GMT Received: from hu-ptalari-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 2 May 2025 10:15:26 -0700 From: Praveen Talari To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , "Praveen Talari" , , , , CC: , , , , , , Subject: [PATCH v4 8/8] serial: qcom-geni: Enable Serial on SA8255p Qualcomm platforms Date: Fri, 2 May 2025 22:44:17 +0530 Message-ID: <20250502171417.28856-9-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250502171417.28856-1-quic_ptalari@quicinc.com> References: <20250502171417.28856-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=Bv6dwZX5 c=1 sm=1 tr=0 ts=6814fdc2 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=_gOkJu00RtHYCxNnkZMA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: XfzqmfvP4Jzqn5Eukud4I7o-GwOaJtMs X-Proofpoint-ORIG-GUID: XfzqmfvP4Jzqn5Eukud4I7o-GwOaJtMs X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDEzOCBTYWx0ZWRfX/G9L3dmZR/rj TJcOCWv2Pjau0AT8gtE/EaYZpWbBRRovSq/k9QQwO6Lz18HMTyXl+DJuO1p9zisgeYUgw4nmfQp xm8u/LSFfQKNp/RuWD5xK85DUti4nPDJz85pqKQ79zx2OaVih0xFUhQTI+1v1TURZbc9v+oX+CJ GGIcuhfp+XZsN5EmaWwDw7gQhIZ5YTUGp/3bdJSMU5XKXhvWKdWntQxY53yywvUv0prvHF/xshx T9I+45EzIU0l/d8p7x12/AHLFabekgxGXJ/SlKEPHzSigj/IoLv1FWPY2L2oj7/zYOACWwg6MTK 6iUvrUiMnB27yOv1qVQO5ezOlurj48tqRh8SyxS4AlM2PKU53JVwsnc9Y+kgNDk6OU5Rmq2Y6W9 3QAEsOIS8yC3NK1jtOnBzNzle3QfcWttX03xNIiZ6gpPQxR27aNtBaeGBQwL3UC2GK3A4o7Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-02_03,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 mlxlogscore=999 phishscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020138 The Qualcomm automotive SA8255p SoC relies on firmware to configure platform resources, including clocks, interconnects and TLMM. The driver requests resources operations over SCMI using power and performance protocols. The SCMI power protocol enables or disables resources like clocks, interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs, such as resume/suspend, to control power states(on/off). The SCMI performance protocol manages UART baud rates, with each baud rate represented by a performance level. The driver uses the dev_pm_opp_set_level() API to request the desired baud rate by specifying the performance level. Signed-off-by: Praveen Talari --- v3 -> v4 - renamed callback function names to resources_init, set_rate and power_state --- drivers/tty/serial/qcom_geni_serial.c | 150 +++++++++++++++++++++++--- 1 file changed, 135 insertions(+), 15 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 9d698c354510..77bca899e913 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -99,10 +100,16 @@ #define DMA_RX_BUF_SIZE 2048 static DEFINE_IDA(port_ida); +#define DOMAIN_IDX_POWER 0 +#define DOMAIN_IDX_PERF 1 struct qcom_geni_device_data { bool console; enum geni_se_xfer_mode mode; + struct dev_pm_domain_attach_data pd_data; + int (*resources_init)(struct uart_port *uport); + int (*set_rate)(struct uart_port *uport, unsigned long clk_freq); + int (*power_state)(struct uart_port *uport, bool state); }; struct qcom_geni_private_data { @@ -140,6 +147,7 @@ struct qcom_geni_serial_port { struct qcom_geni_private_data private_data; const struct qcom_geni_device_data *dev_data; + struct dev_pm_domain_list *pd_list; }; static const struct uart_ops qcom_geni_console_pops; @@ -1331,6 +1339,42 @@ static int geni_serial_set_rate(struct uart_port *uport, unsigned long baud) return 0; } +static int geni_serial_set_level(struct uart_port *uport, unsigned long baud) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + struct device *perf_dev = port->pd_list->pd_devs[DOMAIN_IDX_PERF]; + + /* + * The performance protocol sets UART communication + * speeds by selecting different performance levels + * through the OPP framework. + * + * Supported perf levels for baudrates in firmware are below + * +---------------------+--------------------+ + * | Perf level value | Baudrate values | + * +---------------------+--------------------+ + * | 300 | 300 | + * | 1200 | 1200 | + * | 2400 | 2400 | + * | 4800 | 4800 | + * | 9600 | 9600 | + * | 19200 | 19200 | + * | 38400 | 38400 | + * | 57600 | 57600 | + * | 115200 | 115200 | + * | 230400 | 230400 | + * | 460800 | 460800 | + * | 921600 | 921600 | + * | 2000000 | 2000000 | + * | 3000000 | 3000000 | + * | 3200000 | 3200000 | + * | 4000000 | 4000000 | + * +---------------------+--------------------+ + */ + + return dev_pm_opp_set_level(perf_dev, baud); +} + static void qcom_geni_serial_set_termios(struct uart_port *uport, struct ktermios *termios, const struct ktermios *old) @@ -1349,7 +1393,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, /* baud rate */ baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); - ret = geni_serial_set_rate(uport, baud); + ret = port->dev_data->set_rate(uport, baud); if (ret) { dev_err(port->se.dev, "%s: Failed to set baud:%u ret:%d\n", @@ -1640,8 +1684,27 @@ static int geni_serial_resources_on(struct uart_port *uport) return 0; } -static int geni_serial_resource_init(struct qcom_geni_serial_port *port) +static int geni_serial_resource_state(struct uart_port *uport, bool power_on) { + return power_on ? geni_serial_resources_on(uport) : geni_serial_resources_off(uport); +} + +static int geni_serial_pwr_init(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + int ret; + + ret = dev_pm_domain_attach_list(port->se.dev, + &port->dev_data->pd_data, &port->pd_list); + if (ret <= 0) + return -EINVAL; + + return 0; +} + +static int geni_serial_resource_init(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); int ret; port->se.clk = devm_clk_get(port->se.dev, "se"); @@ -1680,7 +1743,6 @@ static int geni_serial_resource_init(struct qcom_geni_serial_port *port) static void qcom_geni_serial_pm(struct uart_port *uport, unsigned int new_state, unsigned int old_state) { - /* If we've never been called, treat it as off */ if (old_state == UART_PM_STATE_UNDEFINED) old_state = UART_PM_STATE_OFF; @@ -1774,13 +1836,16 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) port->se.dev = &pdev->dev; port->se.wrapper = dev_get_drvdata(pdev->dev.parent); - ret = geni_serial_resource_init(port); + ret = port->dev_data->resources_init(uport); if (ret) return ret; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -EINVAL; + if (!res) { + ret = -EINVAL; + goto error; + } + uport->mapbase = res->start; port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; @@ -1790,19 +1855,26 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) if (!data->console) { port->rx_buf = devm_kzalloc(uport->dev, DMA_RX_BUF_SIZE, GFP_KERNEL); - if (!port->rx_buf) - return -ENOMEM; + if (!port->rx_buf) { + ret = -ENOMEM; + goto error; + } } port->name = devm_kasprintf(uport->dev, GFP_KERNEL, "qcom_geni_serial_%s%d", uart_console(uport) ? "console" : "uart", uport->line); - if (!port->name) - return -ENOMEM; + if (!port->name) { + ret = -ENOMEM; + goto error; + } irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; + if (irq < 0) { + ret = irq; + goto error; + } + uport->irq = irq; uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); @@ -1824,7 +1896,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) IRQF_TRIGGER_HIGH, port->name, uport); if (ret) { dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); - return ret; + goto error; } pm_runtime_enable(port->se.dev); @@ -1849,6 +1921,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) error: pm_runtime_disable(port->se.dev); + dev_pm_domain_detach_list(port->pd_list); return ret; } @@ -1863,22 +1936,31 @@ static void qcom_geni_serial_remove(struct platform_device *pdev) ida_free(&port_ida, uport->line); pm_runtime_disable(port->se.dev); uart_remove_one_port(drv, &port->uport); + dev_pm_domain_detach_list(port->pd_list); } static int qcom_geni_serial_runtime_suspend(struct device *dev) { struct qcom_geni_serial_port *port = dev_get_drvdata(dev); struct uart_port *uport = &port->uport; + int ret = 0; - return geni_serial_resources_off(uport); + if (port->dev_data->power_state) + ret = port->dev_data->power_state(uport, false); + + return ret; }; static int qcom_geni_serial_runtime_resume(struct device *dev) { struct qcom_geni_serial_port *port = dev_get_drvdata(dev); struct uart_port *uport = &port->uport; + int ret = 0; + + if (port->dev_data->power_state) + ret = port->dev_data->power_state(uport, true); - return geni_serial_resources_on(uport); + return ret; }; static int qcom_geni_serial_suspend(struct device *dev) @@ -1916,11 +1998,41 @@ static int qcom_geni_serial_resume(struct device *dev) static const struct qcom_geni_device_data qcom_geni_console_data = { .console = true, .mode = GENI_SE_FIFO, + .resources_init = geni_serial_resource_init, + .set_rate = geni_serial_set_rate, + .power_state = geni_serial_resource_state, }; static const struct qcom_geni_device_data qcom_geni_uart_data = { .console = false, .mode = GENI_SE_DMA, + .resources_init = geni_serial_resource_init, + .set_rate = geni_serial_set_rate, + .power_state = geni_serial_resource_state, +}; + +static const struct qcom_geni_device_data sa8255p_qcom_geni_console_data = { + .console = true, + .mode = GENI_SE_FIFO, + .pd_data = { + .pd_flags = PD_FLAG_DEV_LINK_ON, + .pd_names = (const char*[]) { "power", "perf" }, + .num_pd_names = 2, + }, + .resources_init = geni_serial_pwr_init, + .set_rate = geni_serial_set_level, +}; + +static const struct qcom_geni_device_data sa8255p_qcom_geni_uart_data = { + .console = false, + .mode = GENI_SE_DMA, + .pd_data = { + .pd_flags = PD_FLAG_DEV_LINK_ON, + .pd_names = (const char*[]) { "power", "perf" }, + .num_pd_names = 2, + }, + .resources_init = geni_serial_pwr_init, + .set_rate = geni_serial_set_level, }; static const struct dev_pm_ops qcom_geni_serial_pm_ops = { @@ -1934,10 +2046,18 @@ static const struct of_device_id qcom_geni_serial_match_table[] = { .compatible = "qcom,geni-debug-uart", .data = &qcom_geni_console_data, }, + { + .compatible = "qcom,sa8255p-geni-debug-uart", + .data = &sa8255p_qcom_geni_console_data, + }, { .compatible = "qcom,geni-uart", .data = &qcom_geni_uart_data, }, + { + .compatible = "qcom,sa8255p-geni-uart", + .data = &sa8255p_qcom_geni_uart_data, + }, {} }; MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);