From patchwork Sat May 3 19:15:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 887010 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A1CD27E1DC; Sat, 3 May 2025 19:10:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299413; cv=none; b=XqQYHIxcx4Sw0pLiGi2qhqx+OlIjeEhgF8auj9D6nKpSjxJrl12bgeCLXQuBstzE4VufR2WtAqrSSzGECY9ixG27Yzn4bhfh4McT4vV/NPzm/6sIM9eu7jtUHT5lZTDV0Um6nARhCdTx89RzqxlTtfxph7knEipQxaseQp2Lt1g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299413; c=relaxed/simple; bh=v4Qdkyf8Y3iGQ05r5Hs38Sy/RlRbceKXnRy9fjwloE4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=BXsvhdHZ3kIXPTFRLO06ZtxBNEIAp+6hv4gpu9BzIpa6po/a7raCyjN9Llu1E7YYa+5m9aebEmUY9bxzoWoLryaobreiXFQlYkMMTg/n/nPKKSDmYGENe3jDvIS2DLwc1aC+Tgw3dxpu22skmsrEi6ZvTouolhM/c5QfQbDMRxw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YAll8NmU; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YAll8NmU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746299412; x=1777835412; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=v4Qdkyf8Y3iGQ05r5Hs38Sy/RlRbceKXnRy9fjwloE4=; b=YAll8NmUFmAOEw3aT35yY8ypWHVm5yvnnEQrP0BA+BDoat1Jl/3deARo 0x8sgpMvJgFttW5U+nBH4G1a9+IPfXamNpW8cqY2zYP4QWhTIRgIg7yw7 94kYuaLz9pWlRcrY7gCwdlJk4pSuP2eIhfmc6sG0WzO//arqIrrjg9vi8 O1o18bUz+LQhZf53+e9PLddDZS6UPFp5ur8n6XkkkNRfrwVDNYkMVWEie 8IeGlwowrGuE9/i3vZUSy+YjCdYju7yYe0Pg8sk8w8DWBbZFKvZcH5eQm 4XOyXpP9zanmUBFTAwZmKCXJFgjrAnnX7K70PfG70ZHv/JAn3r1HzuBM/ Q==; X-CSE-ConnectionGUID: eTJ9ddaUTu2TiHO4ktGgNA== X-CSE-MsgGUID: anHjMvW/Tdalu6VPCpk47Q== X-IronPort-AV: E=McAfee;i="6700,10204,11422"; a="48095604" X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="48095604" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2025 12:10:10 -0700 X-CSE-ConnectionGUID: 3l3QVmyPRi2Yvw4UWZsr+g== X-CSE-MsgGUID: FHmJDk/kRXWQ79jZnLHYrg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="140046082" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmviesa004.fm.intel.com with ESMTP; 03 May 2025 12:10:09 -0700 From: Ricardo Neri To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley Cc: devicetree@vger.kernel.org, Saurabh Sengar , Chris Oo , linux-hyperv@vger.kernel.org, "Kirill A. Shutemov" , linux-acpi@vger.kernel.org , linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri Subject: [PATCH v3 01/13] x86/acpi: Add a helper function to setup the wakeup mailbox Date: Sat, 3 May 2025 12:15:03 -0700 Message-Id: <20250503191515.24041-2-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> References: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: In preparation to move the functionality to wake secondary CPUs up out of the ACPI code, add a helper function that stores the physical address of the mailbox and updates the wakeup_secondary_cpu_64() APIC callback. There is a slight change in behavior: now the APIC callback is updated before configuring CPU hotplug offline behavior. This is fine as the APIC callback continues to be updated unconditionally, regardless of the restriction on CPU offlining. The wakeup mailbox is only supported for CONFIG_X86_64 and needed only with CONFIG_SMP=y. Signed-off-by: Ricardo Neri --- Changes since v2: - Introduced this patch. Changes since v1: - N/A --- arch/x86/include/asm/smp.h | 4 ++++ arch/x86/kernel/acpi/madt_wakeup.c | 10 +++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index 0c1c68039d6f..3622951d2ee0 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -146,6 +146,10 @@ static inline struct cpumask *cpu_l2c_shared_mask(int cpu) return per_cpu(cpu_l2c_shared_map, cpu); } +#ifdef CONFIG_X86_64 +void setup_mp_wakeup_mailbox(u64 addr); +#endif + #else /* !CONFIG_SMP */ #define wbinvd_on_cpu(cpu) wbinvd() static inline int wbinvd_on_all_cpus(void) diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt_wakeup.c index f36f28405dcc..04de3db307de 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -227,7 +227,7 @@ int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, acpi_table_print_madt_entry(&header->common); - acpi_mp_wake_mailbox_paddr = mp_wake->mailbox_address; + setup_mp_wakeup_mailbox(mp_wake->mailbox_address); if (mp_wake->version >= ACPI_MADT_MP_WAKEUP_VERSION_V1 && mp_wake->header.length >= ACPI_MADT_MP_WAKEUP_SIZE_V1) { @@ -243,7 +243,11 @@ int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, acpi_mp_disable_offlining(mp_wake); } - apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); - return 0; } + +void __init setup_mp_wakeup_mailbox(u64 mailbox_paddr) +{ + acpi_mp_wake_mailbox_paddr = mailbox_paddr; + apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); +} From patchwork Sat May 3 19:15:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 887009 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E86227E7D0; Sat, 3 May 2025 19:10:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299415; cv=none; b=kwixLKr8LGM8Lv5aH1WH7UCHXKwm2XPqqTdxxPgw3qWyfCT7SP2vJGmT4V8xaIjt1I8r/Q6KT9HQ7GlomxmPhfnp7CpDwksc+6WWj0P/QQ7VO8UF77/xF1JPo1WYWqMlqnjI1yfkv1i91GrK4LRnOGrlYrUWuoSF3yFh1R7igGk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299415; c=relaxed/simple; bh=CcBd5muWd0bFU2n4MW9K/uESkZokPGbZ1FllJgz4DJ0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=X5yP6o/IaFicr8ZaWdStZtVUcj86U+54h8CvdwBmrv/BaZCYyHdAGN7WbsdDQRnVXjs8ZsEEvryz7EZ1Yiqsji9De4msDTEoY2f37nlRmJAPA76lLIubTVgLCJ2nFpJQWdV8C6VF5bza5LMI5fr1fw4LqZDQk3uulseWF+zQoVU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=fYzesCcE; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="fYzesCcE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746299414; x=1777835414; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=CcBd5muWd0bFU2n4MW9K/uESkZokPGbZ1FllJgz4DJ0=; b=fYzesCcE85FUZbbuVzHz0ytJdR6q3gRI9CwYalH2Rew3Elp1F0+44tpE vD2OES/yexIz29icJXLtpouAhiJtnCMNf1MCUkkRT+o63S0E3R76sCqGv BtQlhwXCJwADynx4SC1/ZX8DPRF/O/TmK3fDMQ+X4XK7XqoKO28v5V+hK k52xE4Y6Jn8hGVdw5u5+4dc0/zh7iK0KQnwVvYdHQD9GzCHWT4OX/i3fs LmDJyIXFzpEfrqZqS5cvXnw578dLyzuRFHMHDhwFh2hiYCqe3dJxA4ONf dFVgMjHDbKvZN+pgi9zwv9T8W/TIDpIcjMHs2w1QJTTuFBbgbRtHng8xI w==; X-CSE-ConnectionGUID: 5vef0Qw9ThKAzsAHj0QS7A== X-CSE-MsgGUID: I1v86+cuRamqr/zc71yADg== X-IronPort-AV: E=McAfee;i="6700,10204,11422"; a="48095609" X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="48095609" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2025 12:10:11 -0700 X-CSE-ConnectionGUID: uVKts7upQuqc3OwM7RW0Eg== X-CSE-MsgGUID: zRLZuPgTRkOjwmEz5GV2qg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="140046085" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmviesa004.fm.intel.com with ESMTP; 03 May 2025 12:10:10 -0700 From: Ricardo Neri To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley Cc: devicetree@vger.kernel.org, Saurabh Sengar , Chris Oo , linux-hyperv@vger.kernel.org, "Kirill A. Shutemov" , linux-acpi@vger.kernel.org , linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri Subject: [PATCH v3 02/13] x86/acpi: Add a helper function to get a pointer to the wakeup mailbox Date: Sat, 3 May 2025 12:15:04 -0700 Message-Id: <20250503191515.24041-3-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> References: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: In preparation to move the functionality to wake secondary CPUs up out of the ACPI code, add a helper function to get a pointer to the mailbox. Use this helper function only in the portions of the code for which the variable acpi_mp_wake_mailbox will be out of scope once it is relocated out of the ACPI directory. The wakeup mailbox is only supported for CONFIG_X86_64 and needed only with CONFIG_SMP. Signed-off-by: Ricardo Neri --- Changes since v2: - Introduced this patch. Changes since v1: - N/A --- arch/x86/include/asm/smp.h | 1 + arch/x86/kernel/acpi/madt_wakeup.c | 12 +++++++++--- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index 3622951d2ee0..97bfbd0d24d4 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -148,6 +148,7 @@ static inline struct cpumask *cpu_l2c_shared_mask(int cpu) #ifdef CONFIG_X86_64 void setup_mp_wakeup_mailbox(u64 addr); +struct acpi_madt_multiproc_wakeup_mailbox *get_mp_wakeup_mailbox(void); #endif #else /* !CONFIG_SMP */ diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt_wakeup.c index 04de3db307de..6b9e41a24574 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -37,6 +37,7 @@ static void acpi_mp_play_dead(void) static void acpi_mp_cpu_die(unsigned int cpu) { + struct acpi_madt_multiproc_wakeup_mailbox *mailbox = get_mp_wakeup_mailbox(); u32 apicid = per_cpu(x86_cpu_to_apicid, cpu); unsigned long timeout; @@ -46,13 +47,13 @@ static void acpi_mp_cpu_die(unsigned int cpu) * * BIOS has to clear 'command' field of the mailbox. */ - acpi_mp_wake_mailbox->apic_id = apicid; - smp_store_release(&acpi_mp_wake_mailbox->command, + mailbox->apic_id = apicid; + smp_store_release(&mailbox->command, ACPI_MP_WAKE_COMMAND_TEST); /* Don't wait longer than a second. */ timeout = USEC_PER_SEC; - while (READ_ONCE(acpi_mp_wake_mailbox->command) && --timeout) + while (READ_ONCE(mailbox->command) && --timeout) udelay(1); if (!timeout) @@ -251,3 +252,8 @@ void __init setup_mp_wakeup_mailbox(u64 mailbox_paddr) acpi_mp_wake_mailbox_paddr = mailbox_paddr; apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); } + +struct acpi_madt_multiproc_wakeup_mailbox *get_mp_wakeup_mailbox(void) +{ + return acpi_mp_wake_mailbox; +} From patchwork Sat May 3 19:15:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 887008 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10AC327E7EF; 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a="48095614" X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="48095614" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2025 12:10:11 -0700 X-CSE-ConnectionGUID: wUy/Qb8YSg6h8CY66vUBTA== X-CSE-MsgGUID: 7Ed1AHtyQDuXnRhaP2CW9A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="140046088" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmviesa004.fm.intel.com with ESMTP; 03 May 2025 12:10:11 -0700 From: Ricardo Neri To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley Cc: devicetree@vger.kernel.org, Saurabh Sengar , Chris Oo , linux-hyperv@vger.kernel.org, "Kirill A. Shutemov" , linux-acpi@vger.kernel.org , linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri Subject: [PATCH v3 03/13] x86/acpi: Move acpi_wakeup_cpu() and helpers to smpboot.c Date: Sat, 3 May 2025 12:15:05 -0700 Message-Id: <20250503191515.24041-4-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> References: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The bootstrap processor uses acpi_wakeup_cpu() to indicate to firmware that it wants to boot a secondary CPU using a mailbox as described in the Multiprocessor Wakeup Structure of the ACPI specification. The wakeup mailbox does not strictly require support from ACPI. The platform firmware can implement a mailbox compatible in structure and operation and enumerate it using other mechanisms such a DeviceTree graph. Move the code used to setup and use the mailbox out of the ACPI directory to use it when support for ACPI is not available or needed. No functional changes are intended. Originally-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v2: - Only move to smpboot.c the portions of the code that configure and use the mailbox. This also resolved the compile warnings about unused functions that Michael Kelley reported. - Edited the commit message for clarity. Changes since v1: - None. --- arch/x86/kernel/acpi/madt_wakeup.c | 75 ---------------------------- arch/x86/kernel/smpboot.c | 78 ++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 75 deletions(-) diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt_wakeup.c index 6b9e41a24574..15627f63f9f5 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -2,7 +2,6 @@ #include #include #include -#include #include #include #include @@ -15,12 +14,6 @@ #include #include -/* Physical address of the Multiprocessor Wakeup Structure mailbox */ -static u64 acpi_mp_wake_mailbox_paddr __ro_after_init; - -/* Virtual address of the Multiprocessor Wakeup Structure mailbox */ -static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox; - static u64 acpi_mp_pgd __ro_after_init; static u64 acpi_mp_reset_vector_paddr __ro_after_init; @@ -127,63 +120,6 @@ static int __init acpi_mp_setup_reset(u64 reset_vector) return 0; } -static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip) -{ - if (!acpi_mp_wake_mailbox_paddr) { - pr_warn_once("No MADT mailbox: cannot bringup secondary CPUs. Booting with kexec?\n"); - return -EOPNOTSUPP; - } - - /* - * Remap mailbox memory only for the first call to acpi_wakeup_cpu(). - * - * Wakeup of secondary CPUs is fully serialized in the core code. - * No need to protect acpi_mp_wake_mailbox from concurrent accesses. - */ - if (!acpi_mp_wake_mailbox) { - acpi_mp_wake_mailbox = memremap(acpi_mp_wake_mailbox_paddr, - sizeof(*acpi_mp_wake_mailbox), - MEMREMAP_WB); - } - - /* - * Mailbox memory is shared between the firmware and OS. Firmware will - * listen on mailbox command address, and once it receives the wakeup - * command, the CPU associated with the given apicid will be booted. - * - * The value of 'apic_id' and 'wakeup_vector' must be visible to the - * firmware before the wakeup command is visible. smp_store_release() - * ensures ordering and visibility. - */ - acpi_mp_wake_mailbox->apic_id = apicid; - acpi_mp_wake_mailbox->wakeup_vector = start_ip; - smp_store_release(&acpi_mp_wake_mailbox->command, - ACPI_MP_WAKE_COMMAND_WAKEUP); - - /* - * Wait for the CPU to wake up. - * - * The CPU being woken up is essentially in a spin loop waiting to be - * woken up. It should not take long for it wake up and acknowledge by - * zeroing out ->command. - * - * ACPI specification doesn't provide any guidance on how long kernel - * has to wait for a wake up acknowledgment. It also doesn't provide - * a way to cancel a wake up request if it takes too long. - * - * In TDX environment, the VMM has control over how long it takes to - * wake up secondary. It can postpone scheduling secondary vCPU - * indefinitely. Giving up on wake up request and reporting error opens - * possible attack vector for VMM: it can wake up a secondary CPU when - * kernel doesn't expect it. Wait until positive result of the wake up - * request. - */ - while (READ_ONCE(acpi_mp_wake_mailbox->command)) - cpu_relax(); - - return 0; -} - static void acpi_mp_disable_offlining(struct acpi_madt_multiproc_wakeup *mp_wake) { cpu_hotplug_disable_offlining(); @@ -246,14 +182,3 @@ int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, return 0; } - -void __init setup_mp_wakeup_mailbox(u64 mailbox_paddr) -{ - acpi_mp_wake_mailbox_paddr = mailbox_paddr; - apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); -} - -struct acpi_madt_multiproc_wakeup_mailbox *get_mp_wakeup_mailbox(void) -{ - return acpi_mp_wake_mailbox; -} diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index d6cf1e23c2a3..6f39ebe4d192 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -61,7 +61,9 @@ #include #include #include +#include +#include #include #include #include @@ -1354,3 +1356,79 @@ void native_play_dead(void) } #endif + +#ifdef CONFIG_X86_64 +/* Physical address of the Multiprocessor Wakeup Structure mailbox */ +static u64 acpi_mp_wake_mailbox_paddr __ro_after_init; + +/* Virtual address of the Multiprocessor Wakeup Structure mailbox */ +static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox; + +static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip) +{ + if (!acpi_mp_wake_mailbox_paddr) { + pr_warn_once("No MADT mailbox: cannot bringup secondary CPUs. Booting with kexec?\n"); + return -EOPNOTSUPP; + } + + /* + * Remap mailbox memory only for the first call to acpi_wakeup_cpu(). + * + * Wakeup of secondary CPUs is fully serialized in the core code. + * No need to protect acpi_mp_wake_mailbox from concurrent accesses. + */ + if (!acpi_mp_wake_mailbox) { + acpi_mp_wake_mailbox = memremap(acpi_mp_wake_mailbox_paddr, + sizeof(*acpi_mp_wake_mailbox), + MEMREMAP_WB); + } + + /* + * Mailbox memory is shared between the firmware and OS. Firmware will + * listen on mailbox command address, and once it receives the wakeup + * command, the CPU associated with the given apicid will be booted. + * + * The value of 'apic_id' and 'wakeup_vector' must be visible to the + * firmware before the wakeup command is visible. smp_store_release() + * ensures ordering and visibility. + */ + acpi_mp_wake_mailbox->apic_id = apicid; + acpi_mp_wake_mailbox->wakeup_vector = start_ip; + smp_store_release(&acpi_mp_wake_mailbox->command, + ACPI_MP_WAKE_COMMAND_WAKEUP); + + /* + * Wait for the CPU to wake up. + * + * The CPU being woken up is essentially in a spin loop waiting to be + * woken up. It should not take long for it wake up and acknowledge by + * zeroing out ->command. + * + * ACPI specification doesn't provide any guidance on how long kernel + * has to wait for a wake up acknowledgment. It also doesn't provide + * a way to cancel a wake up request if it takes too long. + * + * In TDX environment, the VMM has control over how long it takes to + * wake up secondary. It can postpone scheduling secondary vCPU + * indefinitely. Giving up on wake up request and reporting error opens + * possible attack vector for VMM: it can wake up a secondary CPU when + * kernel doesn't expect it. Wait until positive result of the wake up + * request. + */ + while (READ_ONCE(acpi_mp_wake_mailbox->command)) + cpu_relax(); + + return 0; +} + +void __init setup_mp_wakeup_mailbox(u64 mailbox_paddr) +{ + acpi_mp_wake_mailbox_paddr = mailbox_paddr; + apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); +} + +struct acpi_madt_multiproc_wakeup_mailbox *get_mp_wakeup_mailbox(void) +{ + return acpi_mp_wake_mailbox; +} +#endif From patchwork Sat May 3 19:15:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 887527 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EFDD27E7ED; Sat, 3 May 2025 19:10:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299415; cv=none; b=AtwbsIVgt5ATj6kW/cxGiIfUyuqalPcJSmJFY3MZboK59c3QoCIHDTArFr1xp2sLXKkcQr0mGL1JpzF9POggIZPGed8AY+VqKDl7nD/dTHGBdb5CE8CL5NzZkMATfLBV3x8ax7Uj1wj4LEY8qu8B9Un5uszx14BowQihifKckxM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299415; c=relaxed/simple; bh=Mm45ENIs0X8EBABbvMlBglzE/tjG4gJ+KwRueBg/+98=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=o04X9llMCvu8v6qiVYomOQMqx8BgTxk6FDPULCH3hHAyiK9HBC6dGAzr0+FErSJUCKpJ/u4m+9hFUZ2T5oSX4EuNQbP7BW30v/vgYZrGfXuhU+bgaUy9eM4G2GfxE0WDGv28aJJa7L34I+/wQG9SvMNtmGSnPHfeQk6N64gJU6A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Xkw92MiG; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Xkw92MiG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746299414; x=1777835414; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Mm45ENIs0X8EBABbvMlBglzE/tjG4gJ+KwRueBg/+98=; b=Xkw92MiGk47XRWZSuOJanMLNZfA9zAwk0btpzdrK92+vE0hSI0oSWUmr Gj3W2oNH0Ci3Je7pKX7DhF2KvMwF06VAv/EltskmemxTKj0awgmfQZwyf +PU+L/RgQHWM16KbboTXK7N4CD/+ZBoem2LtZ8sFRk8TOMogWIFgB0MUJ V4SiDFB0Cq8CY/8LTQ/uajOYLMqv94b0HYO/C7zXwe5Fn9yR/2O0NMzf7 mN5hvG2VGTh3yDw1/3M3pegb9YA3MCNTGOlEwEmr0JiG30F7Rwp8uBHGK Crb8xS3OoOHxJj23BQ3b3fRHbDciVu4bec38s1UKcZCcaE1RpcWUOF9sA A==; X-CSE-ConnectionGUID: af/qQsNJQ9ePcQfjnA6URw== X-CSE-MsgGUID: EMBhOsngSW+RAwNKu0qx7Q== X-IronPort-AV: E=McAfee;i="6700,10204,11422"; a="48095619" X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="48095619" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2025 12:10:12 -0700 X-CSE-ConnectionGUID: MUDMeDGRRW2YBJL7GUPhkA== X-CSE-MsgGUID: IlITNeJ2T3euc0JVo6FNew== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="140046091" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmviesa004.fm.intel.com with ESMTP; 03 May 2025 12:10:11 -0700 From: Ricardo Neri To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley Cc: devicetree@vger.kernel.org, Saurabh Sengar , Chris Oo , linux-hyperv@vger.kernel.org, "Kirill A. Shutemov" , linux-acpi@vger.kernel.org , linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri Subject: [PATCH v3 04/13] dt-bindings: x86: Add CPU bindings for x86 Date: Sat, 3 May 2025 12:15:06 -0700 Message-Id: <20250503191515.24041-5-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> References: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add bindings for CPUs in x86 architecture. Start by defining the `reg` and `enable-method` properties and their relationship to x86 APIC ID and the available mechanisms to boot secondary CPUs. Start defining bindings for Intel processors. Bindings for other vendors can be added later as needed. Signed-off-by: Ricardo Neri --- .../devicetree/bindings/x86/cpus.yaml | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/x86/cpus.yaml diff --git a/Documentation/devicetree/bindings/x86/cpus.yaml b/Documentation/devicetree/bindings/x86/cpus.yaml new file mode 100644 index 000000000000..108b3ad64aea --- /dev/null +++ b/Documentation/devicetree/bindings/x86/cpus.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/x86/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: x86 CPUs + +maintainers: + - Ricardo Neri + +description: | + Description of x86 CPUs in a system through the "cpus" node. + + Detailed information about the CPU architecture can be found in the Intel + Software Developer's Manual: + https://intel.com/sdm + +properties: + compatible: + enum: + - intel,x86 + + reg: + description: | + Local APIC ID of the CPU. If the CPU has more than one execution thread, + then the property is an array with one element per thread. + + enable-method: + $ref: /schemas/types.yaml#/definitions/string + description: | + The method used to wake up secondary CPUs. This property is not needed if + the secondary processors are booted using INIT assert, de-assert followed + by Start-Up IPI messages as described in the Volume 3, Section 11.4 of + Intel Software Developer's Manual. + + It is also optional for the bootstrap CPU. + + oneOf: + - items: + - const: intel,wakeup-mailbox + description: | + CPUs are woken up using the mailbox mechanism. The platform + firmware boots the secondary CPUs and puts them in a state + to check the mailbox for a wakeup command from the operating + system. + +required: + - reg + - compatible + +unevaluatedProperties: false + +examples: + - | + /* + * A system with two CPUs. cpu@0 is the bootstrap CPU and its status is + * "okay". It does not have the enable-method property. cpu@1 is a + * secondary CPU. Its status is "disabled" and defines the enable-method + * property. + */ + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + reg = <0x0 0x1>; + compatible = "intel,x86"; + status = "okay"; + }; + + cpu@1 { + reg = <0x0 0x1>; + compatible = "intel,x86"; + status = "disabled"; + enable-method = "intel,wakeup-mailbox"; + }; + }; + From patchwork Sat May 3 19:15:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 887526 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2815327EC98; Sat, 3 May 2025 19:10:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299417; cv=none; b=UaSDebP5zTPFyrSfhQbJLiNutfuVTImmfCwzDkLm13ARB+0V50JSggM+otanbzdRMLKUlLlsn4Mexxc+YusQv1lBcSeHoCUzu1dt3i85BPAVtUsio8lGSh9eFhL14eOM5QqCAFCEguI37kUADDSzfIG/YPFnOljvUCf5aNe++IY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299417; c=relaxed/simple; bh=BaLb2QakL7PuMfqddKhuZkTxakaJyY5sp9hXxk46Dug=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=e35mlDlGdaOPNy6H1syzda66IiLLwtF8XiQHXON1xde0rAlRW8vC6ZzWigjiOFz6eCe6Oa40oPrSPQ6SCwmOjq2nRiX1FiXqZW+acJm+sJYF3v3CEE+ViGJhNZ0pid4Fgh3QjgUlNBIsdlxJCC9Qm0ZA4MCV8C/ov9bc+weOZxs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZKoA87e+; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZKoA87e+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746299415; x=1777835415; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=BaLb2QakL7PuMfqddKhuZkTxakaJyY5sp9hXxk46Dug=; b=ZKoA87e+AxUudKrKpmytrP5MBs0rbm8vSEEqE9n9ZBHHek4ASz87ccSD zY2u6Btho4Um4CbH6UrfXaqf44jN0M/BsVru/xSxFTvkGKtelVgOCzmeF zuJSKyRFSQEHREY7X7nYA5oklxTbvl4phQUM6wHXl+WAF4EJ/bp5gTOzR DFjwdfBjmF5jV7W74bfKVwOj347lMDamx4k6RmW29YGTJpCsTyLW22/oy +WyRfOcHcLbARcoQA53+mCX/Y6SvZJLkAJIlhMb6SnlkIc6BmFiITOP4H 5Z//1ILKQSXAxeWhIwdXsiNdVEPKcmmkW+boE9/zGOGl1pUmJ1gYKmPTb w==; X-CSE-ConnectionGUID: fiWnhD0eQK220+uRd2eu7g== X-CSE-MsgGUID: MJtYF9HaRgGuJeuBnnT9tA== X-IronPort-AV: E=McAfee;i="6700,10204,11422"; a="48095624" X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="48095624" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2025 12:10:13 -0700 X-CSE-ConnectionGUID: I7xJ/xtGQB6Cuffp6pMekw== X-CSE-MsgGUID: 3uKN/U4zS8WwXlkbDgETuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="140046094" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmviesa004.fm.intel.com with ESMTP; 03 May 2025 12:10:12 -0700 From: Ricardo Neri To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley Cc: devicetree@vger.kernel.org, Saurabh Sengar , Chris Oo , linux-hyperv@vger.kernel.org, "Kirill A. Shutemov" , linux-acpi@vger.kernel.org , linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri Subject: [PATCH v3 05/13] x86/dt: Parse the `enable-method` property of CPU nodes Date: Sat, 3 May 2025 12:15:07 -0700 Message-Id: <20250503191515.24041-6-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> References: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add functionality to parse and validate the `enable-method` property for platforms that use alternative methods to wakeup secondary CPUs (e.g., a wakeup mailbox). Most x86 platforms boot secondary CPUs using INIT assert, de-assert followed by a Start-Up IPI messages. These systems do no need to specify an `enable-method` property in the cpu@N nodes of the DeviceTree. Although it is possible to specify a different `enable-method` for each secondary CPU, the existing functionality relies on using the APIC wakeup_secondary_cpu{ (), _64()} callback to wake up all CPUs. Ensure that either all CPUs specify the same `enable-method` or none at all. Signed-off-by: Ricardo Neri --- Changes since v2: - Introduced this patch. Changes since v1: - N/A --- arch/x86/kernel/devicetree.c | 88 +++++++++++++++++++++++++++++++++++- 1 file changed, 86 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index dd8748c45529..5835afc74acd 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -127,8 +127,59 @@ static void __init dtb_setup_hpet(void) #ifdef CONFIG_X86_LOCAL_APIC +#ifdef CONFIG_SMP +static const char *dtb_supported_enable_methods[] __initconst = { }; + +static bool __init dtb_enable_method_is_valid(const char *enable_method_a, + const char *enable_method_b) +{ + int i; + + if (!enable_method_a && !enable_method_b) + return true; + + if (strcmp(enable_method_a, enable_method_b)) + return false; + + for (i = 0; i < ARRAY_SIZE(dtb_supported_enable_methods); i++) { + if (!strcmp(enable_method_a, dtb_supported_enable_methods[i])) + return true; + } + + return false; +} + +static int __init dtb_configure_enable_method(const char *enable_method) +{ + /* Nothing to do for a missing enable-method or if the system has one CPU */ + if (!enable_method || IS_ERR(enable_method)) + return 0; + + return -ENOTSUPP; +} +#else /* !CONFIG_SMP */ +static inline bool dtb_enable_method_is_valid(const char *enable_method_a, + const char *enable_method_b) +{ + /* No secondary CPUs. We do not care about the enable-method. */ + return true; +} + +static inline int dtb_configure_enable_method(const char *enable_method) +{ + return 0; +} +#endif /* CONFIG_SMP */ + +static void __init dtb_register_apic_id(u32 apic_id, struct device_node *dn) +{ + topology_register_apic(apic_id, CPU_ACPIID_INVALID, true); + set_apicid_to_node(apic_id, of_node_to_nid(dn)); +} + static void __init dtb_cpu_setup(void) { + const char *enable_method = ERR_PTR(-EINVAL), *this_em; struct device_node *dn; u32 apic_id; @@ -138,9 +189,42 @@ static void __init dtb_cpu_setup(void) pr_warn("%pOF: missing local APIC ID\n", dn); continue; } - topology_register_apic(apic_id, CPU_ACPIID_INVALID, true); - set_apicid_to_node(apic_id, of_node_to_nid(dn)); + + /* + * Also check the enable-method of the secondary CPUs, if present. + * + * Systems that use the INIT-!INIT-StartUp IPI sequence to boot + * secondary CPUs do not need to define an enable-method. + * + * All CPUs must have the same enable-method. The enable-method + * must be supported. If absent in one secondary CPU, it must be + * absent for all CPUs. + * + * Compare the first secondary CPU with the rest. We do not care + * about the boot CPU, as it is enabled already. + */ + + if (apic_id == boot_cpu_physical_apicid) { + dtb_register_apic_id(apic_id, dn); + continue; + } + + this_em = of_get_property(dn, "enable-method", NULL); + + if (IS_ERR(enable_method)) { + enable_method = this_em; + dtb_register_apic_id(apic_id, dn); + continue; + } + + if (!dtb_enable_method_is_valid(enable_method, this_em)) + continue; + + dtb_register_apic_id(apic_id, dn); } + + if (dtb_configure_enable_method(enable_method)) + pr_err("enable-method '%s' needed but not configured\n", enable_method); } static void __init dtb_lapic_setup(void) From patchwork Sat May 3 19:15:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 887007 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7A9427F720; Sat, 3 May 2025 19:10:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299417; cv=none; b=irfRCzpTPtyWT058KahgKCUn/1EQMuWhStGw1R81l1/uLx630Kpcx+qMJGiy+EBV7Rjzsxj1OqpNThleog9zw7so2N1JGzDwAO8C6FX4cwUMsRA11X4uYzIlVJb82iswzYNPTQCaplGi+Ix2QKEaDdu03XZgbb/DK0ODaABFeOQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299417; c=relaxed/simple; bh=wTx5/iOJcza0p8s8BG5SJVFyK91RfaaB8NxoOR0pRRk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=UN9Bh7fsLnrZFKd3i97XGrhQFYeL/ixhQtzMoUD7qF2r/ot+Qr5W2nSlZudgbPcdu2Dob6Grzf/vWsD7/mGy/6J/Y9wgArE33WrTQvc4BflbNhKJ7Dd6PRCbVNA7noqRZxs44w5PMD1JZ95bxsOyy95ihRElldhllsZeP0GrKhg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CHUaGMjs; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CHUaGMjs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746299416; x=1777835416; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=wTx5/iOJcza0p8s8BG5SJVFyK91RfaaB8NxoOR0pRRk=; b=CHUaGMjsT7IxVfu1BhaoM3gap7V2udBfeWcU5bYsf2dp4vdgiEqf0vqq OdENMFxvyfeZSan2eZ3k1GWg+8QMZ282s5renwOw9oYlHv9uoZwojU+li ZglALUgz1uwTyq0XYgY25sKb1qruZ7OyUBF1wLAVMU61edYECjiDU+VCF gA4vlBloy5zZE1IDZW5zwUnsxir371vg0bbEBWLVqZTM9xRhaR/TkAC8k Ou0feSpK8T3Xs13rCB+DdNYNl8rlfAWufptVgP7r5WepzqhcDfu/SK7TB vodE/8WeyH5argXoLmsdW8uI6KgQjXDyzC8M4haOpdqZmLaffWNwWwrBr A==; X-CSE-ConnectionGUID: rDH+oDFhQtiJ1KLH9Ubt7Q== X-CSE-MsgGUID: FtE2UcXjQl+drehsZGOrMA== X-IronPort-AV: E=McAfee;i="6700,10204,11422"; a="48095629" X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="48095629" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2025 12:10:13 -0700 X-CSE-ConnectionGUID: 30VHknrlRmiUEXLJ1DNokQ== X-CSE-MsgGUID: Hcm5FjxaTkGd/DLZ8YfWWQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="140046098" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmviesa004.fm.intel.com with ESMTP; 03 May 2025 12:10:12 -0700 From: Ricardo Neri To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley Cc: devicetree@vger.kernel.org, Saurabh Sengar , Chris Oo , linux-hyperv@vger.kernel.org, "Kirill A. Shutemov" , linux-acpi@vger.kernel.org , linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri Subject: [PATCH v3 06/13] dt-bindings: reserved-memory: Wakeup Mailbox for Intel processors Date: Sat, 3 May 2025 12:15:08 -0700 Message-Id: <20250503191515.24041-7-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> References: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add DeviceTree bindings for the wakeup mailbox used on Intel processors. x86 platforms commonly boot secondary CPUs using an INIT assert, de-assert followed by Start-Up IPI messages. The wakeup mailbox can be used when this mechanism unavailable. The wakeup mailbox offers more control to the operating system to boot secondary CPUs than a spin-table. It allows the reuse of same wakeup vector for all CPUs while maintaining control over which CPUs to boot and when. While it is possible to achieve the same level of control using a spin- table, it would require to specify a separate cpu-release-addr for each secondary CPU. Originally-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v2: - Implemented the mailbox as a reserved-memory node. Add to it a `compatible` property. (Krzysztof) - Explained the relationship between the mailbox and the `enable-mehod` property of the CPU nodes. - Expanded the documentation of the binding. Changes since v1: - Added more details to the description of the binding. - Added requirement a new requirement for cpu@N nodes to add an `enable-method`. --- .../reserved-memory/intel,wakeup-mailbox.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml diff --git a/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml b/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml new file mode 100644 index 000000000000..d97755b4673d --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/intel,wakeup-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Wakeup Mailbox for Intel processors + +description: | + The Wakeup Mailbox provides a mechanism for the operating system to wake up + secondary CPUs on Intel processors. It is an alternative to the INIT-!INIT- + SIPI sequence used on most x86 systems. + + Firmware must define the enable-method property in the CPU nodes as + "intel,wakeup-mailbox" to use the mailbox. + + Firmware implements the wakeup mailbox as a 4KB-aligned memory region of size + of 4KB. It is memory that the firmware reserves so that each secondary CPU can + have the operating system send a single message to them. The firmware is + responsible for putting the secondary CPUs in a state to check the mailbox. + + The structure of the mailbox is as follows: + + Field Byte Byte Description + Length Offset + ------------------------------------------------------------------------------ + Command 2 0 Command to wake up the secondary CPU: + 0: Noop + 1: Wakeup: Jump to the wakeup_vector + 2-0xFFFF: Reserved: + Reserved 2 2 Must be 0. + APIC_ID 4 4 APIC ID of the secondary CPU to wake up. + Wakeup_Vector 8 8 The wakeup address for the secondary CPU. + ReservedForOs 2032 16 Reserved for OS use. + ReservedForFW 2048 2048 Reserved for firmware use. + ------------------------------------------------------------------------------ + + To wake up a secondary CPU, the operating system 1) prepares the wakeup + routine; 2) populates the address of the wakeup routine address into the + Wakeup_Vector field; 3) populates the APIC_ID field with the APIC ID of the + secondary CPU; 4) writes Wakeup in the Command field. Upon receiving the + Wakeup command, the secondary CPU acknowledges the command by writing Noop in + the Command field and jumps to the Wakeup_Vector. The operating system can + send the next command only after the Command field is changed to Noop. + + The secondary CPU will no longer check the mailbox after waking up. The + secondary CPU must ignore the command if its APIC_ID written in the mailbox + does not match its own. + + When entering the Wakeup_Vector, interrupts must be disabled and 64-bit + addressing mode must be enabled. Paging mode must be enabled. The virtual + address of the Wakeup_Vector page must be equal to its physical address. + Segment selectors are not used. + +maintainers: + - Ricardo Neri + +allOf: + - $ref: reserved-memory.yaml + +properties: + compatible: + const: intel,wakeup-mailbox + + alignment: + description: The mailbox must be 4KB-aligned. + const: 0x1000 + +required: + - compatible + - alignment + - reg + +unevaluatedProperties: false + +examples: + - | + reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + + wakeup-mailbox@12340000 { + compatible = "intel,wakeup-mailbox"; + alignment = <0x1000>; + reg = <0x0 0x12340000 0x1000>; + }; + }; From patchwork Sat May 3 19:15:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 887525 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B16E27F738; Sat, 3 May 2025 19:10:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299417; cv=none; b=QIGVpUCmnWd3l1XcM5Sau34O5lKkCqHBA52tOQEJK55lmmedveDGaxRM3YyGK5ex2/0FjRVThjyT1ND9uf+tw9MtMKAbIWWpO1TlA+7e6XwFmP0rqUaxNP6wkLEPRsMiH/wb1sU5ZCoHe3BM2D69zOs6x6rrz5kIMBeXQAevgpA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299417; c=relaxed/simple; bh=8yh12neJuVAsQUujZm/Vfdbuz1pj4bfgQ7MsKN5YAU4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=UraiaB/t5qLM2Y2ls3awRuAiPvcnzsfweYYfrO2jm5NSUwXT0IfGC/xocPs6n81S3U4OpHtuwmwiUDIb0voRN04VqQIUeJQh5iKvPmjFrRWgGTipJs2a9r02HHboPWSu+dzNT/p74LTz83ZfgulNBlRRPDlPigVKY/b3sYWJLE4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mfyg5vhd; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mfyg5vhd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746299416; x=1777835416; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=8yh12neJuVAsQUujZm/Vfdbuz1pj4bfgQ7MsKN5YAU4=; b=mfyg5vhdmOxxW3bfUSG9GpjFLT3vT2HBUj3l5/QQEJzOO08gpLE+DhI8 sgjeUq396qrtMw3LBvjmRNcOR6yQG52PAe7rHEFPJgPa2e5niouknZ3h9 3FEaMMzP3nSGe8PCjkA4BrDLh11eqAvHHc+eQpacLJ2EeszDs6T1lCHST xW1oTBVcx9Rx+NRdYNXN4RJcfPbZEBSFRKCy3x8peeqt4+zomIxAJzE+6 kl4+5djaD3vTC0p+ghPElJqypuPHUJU9SCwZ+ReAb5eBq7ot66WqCu2wg w3wgFsuA2rT077UTrhKt0Mp7DvDtZDhYOTjATkcEHEkGUyzxrQ07BWRYR Q==; X-CSE-ConnectionGUID: yhx4rgsPR9Chv8/COuw3XA== X-CSE-MsgGUID: kSoVO3/qTHywrTGiot5qSA== X-IronPort-AV: E=McAfee;i="6700,10204,11422"; a="48095634" X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="48095634" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2025 12:10:14 -0700 X-CSE-ConnectionGUID: j0CcJvp3TlG/WY77LKjhhw== X-CSE-MsgGUID: NZWvzE9CTBKfxfhmtAB56w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="140046101" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmviesa004.fm.intel.com with ESMTP; 03 May 2025 12:10:13 -0700 From: Ricardo Neri To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley Cc: devicetree@vger.kernel.org, Saurabh Sengar , Chris Oo , linux-hyperv@vger.kernel.org, "Kirill A. Shutemov" , linux-acpi@vger.kernel.org , linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri Subject: [PATCH v3 07/13] x86/dt: Parse the Wakeup Mailbox for Intel processors Date: Sat, 3 May 2025 12:15:09 -0700 Message-Id: <20250503191515.24041-8-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> References: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The Wakeup Mailbox is a mechanism to boot secondary CPUs used on systems that do not want or cannot use the INIT + StartUp IPI messages. Add `intel,wakeup-mailbox` to the set of supported enable methods. Also add functionality to find and parse the parameters of the mailbox from the DeviceTree from the platform firmware. The operation and structure of the Wakeup Mailbox are described in the corresponding DeviceTree schema that accompanies the documentation of the Linux kernel. The Wakeup Mailbox is compatible with the Multiprocessor Wakeup Mailbox Structure described in the ACPI specification. Reuse the existing functionality to set the memory location of the mailbox and update the wakeup_secondary_cpu_64() APIC callback. do_boot_cpu() uses wakeup_secondary_cpu_64() when set. If a wakeup mailbox is found (enumerated via an ACPI table or a DeviceTree node) it will be used unconditionally. For cases in which this behavior is not desired, this APIC callback can be updated later during boot using platform-specific hooks. Originally-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v2: - Added extra sanity checks when parsing the mailbox node. - Probe the mailbox using its `compatible` property - Setup the Wakeup Mailbox if the `enable-method` is found in the CPU nodes. - Cleaned up unneeded ifdeffery. - Clarified the mechanisms used to override the wakeup_secondary_64() callback to not use the mailbox when not desired. (Michael) - Edited the commit message for clarity. Changes since v1: - Disabled CPU offlining. - Modified dtb_parse_mp_wake() to return the address of the mailbox. --- arch/x86/kernel/devicetree.c | 57 ++++++++++++++++++++++++++++++++++-- 1 file changed, 55 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index 5835afc74acd..d03d9e23c693 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -128,7 +129,59 @@ static void __init dtb_setup_hpet(void) #ifdef CONFIG_X86_LOCAL_APIC #ifdef CONFIG_SMP -static const char *dtb_supported_enable_methods[] __initconst = { }; + +#ifdef CONFIG_X86_64 + +#define WAKEUP_MAILBOX_SIZE 0x1000 +#define WAKEUP_MAILBOX_ALIGN 0x1000 + +static int __init dtb_parse_wakeup_mailbox(const char *enable_method) +{ + struct device_node *node; + struct resource res; + int ret = 0; + + if (strcmp(enable_method, "intel,wakeup-mailbox")) + return -EINVAL; + + node = of_find_compatible_node(NULL, NULL, "intel,wakeup-mailbox"); + if (!node) + return -ENODEV; + + ret = of_address_to_resource(node, 0, &res); + if (ret) + goto done; + + /* The mailbox is a 4KB-aligned region.*/ + if (res.start & (WAKEUP_MAILBOX_ALIGN - 1)) { + ret = -EINVAL; + goto done; + } + + /* The mailbox has a size of 4KB. */ + if (res.end - res.start + 1 != WAKEUP_MAILBOX_SIZE) { + ret = -EINVAL; + goto done; + } + + /* Not supported when the mailbox is used. */ + cpu_hotplug_disable_offlining(); + + setup_mp_wakeup_mailbox(res.start); +done: + of_node_put(node); + return ret; +} +#else /* !CONFIG_X86_64 */ +static inline int dtb_parse_wakeup_mailbox(const char *enable_method) +{ + return -ENOTSUPP; +} +#endif /* CONFIG_X86_64 */ + +static const char *dtb_supported_enable_methods[] __initconst = { + "intel,wakeup-mailbox" +}; static bool __init dtb_enable_method_is_valid(const char *enable_method_a, const char *enable_method_b) @@ -155,7 +208,7 @@ static int __init dtb_configure_enable_method(const char *enable_method) if (!enable_method || IS_ERR(enable_method)) return 0; - return -ENOTSUPP; + return dtb_parse_wakeup_mailbox(enable_method); } #else /* !CONFIG_SMP */ static inline bool dtb_enable_method_is_valid(const char *enable_method_a, From patchwork Sat May 3 19:15:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 887006 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28AD227FD4D; Sat, 3 May 2025 19:10:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299418; cv=none; b=AMQfeaXmv8/hZi2ubaGeUaFV12jvIOhSvK0YWS0EyEK+zCXBKZpRtOM0eg+XTD4zXIOiJr6qq3iIl6fV3yZQSoghk/J+NZzddbziQeMwDmViFvS71MHvn2Uq+ORqiWx3jko+B7y1aPFulEIPP5J7+xhGaJBPJ8EwMcU/QesWk+w= ARC-Message-Signature: i=1; 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d="scan'208";a="140046107" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmviesa004.fm.intel.com with ESMTP; 03 May 2025 12:10:13 -0700 From: Ricardo Neri To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley Cc: devicetree@vger.kernel.org, Saurabh Sengar , Chris Oo , linux-hyperv@vger.kernel.org, "Kirill A. Shutemov" , linux-acpi@vger.kernel.org , linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri Subject: [PATCH v3 08/13] x86/hyperv/vtl: Set real_mode_header in hv_vtl_init_platform() Date: Sat, 3 May 2025 12:15:10 -0700 Message-Id: <20250503191515.24041-9-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> References: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: From: Yunhong Jiang Hyper-V VTL clears x86_platform.realmode_{init(), reserve()} in hv_vtl_platform_init() whereas it sets real_mode_header later in hv_vtl_early_init(). There is no need to deal with the real mode memory in two places: x86_platform.realmode_init() is invoked much later via an early_initcall. Set real_mode_header in hv_vtl_init_platform() to keep all code dealing with memory for the real mode trampoline in one place. Besides making the code more readable, it prepares it for a subsequent changeset in which the behavior needs to change to support Hyper-V VTL guests in TDX environment. Suggested-by: Thomas Gleixner Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v2: - Edited the commit message for clarity. Changes since v1: - Introduced this patch. --- arch/x86/hyperv/hv_vtl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 4580936dcb03..6bd183ee484f 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -60,6 +60,7 @@ void __init hv_vtl_init_platform(void) x86_platform.realmode_reserve = x86_init_noop; x86_platform.realmode_init = x86_init_noop; + real_mode_header = &hv_vtl_real_mode_header; x86_init.irqs.pre_vector_init = x86_init_noop; x86_init.timers.timer_init = x86_init_noop; x86_init.resources.probe_roms = x86_init_noop; @@ -279,7 +280,6 @@ int __init hv_vtl_early_init(void) panic("XSAVE has to be disabled as it is not supported by this module.\n" "Please add 'noxsave' to the kernel command line.\n"); - real_mode_header = &hv_vtl_real_mode_header; apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cpu); return 0; From patchwork Sat May 3 19:15:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 887524 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C80A327FD75; Sat, 3 May 2025 19:10:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299419; cv=none; b=FTQQ7WRrblkcaqWZjSEYQO2JPJYzhBHSbKVO5ZqZNqheVGqYuLQZZP8mVtgoJCET6vzy3xiOiYr6jUlpUmaK0ghbwAyfh+muCZeK8+VS/0Ia56NYrkVu5MK2oYANauTNHxoSuToqY6B84RSgrXU1ob06FMGoJ7FIphZS2LVE8+4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299419; c=relaxed/simple; bh=B6axyb2KV+UrgzmgnYGTQ1Bq6srlUV5UH9OE6so1vs8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=SHyFkhV8XJRilxC4DXR2CJW6Jj/HSO8ZA/C0mYXe2KTPayGaAvVpLY+Sf6AbVXzH/tJUQ7yESdo4B0T7+lw6bA8fcp/8pbmUBVIIgiUOb+vLd5BxIn+sc4Anr9QnzTqTyiOHsjJcG8Em7fgGAm/W5qp8VQQwk7sq0RkpSjEQO6Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=J833lDcj; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="J833lDcj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746299418; x=1777835418; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=B6axyb2KV+UrgzmgnYGTQ1Bq6srlUV5UH9OE6so1vs8=; b=J833lDcjdHmbu5QU+U7M4ZfJm2Of6kWn54I6PBsJyPKrByjgOqFgIOB/ dit1yP6abZMCfobYigIgris1tPzwcNu0PS2tzY/T+bLS6b854j9ur1dut 2l/+7WasTJjjZ/5ttJLrgE963pif9UcGILjFjvDV9ieKCQdMhh/pRSQ6a Mt5asMIbyB3ZJ77wLa7s/JL8aHBrU8Fn0DQhJVfglojWnOT8fgPVJybP5 Wbs03FqLk0x7qJwU7BRR2ZmHdxvPPU9/PRACBjaDZhpk52iUaeZ5Vmjp+ e/GkHFAfQXvWJ5vn26jjwqAmXHotHu2nrf9bO93Sj4oVnv+S6A1yKPADR w==; X-CSE-ConnectionGUID: y/FTjRvZRMiq4NtTRLSFcg== X-CSE-MsgGUID: xZF+YUHfTHq6pq+UMAcL8g== X-IronPort-AV: E=McAfee;i="6700,10204,11422"; a="48095645" X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="48095645" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2025 12:10:15 -0700 X-CSE-ConnectionGUID: mYiZvxssRQKfRCxJsOJ0YA== X-CSE-MsgGUID: ius8xGQMTKC5F3k4ygrgLQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="140046110" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmviesa004.fm.intel.com with ESMTP; 03 May 2025 12:10:14 -0700 From: Ricardo Neri To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley Cc: devicetree@vger.kernel.org, Saurabh Sengar , Chris Oo , linux-hyperv@vger.kernel.org, "Kirill A. Shutemov" , linux-acpi@vger.kernel.org , linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri Subject: [PATCH v3 09/13] x86/realmode: Make the location of the trampoline configurable Date: Sat, 3 May 2025 12:15:11 -0700 Message-Id: <20250503191515.24041-10-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> References: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: From: Yunhong Jiang x86 CPUs boot in real mode. This mode uses 20-bit memory addresses (16-bit registers plus 4-bit segment selectors). This implies that the trampoline must reside under the 1MB memory boundary. There are platforms in which the firmware boots the secondary CPUs, switches them to long mode and transfers control to the kernel. An example of such mechanism is the ACPI Multiprocessor Wakeup Structure. In this scenario there is no restriction to locate the trampoline under 1MB memory. Moreover, certain platforms (for example, Hyper-V VTL guests) may not have memory available for allocation under 1MB. Add a new member to struct x86_init_resources to specify the upper bound for the location of the trampoline memory. Keep the default upper bound of 1MB to conserve the current behavior. Originally-by: Thomas Gleixner Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v2: - Edited the commit message for clarity. - Minor tweaks to comments. - Removed the option to not reserve the first 1MB of memory as it is not needed. Changes since v1: - Added this patch using code that Thomas suggested: https://lore.kernel.org/lkml/87a5ho2q6x.ffs@tglx/ --- arch/x86/include/asm/x86_init.h | 3 +++ arch/x86/kernel/x86_init.c | 3 +++ arch/x86/realmode/init.c | 7 +++---- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h index 36698cc9fb44..e770ce507a87 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -31,12 +31,15 @@ struct x86_init_mpparse { * platform * @memory_setup: platform specific memory setup * @dmi_setup: platform specific DMI setup + * @realmode_limit: platform specific address limit for the real mode trampoline + * (default 1M) */ struct x86_init_resources { void (*probe_roms)(void); void (*reserve_resources)(void); char *(*memory_setup)(void); void (*dmi_setup)(void); + unsigned long realmode_limit; }; /** diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index 0a2bbd674a6d..a25fd7282811 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -69,6 +70,8 @@ struct x86_init_ops x86_init __initdata = { .reserve_resources = reserve_standard_io_resources, .memory_setup = e820__memory_setup_default, .dmi_setup = dmi_setup, + /* Has to be under 1M so we can execute real-mode AP code. */ + .realmode_limit = SZ_1M, }, .mpparse = { diff --git a/arch/x86/realmode/init.c b/arch/x86/realmode/init.c index ed5c63c0b4e5..01155f995b2b 100644 --- a/arch/x86/realmode/init.c +++ b/arch/x86/realmode/init.c @@ -46,7 +46,7 @@ void load_trampoline_pgtable(void) void __init reserve_real_mode(void) { - phys_addr_t mem; + phys_addr_t mem, limit = x86_init.resources.realmode_limit; size_t size = real_mode_size_needed(); if (!size) @@ -54,10 +54,9 @@ void __init reserve_real_mode(void) WARN_ON(slab_is_available()); - /* Has to be under 1M so we can execute real-mode AP code. */ - mem = memblock_phys_alloc_range(size, PAGE_SIZE, 0, 1<<20); + mem = memblock_phys_alloc_range(size, PAGE_SIZE, 0, limit); if (!mem) - pr_info("No sub-1M memory is available for the trampoline\n"); + pr_info("No memory below %pa for the real-mode trampoline\n", &limit); else set_real_mode_mem(mem); From patchwork Sat May 3 19:15:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 887005 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B1C9280309; Sat, 3 May 2025 19:10:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="48095651" X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="48095651" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2025 12:10:15 -0700 X-CSE-ConnectionGUID: 3BIjFLjoRcy2YFC8rrVosQ== X-CSE-MsgGUID: MjcGbIRPTVCmjnr/bIX9kA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="140046114" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmviesa004.fm.intel.com with ESMTP; 03 May 2025 12:10:14 -0700 From: Ricardo Neri To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley Cc: devicetree@vger.kernel.org, Saurabh Sengar , Chris Oo , linux-hyperv@vger.kernel.org, "Kirill A. Shutemov" , linux-acpi@vger.kernel.org , linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri Subject: [PATCH v3 10/13] x86/hyperv/vtl: Setup the 64-bit trampoline for TDX guests Date: Sat, 3 May 2025 12:15:12 -0700 Message-Id: <20250503191515.24041-11-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> References: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: From: Yunhong Jiang The hypervisor is an untrusted entity for TDX guests. It cannot be used to boot secondary CPUs - neither via hypercalls not the INIT assert, de-assert plus Start-Up IPI messages. Instead, the platform virtual firmware boots the secondary CPUs and puts them in a state to transfer control to the kernel. This mechanism uses the wakeup mailbox described in the Multiprocessor Wakeup Structure of the ACPI specification. The entry point to the kernel is trampoline_start64. Allocate and setup the trampoline using the default x86_platform callbacks. The platform firmware configures the secondary CPUs in long mode. It is no longer necessary to locate the trampoline under 1MB memory. After handoff from firmware, the trampoline code switches briefly to 32-bit addressing mode, which has an addressing limit of 4GB. Set the upper bound of the trampoline memory accordingly. Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v2: - Added a note regarding there is no need to check for a present paravisor. - Edited commit message for clarity. Changes since v1: - Dropped the function hv_reserve_real_mode(). Instead, used the new members realmode_limit and reserve_bios members of x86_init to set the upper bound of the trampoline memory. (Thomas) --- arch/x86/hyperv/hv_vtl.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 6bd183ee484f..8b497c8292d3 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -58,9 +58,14 @@ void __init hv_vtl_init_platform(void) { pr_info("Linux runs in Hyper-V Virtual Trust Level\n"); - x86_platform.realmode_reserve = x86_init_noop; - x86_platform.realmode_init = x86_init_noop; - real_mode_header = &hv_vtl_real_mode_header; + /* There is no paravisor present if we are here. */ + if (hv_isolation_type_tdx()) { + x86_init.resources.realmode_limit = SZ_4G; + } else { + x86_platform.realmode_reserve = x86_init_noop; + x86_platform.realmode_init = x86_init_noop; + real_mode_header = &hv_vtl_real_mode_header; + } x86_init.irqs.pre_vector_init = x86_init_noop; x86_init.timers.timer_init = x86_init_noop; x86_init.resources.probe_roms = x86_init_noop; From patchwork Sat May 3 19:15:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 887523 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 001B8280A21; Sat, 3 May 2025 19:10:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299420; cv=none; b=ZsKi+yxppihKf7NLVi8/GaFNwxV24U0nsTI5ullCTFrBWcaTp2Jm10VTD0aVMhVNOxLxBmRYD7fhMxOQfGUQoi72A8MFFZvxT4SEJVU91e9+CngJ+QVqsbI1WBWq2sBoVVchsHkKlOJ2PyfLcnFmC0NjduHp1sryy51LlBGftro= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299420; c=relaxed/simple; bh=V/Xkg7yztJbvfzhW1m8IZa8xRkZUWnqLeYD/o43R6SA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=fUhP2HhygAXGmP2Ic3cR5eamw9K2vl1HUzK7A82A9KDngijxFG4Y1GrBBiGWcK7W855XN1XDKURg4eZntuuXJtL1FHx4UJF7boZoU1a/XCTG2/RvGDKB9Lrp7SBxjyGIT2gJncSfT6xDZiroZFFyuq0Whv5rS4KUrU7dWtyvW+M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=V9WHCtgJ; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="V9WHCtgJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746299419; x=1777835419; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=V/Xkg7yztJbvfzhW1m8IZa8xRkZUWnqLeYD/o43R6SA=; b=V9WHCtgJBnRh9sq8tqVwLiTkXuMns+l2texgQ1u8TphwoD21nTh7v4ST 54Ru7sa832aB6hipbMHDkIJ+NVBjZ1PVj8hA535uAm19iKn/eJUFTbr0Y h/B9DCvTJ9GfvONAoNbrV1Pl7Sub6b179gjRwXerDCgl4auc//qVwcxkh 0+KPIriUarpBvRrJ02bHdmtnxz1gx19zSTuDAz6lwjPXC67PdNVHaqPpn 28Lpa3WBBp/Rv7kwuCiYylccAEa/FMwta4Rjg7JcJBV3dHiBRv4gNsH+2 Xlq2+y6nBxRbFhxvTQhwpSBGdf4ehursGa2Y07asTnAO9ayLwtQljWH4u Q==; X-CSE-ConnectionGUID: KPDJa/4tT8KijalqAdtn2Q== X-CSE-MsgGUID: fGLSD22zQSm2RzrcW4Oiqw== X-IronPort-AV: E=McAfee;i="6700,10204,11422"; a="48095656" X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="48095656" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2025 12:10:16 -0700 X-CSE-ConnectionGUID: SYXTj6XjTw+94e88nzCb/w== X-CSE-MsgGUID: DEDs71WMSDm3TeRqzmbe+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="140046118" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmviesa004.fm.intel.com with ESMTP; 03 May 2025 12:10:15 -0700 From: Ricardo Neri To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley Cc: devicetree@vger.kernel.org, Saurabh Sengar , Chris Oo , linux-hyperv@vger.kernel.org, "Kirill A. Shutemov" , linux-acpi@vger.kernel.org , linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri Subject: [PATCH v3 11/13] x86/smpboot: Add a helper get the address of the wakeup mailbox Date: Sat, 3 May 2025 12:15:13 -0700 Message-Id: <20250503191515.24041-12-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> References: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: A Hyper-V VTL level 2 guest on a TDX environment needs to map the physical page of the ACPI Multiprocessor Wakeup Structure as private (encrypted). It needs to know the physical address of this structure. Add a helper function. Suggested-by: Michael Kelley Signed-off-by: Ricardo Neri --- Changes since v2: - Introduced this patch Changes since v1: - N/A --- arch/x86/include/asm/smp.h | 1 + arch/x86/kernel/smpboot.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index 97bfbd0d24d4..18003453569a 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -149,6 +149,7 @@ static inline struct cpumask *cpu_l2c_shared_mask(int cpu) #ifdef CONFIG_X86_64 void setup_mp_wakeup_mailbox(u64 addr); struct acpi_madt_multiproc_wakeup_mailbox *get_mp_wakeup_mailbox(void); +u64 get_mp_wakeup_mailbox_paddr(void); #endif #else /* !CONFIG_SMP */ diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 6f39ebe4d192..1e211c78c1d3 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1431,4 +1431,9 @@ struct acpi_madt_multiproc_wakeup_mailbox *get_mp_wakeup_mailbox(void) { return acpi_mp_wake_mailbox; } + +u64 get_mp_wakeup_mailbox_paddr(void) +{ + return acpi_mp_wake_mailbox_paddr; +} #endif From patchwork Sat May 3 19:15:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 887004 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F00F6280CD0; Sat, 3 May 2025 19:10:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299421; cv=none; b=RlBgAR7mJzwhDwMTXOO4UGLPPdY5Thj91XWXW+hSl9gJcHiCtoSko7CBBwmnCmG6xKiBAK3ZRjhHJgy1BX0SoKtW+nXJSTjNYkeXGzzieXRdZTWoqd1Nea048qnGZizfGFbvX3qW9bn3/+C6XToTWnJZYyrlVrOnHOf2SKwGTBE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299421; c=relaxed/simple; bh=BWV+hPZ8NwIXIk/iN6QTrvYj4GcwemlrTx2HSjeDVEg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=SsYGtwswLwGprsCndVpbplBdRozU2Mi/WGhvctp56Df552KsMZTp7QPHqdcwnyuyijUcMgkqIX/C6qz0G425dWoOc7MAjKpEhGILNVFA7xaAG5IftI6nN6LkIao/9jCxCKeNKiUWS23zZqvCuL+p1XzdEIvmuOyZu+G/+dcWzYM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MUPuLdbv; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MUPuLdbv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746299420; x=1777835420; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=BWV+hPZ8NwIXIk/iN6QTrvYj4GcwemlrTx2HSjeDVEg=; b=MUPuLdbvMu77nqPkYZamepXVbStXZqhqO+q4Ldkpk71iWp31v7vUQNc4 +ip3iWAfgdRYfQ9XuJnKjDAVrIMvaQvHGWZwEonlqvPWQT3YRDxahbKf0 Hac+E77u6F2Suj7jHoQcSog+PV1MgHxInMwjmA8IKZKf2Hm2iJTiZSaSp fZKtAbuwG4MCTVVR5HeOg7vqvKC8M6vdN746mP1UqBX1kF1aAsUJ7eHgJ ODaO8kCLpvZwE5bAc256eKzsGr/J0J3Tlw3nXwawVqlvoiixcHuphUcS5 Ci55DCdk1VSTWXOp75FHdfecWUOMGoSKzbASZ4BESI018uxS/JseU4/t3 w==; X-CSE-ConnectionGUID: 95YW6nJ7RX60mXGY2MzGrg== X-CSE-MsgGUID: wbqVcaLqSn++xl6WDKEoHg== X-IronPort-AV: E=McAfee;i="6700,10204,11422"; a="48095661" X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="48095661" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2025 12:10:16 -0700 X-CSE-ConnectionGUID: GIeKs3QCTPy4WXrwna3ECQ== X-CSE-MsgGUID: TZDOebLbSsS+LelOY7bhww== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="140046121" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmviesa004.fm.intel.com with ESMTP; 03 May 2025 12:10:15 -0700 From: Ricardo Neri To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley Cc: devicetree@vger.kernel.org, Saurabh Sengar , Chris Oo , linux-hyperv@vger.kernel.org, "Kirill A. Shutemov" , linux-acpi@vger.kernel.org , linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri Subject: [PATCH v3 12/13] x86/hyperv/vtl: Mark the wakeup mailbox page as private Date: Sat, 3 May 2025 12:15:14 -0700 Message-Id: <20250503191515.24041-13-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> References: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: From: Yunhong Jiang The current code maps MMIO devices as shared (decrypted) by default in a confidential computing VM. In a TDX environment, secondary CPUs are booted using the Multiprocessor Wakeup Structure defined in the ACPI specification. The virtual firmware and the operating system function in the guest context, without intervention from the VMM. Map the physical memory of the mailbox as private. Use the is_private_mmio() callback. Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v2: - Use the new helper function get_mp_wakeup_mailbox_paddr(). - Edited the commit message for clarity. Changes since v1: - Added the helper function within_page() to improve readability - Override the is_private_mmio() callback when detecting a TDX environment. The address of the mailbox is checked in hv_is_private_mmio_tdx(). --- arch/x86/hyperv/hv_vtl.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 8b497c8292d3..cd48bedd21f0 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -54,6 +54,18 @@ static void __noreturn hv_vtl_restart(char __maybe_unused *cmd) hv_vtl_emergency_restart(); } +static inline bool within_page(u64 addr, u64 start) +{ + return addr >= start && addr < (start + PAGE_SIZE); +} + +static bool hv_vtl_is_private_mmio_tdx(u64 addr) +{ + u64 mb_addr = get_mp_wakeup_mailbox_paddr(); + + return mb_addr && within_page(addr, mb_addr); +} + void __init hv_vtl_init_platform(void) { pr_info("Linux runs in Hyper-V Virtual Trust Level\n"); @@ -61,6 +73,8 @@ void __init hv_vtl_init_platform(void) /* There is no paravisor present if we are here. */ if (hv_isolation_type_tdx()) { x86_init.resources.realmode_limit = SZ_4G; + x86_platform.hyper.is_private_mmio = hv_vtl_is_private_mmio_tdx; + } else { x86_platform.realmode_reserve = x86_init_noop; x86_platform.realmode_init = x86_init_noop; From patchwork Sat May 3 19:15:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 887522 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A887280CE7; Sat, 3 May 2025 19:10:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299422; cv=none; b=XnDtHqvsDjKRFXxXRK8wL7h5LHMwN3LCDQUJrp5aMdh1tmwBrpfooZqHGPTiSeQNnbiIOMfzsD8gt2jtVBkuhww3hE9iKdQ4WccV4S/wPkiiRDPr/wcfaZMzB9yX8k9Obcn/etsdz3gj0JT1wdU8hUljMBaKipvmEayFjJ+hC9k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746299422; c=relaxed/simple; bh=ETQow3I3jVQQbfoDkbZ6LD9Df4riH/sjwHO2fajMiE0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=LKIehVKFQZ53rhzP9rGhvJAnpPewrsW39L8UXTuz/hqHcEEn7/VUnOrn7eIxrrEmb+q2AfrrckLuEGg5U4p4lg7ZdfUdwIdCtHsh8OVzqAQ2DSfEuVo/PwEUODe2gc/NqrRDkPND+Amr6rBWOrOl5yb8BUUEpbfFyZCctscMgEw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=aZO5uDaW; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="aZO5uDaW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746299420; x=1777835420; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=ETQow3I3jVQQbfoDkbZ6LD9Df4riH/sjwHO2fajMiE0=; b=aZO5uDaWGvdggdlPNJFlXva1la+oZ+B1/6k3mpn3mrlzNG/Rv4yd6OVX CRHu5wF2mDlYDu1vlVKK7ptgxOEEtxHuyqUbMUtLRXiTSWyiuruEnM534 nkI09cQFtVJpFtBSLr0FS919g8orUgJH0FPlwMl2eemyZxoFJoXgVS1PR UxZHw7+kAJjThbO0kyFMbThP1J3i6QxNBrrc00PcyscxWfzzQupPErY+y DYxtT+h1Q5KR/PaF6jPY0GSZib39GJVo4lsKFb2rGddzKEK5G4Qgjrhsk REHZCWjuTFGWyUNVGdR0f9rQWQVCu4eMWRymC196DPqjfhUwZCSVHYUeF A==; X-CSE-ConnectionGUID: J4F2she8Tf+h4phYEaiVcQ== X-CSE-MsgGUID: 9MM4zJbWSNCN2ORaTZ8iMQ== X-IronPort-AV: E=McAfee;i="6700,10204,11422"; a="48095666" X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="48095666" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2025 12:10:17 -0700 X-CSE-ConnectionGUID: Cg2HYCxrS3K8KM6RbaS3ew== X-CSE-MsgGUID: AOkYwIMJRhiXoovjmJrE9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,258,1739865600"; d="scan'208";a="140046125" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmviesa004.fm.intel.com with ESMTP; 03 May 2025 12:10:16 -0700 From: Ricardo Neri To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley Cc: devicetree@vger.kernel.org, Saurabh Sengar , Chris Oo , linux-hyperv@vger.kernel.org, "Kirill A. Shutemov" , linux-acpi@vger.kernel.org , linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri Subject: [PATCH v3 13/13] x86/hyperv/vtl: Use the wakeup mailbox to boot secondary CPUs Date: Sat, 3 May 2025 12:15:15 -0700 Message-Id: <20250503191515.24041-14-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> References: <20250503191515.24041-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The hypervisor is an untrusted entity for TDX guests. It cannot be used to boot secondary CPUs. The function hv_vtl_wakeup_secondary_cpu() cannot be used. Instead, the virtual firmware boots the secondary CPUs and places them in a state to transfer control to the kernel using the wakeup mailbox. The kernel updates the APIC callback wakeup_secondary_cpu_64() to use the mailbox if detected early during boot (enumerated via either an ACPI table or a DeviceTree node). Signed-off-by: Ricardo Neri --- Changes since v2: - Unconditionally use the wakeup mailbox in a TDX confidential VM. (Michael). - Edited the commit message for clarity. Changes since v1: - None --- arch/x86/hyperv/hv_vtl.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index cd48bedd21f0..30a5a0c156c1 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -299,7 +299,15 @@ int __init hv_vtl_early_init(void) panic("XSAVE has to be disabled as it is not supported by this module.\n" "Please add 'noxsave' to the kernel command line.\n"); - apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cpu); + /* + * TDX confidential VMs do not trust the hypervisor and cannot use it to + * boot secondary CPUs. Instead, they will be booted using the wakeup + * mailbox if detected during boot. See setup_arch(). + * + * There is no paravisor present if we are here. + */ + if (!hv_isolation_type_tdx()) + apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cpu); return 0; }