From patchwork Sat May 3 10:39:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Travkin X-Patchwork-Id: 887563 Received: from box.trvn.ru (box.trvn.ru [45.141.101.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B80191B4248; Sat, 3 May 2025 10:40:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.141.101.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746268808; cv=none; b=pcm0q8nY+i+OwSWoctUj3K/sItKMihPIbD620ogPFdKkyCli02T5Vm1I0RH+rIGLAaEyfePrh7q5mVMWfe4NOqzfRC6TQGnFizBMODGHRvz0jOO+DNWlBfv8RdKBUAMyUvha0OWe0UVZSxbyTzR/+PM9/3mOs9UuzNNDHgYsLJo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746268808; c=relaxed/simple; bh=PsJs2on36RmRejiUBvCHrDrk5iO37M0LIWA8gc5UU+g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qOEWtwytEs1BYwkjySc0XTE6rwU1vNZStcXr6fO48H0JgZfJbK3M00WYhlzkawSyOlcYPZyqlk6dUiXuECkByv7Sb8SMAcAZe6X452wq8X/XSIHURMKh16mjj3fnMMpz7RBkji+7IqMN9SVRdRup8m6TmYOH4WVhVayLMGu76Ms= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=trvn.ru; spf=pass smtp.mailfrom=trvn.ru; dkim=pass (2048-bit key) header.d=trvn.ru header.i=@trvn.ru header.b=wy8biJhs; arc=none smtp.client-ip=45.141.101.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=trvn.ru Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=trvn.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=trvn.ru header.i=@trvn.ru header.b="wy8biJhs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=trvn.ru; s=mail; t=1746268799; bh=PsJs2on36RmRejiUBvCHrDrk5iO37M0LIWA8gc5UU+g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=wy8biJhsZvTe8aZLZDuQTIk9+QthKGXJto0p4qoT94ZUNAGufDkHYtdPjWjuypdJM TmyzGPfrpYA0FTDZD5r/QQJufc8PQf0COxqmeOp/cdomAXlMmH4ZrXRvHbYaggnIqB EPd6fSTddqnYhWvHAdV83drRXi9BoCbJXrLAE0EpAZVemhvsv+awPb0kNmN1ZQL+az iLtrBEO9KN9kCDjWsgI42a/whP5bv3myvLmEoW9A6rXQKEZzwXjGg/7nE0FGI4CNao smq0n/6+aun1hCVEPCOtTu88lJ4W9ZuOB+xIsynjzU9mui9K2xoDY1WiDmCFgEXdcN NfDf87hpknNLw== Received: from authenticated-user (box.trvn.ru [45.141.101.25]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by box.trvn.ru (Postfix) with ESMTPSA id D310FC970; Sat, 3 May 2025 15:39:57 +0500 (+05) From: Nikita Travkin Date: Sat, 03 May 2025 15:39:28 +0500 Subject: [PATCH v2 1/5] arm64: dts: qcom: sc7180: Add EL2 overlay for WoA devices Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250503-sc-el2-overlays-v2-1-24e9b4572e15@trvn.ru> References: <20250503-sc-el2-overlays-v2-0-24e9b4572e15@trvn.ru> In-Reply-To: <20250503-sc-el2-overlays-v2-0-24e9b4572e15@trvn.ru> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marc Zyngier , Jens Glathe , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nikita Travkin X-Developer-Signature: v=1; a=openpgp-sha256; l=2416; i=nikita@trvn.ru; h=from:subject:message-id; bh=PsJs2on36RmRejiUBvCHrDrk5iO37M0LIWA8gc5UU+g=; b=owEBbQKS/ZANAwAIAUMc7O4oGb91AcsmYgBoFfJ7RlS9PLDUos+d10Kfi/0N5eXPeY/wQ+nk/ 7xUw+YDvAiJAjMEAAEIAB0WIQTAhK9UUj+qg34uxUdDHOzuKBm/dQUCaBXyewAKCRBDHOzuKBm/ dc77D/kBF/Cxy28SDF5cWtPzl4bvWkfy4c108avGiM+/5T8fO5ADY2g1F8GPUGi8I4lflMYiPT9 TUmbe4SzAcnkxn0EYukMb/I9Osd/Rd/0IUz27vP/fF1YLA/1+DG6VNZdcEK/GzyzS+LZ8PWyyEy IBsfH+QzMfKjQFRINGodipA9J/CHb5yuT6tMbCoT2U7rz2Clr84OxZl6pqOuDKONjiDwUTnWnYi V87FHgl49RGQ4Yc9Gh0IbgjfQmS6eHb2p0hHIIxwl+mvUzYOclFnN2Bydkt+4Lc4qSpBBAoTftM yoW5W3Hm6P5G0ft7Pm5MlDKeSvDJtMJ+OwBBaUCBhDjTHmIctbfPIfPXZpkXqoQQsJAhDJ2u8YX sDY0BOr3fc1qMamNYL3p58W+TJKhmFjbYoQe8bLNCT7fxYHVzwx2Gy6CXss+bF9TWpOM5jJ0oOD BYo+DtZXn7SAbQdOgvIoL2HyAjhEr9iG/rb3qDPKpD+ny/aVSHiX4SvJZp9RTHmV98NHrWiUvHY 9rRb3y1gxeTEGSx7ZAB1X4lFrfFwj/4v4M/VnkVvQAbWYDBUMcNWJRaT7WtYO3NwF/U/lwhbXEe jiPfHJTfoVpLV2W2FIHoEXr6YKb2uWNa7ISxCvlnife1bRBrHMAwuZh6HO2yvjOmVtTU9IBIj5L yzOlIFDgPW40RdQ== X-Developer-Key: i=nikita@trvn.ru; a=openpgp; fpr=C084AF54523FAA837E2EC547431CECEE2819BF75 WoA devices using sc7180 use android firmware to boot, which notably includes QHEE hypervisor. This means that, so far, Linux-based OS could only boot in EL1 on those devices. However Windows can replace QHEE upon boot with it's own hypervisor, and with the use of tools such as "slbounce", it's possible to do the same for Linux-based OS, in which case some modifications to the DT are necessary to facilitate the absence of QHEE services. Add a EL2-specific DT overlay and apply it to sc7180 WoA devices to create -el2.dtb for each of them alongside "normal" dtb. Signed-off-by: Nikita Travkin --- arch/arm64/boot/dts/qcom/Makefile | 3 ++- arch/arm64/boot/dts/qcom/sc7180-el2.dtso | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index adb4d026bcc4b24d73de92e204db8d525b0770e6..06da6f6791d69f56bafc3dad3e721c9ff2a1a68a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -138,7 +138,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-r3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-acer-aspire1.dtb +sc7180-acer-aspire1-el2-dtbs := sc7180-acer-aspire1.dtb sc7180-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc7180-acer-aspire1.dtb sc7180-acer-aspire1-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-el2.dtso b/arch/arm64/boot/dts/qcom/sc7180-el2.dtso new file mode 100644 index 0000000000000000000000000000000000000000..49a98676ca4db270ecb55e8f801d0800ef9e4def --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-el2.dtso @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * sc7180 specific modifications required to boot in EL2. + */ + +/dts-v1/; +/plugin/; + +/* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */ +&gpu { + zap-shader { + status = "disabled"; + }; +}; + +/* Venus can be used in EL2 if booted similarly to ChromeOS devices. */ +&venus { + video-firmware { + iommus = <&apps_smmu 0x0c42 0x0>; + }; +}; From patchwork Sat May 3 10:39:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Travkin X-Patchwork-Id: 887022 Received: from box.trvn.ru (box.trvn.ru [45.141.101.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B235D1E3DD0; Sat, 3 May 2025 10:40:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.141.101.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746268809; cv=none; b=i5zmVtZlQW2ZZZi4ecKD8H1ZXhafo3LD5xDzTBfA/vjOYlf7lV9z8GxMZHr+9gA11+XSB/ziJGMTJOIIEtD5UNzXJKY4w99Tpz64xXXymDpAeukC6RE8XOh/cfLjqDh/C48lkCIbtAUii+Jl8+tWXqAuhsU8EEGMIWrgmSErwdU= ARC-Message-Signature: i=1; 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a=openpgp; fpr=C084AF54523FAA837E2EC547431CECEE2819BF75 sc8280xp has an SMMUv3 connected to PCIe which is normally controlled by QHEE and is thus transparent to the OS. However if we boot Linux in EL2, without QHEE, we need to manage this IOMMU ourselves. To make that easier, and since the hardware actually exists, just not "usually" managed by Linux, describe it in the dts as "reserved". Signed-off-by: Nikita Travkin --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 35ef31d4ecf26125407bb64dd2de6e777a3400a3..27d21e1a2d50c6fc12f324ab2b4dfa4b99791b81 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4927,6 +4927,20 @@ rx-pins { }; }; + pcie_smmu: iommu@14f80000 { + compatible = "arm,smmu-v3"; + reg = <0 0x14f80000 0 0x80000>; + #iommu-cells = <1>; + interrupts = , + , + ; + interrupt-names = "eventq", + "gerror", + "cmdq-sync"; + dma-coherent; + status = "reserved"; /* Controlled by QHEE. */ + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; From patchwork Sat May 3 10:39:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Travkin X-Patchwork-Id: 887021 Received: from box.trvn.ru (box.trvn.ru [45.141.101.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B339D1EEA5F; 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Sat, 3 May 2025 15:40:00 +0500 (+05) From: Nikita Travkin Date: Sat, 03 May 2025 15:39:30 +0500 Subject: [PATCH v2 3/5] arm64: dts: qcom: sc8280xp: Add EL2 overlay for WoA devices Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250503-sc-el2-overlays-v2-3-24e9b4572e15@trvn.ru> References: <20250503-sc-el2-overlays-v2-0-24e9b4572e15@trvn.ru> In-Reply-To: <20250503-sc-el2-overlays-v2-0-24e9b4572e15@trvn.ru> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marc Zyngier , Jens Glathe , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nikita Travkin X-Developer-Signature: v=1; a=openpgp-sha256; l=3816; i=nikita@trvn.ru; h=from:subject:message-id; bh=yZ5AUrLf7fwFTnXazjJiDVbDwXh8gK863PfsGEF+COE=; b=owEBbQKS/ZANAwAIAUMc7O4oGb91AcsmYgBoFfJ7W3JhVsSMdFH3UYKcvKN2kRJvh3XzL9RkZ WHrKS4fMnGJAjMEAAEIAB0WIQTAhK9UUj+qg34uxUdDHOzuKBm/dQUCaBXyewAKCRBDHOzuKBm/ dXoFEACwm+C1nTTALVRMuoVoDZOgQ3lsjOnA/jfN4TQjr9fcwjOx+2WHqSUe/YbYpKJClWjsuqA J2s7dqK6eUKoD0L7KziywERMIrhSYJcbAMvcXZZzCVvEktKXNqO71lYiz1iwFHnU/65jjmFsDf1 acncroD/kb6OZ8B77ICCEqH2e/3Sy+pOQAhUDP7psNWPw6UzBn1pmQIvZM7gIYVAMMJ50unl1Ia 1bdvUxm/GzLKFCUymL57fB9Mkuzy9SyMJIlU2ZBwZfgB98TdPVxnyrYVa6jGfdMFv29SHVZEu1w PB2sf4So472FuHnPlIoWVteVlPhxWdebL2oIbhsMQkufuEBeFPmYLPTdhxpyFA3w8/AHowE5iMw ePAxLhBaQCgyvnmLrD6QcvtH6fq9aqEOvsqHeAg0OzejkILGWaYxUhyJ0Wrr21+6Pel2zwWBJEl kqFg1R/kjJuECpiBO2qjx7IvdccGW1XECqL+k0ub5NGGZzzuMHMn2PgfE6me7SdIXUi2AhiDyhk jZk+ZjvM7zoEoqrbvpIcz4oXmH+mLOq8gGIAADYZflscY1Lto8viMxTEH5P/ilD/FuGbAPUKWJn i19Eyjd95n0Sr9gmLkSq/YkPsM7EVFlp0hXSRbEE5rOPn/C59qoLJNwe+aOulD597Jdc8aOEJ5c K7jN+/9Q1KZK5zQ== X-Developer-Key: i=nikita@trvn.ru; a=openpgp; fpr=C084AF54523FAA837E2EC547431CECEE2819BF75 WoA devices using sc8280xp use android firmware to boot, which notably includes QHEE hypervisor. This means that, so far, Linux-based OS could only boot in EL1 on those devices. However Windows can replace QHEE upon boot with it's own hypervisor, and with the use of tools such as "slbounce", it's possible to do the same for Linux-based OS, in which case some modifications to the DT are necessary to facilitate the absence of QHEE services. Add a EL2-specific DT overlay and apply it to sc8280xp WoA devices to create -el2.dtb for each of them alongside "normal" dtb. Signed-off-by: Nikita Travkin --- arch/arm64/boot/dts/qcom/Makefile | 15 ++++++---- arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso | 44 ++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 06da6f6791d69f56bafc3dad3e721c9ff2a1a68a..12d9ed1129b4e83146e561910aca9fc3718b0820 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -205,11 +205,16 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8180x-lenovo-flex-5g.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8180x-primus.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-huawei-gaokun3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-arcata.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-blackrock.dtb +sc8280xp-crd-el2-dtbs := sc8280xp-crd.dtb sc8280xp-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb sc8280xp-crd-el2.dtb +sc8280xp-huawei-gaokun3-el2-dtbs := sc8280xp-huawei-gaokun3.dtb sc8280xp-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-huawei-gaokun3.dtb sc8280xp-huawei-gaokun3-el2.dtb +sc8280xp-lenovo-thinkpad-x13s-el2-dtbs := sc8280xp-lenovo-thinkpad-x13s.dtb sc8280xp-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb sc8280xp-lenovo-thinkpad-x13s-el2.dtb +sc8280xp-microsoft-arcata-el2-dtbs := sc8280xp-microsoft-arcata.dtb sc8280xp-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-arcata.dtb sc8280xp-microsoft-arcata-el2.dtb +sc8280xp-microsoft-blackrock-el2-dtbs := sc8280xp-microsoft-blackrock.dtb sc8280xp-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-blackrock.dtb sc8280xp-microsoft-blackrock-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm450-lenovo-tbx605f.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm450-motorola-ali.dtb diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso b/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso new file mode 100644 index 0000000000000000000000000000000000000000..25d1fa4bc2055e67db0508aa09c8a8bd7fa01687 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * sc8280xp specific modifications required to boot in EL2. + */ + +/dts-v1/; +/plugin/; + +/* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */ +&gpu { + zap-shader { + status = "disabled"; + }; +}; + +/* + * When running under QHEE, this IOMMU is controlled by the firmware, + * however when we take ownership of it in EL2, we need to configure + * it properly to use PCIe. + */ +&pcie2a { + iommu-map = <0 &pcie_smmu 0x20000 0x10000>; +}; + +&pcie2b { + iommu-map = <0 &pcie_smmu 0x30000 0x10000>; +}; + +&pcie3a { + iommu-map = <0 &pcie_smmu 0x40000 0x10000>; +}; + +&pcie3b { + iommu-map = <0 &pcie_smmu 0x50000 0x10000>; +}; + +&pcie4 { + iommu-map = <0 &pcie_smmu 0x60000 0x10000>; +}; + +&pcie_smmu { + status = "okay"; +}; From patchwork Sat May 3 10:39:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Travkin X-Patchwork-Id: 887023 Received: from box.trvn.ru (box.trvn.ru [45.141.101.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63E8B1DDA00; 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Sat, 3 May 2025 15:40:02 +0500 (+05) From: Nikita Travkin Date: Sat, 03 May 2025 15:39:31 +0500 Subject: [PATCH v2 4/5] arm64: dts: qcom: x1e80100: Add PCIe IOMMU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250503-sc-el2-overlays-v2-4-24e9b4572e15@trvn.ru> References: <20250503-sc-el2-overlays-v2-0-24e9b4572e15@trvn.ru> In-Reply-To: <20250503-sc-el2-overlays-v2-0-24e9b4572e15@trvn.ru> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marc Zyngier , Jens Glathe , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nikita Travkin X-Developer-Signature: v=1; a=openpgp-sha256; l=1435; i=nikita@trvn.ru; h=from:subject:message-id; bh=VM78bnqXE6eBOsA+BcpvbWTxuAL5iTO9ndxW92ZfweM=; b=owEBbQKS/ZANAwAIAUMc7O4oGb91AcsmYgBoFfJ7aOsXspvdR4afafYLHfc7zVuVmThcjx+y+ YgWuneG8wmJAjMEAAEIAB0WIQTAhK9UUj+qg34uxUdDHOzuKBm/dQUCaBXyewAKCRBDHOzuKBm/ dRFpD/9A97XMAN+kp2VjUzOrl3pQ1Fb8f7wH57nYgMHqsnCcQvyaI7ZoPIjzSrQwXfvA8VrLPLz uLkSho69HjBlPPF0SPJ8e4TPaEQOWtlaq2tHPOWcHKRcE7CklL5ZcVmSS+eDlRTtr9blhkiScMZ vAop/Rfa3eOM2yq++dG0bbd+gRF2mNpQkbSNlJFXv1dW4xhsGogvpJHLDiw/8rnv1c4f4nzx4AX zBZE6Sk9H5QI/HZcFkcAa4klhAy6xZlHxYKTEWBXIMVcux8vGMuSjDU3bSUzJHJbVLLKlATXpS4 rWOlYgmOKzM96Nnhz8xbysoHRuXdYSnw6jbvOZSiQnS0lwRTYzprHcdcaoFcXNaKd+OfteMvL70 h8jDHu18DI9qIt5FbGBK19nnbuIvNPnLqkykQ65YPyzqfivH/d2fZuamLMg/cv0VelSu0+iGSy1 buTwtGa3RueP/ArQ3KPWudqwklNbu0voCO6gmcEq9HpKVQ6rR5VkYSdTzcck5FkgR7BM4e7AnHF nFIwxDkBe8JasUeeFTUZ+NxpJM0cha64OKrRCm0WyzeZNcnwxZLqmXTVTX1KS7rkeR42waPUD/U klMFyfJG/VcgpZs86KCaSWmtYpvPe2WkEVKycHW3XBrqsrXdo9KoleHOwcRKao9nSXhl+LIxFPp dPiDuVdbpy9FRJQ== X-Developer-Key: i=nikita@trvn.ru; a=openpgp; fpr=C084AF54523FAA837E2EC547431CECEE2819BF75 x1e80100 has an SMMUv3 connected to PCIe which is normally controlled by Gunyah and is thus transparent to the OS. However if we boot Linux in EL2, without Gunyah, we need to manage this IOMMU ourselves. To make that easier, and since the hardware actually exists, just not "usually" managed by Linux, describe it in the dts as "reserved". Signed-off-by: Nikita Travkin --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 46b79fce92c90d969e3de48bc88e27915d1592bb..7a3e75294be545a719f3543a8b874900f7c78f99 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -7940,6 +7940,20 @@ apps_smmu: iommu@15000000 { dma-coherent; }; + pcie_smmu: iommu@15400000 { + compatible = "arm,smmu-v3"; + reg = <0 0x15400000 0 0x80000>; + #iommu-cells = <1>; + interrupts = , + , + ; + interrupt-names = "eventq", + "gerror", + "cmdq-sync"; + dma-coherent; + status = "reserved"; /* Controlled by Gunyah. */ + }; + intc: interrupt-controller@17000000 { compatible = "arm,gic-v3"; reg = <0 0x17000000 0 0x10000>, /* GICD */ From patchwork Sat May 3 10:39:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Travkin X-Patchwork-Id: 887561 Received: from box.trvn.ru (box.trvn.ru [45.141.101.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91EB61F09A8; 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Sat, 3 May 2025 15:40:03 +0500 (+05) From: Nikita Travkin Date: Sat, 03 May 2025 15:39:32 +0500 Subject: [PATCH v2 5/5] arm64: dts: qcom: x1e/x1p: Add EL2 overlay for WoA devices Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250503-sc-el2-overlays-v2-5-24e9b4572e15@trvn.ru> References: <20250503-sc-el2-overlays-v2-0-24e9b4572e15@trvn.ru> In-Reply-To: <20250503-sc-el2-overlays-v2-0-24e9b4572e15@trvn.ru> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marc Zyngier , Jens Glathe , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nikita Travkin X-Developer-Signature: v=1; a=openpgp-sha256; l=6029; i=nikita@trvn.ru; h=from:subject:message-id; bh=MPBTfFU0Xf6+ddYrvZbmg422nM4nFrs0KVb2QdwKdPM=; b=owEBbQKS/ZANAwAIAUMc7O4oGb91AcsmYgBoFfJ7R9fCT2kh6+Q5ZE7r/8m/VnbY7MVlM3NbL qkXlvMvvkqJAjMEAAEIAB0WIQTAhK9UUj+qg34uxUdDHOzuKBm/dQUCaBXyewAKCRBDHOzuKBm/ dbAHEACMiCFQWxv8glvEerRJrCWcSd87E9TDVPcY47/ED936iN2924VGIVnHHWf5fdYidw1s8fb YDN7LEIDWltCFMlva1Pk0H96cg9XFovfLjcmbwljTLCtQKXPa8IURzDJoOGrBHU5ublOANhw55B Ma6RAY9PZwL1TvohADrZOw6wa1zCaCHcEdWfzlubEL3LOmr/8xcvb9zR7f1uQSfPbHKXs4kfsDm YhHA3VEACeen16dv1+9XFaRKOcZtZDtKBfO3xjzcdFoLQp4AvRP23VVfmdyecciiCHVFaL6i+Zh 20JaPfFAeBS0/UUI981PG6olu4lFTv4Z4HDIl9OxBbNKGE87bVFdVPQ3Pt+9S9KH2JhRJIb+afj VCxmlpNWOOyFGLP8QNh92PIsx/qwpuNT6xWwfvyVB1upOmHT36aCbWknIP/5FEtsLoUX1A5U3Pj 93Mz9F4YIXAXDjzidjspsCJUIITlkAj6ONtFk8hk50IeLFVzVvMoNcOFUUpRRZqFWQfsfDpkyLS Axu05/9Oe5Kh1mgbc4zsYJnfWerXphFSYa5AfnQ97ZPGJw7i25EjeNjF0T7Np7DlxcWjjgl9GP1 j/lpciJpaSk86NSZRVnCL1oH7ryNFRZOLZ+JOmDGuHnPBfA1KXBbM7p0gypNlyaRcSFUHpx08dS ox64w9apbIsYKlQ== X-Developer-Key: i=nikita@trvn.ru; a=openpgp; fpr=C084AF54523FAA837E2EC547431CECEE2819BF75 WoA devices using x1e/x1p use android firmware to boot, which notably includes Gunyah hypervisor. This means that, so far, Linux-based OS could only boot in EL1 on those devices. However Windows can replace Gunyah upon boot with it's own hypervisor, and with the use of tools such as "slbounce", it's possible to do the same for Linux-based OS, in which case some modifications to the DT are necessary to facilitate the absence of Gunyah services. Add a EL2-specific DT overlay and apply it to x1e/x1p WoA devices to create -el2.dtb for each of them alongside "normal" dtb. Signed-off-by: Nikita Travkin --- arch/arm64/boot/dts/qcom/Makefile | 36 +++++++++++++++-------- arch/arm64/boot/dts/qcom/x1-el2.dtso | 52 ++++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 +- 3 files changed, 77 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 12d9ed1129b4e83146e561910aca9fc3718b0820..4300b29397c6a0087e5c5909d756d733f308d373 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -299,15 +299,27 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8750-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8750-qrd.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s-oled.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-vivobook-s15.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-xps13-9345.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e80100-hp-omnibook-x14.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus13.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus15.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1p42100-crd.dtb +x1e001de-devkit-el2-dtbs := x1e001de-devkit.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit.dtb x1e001de-devkit-el2.dtb +x1e78100-lenovo-thinkpad-t14s-el2-dtbs := x1e78100-lenovo-thinkpad-t14s.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s.dtb x1e78100-lenovo-thinkpad-t14s-el2.dtb +x1e78100-lenovo-thinkpad-t14s-oled-el2-dtbs := x1e78100-lenovo-thinkpad-t14s-oled.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s-oled.dtb x1e78100-lenovo-thinkpad-t14s-oled-el2.dtb +x1e80100-asus-vivobook-s15-el2-dtbs := x1e80100-asus-vivobook-s15.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-vivobook-s15.dtb x1e80100-asus-vivobook-s15-el2.dtb +x1e80100-crd-el2-dtbs := x1e80100-crd.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb x1e80100-crd-el2.dtb +x1e80100-dell-xps13-9345-el2-dtbs := x1e80100-dell-xps13-9345.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-xps13-9345.dtb x1e80100-dell-xps13-9345-el2.dtb +x1e80100-hp-omnibook-x14-el2-dtbs := x1e80100-hp-omnibook-x14.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-hp-omnibook-x14.dtb x1e80100-hp-omnibook-x14-el2.dtb +x1e80100-lenovo-yoga-slim7x-el2-dtbs := x1e80100-lenovo-yoga-slim7x.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb x1e80100-lenovo-yoga-slim7x-el2.dtb +x1e80100-microsoft-romulus13-el2-dtbs := x1e80100-microsoft-romulus13.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus13.dtb x1e80100-microsoft-romulus13-el2.dtb +x1e80100-microsoft-romulus15-el2-dtbs := x1e80100-microsoft-romulus15.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus15.dtb x1e80100-microsoft-romulus15-el2.dtb +x1e80100-qcp-el2-dtbs := x1e80100-qcp.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb x1e80100-qcp-el2.dtb +x1p42100-crd-el2-dtbs := x1p42100-crd.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-crd.dtb x1p42100-crd-el2.dtb diff --git a/arch/arm64/boot/dts/qcom/x1-el2.dtso b/arch/arm64/boot/dts/qcom/x1-el2.dtso new file mode 100644 index 0000000000000000000000000000000000000000..380441deca65d1b443962fbe6151f4aadd918383 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1-el2.dtso @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * x1 specific modifications required to boot in EL2. + */ + +/dts-v1/; +/plugin/; + +/* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */ +&gpu_zap_shader { + status = "disabled"; +}; + +/* + * When running under Gunyah, this IOMMU is controlled by the firmware, + * however when we take ownership of it in EL2, we need to configure + * it properly to use PCIe. + * + * Additionally, it seems like ITS emulation in Gunyah is broken so we + * can't use MSI on some PCIe controllers in EL1. But we can add them + * here for EL2. + */ +&pcie3 { + iommu-map = <0 &pcie_smmu 0x30000 0x10000>; + msi-map = <0 &gic_its 0xb0000 0x10000>; +}; + +&pcie4 { + iommu-map = <0 &pcie_smmu 0x40000 0x10000>; +}; + +&pcie5 { + iommu-map = <0 &pcie_smmu 0x50000 0x10000>; + msi-map = <0 &gic_its 0xd0000 0x10000>; +}; + +&pcie6a { + iommu-map = <0 &pcie_smmu 0x60000 0x10000>; +}; + +&pcie_smmu { + status = "okay"; +}; + +/* + * The "SBSA watchdog" is implemented in software in Gunyah + * and can't be used when running in EL2. + */ +&sbsa_watchdog { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 7a3e75294be545a719f3543a8b874900f7c78f99..c04a2615ca77629b27fbd6fd98f1a25a3b6697db 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -8163,7 +8163,7 @@ frame@1780d000 { }; }; - watchdog@1c840000 { + sbsa_watchdog: watchdog@1c840000 { compatible = "arm,sbsa-gwdt"; reg = <0 0x1c840000 0 0x1000>, <0 0x1c850000 0 0x1000>;