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Mon, 05 May 2025 04:37:53 -0700 (PDT) Date: Mon, 5 May 2025 14:37:50 +0300 From: Dan Carpenter To: Linus Walleij Cc: Bartosz Golaszewski , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Takahiro AKASHI Subject: [RFC 3/7] pinctrl: introduce pinctrl_gpio_get_config() Message-ID: <0e982ace876920162d27a521f5f460b1dd6fc929.1746443762.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: From: AKASHI Takahiro This is a counterpart of pinctrl_gpio_set_config(), which will initially be used to implement gpio_get interface in SCMI pinctrl based GPIO driver. Signed-off-by: AKASHI Takahiro Signed-off-by: Dan Carpenter --- drivers/pinctrl/core.c | 35 ++++++++++++++++++++++++++++++++ include/linux/pinctrl/consumer.h | 9 ++++++++ 2 files changed, 44 insertions(+) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 4bdbf6bb26e2..4310f9e2118b 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include "core.h" @@ -937,6 +938,40 @@ int pinctrl_gpio_set_config(struct gpio_chip *gc, unsigned int offset, } EXPORT_SYMBOL_GPL(pinctrl_gpio_set_config); +/** + * pinctrl_gpio_get_config() - Get the config for a given GPIO pin + * @gc: GPIO chip structure from the GPIO subsystem + * @offset: hardware offset of the GPIO relative to the controller + * @config: the configuration to query. On success it holds the result + */ +int pinctrl_gpio_get_config(struct gpio_chip *gc, unsigned int offset, unsigned long *config) +{ + struct pinctrl_gpio_range *range; + const struct pinconf_ops *ops; + struct pinctrl_dev *pctldev; + int ret, pin; + + ret = pinctrl_get_device_gpio_range(gc, offset, &pctldev, &range); + if (ret) + return ret; + + ops = pctldev->desc->confops; + if (!ops || !ops->pin_config_get) + return -EINVAL; + + mutex_lock(&pctldev->mutex); + pin = gpio_to_pin(range, gc, offset); + ret = ops->pin_config_get(pctldev, pin, config); + mutex_unlock(&pctldev->mutex); + + if (ret) + return ret; + + *config = pinconf_to_config_argument(*config); + return 0; +} +EXPORT_SYMBOL_GPL(pinctrl_gpio_get_config); + static struct pinctrl_state *find_state(struct pinctrl *p, const char *name) { diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h index 73de70362b98..e5815b3382dc 100644 --- a/include/linux/pinctrl/consumer.h +++ b/include/linux/pinctrl/consumer.h @@ -35,6 +35,8 @@ int pinctrl_gpio_direction_output(struct gpio_chip *gc, unsigned int offset); int pinctrl_gpio_set_config(struct gpio_chip *gc, unsigned int offset, unsigned long config); +int pinctrl_gpio_get_config(struct gpio_chip *gc, unsigned int offset, + unsigned long *config); struct pinctrl * __must_check pinctrl_get(struct device *dev); void pinctrl_put(struct pinctrl *p); @@ -96,6 +98,13 @@ pinctrl_gpio_direction_output(struct gpio_chip *gc, unsigned int offset) return 0; } +static inline int +pinctrl_gpio_get_config(struct gpio_chip *gc, unsigned int offset, + unsigned long *config) +{ + return 0; +} + static inline int pinctrl_gpio_set_config(struct gpio_chip *gc, unsigned int offset, unsigned long config) From patchwork Mon May 5 11:38:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Carpenter X-Patchwork-Id: 887644 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D0F6205AA8 for ; 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Mon, 05 May 2025 04:38:06 -0700 (PDT) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-3a099ae8117sm10276584f8f.56.2025.05.05.04.38.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 May 2025 04:38:06 -0700 (PDT) Date: Mon, 5 May 2025 14:38:03 +0300 From: Dan Carpenter To: Sudeep Holla Cc: Cristian Marussi , Linus Walleij , arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Takahiro AKASHI , Peng Fan Subject: [RFC 4/7] pinctrl-scmi: add PIN_CONFIG_INPUT_VALUE Message-ID: <855acdd6fcef4856c4fcc59affd3a191f74dbe82.1746443762.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: In SCMI the value of the pin is just another configuration option. Add this as an option in the pin_config_param enum and creating a mapping to SCMI_PIN_INPUT_VALUE in pinctrl_scmi_map_pinconf_type() Since this is an RFC patch, I'm going to comment that I think the SCMI pinctrl driver misuses the PIN_CONFIG_OUTPUT enum. It should be for enabling and disabling output on pins which can serve as both input and output. Enabling it is supposed to write a 1 and disabling it is supposed to write a 0 but we use that side effect to write 1s and 0s. I did't change this because it would break userspace but I'd like to add a PIN_CONFIG_OUTPUT_VALUE enum as well and use that in the GPIO driver. But in this patchset I just use PIN_CONFIG_OUTPUT. Signed-off-by: Dan Carpenter --- drivers/pinctrl/pinctrl-scmi.c | 3 +++ include/linux/pinctrl/pinconf-generic.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c index df4bbcd7d1d5..362a6d2c3c68 100644 --- a/drivers/pinctrl/pinctrl-scmi.c +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -250,6 +250,9 @@ static int pinctrl_scmi_map_pinconf_type(enum pin_config_param param, case PIN_CONFIG_INPUT_SCHMITT_ENABLE: *type = SCMI_PIN_INPUT_MODE; break; + case PIN_CONFIG_INPUT_VALUE: + *type = SCMI_PIN_INPUT_VALUE; + break; case PIN_CONFIG_MODE_LOW_POWER: *type = SCMI_PIN_LOW_POWER_MODE; break; diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index 1bcf071b860e..b37838171581 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -83,6 +83,8 @@ struct pinctrl_map; * schmitt-trigger mode is disabled. * @PIN_CONFIG_INPUT_SCHMITT_UV: this will configure an input pin to run in * schmitt-trigger mode. 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Mon, 05 May 2025 04:39:31 -0700 (PDT) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-441b2b20aa6sm178602255e9.27.2025.05.05.04.39.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 May 2025 04:39:30 -0700 (PDT) Date: Mon, 5 May 2025 14:39:17 +0300 From: Dan Carpenter To: Sudeep Holla Cc: Cristian Marussi , Linus Walleij , arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Peng Fan Subject: [RFC 5/7] pinctrl: Delete PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS support Message-ID: <81fb0a1b0cf15d73e7635081594d8650bf1a258d.1746443762.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: The argument for PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS is supposed to be expressed in terms of ohms. But the pinctrl-scmi driver was implementing it the same as PIN_CONFIG_OUTPUT and writing either a zero or one to the pin. The SCMI protocol doesn't have an support configuration type so just delete this code instead of fixing it. Signed-off-by: Dan Carpenter --- drivers/pinctrl/pinctrl-scmi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c index 362a6d2c3c68..f369f0354e43 100644 --- a/drivers/pinctrl/pinctrl-scmi.c +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -262,9 +262,6 @@ static int pinctrl_scmi_map_pinconf_type(enum pin_config_param param, case PIN_CONFIG_OUTPUT_ENABLE: *type = SCMI_PIN_OUTPUT_MODE; break; - case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: - *type = SCMI_PIN_OUTPUT_VALUE; - break; case PIN_CONFIG_POWER_SOURCE: *type = SCMI_PIN_POWER_SOURCE; break; From patchwork Mon May 5 11:39:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Carpenter X-Patchwork-Id: 887936 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8400205AB9 for ; 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Mon, 05 May 2025 04:39:51 -0700 (PDT) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-441b8a3113csm129876775e9.33.2025.05.05.04.39.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 May 2025 04:39:50 -0700 (PDT) Date: Mon, 5 May 2025 14:39:27 +0300 From: Dan Carpenter To: Sudeep Holla Cc: Cristian Marussi , Linus Walleij , Bartosz Golaszewski , arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Takahiro AKASHI Subject: [RFC 6/7] pinctrl-scmi: Add GPIO support Message-ID: <901a636b06f5ef25f8c0021c514bfcc01344c5df.1746443762.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: This adds GPIO support to the SCMI pin controller driver. It's an RFC patch because I'm not really sure how these are used and so I don't know how they should be configured via devicetree. I've labeled the places where I think devicetree configuration would go with a FIXME. This driver was based on work from Takahiro AKASHI. Signed-off-by: Dan Carpenter --- drivers/pinctrl/pinctrl-scmi.c | 206 ++++++++++++++++++++++++++++++++- 1 file changed, 205 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c index f369f0354e43..40b432aa4756 100644 --- a/drivers/pinctrl/pinctrl-scmi.c +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -6,6 +6,7 @@ * Copyright 2024 NXP */ +#include #include #include #include @@ -16,6 +17,9 @@ #include #include +#include + +#include #include #include #include @@ -42,6 +46,7 @@ struct scmi_pinctrl { unsigned int nr_functions; struct pinctrl_pin_desc *pins; unsigned int nr_pins; + struct gpio_chip *gc; }; static int pinctrl_scmi_get_groups_count(struct pinctrl_dev *pctldev) @@ -505,6 +510,197 @@ static int pinctrl_scmi_get_pins(struct scmi_pinctrl *pmx, return 0; } +static int pinctrl_gpio_init_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) +{ + bitmap_fill(valid_mask, ngpios); + return 0; +} + +static int pinctrl_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) +{ + unsigned long config; + bool in, out; + int ret; + + config = PIN_CONFIG_INPUT_ENABLE; + ret = pinctrl_gpio_get_config(gc, offset, &config); + if (ret) + return ret; + in = config; + + config = PIN_CONFIG_OUTPUT_ENABLE; + ret = pinctrl_gpio_get_config(gc, offset, &config); + if (ret) + return ret; + out = config; + + /* Consistency check - in theory both can be enabled! */ + if (in && !out) + return GPIO_LINE_DIRECTION_IN; + if (!in && out) + return GPIO_LINE_DIRECTION_OUT; + + return -EINVAL; +} + +static int pinctrl_gpio_direction_output_wrapper(struct gpio_chip *gc, + unsigned int offset, int val) +{ + return pinctrl_gpio_direction_output(gc, offset); +} + +static int pinctrl_gpio_get(struct gpio_chip *gc, unsigned int offset) +{ + unsigned long config; + int ret; + + config = PIN_CONFIG_INPUT_VALUE; + ret = pinctrl_gpio_get_config(gc, offset, &config); + if (ret) + return ret; + + return config; +} + +static void pinctrl_gpio_set(struct gpio_chip *gc, unsigned int offset, int val) +{ + unsigned long config; + + config = PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, val); + pinctrl_gpio_set_config(gc, offset, config); +} + +static int pinctrl_gc_to_func(struct gpio_chip *gc) +{ + struct scmi_pinctrl *pmx = gpiochip_get_data(gc); + + return (gc - pmx->gc); +} + +static int gpio_add_pin_ranges(struct gpio_chip *gc) +{ + struct scmi_pinctrl *pmx = gpiochip_get_data(gc); + const char * const *p_groups; + unsigned int n_groups; + int func = pinctrl_gc_to_func(gc); + int group; + int ret; + + ret = pmx->pctl_desc.pmxops->get_function_groups(pmx->pctldev, func, &p_groups, &n_groups); + if (ret) + return ret; + + // FIXME: fix the correct group from the device tree + for (group = 0; group < n_groups; group++) { + ret = gpiochip_add_pingroup_range(gc, pmx->pctldev, 0, p_groups[group]); + if (ret) + return ret; + } + + return 0; +} + +static int get_nr_pins_in_function(struct scmi_pinctrl *pmx, int func) +{ + const char * const *pin_groups; + unsigned int n_groups; + const unsigned int *pins; + unsigned int n_pins; + int total = 0; + int i, ret; + + // FIXME: get the correct number of gc.ngpio + // Find the right group from the device tree + ret = pmx->pctl_desc.pmxops->get_function_groups(pmx->pctldev, func, &pin_groups, &n_groups); + if (ret) + return ret; + + for (i = 0; i < n_groups; i++) { + ret = pinctrl_get_group_pins(pmx->pctldev, pin_groups[i], &pins, &n_pins); + if (ret) + return ret; + total += n_pins; + } + + return total; +} + +static int register_scmi_pinctrl_gpio_handler(struct device *dev, struct scmi_pinctrl *pmx) +{ + struct fwnode_handle *gpio = NULL; + int ret, i; + + gpio = fwnode_get_named_child_node(dev->fwnode, "gpio"); + if (!gpio) + return 0; + + pmx->gc = devm_kcalloc(dev, pmx->nr_functions, sizeof(*pmx->gc), GFP_KERNEL); + if (!pmx->gc) + return -ENOMEM; + + for (i = 0; i < pmx->nr_functions; i++) { + const char *fn_name; + + ret = pinctrl_ops->is_gpio(pmx->ph, i, FUNCTION_TYPE); + if (ret < 0) + return ret; + if (ret == false) + continue; + + ret = pinctrl_ops->name_get(pmx->ph, i, FUNCTION_TYPE, &fn_name); + if (ret) + return ret; + + pmx->gc[i].label = devm_kasprintf(dev, GFP_KERNEL, "%s", fn_name); + if (!pmx->gc[i].label) + return -ENOMEM; + + pmx->gc[i].owner = THIS_MODULE; + pmx->gc[i].get = pinctrl_gpio_get; + pmx->gc[i].set = pinctrl_gpio_set; + pmx->gc[i].get_direction = pinctrl_gpio_get_direction; + pmx->gc[i].direction_input = pinctrl_gpio_direction_input; + pmx->gc[i].direction_output = pinctrl_gpio_direction_output_wrapper; + pmx->gc[i].add_pin_ranges = gpio_add_pin_ranges; + + // FIXME: verify that this is correct + pmx->gc[i].can_sleep = true; + + ret = get_nr_pins_in_function(pmx, i); + if (ret < 0) + return ret; + pmx->gc[i].ngpio = ret; + + pmx->gc[i].init_valid_mask = pinctrl_gpio_init_valid_mask; + pmx->gc[i].parent = dev; + pmx->gc[i].base = -1; + } + + return 0; +} + +static int scmi_gpiochip_add_data(struct device *dev, struct scmi_pinctrl *pmx) +{ + int ret; + int i; + + for (i = 0; i < pmx->nr_functions; i++) { + ret = pinctrl_ops->is_gpio(pmx->ph, i, FUNCTION_TYPE); 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Mon, 05 May 2025 04:39:43 -0700 (PDT) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-441b89ee37dsm129618395e9.22.2025.05.05.04.39.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 May 2025 04:39:43 -0700 (PDT) Date: Mon, 5 May 2025 14:39:35 +0300 From: Dan Carpenter To: Sudeep Holla Cc: Cristian Marussi , Linus Walleij , arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC 7/7] pinctrl-scmi: remove unused struct member Message-ID: References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: The ->nr_pins is not used so delete that. Signed-off-by: Dan Carpenter --- drivers/pinctrl/pinctrl-scmi.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c index 40b432aa4756..d1f3c126c3cb 100644 --- a/drivers/pinctrl/pinctrl-scmi.c +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -45,7 +45,6 @@ struct scmi_pinctrl { struct pinfunction *functions; unsigned int nr_functions; struct pinctrl_pin_desc *pins; - unsigned int nr_pins; struct gpio_chip *gc; };