From patchwork Mon May 5 16:26:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 887694 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DA17269CE6; Mon, 5 May 2025 16:26:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746462402; cv=none; b=U5gJ6JgR7bQHG8JHDlij/b7fx3g9CHlrWdoWk6TgTcGlD+hS0WPJNEpfZxSYuG2ODtxJaV8SRq1hkSPcVuMmLdh29tO+k44iyJOdtgukpiToE9IgaMEMiRHoq42W6XWTpOU2BYIceVBqmC1/3/1b0/QlUKkR2yc3nZONFeIhL8k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746462402; c=relaxed/simple; bh=u7HKkwOPvItFSrEFnYEsRbbOURBbm71UWURQboRepAs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ADwUZeQIZ41ugshPbPluL8eqZsUcaeh6TgpaKfIcYpZ/cQhFTKyNtT3kP5d+ERycFErkyQlrxy9cGgfOoSxATXL9yxQaLriY4P86Vhua26Enk0PsKewdFClVVjKRVi7y9vwL0ZMpf8RB+/F5cpvOfljivh8OabU8jb9J2TsKvG4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SyYkNTZD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SyYkNTZD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 18D25C4CEEE; Mon, 5 May 2025 16:26:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746462401; bh=u7HKkwOPvItFSrEFnYEsRbbOURBbm71UWURQboRepAs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SyYkNTZDG2/wL/ye+SB93kdqQHWQWGYZ8uT70cNjPeUig78gUDFhnokhvw+m2mroa tD21CBWbth0iL3kRP73cRkO6TX/HfUTMTCLqKvjuNB8cbClMxk5xa20uyF4FYbsOf+ kB0k2YCpJJeh6eyq4CJkKRMurmV/kXjCxeV1ASLxFryvoTifjHt+VkhwV717y4SIl6 6UPLNgwJjFpgqrkXVCJGPnpM0I/C81AreJ2/E/8PiguvsHx3TxRjW8BcLWK1kYWrwe tlMa7v0LcYsnIXEpWAK2MgZVoK88ygD2tVK/UL2BXL0HQN+kzhpT3ZgQ9rKX2hrHlP RGds7vzvtEVmA== From: Roger Quadros Date: Mon, 05 May 2025 19:26:31 +0300 Subject: [PATCH net-next v2 1/9] net: ethernet: ti: cpsw_ale: Update Policer fields for more ALE size/ports Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250505-am65-cpsw-rx-class-v2-1-5359ea025144@kernel.org> References: <20250505-am65-cpsw-rx-class-v2-0-5359ea025144@kernel.org> In-Reply-To: <20250505-am65-cpsw-rx-class-v2-0-5359ea025144@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2711; i=rogerq@kernel.org; h=from:subject:message-id; bh=u7HKkwOPvItFSrEFnYEsRbbOURBbm71UWURQboRepAs=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoGOa6f11vlH1akMfGGi2ce9Q9UGvEtRj5pn5W/ CYgx4P1Zp2JAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaBjmugAKCRDSWmvTvnYw kyStD/9LH21q8ModEJVKq9rYaAq1MaMhKO33F4ioQ3seBTURZg4h7oQ74jhgbV/YArCOt854O42 EzOd+IgoutZn8ODyZape1HVUFfoG1HRYgAyWyV6GYGnb47V7HAEPr0a475G6+N4mAS3AefyIC98 lRWpdKoECtYwtUxgk/4YCxOXgUVARD44jQ3DiwDyAfXyTkdpO/ZLd2QiedWwQPE1XNoOR3GLjS8 vkiDaQzYH1rHQyTGDPwMQLmCCaesDiucxmHYvND0JBx9KTpDdbh7Pt0wI+R7HGMY/egABbX9etJ qpNnbkLxfEIq5QhHu/FrnvMT4YTb2X3uacWh2hsLoQy5WU/zMUofZFEiYd2gJd3rLy3Akgu9Py9 80xpiZJlbRCVKZxemKJVEf2Jl89gNbXUV00/Rxe32XPQgFARpbAy5O1tClDhUL19yE3Q3qw+yig Z5JFNAMNvQgYI96vQfoQ59620V6OoGaJum1vHpnyf7yUSJGNU/PcNLWblNv9XdWEI3M59uY7J1a 4JPRVhUO08XneAuiWUQ1wWNHpFJ5Mo93CTsjQBbA/glHVjO+ea2zaqiuENjARyR0b1ZkVVzaybc pc86SSu31CvrfTy7FvBBX0jumB7U5aBvmjVCW9Cgukq0Kb9FbrkkyIwGovoB7nFlJMXSiCMyz8P xUFyNH8nQq1KfHQ== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Different SoCs have different sized ALE table and number of ports. Expand the Policer fields to support 16 ports and 1024 ALE entries. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw_ale.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 7f77694ecfba..7bb63aad7724 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -1341,33 +1341,33 @@ static const struct reg_field ale_fields_cpsw_nu[] = { /* CPSW_ALE_POLICER_PORT_OUI_REG */ [POL_PORT_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 31, 31), [POL_TRUNK_ID] = REG_FIELD(ALE_POLICER_PORT_OUI, 30, 30), - [POL_PORT_NUM] = REG_FIELD(ALE_POLICER_PORT_OUI, 25, 25), + [POL_PORT_NUM] = REG_FIELD(ALE_POLICER_PORT_OUI, 25, 28), [POL_PRI_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 19, 19), [POL_PRI_VAL] = REG_FIELD(ALE_POLICER_PORT_OUI, 16, 18), [POL_OUI_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 15, 15), - [POL_OUI_INDEX] = REG_FIELD(ALE_POLICER_PORT_OUI, 0, 5), + [POL_OUI_INDEX] = REG_FIELD(ALE_POLICER_PORT_OUI, 0, 9), /* CPSW_ALE_POLICER_DA_SA_REG */ [POL_DST_MEN] = REG_FIELD(ALE_POLICER_DA_SA, 31, 31), - [POL_DST_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 16, 21), + [POL_DST_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 16, 25), [POL_SRC_MEN] = REG_FIELD(ALE_POLICER_DA_SA, 15, 15), - [POL_SRC_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 0, 5), + [POL_SRC_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 0, 9), /* CPSW_ALE_POLICER_VLAN_REG */ [POL_OVLAN_MEN] = REG_FIELD(ALE_POLICER_VLAN, 31, 31), - [POL_OVLAN_INDEX] = REG_FIELD(ALE_POLICER_VLAN, 16, 21), + [POL_OVLAN_INDEX] = REG_FIELD(ALE_POLICER_VLAN, 16, 25), [POL_IVLAN_MEN] = REG_FIELD(ALE_POLICER_VLAN, 15, 15), - [POL_IVLAN_INDEX] = REG_FIELD(ALE_POLICER_VLAN, 0, 5), + [POL_IVLAN_INDEX] = REG_FIELD(ALE_POLICER_VLAN, 0, 9), /* CPSW_ALE_POLICER_ETHERTYPE_IPSA_REG */ [POL_ETHERTYPE_MEN] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 31, 31), - [POL_ETHERTYPE_INDEX] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 16, 21), + [POL_ETHERTYPE_INDEX] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 16, 25), [POL_IPSRC_MEN] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 15, 15), - [POL_IPSRC_INDEX] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 0, 5), + [POL_IPSRC_INDEX] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 0, 9), /* CPSW_ALE_POLICER_IPDA_REG */ [POL_IPDST_MEN] = REG_FIELD(ALE_POLICER_IPDA, 31, 31), - [POL_IPDST_INDEX] = REG_FIELD(ALE_POLICER_IPDA, 16, 21), + [POL_IPDST_INDEX] = REG_FIELD(ALE_POLICER_IPDA, 16, 25), /* CPSW_ALE_POLICER_TBL_CTL_REG */ /** From patchwork Mon May 5 16:26:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 887980 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A295325DCEC; Mon, 5 May 2025 16:26:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746462405; cv=none; b=N9DF3fI7RmPg4fjf74Vg8+5QrhvV0lc61j+ms6euWwvGr+sLdGC1MyXz7G88FuYdYQ4BDlHp0oK3429xtbi1cPAYGR1IdMI4eOSiNr+pVvhStSqTHmnNigypHPRG1FClvFaMFn0Gk9G9Duhad9rVo5Rs46kA4Fzz0rafKg9nFMo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746462405; c=relaxed/simple; bh=YbtaSFXvEqscgWdaWU4X/6cPyfGpueE1ti1NCjiITjk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2474; i=rogerq@kernel.org; h=from:subject:message-id; bh=YbtaSFXvEqscgWdaWU4X/6cPyfGpueE1ti1NCjiITjk=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoGOa6TQt6aiPNyp839anENScUA0fz9kZx8hXM6 6KPV9mhAGWJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaBjmugAKCRDSWmvTvnYw k6HLEADILWBsl/ODdlvVbpq71DOfdKVCgrMrAwaOPiOcSK2BplMNYjE1LKvyQJi+S6KFjn38mJv CILD2gIivEqh4XHiMToDJFswZ2L/LuPr+7ZvEcO1n5SnOufSIih5P8oemMeWEPUWUFACe76VfFY lB3uhknLDzmvdytTRVFbkYooGC8SVVibpZpWacp4Bzmj7OS7DTIpy5ymfEgbgxgbyN1zh2N6ZjO kkqh+laUImVcebSGwKPNq6bV5L9Xsz06Gxb2hmoLzICCUCP1trloIhRS3owBOtQTk6RpkAUuCcq MNUuTAJuzaM0ua81xj0pYyzOh/jTonWxTlMeuMP1QiEhm8t5Htw1PvU5z77iXazM6jDmrIz/t1d xw1pHzW+z8OeUrgMzXH3zFZyVKdaKOG1KmjPcBctnImeSw0Aoy7TsCh8YpOzGwOi+2Co7mskzT1 YpzY2uJCiCfeBNfgKHLRmbUir5TOGzyQ9UMfcb95yB77ULYvPKUUXSgx35pbtD/3IoguB9uLsXw tWUIaCSssA7MK/10hhnp7vZOEVUHtqOl6+dWmH6SKbM4QMCmE7zTnWaotMEp/aRheNLfCkt35G8 MTmntHPSdtr2zrJGltg/lpmvfYDLi0d/Ya2BR++JUq/DBMzlucVom+/pzWkN1rTCRjTx1+tGXmQ 8BvhDVaPjf+34xQ== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Policer helpers will be interested to know what ALE index was used for the added VLAN entry. So return the ALE index instead of zero on success. Modify existing users to check for less than zero as error case. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw.c | 2 +- drivers/net/ethernet/ti/cpsw_ale.c | 6 +++--- drivers/net/ethernet/ti/cpsw_new.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index a984b7d84e5e..2d23cba557f3 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -1026,7 +1026,7 @@ static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask, unreg_mcast_mask); - if (ret != 0) + if (ret < 0) return ret; ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 7bb63aad7724..0bdc95552410 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -680,7 +680,7 @@ int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag, return -ENOMEM; cpsw_ale_write(ale, idx, ale_entry); - return 0; + return idx; } static void cpsw_ale_vlan_del_modify_int(struct cpsw_ale *ale, u32 *ale_entry, @@ -803,14 +803,14 @@ int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, ret = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members, reg_mcast_members, unreg_mcast_members); - if (ret) { + if (ret < 0) { dev_err(ale->params.dev, "Unable to add vlan\n"); return ret; } dev_dbg(ale->params.dev, "port mask 0x%x untag 0x%x\n", vlan_members, untag_mask); - return ret; + return 0; } void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, diff --git a/drivers/net/ethernet/ti/cpsw_new.c b/drivers/net/ethernet/ti/cpsw_new.c index 5b5b52e4e7a7..1516171352cd 100644 --- a/drivers/net/ethernet/ti/cpsw_new.c +++ b/drivers/net/ethernet/ti/cpsw_new.c @@ -417,7 +417,7 @@ static int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask, unreg_mcast_mask); - if (ret != 0) + if (ret < 0) return ret; ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, From patchwork Mon May 5 16:26:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 887693 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 037B425DCEC; Mon, 5 May 2025 16:26:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746462409; cv=none; b=mlzU7tH6V4tp45GPdjLVWnQbnAWbZ+E1R4fbbrtSJWR1n3Ba9yv3iQSMmeYHDb/Ut+LOw0VFrxZlKgOqal4RWQavaA8D0cs8U3Wgv09AMBnDAXf8pvBpbkDGNOPQj5WJTFubrCiqH+EHy3krvA9x8Z0KE0hVrlB+bcASjDW4WbQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746462409; c=relaxed/simple; bh=XODr01mBk67NGT5K13Cytm++Hq/blxxRyGOdquDJpL4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mPZklA08v7fGPk8E/7RliEwBDR+PlXIIhuv9K68wVBWum0vW6Y2Fi5nRWI9rtGR6zACFkLhS2RHWx9kJvocp4JKh7zOI6xp0UT0O9H3LH+6C/8c4/XhRCxGTF3c2c4831ponoqykOmpqW+XIl9vVirJU3kCX/KtvBt4GqKwC6m8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qqS5uUyl; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qqS5uUyl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9C408C4CEE4; Mon, 5 May 2025 16:26:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746462408; bh=XODr01mBk67NGT5K13Cytm++Hq/blxxRyGOdquDJpL4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qqS5uUylBdTIF4Lj64x57u4EfOaQRDEvI8/p5zof67F9/lIq9IF/BTqsK1kb0xdy/ JeZA4BBNC9hlu9TLWxjG+J9R2/EpHo2ykDr3PnzLkpNbS/NOZaKjJd2h0vM+iW60xI /5pW+r6aj41DEbbWE21a19juHPb9RTR47r+sK062Pm3qf3Nbrfn/oSn02GNYB6VZhu FmyJv49XLy+WAvpmhrf0tKBx5HwSpbXS7xJlsFrU0xFjW4oTD+Pw8jFqt0lbp1OzQj OXtk3PTUcXOAgB57vi+N9qiDZZq23mslDIR7WFQcNQnCyPgtqIk6wYhVGAu5arJXJe ZvczoHWbI4vew== From: Roger Quadros Date: Mon, 05 May 2025 19:26:33 +0300 Subject: [PATCH net-next v2 3/9] net: ethernet: ti: cpsw_ale: return ALE index in cpsw_ale_vlan_add_modify() Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250505-am65-cpsw-rx-class-v2-3-5359ea025144@kernel.org> References: <20250505-am65-cpsw-rx-class-v2-0-5359ea025144@kernel.org> In-Reply-To: <20250505-am65-cpsw-rx-class-v2-0-5359ea025144@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4563; i=rogerq@kernel.org; h=from:subject:message-id; bh=XODr01mBk67NGT5K13Cytm++Hq/blxxRyGOdquDJpL4=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoGOa6FwLNbYchKsPQR5sUS7g1ukY1KSqi2NZRm MSir8ilsxyJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaBjmugAKCRDSWmvTvnYw kw4hEADSwMayGELoT4nXwP0HkwBWxJ1Va8NuPdkj7FpQEo96vuT+/26Xd+VUKQzlFWmoRtIZQFD 0tKfTPr0LOMwOE1DAwNstirqocAKfr847jfh+mz8XkmB4zFM5v5mOeUNDqrAI9AXsq1hnFSYVKn b+cZi8CUqMJRQH9s380YWUNJiWHzRqQPrIWsAA6V/5Tf4OyjAEsMHknIRdAVAvr4d5KdFykpA5Y 8BPaE8jRz/aNeVZIrfoVu8XEmajGEr92crh+bvk9qFtgDPTDrDPk9QesSuF0hRmzwSCtHKDrRZl TTVRI/eQJFUchWRHVkX7jU+aivy4nXNA9z0+1Vn6WiyaCwaeXkgPaefUEib48w58jMUHk0+5Ijh Omp//x2LLbXtWWpZxdtydQB1lvOXEQogec+Nln0AtlNv4UGWL/wQrdLNrDdPukeKKxoZKkEcMi3 9UKh3OD32+dbGgDI+OpVUNASb1a7MMtGdq7PdBIVCKBd+C6c41qPOafV0CqsQzgXRHCSTJw95y/ ovztIp7y8vojQIgw8snEMeHu2vkRAlcmaNY7ZcmiL1c48Hfp+bRD4rIE11kMnDEH9j6L+jHawD5 eESNGGidWm31ahMHVqWPDWG8/7AqAdHmvc6Bc59NOhrMcMKq9XnuJOnx/AgPa1Krre2WVQYqPKP dXb+lJMHqRS4z6Q== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Policer helpers will need to know what ALE index was used for the added VLAN entry. So return the ALE index instead of zero on success. Modify existing users to check for less than zero as error case. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 2 ++ drivers/net/ethernet/ti/am65-cpsw-switchdev.c | 6 +++--- drivers/net/ethernet/ti/cpsw_ale.c | 10 +++++----- drivers/net/ethernet/ti/cpsw_switchdev.c | 6 +++--- 4 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 988ce9119306..41dc963493de 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -321,6 +321,8 @@ static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, unreg_mcast, port_mask, 0); + if (ret > 0) + ret = 0; pm_runtime_put(common->dev); return ret; diff --git a/drivers/net/ethernet/ti/am65-cpsw-switchdev.c b/drivers/net/ethernet/ti/am65-cpsw-switchdev.c index d4c56da98a6a..b284202bf480 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-switchdev.c +++ b/drivers/net/ethernet/ti/am65-cpsw-switchdev.c @@ -175,7 +175,7 @@ static int am65_cpsw_port_vlan_add(struct am65_cpsw_port *port, bool untag, bool ret = cpsw_ale_vlan_add_modify(cpsw->ale, vid, port_mask, untag_mask, reg_mcast_mask, unreg_mcast_mask); - if (ret) { + if (ret < 0) { netdev_err(port->ndev, "Unable to add vlan\n"); return ret; } @@ -184,14 +184,14 @@ static int am65_cpsw_port_vlan_add(struct am65_cpsw_port *port, bool untag, bool cpsw_ale_add_ucast(cpsw->ale, port->slave.mac_addr, HOST_PORT_NUM, ALE_VLAN | ALE_SECURE, vid); if (!pvid) - return ret; + return 0; am65_cpsw_set_pvid(port, vid, 0, 0); netdev_dbg(port->ndev, "VID add: %s: vid:%u ports:%X\n", port->ndev->name, vid, port_mask); - return ret; + return 0; } static int am65_cpsw_port_vlan_del(struct am65_cpsw_port *port, u16 vid, diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 0bdc95552410..952444b0c436 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -780,7 +780,7 @@ int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; int reg_mcast_members, unreg_mcast_members; int vlan_members, untag_members; - int idx, ret = 0; + int idx; idx = cpsw_ale_match_vlan(ale, vid); if (idx >= 0) @@ -801,16 +801,16 @@ int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, reg_mcast_members = (reg_mcast_members & ~port_mask) | reg_mask; unreg_mcast_members = (unreg_mcast_members & ~port_mask) | unreg_mask; - ret = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members, + idx = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members, reg_mcast_members, unreg_mcast_members); - if (ret < 0) { + if (idx < 0) { dev_err(ale->params.dev, "Unable to add vlan\n"); - return ret; + return idx; } dev_dbg(ale->params.dev, "port mask 0x%x untag 0x%x\n", vlan_members, untag_mask); - return 0; + return idx; } void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, diff --git a/drivers/net/ethernet/ti/cpsw_switchdev.c b/drivers/net/ethernet/ti/cpsw_switchdev.c index ce85f7610273..c767a47b2039 100644 --- a/drivers/net/ethernet/ti/cpsw_switchdev.c +++ b/drivers/net/ethernet/ti/cpsw_switchdev.c @@ -191,7 +191,7 @@ static int cpsw_port_vlan_add(struct cpsw_priv *priv, bool untag, bool pvid, ret = cpsw_ale_vlan_add_modify(cpsw->ale, vid, port_mask, untag_mask, reg_mcast_mask, unreg_mcast_mask); - if (ret) { + if (ret < 0) { dev_err(priv->dev, "Unable to add vlan\n"); return ret; } @@ -200,13 +200,13 @@ static int cpsw_port_vlan_add(struct cpsw_priv *priv, bool untag, bool pvid, cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, ALE_VLAN, vid); if (!pvid) - return ret; + return 0; cpsw_set_pvid(priv, vid, 0, 0); dev_dbg(priv->dev, "VID add: %s: vid:%u ports:%X\n", priv->ndev->name, vid, port_mask); - return ret; + return 0; } static int cpsw_port_vlan_del(struct cpsw_priv *priv, u16 vid, From patchwork Mon May 5 16:26:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 887979 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FC6226C39B; Mon, 5 May 2025 16:26:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 5 May 2025 16:26:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746462411; bh=7wsQp+uaWY2u0ja4R/dpHDQPnssNtRTBw5npmaUzg0A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=gj2aZOo4MghVr6PTzgSlY9bCgmt9o/7awBC/+9hoIixc/6EyWXan/Tv4P90oDaBST aS5dpBxuY++WZKMjSaPqshLXoJkBw0vnQSHx2zvmufuVjBn08j0K/Tcec1YRmKff2B uFhRb56vyXQoz7euov9Fckr1iNMRtvNBz3AOPkG37TTSd1b5S28EkT2r/uN7btwyBN U/9PpyIHB4iM3JKayvDMYQdJlYlHIC8DyHVuBlyB00e87gfUgPqWD4NqM9orS0Ka9t R6sT/qHqsp6I2CbpzZjAcoyGFbzo0yjwJ6r7zPQe31zY8/iii2PXHroxNQgq0zi6WQ dXz3ekFSzLT9A== From: Roger Quadros Date: Mon, 05 May 2025 19:26:34 +0300 Subject: [PATCH net-next v2 4/9] net: ethernet: ti: cpsw_ale: return ALE index in cpsw_ale_add_ucast() Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250505-am65-cpsw-rx-class-v2-4-5359ea025144@kernel.org> References: <20250505-am65-cpsw-rx-class-v2-0-5359ea025144@kernel.org> In-Reply-To: <20250505-am65-cpsw-rx-class-v2-0-5359ea025144@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1944; i=rogerq@kernel.org; h=from:subject:message-id; bh=7wsQp+uaWY2u0ja4R/dpHDQPnssNtRTBw5npmaUzg0A=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoGOa6yvThunF18TA8PcqL2OmM0u/QrmdXDtTqP bgjjBlfg+iJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaBjmugAKCRDSWmvTvnYw k9KyEADDMfoT/r0h/Sk73TNq9pb3xg58b+6J7Uw66LJka/0DdFijL40nn8j0U0Au+GhPjhJzAyx XBgp/Im/QXLJadyXfK/CRDirYIAJds2Hkr5uwdBerfM009o/OLQf59Np/IVMFYqTIh+X9fu11SM iN7HrASNogzvSN6X8Ho6RCGMxZyWPlc4PHRyMDN6kYg3+h0r2pNfrVRcsyGtyStFEH8glABGn2Z Y5WWCAikWUghqgukCcekv3/uUPPiUa9N7byH91LYV83P/v5JV0iJpZKuZOtzbKttfDlIKzdsDCs 0meNw2rMkuHuMZd0fXa2kdNMUX9F1YMy1c37vQmw/kYpU6kvOwgfZJKb1lRPfGZsuS2jy6Yo8sW 3D8BQj09I3M7DdyMFQa3YpXwMpx7TYaw+DC0c7uphuydBJMwqwzP4wWcWY+sRjsNRul5uvi9Bbn f7RIRquMgdgKP2xIlL1Qva/uq/Z5wAYQbI5npbAjIhSkl3bxms45NwfCAcCh//dZoBrunV5xLRn sSHTBaxAgd9JwkQClCdRXscRDaxxa3E2co8cj9JoTbrx2H0ahx9Bcq6gmxkApKmlZ64jle5QBG/ ytDJfHu6AENeq/4JgOKOf6bqEIuUrUENIJAfleF4s5MgF8tMRD337qzlyCI52uApCe11DSQTtiH E5XIy7+fJtNgAHg== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Policer helpers will need to know what ALE index was used for the added unicast entry. So return the ALE index instead of zero on success. Modify existing users to check for less than zero as error case. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw.c | 2 +- drivers/net/ethernet/ti/cpsw_ale.c | 2 +- drivers/net/ethernet/ti/cpsw_new.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 2d23cba557f3..d1abd2fb63c9 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -1031,7 +1031,7 @@ static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, ALE_VLAN, vid); - if (ret != 0) + if (ret < 0) goto clean_vid; ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 952444b0c436..74dc431f1c1b 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -534,7 +534,7 @@ int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port, return -ENOMEM; cpsw_ale_write(ale, idx, ale_entry); - return 0; + return idx; } int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port, diff --git a/drivers/net/ethernet/ti/cpsw_new.c b/drivers/net/ethernet/ti/cpsw_new.c index 1516171352cd..944fa3db94a2 100644 --- a/drivers/net/ethernet/ti/cpsw_new.c +++ b/drivers/net/ethernet/ti/cpsw_new.c @@ -422,7 +422,7 @@ static int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, ALE_VLAN, vid); - if (ret != 0) + if (ret < 0) goto clean_vid; ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, From patchwork Mon May 5 16:26:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 887692 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84D5D268684; Mon, 5 May 2025 16:26:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746462415; cv=none; b=Q+399RrGL7aoW9McSt8+fOOTsPb/Bjv2VikfgBSB0emHvuhWGsqAS2IMIBEoxGCeTpKrlWth/uMmFUc773uffB+UdbePXlvMgxG/hmIsFlAhcWPIHpc/awgdt5rMK2b3qEbqEOkF0h+Rw8jfCdqVeDVJvEHG3z3JtPCsEQnYBDg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746462415; c=relaxed/simple; bh=GdBpx6MqbpI0u0QoDfqyPuHJ43rlaIHaOD2v+M+Vh8Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dgTEv0UHZCwSbtP2AhcGrRuN3FD1umZLsDPcO5HCCecL4bUNBXCfU6PhSIFJX9eMZN6MGRJHCWh5rKadbrUegaE4gCD1xXDCZnIusnHKhI+fjyp3lCjj7axleGTag1ZSlW7gEQ/VpyR/Ig+Dw69v4x6u32Ivd9U2VP6lJIHYD+M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JARlo/aQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JARlo/aQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2A504C4CEE4; Mon, 5 May 2025 16:26:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746462415; bh=GdBpx6MqbpI0u0QoDfqyPuHJ43rlaIHaOD2v+M+Vh8Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=JARlo/aQbI7ylo0Vy3ogw5tZDew3Oc6tO/hmWy/S/xSS3l6xfekVIjs0Fse1BJWUt kudDcBbQOHt1P7aIUozT1XwCV5WaZ7ge7szrsOJaPsfFrYVtCfVWQ5rb8Em67tXckG cEfkSh6dCA/Xyw0KAAbqLYaznp6U9ii9cLFz3aCx60bMQAEJMiWKQ4pd/TBXBfxmQN tGL9oROteGApKcV0X8u5DnENXlVvd5HiA/BLUR+M5v+6zMGoGmBqqWkCoAkUy5XrMc SunMbdSlWL38JPo28VETR9A8QY6t73fPyS2RBEjfxP9p6Qj+LjUsY7+zSOJmh2D9sP +E5lj7SNw0BfA== From: Roger Quadros Date: Mon, 05 May 2025 19:26:35 +0300 Subject: [PATCH net-next v2 5/9] net: ethernet: ti: cpsw_ale: add cpsw_ale_policer_reset_entry() Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250505-am65-cpsw-rx-class-v2-5-5359ea025144@kernel.org> References: <20250505-am65-cpsw-rx-class-v2-0-5359ea025144@kernel.org> In-Reply-To: <20250505-am65-cpsw-rx-class-v2-0-5359ea025144@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3404; i=rogerq@kernel.org; h=from:subject:message-id; bh=GdBpx6MqbpI0u0QoDfqyPuHJ43rlaIHaOD2v+M+Vh8Q=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoGOa7Vg1u72naCQzy8UvJEsYjzls5dgOPKFeYM kJwVzsLSteJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaBjmuwAKCRDSWmvTvnYw kz51D/9LvdfA+35GD8sdnoS102Q6W4wp3TJccLJTfYtWENtaRrpjNz3LusNzmgwdd7ICPNEOM04 RgPfKsTbqu/zO44mbVLekHY9XAYTwlotbE18EMIxruv2u9MbCDTEmUqh+pEm9TrOWFd3PG7GUTW SU0ZtXWho5hGSPCnqK2wo7eoyUNBe/xH8dE2bN810T7vIZ05lgPsCQXxMq4JHdeS9N30YKb/BCW CczmIeDgs2IST8AfD9iJpo3uhqu2apaiRx6UQvmjG1VwOEuskxwOoKiY5YN+m6MliZd6LJWbMYY uJOwLy6u/F2mLZUDpYMLkIYOLFwxbCyOYy6Aw1a3nPEAZZRLzHm15m6AUp8wooFOHKNeUfQ8S1+ D4Xb4VRLk0IDDC7D1xi9b4g49Nj5jXxvrqcQoiYlE4I8bna5CFIduOumd59lXwPZHKiN6yiwjFC zgaWrwsVh36C+TjqFcqL5sgSYpGqeuPstVPw78/Zl8HNiWDDZEzZhReB4BlTBYBqlzwwUauJR6D zkS4gXrp8yH0OwQrtcB2IVSKtjScENaVNlgKMgMTqNiofEaiRJ6Ya7yR4RCHsT0LAn5ip+J5tTo Dau7kURa6B1Y/aC9SYuDmif5nsllE+Q1yvL7cEkQakRxv0FtrCnnd+TcDUrAxUCnhF0YudZZWY1 Vj4suJoT0FuvlEQ== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Add new helper cpsw_ale_policer_reset_entry() to reset a single policer entry. Clear all fields instead of just clearing the enable bits. Export cpsw_ale_policer_reset() as it will be required by cpsw drivers using policer. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw_ale.c | 35 +++++++++++++++-------------------- drivers/net/ethernet/ti/cpsw_ale.h | 4 ++++ 2 files changed, 19 insertions(+), 20 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 74dc431f1c1b..49ea1c00be3d 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -1674,30 +1674,25 @@ static void cpsw_ale_policer_thread_idx_enable(struct cpsw_ale *ale, u32 idx, regmap_field_write(ale->fields[ALE_THREAD_ENABLE], enable ? 1 : 0); } +static void cpsw_ale_policer_reset_entry(struct cpsw_ale *ale, u32 idx) +{ + int i; + + cpsw_ale_policer_read_idx(ale, idx); + for (i = 0; i < CPSW_ALE_POLICER_ENTRY_WORDS; i++) + writel_relaxed(0, ale->params.ale_regs + + ALE_POLICER_PORT_OUI + 4 * i); + cpsw_ale_policer_thread_idx_enable(ale, idx, 0, 0); + cpsw_ale_policer_write_idx(ale, idx); +} + /* Disable all policer entries and thread mappings */ -static void cpsw_ale_policer_reset(struct cpsw_ale *ale) +void cpsw_ale_policer_reset(struct cpsw_ale *ale) { int i; - for (i = 0; i < ale->params.num_policers ; i++) { - cpsw_ale_policer_read_idx(ale, i); - regmap_field_write(ale->fields[POL_PORT_MEN], 0); - regmap_field_write(ale->fields[POL_PRI_MEN], 0); - regmap_field_write(ale->fields[POL_OUI_MEN], 0); - regmap_field_write(ale->fields[POL_DST_MEN], 0); - regmap_field_write(ale->fields[POL_SRC_MEN], 0); - regmap_field_write(ale->fields[POL_OVLAN_MEN], 0); - regmap_field_write(ale->fields[POL_IVLAN_MEN], 0); - regmap_field_write(ale->fields[POL_ETHERTYPE_MEN], 0); - regmap_field_write(ale->fields[POL_IPSRC_MEN], 0); - regmap_field_write(ale->fields[POL_IPDST_MEN], 0); - regmap_field_write(ale->fields[POL_EN], 0); - regmap_field_write(ale->fields[POL_RED_DROP_EN], 0); - regmap_field_write(ale->fields[POL_YELLOW_DROP_EN], 0); - regmap_field_write(ale->fields[POL_PRIORITY_THREAD_EN], 0); - - cpsw_ale_policer_thread_idx_enable(ale, i, 0, 0); - } + for (i = 0; i < ale->params.num_policers ; i++) + cpsw_ale_policer_reset_entry(ale, i); } /* Default classifier is to map 8 user priorities to N receive channels */ diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index 87b7d1b3a34a..ce59fec75774 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -156,6 +156,9 @@ enum cpsw_ale_port_state { #define ALE_ENTRY_BITS 68 #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32) +/* Policer */ +#define CPSW_ALE_POLICER_ENTRY_WORDS 8 + struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params); void cpsw_ale_start(struct cpsw_ale *ale); @@ -195,5 +198,6 @@ int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask); void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, bool add); void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch); +void cpsw_ale_policer_reset(struct cpsw_ale *ale); #endif From patchwork Mon May 5 16:26:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 887978 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AC2226FA4C; Mon, 5 May 2025 16:26:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Mon, 5 May 2025 16:26:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746462418; bh=yvDolz4DU7x4F3IPiMMAYL9Zyt+CPJcn+6QaEzC3KRo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=V/MAOkKnjiopeNpR9BhSqWbvOdIrJQyGYYVmHA6ZqpIUtl9KPh4A8oWKO9AWk89yh KEIec7XTE5laMY1a4w8faxr9XsL3eyUfXLZEzvJApTC+jeJmuJ6pxj54+VG/ppeZYU W2F+vfJEUClKexCnfvcU4cE5VJXX9QwVgQocmI50Zry9VRO4dqb/wk4OPeMrGjwqCK a4JynTW5Bk2sIS7EPGPSubneQDOv1jvZdnapsOZCDOoNS2azXmt1WaejMRQ4C6xt+r Pfwdf7ojcaZikbBBdKqI8sNOX83LrBweSmULgTn6VSAEO/pup03Ev4CQoV+thLWUBB lyTlfPbyMXvYg== From: Roger Quadros Date: Mon, 05 May 2025 19:26:36 +0300 Subject: [PATCH net-next v2 6/9] net: ethernet: ti: cpsw_ale: add cpsw_ale_policer_set/clr_entry() Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250505-am65-cpsw-rx-class-v2-6-5359ea025144@kernel.org> References: <20250505-am65-cpsw-rx-class-v2-0-5359ea025144@kernel.org> In-Reply-To: <20250505-am65-cpsw-rx-class-v2-0-5359ea025144@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4792; i=rogerq@kernel.org; h=from:subject:message-id; bh=yvDolz4DU7x4F3IPiMMAYL9Zyt+CPJcn+6QaEzC3KRo=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoGOa7Gm21sYBhG1CpZRJf0DHMG87OOk7k+WGzR Y6C4ZXrxVGJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaBjmuwAKCRDSWmvTvnYw kwG2EADBvVqydLT3rg1z+ex9erQ19pF2wu8cGBNQmfJg7OJM14/Grj/DrtQYoUsO8w6d6wdFN3T ajjwDgdOyhfv3ZYvL3jeoKmz8uV1Q7UA6Zd6a6gpXwMlUO/OwUyDazvvVGjNScjPsW/txzU0Lfy iNMj29w7yeZGffQ200gdcDx0SaRnI4Y7KhKLY0O+XoXH+HdbcUg0NLXzFdEjEfpRI/TCG+Q6xfY ZOuht8LfM5xTjYh2HhqJrHPmG7CGrn11SWNp525SY+7f6R1eKt0CYOq+IT/FETMlLb2WUb9fv3S d1s0BBQdeR/dzn39bmWlg1SQAbhaEMYoa4U8y4jv2iCC8L+MxZedc8gMiG8l+qWA/RAbbfuMKeA T6wBS3m+rAwCTtPIWme/ZYbEfH/iV2whGdOE9JNUSxQh/nCaSKXCfAmF7wODoxtoER9EypgNhNb Ru3FEb7AO3ADk0EVo/NVRPTlCYScN27hW4oteLs87ZgF7jlL3KzYCyCemOy9FROmkCFtHQKFf+z tN//ychvL5Yuk44nBLsmkWkyFqBxECazLJ9IRNI3fjoic3/nVOkRt94OouVzZcRLk74TnKYcs9F GTY9/pld0+vpb/KQBpOH8iv0mq/6J6cylgftuxDvCK7CdawdKD9VVvtsdujjpd8BP5qGwqV8LDE LF0TW5x/4I+Q1fg== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Add cpsw_ale_policer_set/clr_entry() helpers. So far Raw Ethernet matching based on Source/Destination address and VLAN Priority (PCP) is supported. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw_ale.c | 77 ++++++++++++++++++++++++++++++++++++++ drivers/net/ethernet/ti/cpsw_ale.h | 28 ++++++++++++++ 2 files changed, 105 insertions(+) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 49ea1c00be3d..ce216606d915 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -1746,3 +1746,80 @@ void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch) 1); } } + +#define HOST_PORT_NUM 0 + +/* Clear Policer and associated ALE table entries */ +void cpsw_ale_policer_clr_entry(struct cpsw_ale *ale, u32 policer_idx, + struct cpsw_ale_policer_cfg *cfg) +{ + cpsw_ale_policer_reset_entry(ale, policer_idx); + + /* We do not delete ALE entries that were added in set_entry + * as they might still be in use by the port e.g. VLAN id + * or port MAC address + */ + + /* clear BLOCKED in case we set it */ + if ((cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACSRC) && cfg->drop) + cpsw_ale_add_ucast(ale, cfg->src_addr, HOST_PORT_NUM, 0, 0); + + if ((cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACDST) && cfg->drop) + cpsw_ale_add_ucast(ale, cfg->dst_addr, HOST_PORT_NUM, 0, 0); +} + +int cpsw_ale_policer_set_entry(struct cpsw_ale *ale, u32 policer_idx, + struct cpsw_ale_policer_cfg *cfg) +{ + int ale_idx; + u16 ale_flags = cfg->drop ? ALE_BLOCKED : 0; + + /* A single policer can support multiple match types simultaneously + * There can be only one ALE entry per address + */ + cpsw_ale_policer_reset_entry(ale, policer_idx); + cpsw_ale_policer_read_idx(ale, policer_idx); + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACSRC) { + ale_idx = cpsw_ale_add_ucast(ale, cfg->src_addr, HOST_PORT_NUM, + ale_flags, 0); + if (ale_idx < 0) + return -ENOENT; + + /* update policer entry */ + regmap_field_write(ale->fields[POL_SRC_INDEX], ale_idx); + regmap_field_write(ale->fields[POL_SRC_MEN], 1); + } + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACDST) { + ale_idx = cpsw_ale_add_ucast(ale, cfg->dst_addr, HOST_PORT_NUM, + ale_flags, 0); + if (ale_idx < 0) + return -ENOENT; + + /* update policer entry */ + regmap_field_write(ale->fields[POL_DST_INDEX], ale_idx); + regmap_field_write(ale->fields[POL_DST_MEN], 1); + } + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_OVLAN) { + /* VLAN ID based flow routing not yet working, + * only PCP matching for now + */ + if (cfg->vid > 0) + return -EINVAL; + + regmap_field_write(ale->fields[POL_PRI_VAL], cfg->vlan_prio); + regmap_field_write(ale->fields[POL_PRI_MEN], 1); + } + + cpsw_ale_policer_write_idx(ale, policer_idx); + + /* Map to thread id provided by the config */ + if (!cfg->drop) { + cpsw_ale_policer_thread_idx_enable(ale, policer_idx, + cfg->thread_id, true); + } + + return 0; +} diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index ce59fec75774..11d333bf5a52 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -159,6 +159,30 @@ enum cpsw_ale_port_state { /* Policer */ #define CPSW_ALE_POLICER_ENTRY_WORDS 8 +/* Policer match flags */ +#define CPSW_ALE_POLICER_MATCH_PORT BIT(0) +#define CPSW_ALE_POLICER_MATCH_PRI BIT(1) +#define CPSW_ALE_POLICER_MATCH_OUI BIT(2) +#define CPSW_ALE_POLICER_MATCH_MACDST BIT(3) +#define CPSW_ALE_POLICER_MATCH_MACSRC BIT(4) +#define CPSW_ALE_POLICER_MATCH_OVLAN BIT(5) +#define CPSW_ALE_POLICER_MATCH_IVLAN BIT(6) +#define CPSW_ALE_POLICER_MATCH_ETHTYPE BIT(7) +#define CPSW_ALE_POLICER_MATCH_IPSRC BIT(8) +#define CPSW_ALE_POLICER_MATCH_IPDST BIT(9) + +struct cpsw_ale_policer_cfg { + u32 match_flags; + u16 ether_type; + u16 vid; + u8 vlan_prio; + u8 src_addr[ETH_ALEN]; + u8 dst_addr[ETH_ALEN]; + bool drop; + u64 thread_id; + int port_id; +}; + struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params); void cpsw_ale_start(struct cpsw_ale *ale); @@ -199,5 +223,9 @@ void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, bool add); void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch); void cpsw_ale_policer_reset(struct cpsw_ale *ale); +int cpsw_ale_policer_set_entry(struct cpsw_ale *ale, u32 policer_idx, + struct cpsw_ale_policer_cfg *cfg); +void cpsw_ale_policer_clr_entry(struct cpsw_ale *ale, u32 policer_idx, + struct cpsw_ale_policer_cfg *cfg); #endif From patchwork Mon May 5 16:26:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 887691 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD02A2701BA; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZZa8olk+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B2199C4CEE4; Mon, 5 May 2025 16:26:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746462421; bh=vOL7NsEODFLHbpLefZlvmBkCViCZUZ+0w8a2r6CmrnA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ZZa8olk+pdPhq2zXn05ImM/+HL8KLXc1BPEHndev5byO5/kiFPtM+GpYgcf2WSac1 5RjXiua9Q735ppnAeSgGGrZa7AuGWMDaob1P9utPk6ekQQhVanSiiSPn6UXQ9oM8mf vSRoxs4ZDVDYCmAKMNJDR5BSsAb8HkTWrkkEEdkxjWhJ+QnU4hPJ5L6vYIGzY/jcm2 fNqofcRq3pH05xquh267a0CL0y52NOCpE13ZoHncHFsy8eNA5vxtc7ayeLFnGXlacx sgu2qtK5Uj/D9L/H3L2R7qM93sTLRBf9HkPDmxX4L5n1kkdA5DYhsQEyS4ZFOXd3pp DivjLuVXeE1tA== From: Roger Quadros Date: Mon, 05 May 2025 19:26:37 +0300 Subject: [PATCH net-next v2 7/9] net: ethernet: ti: cpsw_ale: add policer save restore for PM sleep Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250505-am65-cpsw-rx-class-v2-7-5359ea025144@kernel.org> References: <20250505-am65-cpsw-rx-class-v2-0-5359ea025144@kernel.org> In-Reply-To: <20250505-am65-cpsw-rx-class-v2-0-5359ea025144@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=5549; i=rogerq@kernel.org; h=from:subject:message-id; bh=vOL7NsEODFLHbpLefZlvmBkCViCZUZ+0w8a2r6CmrnA=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoGOa7cSAtKiTAgiDZN/YPupjeyoFWuZsF4zj5O FSgKIG1dhSJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaBjmuwAKCRDSWmvTvnYw kxPNEADMUrkK1nIU2BfUtmvw3qxTOW7nauunnaVaIpMTkc9c2utonY2I/uYRAt8P4gUSntW2jrK AQQ8ZnuzC4/ErDu+YdalAefnB6STCVVE4PTWJe73T3dei21MIvRig2+/4bJ6DGwY12fUEavXEw/ am/xWVW2oRwP0y7g5D64ns1Mc7xj9YxkzOLwxdfBqnh0duGNq4BfcaqThNQYU4mfDJoSN8XbMGN iIWaKNPGMiIXkcM4CvhUEyylfI9NxArNjlJmT3gkJPD7va3oUJWDJeOSK87vYKR+ehjJDABj4k1 DpKwPyGvj3mDfyoIEkIOqV+eyzLjZOs4Ej3DUk0PkM6wyqbTFSnxIBPZ+/bXqnB8JfdpDZlSwP4 rNMEyQoFmDfj530vER94c+ao7r1ci3c5iIeg/vwhtiNHVfP+t6uh5T5B0vnbk64+3b9iiBMOE6I 3QH1uXrtOkcdLSjKWkiOE/xOApbEiWI3grv92Eraw31by1XP8uKgponx1yWRKLdChSTWgPI8pSJ iLzCUSMSUvlGx0RmzTpSFTZXCRojDEJ1ES4jX3ac6ew9UsMQwmvEm4uell5eIXKFdC3ZfxuiAcl R0bJryoVZpXVa1PDrf2sbndVw/ZvvKhtYyB5+h+GQtffhppGwrY61meNH+ivSnnqk/STvzH5fB9 s7PMi7EUJn7CTKg== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 On some K3 platforms CPSW context is lost during PM sleep. Add cpsw_ale_policer_save() and cpsw_ale_policer_restore() helpers. In am65-cpsw driver, save the policer context during PM suspend and restore it during PM resume. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 24 +++++++++++++++--- drivers/net/ethernet/ti/am65-cpsw-nuss.h | 1 + drivers/net/ethernet/ti/cpsw_ale.c | 42 ++++++++++++++++++++++++++++++++ drivers/net/ethernet/ti/cpsw_ale.h | 4 +++ 4 files changed, 68 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 41dc963493de..07df61f343d3 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -3503,7 +3503,7 @@ static int am65_cpsw_nuss_probe(struct platform_device *pdev) struct device_node *node; struct resource *res; struct clk *clk; - int ale_entries; + int tbl_entries; __be64 id_temp; int ret, i; @@ -3606,10 +3606,26 @@ static int am65_cpsw_nuss_probe(struct platform_device *pdev) goto err_of_clear; } - ale_entries = common->ale->params.ale_entries; + tbl_entries = common->ale->params.ale_entries; common->ale_context = devm_kzalloc(dev, - ale_entries * ALE_ENTRY_WORDS * sizeof(u32), + tbl_entries * ALE_ENTRY_WORDS * sizeof(u32), GFP_KERNEL); + if (!common->ale_context) { + ret = -ENOMEM; + goto err_of_clear; + } + + tbl_entries = common->ale->params.num_policers; + i = CPSW_ALE_POLICER_ENTRY_WORDS + 1; /* 8 CFG + 1 Thread_val */ + i *= tbl_entries; /* for all policers */ + i += 1; /* thread_def register */ + common->policer_context = devm_kzalloc(dev, i * sizeof(u32), + GFP_KERNEL); + if (!common->policer_context) { + ret = -ENOMEM; + goto err_of_clear; + } + ret = am65_cpsw_init_cpts(common); if (ret) goto err_of_clear; @@ -3695,6 +3711,7 @@ static int am65_cpsw_nuss_suspend(struct device *dev) int i, ret; cpsw_ale_dump(common->ale, common->ale_context); + cpsw_ale_policer_save(common->ale, common->policer_context); host_p->vid_context = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); for (i = 0; i < common->port_num; i++) { port = &common->ports[i]; @@ -3772,6 +3789,7 @@ static int am65_cpsw_nuss_resume(struct device *dev) writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); cpsw_ale_restore(common->ale, common->ale_context); + cpsw_ale_policer_restore(common->ale, common->policer_context); return 0; } diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.h b/drivers/net/ethernet/ti/am65-cpsw-nuss.h index 917c37e4e89b..61daa5db12e6 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.h +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.h @@ -190,6 +190,7 @@ struct am65_cpsw_common { unsigned char switch_id[MAX_PHYS_ITEM_ID_LEN]; /* only for suspend/resume context restore */ u32 *ale_context; + u32 *policer_context; }; struct am65_cpsw_ndev_priv { diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index ce216606d915..4e29702b86ea 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -1823,3 +1823,45 @@ int cpsw_ale_policer_set_entry(struct cpsw_ale *ale, u32 policer_idx, return 0; } + +void cpsw_ale_policer_save(struct cpsw_ale *ale, u32 *data) +{ + int i, idx; + + for (idx = 0; idx < ale->params.num_policers; idx++) { + cpsw_ale_policer_read_idx(ale, idx); + + for (i = 0; i < CPSW_ALE_POLICER_ENTRY_WORDS; i++) + data[i] = readl_relaxed(ale->params.ale_regs + + ALE_POLICER_PORT_OUI + 4 * i); + + regmap_field_write(ale->fields[ALE_THREAD_CLASS_INDEX], idx); + data[i++] = readl_relaxed(ale->params.ale_regs + + ALE_THREAD_VAL); + data += i * 4; + } + + data[0] = readl_relaxed(ale->params.ale_regs + ALE_THREAD_DEF); +} + +void cpsw_ale_policer_restore(struct cpsw_ale *ale, u32 *data) +{ + int i, idx; + + for (idx = 0; idx < ale->params.num_policers; idx++) { + cpsw_ale_policer_read_idx(ale, idx); + + for (i = 0; i < CPSW_ALE_POLICER_ENTRY_WORDS; i++) + writel_relaxed(data[i], ale->params.ale_regs + + ALE_POLICER_PORT_OUI + 4 * i); + + cpsw_ale_policer_write_idx(ale, idx); + + regmap_field_write(ale->fields[ALE_THREAD_CLASS_INDEX], idx); + writel_relaxed(data[i++], ale->params.ale_regs + + ALE_THREAD_VAL); + data += i * 4; + } + + writel_relaxed(data[0], ale->params.ale_regs + ALE_THREAD_DEF); +} diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index 11d333bf5a52..dbc095397389 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -171,6 +171,8 @@ enum cpsw_ale_port_state { #define CPSW_ALE_POLICER_MATCH_IPSRC BIT(8) #define CPSW_ALE_POLICER_MATCH_IPDST BIT(9) +#define CPSW_ALE_POLICER_ENTRY_WORDS 8 + struct cpsw_ale_policer_cfg { u32 match_flags; u16 ether_type; @@ -227,5 +229,7 @@ int cpsw_ale_policer_set_entry(struct cpsw_ale *ale, u32 policer_idx, struct cpsw_ale_policer_cfg *cfg); void cpsw_ale_policer_clr_entry(struct cpsw_ale *ale, u32 policer_idx, struct cpsw_ale_policer_cfg *cfg); +void cpsw_ale_policer_save(struct cpsw_ale *ale, u32 *data); +void cpsw_ale_policer_restore(struct cpsw_ale *ale, u32 *data); #endif From patchwork Mon May 5 16:26:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 887977 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCA41269B12; Mon, 5 May 2025 16:27:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Mon, 5 May 2025 16:27:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746462424; bh=kqK6hHQTaJHQ96VDODJ0v+DmrVHAtIh7xRRj3giLYMM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=PclBL1z+/u5YHJJV3CBjDkyvkz7qgqF6JOnrdKM8uPygOqE+1DaMuoHSJ1DV5zL92 jtw/5v0xjUQZkfdaNJzhXMMUkspA3ZrnbaTRWnbigUX5GyniQTv86FATCuoP+yyK7L LM70NnDDKKMZ1zyMRYBovbVpj3FBUGKt7ue5Di45PE0AvXrFTEd16q+GBZ+hgK0C85 UzhaPCsA9usjbaqXTs/wqfUpZm7aNJul2cKCZk9GyfOEjDjc3paVRCgRvxCaJjo2NH GGiadVc5vCEHPPAZp8StxWZTX+GfDbSgMJel83TQG1CTbaOvvYybSkdmSGTnYR6tU5 4+Se7+L4ZuD2Q== From: Roger Quadros Date: Mon, 05 May 2025 19:26:38 +0300 Subject: [PATCH net-next v2 8/9] net: ethernet: ti: am65-cpsw: add network flow classification support Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250505-am65-cpsw-rx-class-v2-8-5359ea025144@kernel.org> References: <20250505-am65-cpsw-rx-class-v2-0-5359ea025144@kernel.org> In-Reply-To: <20250505-am65-cpsw-rx-class-v2-0-5359ea025144@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=13832; i=rogerq@kernel.org; h=from:subject:message-id; bh=kqK6hHQTaJHQ96VDODJ0v+DmrVHAtIh7xRRj3giLYMM=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoGOa76XSV38ZusH2BtsxJrQX5o6IL1sg3S3bdG K+3xVY/w9KJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaBjmuwAKCRDSWmvTvnYw kxeYD/9+SxD/53ObxwyGvVA9VPJV7Z4gVFqxu+xHETeLzhkZ3EFfe4hUQ8koZVpHueaUJ2SJ08Y eZJbUuUDqD83y38CGSkFFAjh9MkBnhU5bfpBqq2WtUHFjAAqRyRCuIbt3/FEICBcKhdx2ncTk6i SChbVom0nA1+RCqn5vUWN3PzPgk2lbOIf3FYLDNJ18wk1eb0i4Uv2cFILpAcqdGy3wiGkMXxmNu P/7BVyodqIltraCM9LS5KbxmOgSmHVOpSr2rRJZV5DlbT6aSFV2GRvJJdzMdj9tS+BTsxZ+iTpp Vcb2CODwA2tiIqVBJ6dUiOk3/dz4bL+2XY+E/RMJZQ+pU+kEdhkJMt97ar9qqUNBx+Qu7Kljox1 txMee5QdBNMqwLjfbvLlO1BuAeBMd8I+8jrzwJ17eClPI5d2GliAHgj0Aw4tvab+l1c7l5IbZNg KAqKaH/uV+eRBX89BpiBBYjeRf2JGzhu1p/A8h469JXY609JANoQdSNuwng0Xq0NuROxsJdtrFm 7qdEHE4i2y72UjmEz4Lm8fEjENxSdiI6HAGpD7+UNRdHBPNCpHrn02vCsrFGjfkdftQINgBbYXD h1nTd/xlUXdmya+eYMeOcpmgw+B52ZEIYlFY+yef4leI2lUd1eCgqiceGDkFOoShEcxadw2P0cL oh+ekVdxOfjsJKA== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Adds support for -N/--config-nfc ethtool command for configuring RX classfiers. Currently only raw Ethernet (flow-type ether) matching is added based on source/destination addresses and VLAN Priority (PCP). The ALE policer engine is used to perform the matching and routing to a specific RX channel. The TRM doesn't mention anything about order of evaluation of the classifier rules however it does mention in [1] "if multiple classifier matches occur, the highest match with thread enable bit set will be used." [1] 3.1.4.6.1.12.3.1 Classifier to CPPI Transmit Flow ID Mapping in AM62x TRM https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/am65-cpsw-ethtool.c | 355 ++++++++++++++++++++++++++++ drivers/net/ethernet/ti/am65-cpsw-nuss.c | 3 + drivers/net/ethernet/ti/am65-cpsw-nuss.h | 15 ++ 3 files changed, 373 insertions(+) diff --git a/drivers/net/ethernet/ti/am65-cpsw-ethtool.c b/drivers/net/ethernet/ti/am65-cpsw-ethtool.c index 9032444435e9..a558f186d54f 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-ethtool.c +++ b/drivers/net/ethernet/ti/am65-cpsw-ethtool.c @@ -970,6 +970,359 @@ static int am65_cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coales return am65_cpsw_set_per_queue_coalesce(ndev, 0, coal); } +#define AM65_CPSW_FLOW_TYPE(f) ((f) & ~(FLOW_EXT | FLOW_MAC_EXT)) + +/* rxnfc_lock must be held */ +static struct am65_cpsw_rxnfc_rule *am65_cpsw_get_rule(struct am65_cpsw_port *port, + int location) +{ + struct am65_cpsw_rxnfc_rule *rule; + + list_for_each_entry(rule, &port->rxnfc_rules, list) { + if (rule->location == location) + return rule; + } + + return NULL; +} + +/* rxnfc_lock must be held */ +static void am65_cpsw_del_rule(struct am65_cpsw_port *port, + struct am65_cpsw_rxnfc_rule *rule) +{ + cpsw_ale_policer_clr_entry(port->common->ale, rule->location, + &rule->cfg); + list_del(&rule->list); + port->rxnfc_count--; + devm_kfree(port->common->dev, rule); +} + +/* rxnfc_lock must be held */ +static int am65_cpsw_add_rule(struct am65_cpsw_port *port, + struct am65_cpsw_rxnfc_rule *rule) +{ + struct am65_cpsw_rxnfc_rule *prev = NULL, *cur; + int ret; + + ret = cpsw_ale_policer_set_entry(port->common->ale, rule->location, + &rule->cfg); + if (ret) + return ret; + + list_for_each_entry(cur, &port->rxnfc_rules, list) { + if (cur->location >= rule->location) + break; + prev = cur; + } + + list_add(&rule->list, prev ? &prev->list : &port->rxnfc_rules); + port->rxnfc_count++; + + return 0; +} + +#define ETHER_TYPE_FULL_MASK cpu_to_be16(FIELD_MAX(U16_MAX)) +#define VLAN_TCI_FULL_MASK ETHER_TYPE_FULL_MASK + +static int am65_cpsw_rxnfc_get_rule(struct am65_cpsw_port *port, + struct ethtool_rxnfc *rxnfc) +{ + struct ethtool_rx_flow_spec *fs = &rxnfc->fs; + struct am65_cpsw_rxnfc_rule *rule; + struct cpsw_ale_policer_cfg *cfg; + + mutex_lock(&port->rxnfc_lock); + rule = am65_cpsw_get_rule(port, fs->location); + if (!rule) { + mutex_unlock(&port->rxnfc_lock); + return -ENOENT; + } + + cfg = &rule->cfg; + + /* build flowspec from policer_cfg */ + fs->flow_type = ETHER_FLOW; + fs->ring_cookie = cfg->thread_id; + + /* clear all masks. Seems to be inverted */ + eth_broadcast_addr(fs->m_u.ether_spec.h_dest); + eth_broadcast_addr(fs->m_u.ether_spec.h_source); + fs->m_u.ether_spec.h_proto = ETHER_TYPE_FULL_MASK; + fs->m_ext.vlan_tci = htons(0xFFFF); + fs->m_ext.vlan_etype = ETHER_TYPE_FULL_MASK; + fs->m_ext.data[0] = cpu_to_be32(FIELD_MAX(U32_MAX)); + fs->m_ext.data[1] = cpu_to_be32(FIELD_MAX(U32_MAX)); + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACDST) { + ether_addr_copy(fs->h_u.ether_spec.h_dest, + cfg->dst_addr); + eth_zero_addr(fs->m_u.ether_spec.h_dest); + } + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACSRC) { + ether_addr_copy(fs->h_u.ether_spec.h_source, + cfg->src_addr); + eth_zero_addr(fs->m_u.ether_spec.h_source); + } + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_OVLAN) { + fs->flow_type |= FLOW_EXT; + fs->h_ext.vlan_tci = htons(FIELD_PREP(VLAN_VID_MASK, cfg->vid) + | FIELD_PREP(VLAN_PRIO_MASK, cfg->vlan_prio)); + fs->m_ext.vlan_tci = 0; + } + + mutex_unlock(&port->rxnfc_lock); + + return 0; +} + +static int am65_cpsw_rxnfc_get_all(struct am65_cpsw_port *port, + struct ethtool_rxnfc *rxnfc, + u32 *rule_locs) +{ + struct am65_cpsw_rxnfc_rule *rule; + int count = 0; + + rxnfc->data = port->rxnfc_max; + mutex_lock(&port->rxnfc_lock); + + list_for_each_entry(rule, &port->rxnfc_rules, list) { + if (count == rxnfc->rule_cnt) { + mutex_unlock(&port->rxnfc_lock); + return -EMSGSIZE; + } + + rule_locs[count] = rule->location; + count++; + } + + mutex_unlock(&port->rxnfc_lock); + rxnfc->rule_cnt = count; + + return 0; +} + +static int am65_cpsw_get_rxnfc(struct net_device *ndev, + struct ethtool_rxnfc *rxnfc, + u32 *rule_locs) +{ + struct am65_cpsw_common *common = am65_ndev_to_common(ndev); + struct am65_cpsw_port *port = am65_ndev_to_port(ndev); + + switch (rxnfc->cmd) { + case ETHTOOL_GRXRINGS: + rxnfc->data = common->rx_ch_num_flows; + return 0; + case ETHTOOL_GRXCLSRLCNT: /* Get RX classification rule count */ + rxnfc->rule_cnt = port->rxnfc_count; + rxnfc->data = port->rxnfc_max; + return 0; + case ETHTOOL_GRXCLSRULE: /* Get RX classification rule */ + return am65_cpsw_rxnfc_get_rule(port, rxnfc); + case ETHTOOL_GRXCLSRLALL: /* Get all RX classification rules */ + return am65_cpsw_rxnfc_get_all(port, rxnfc, rule_locs); + default: + return -EOPNOTSUPP; + } +} + +/* validate the rxnfc rule and convert it to policer config */ +static int am65_cpsw_rxnfc_validate(struct am65_cpsw_port *port, + struct ethtool_rxnfc *rxnfc, + struct cpsw_ale_policer_cfg *cfg) +{ + struct ethtool_rx_flow_spec *fs = &rxnfc->fs; + int flow_type = AM65_CPSW_FLOW_TYPE(fs->flow_type); + struct ethhdr *eth_mask; + + memset(cfg, 0, sizeof(*cfg)); + + if (flow_type & FLOW_RSS) + return -EINVAL; + + if (fs->location == RX_CLS_LOC_ANY || + fs->location >= port->rxnfc_max) + return -EINVAL; + + if (fs->ring_cookie == RX_CLS_FLOW_DISC) + cfg->drop = true; + else if (fs->ring_cookie > AM65_CPSW_MAX_QUEUES) + return -EINVAL; + + cfg->port_id = port->port_id; + cfg->thread_id = fs->ring_cookie; + + switch (flow_type) { + case ETHER_FLOW: + eth_mask = &fs->m_u.ether_spec; + + /* etherType matching is supported by h/w but not yet here */ + if (eth_mask->h_proto) + return -EINVAL; + + /* Only support source matching addresses by full mask */ + if (is_broadcast_ether_addr(eth_mask->h_source)) { + cfg->match_flags |= CPSW_ALE_POLICER_MATCH_MACSRC; + ether_addr_copy(cfg->src_addr, + fs->h_u.ether_spec.h_source); + } + + /* Only support destination matching addresses by full mask */ + if (is_broadcast_ether_addr(eth_mask->h_dest)) { + cfg->match_flags |= CPSW_ALE_POLICER_MATCH_MACDST; + ether_addr_copy(cfg->dst_addr, + fs->h_u.ether_spec.h_dest); + } + + if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { + /* Don't yet support vlan ethertype */ + if (fs->m_ext.vlan_etype) + return -EINVAL; + + if (fs->m_ext.vlan_tci != VLAN_TCI_FULL_MASK) + return -EINVAL; + + cfg->vid = FIELD_GET(VLAN_VID_MASK, + ntohs(fs->h_ext.vlan_tci)); + cfg->vlan_prio = FIELD_GET(VLAN_PRIO_MASK, + ntohs(fs->h_ext.vlan_tci)); + cfg->match_flags |= CPSW_ALE_POLICER_MATCH_OVLAN; + } + + break; + default: + return -EINVAL; + } + + return 0; +} + +static int am65_cpsw_policer_find_match(struct am65_cpsw_port *port, + struct cpsw_ale_policer_cfg *cfg) +{ + struct am65_cpsw_rxnfc_rule *rule; + int loc = -EINVAL; + + mutex_lock(&port->rxnfc_lock); + list_for_each_entry(rule, &port->rxnfc_rules, list) { + if (!memcmp(&rule->cfg, cfg, sizeof(*cfg))) { + loc = rule->location; + break; + } + } + + mutex_unlock(&port->rxnfc_lock); + + return loc; +} + +static int am65_cpsw_rxnfc_add_rule(struct am65_cpsw_port *port, + struct ethtool_rxnfc *rxnfc) +{ + struct ethtool_rx_flow_spec *fs = &rxnfc->fs; + struct am65_cpsw_rxnfc_rule *rule; + struct cpsw_ale_policer_cfg cfg; + int loc, ret; + + if (am65_cpsw_rxnfc_validate(port, rxnfc, &cfg)) + return -EINVAL; + + /* need to check if similar rule is already present at another location, + * if yes error out + */ + loc = am65_cpsw_policer_find_match(port, &cfg); + if (loc >= 0 && loc != fs->location) { + netdev_info(port->ndev, + "rule already exists in location %d. not adding\n", + loc); + return -EINVAL; + } + + /* delete exisiting rule */ + if (loc >= 0) { + mutex_lock(&port->rxnfc_lock); + rule = am65_cpsw_get_rule(port, loc); + if (rule) + am65_cpsw_del_rule(port, rule); + + mutex_unlock(&port->rxnfc_lock); + } + + rule = devm_kzalloc(port->common->dev, sizeof(*rule), GFP_KERNEL); + if (!rule) + return -ENOMEM; + + INIT_LIST_HEAD(&rule->list); + memcpy(&rule->cfg, &cfg, sizeof(cfg)); + rule->location = fs->location; + + mutex_lock(&port->rxnfc_lock); + ret = am65_cpsw_add_rule(port, rule); + mutex_unlock(&port->rxnfc_lock); + + return ret; +} + +static int am65_cpsw_rxnfc_del_rule(struct am65_cpsw_port *port, + struct ethtool_rxnfc *rxnfc) +{ + struct ethtool_rx_flow_spec *fs = &rxnfc->fs; + struct am65_cpsw_rxnfc_rule *rule; + + mutex_lock(&port->rxnfc_lock); + rule = am65_cpsw_get_rule(port, fs->location); + if (!rule) { + mutex_unlock(&port->rxnfc_lock); + return -ENOENT; + } + + am65_cpsw_del_rule(port, rule); + mutex_unlock(&port->rxnfc_lock); + + return 0; +} + +void am65_cpsw_rxnfc_init(struct am65_cpsw_port *port) +{ + struct cpsw_ale *ale = port->common->ale; + + mutex_init(&port->rxnfc_lock); + INIT_LIST_HEAD(&port->rxnfc_rules); + port->rxnfc_max = ale->params.num_policers; + + /* disable all rules */ + cpsw_ale_policer_reset(ale); +} + +void am65_cpsw_rxnfc_cleanup(struct am65_cpsw_port *port) +{ + struct am65_cpsw_rxnfc_rule *rule, *tmp; + + mutex_lock(&port->rxnfc_lock); + + list_for_each_entry_safe(rule, tmp, &port->rxnfc_rules, list) + am65_cpsw_del_rule(port, rule); + + mutex_unlock(&port->rxnfc_lock); +} + +static int am65_cpsw_set_rxnfc(struct net_device *ndev, + struct ethtool_rxnfc *rxnfc) +{ + struct am65_cpsw_port *port = am65_ndev_to_port(ndev); + + netdev_info(ndev, "set_rxnfc %d\n", rxnfc->cmd); + switch (rxnfc->cmd) { + case ETHTOOL_SRXCLSRLINS: + return am65_cpsw_rxnfc_add_rule(port, rxnfc); + case ETHTOOL_SRXCLSRLDEL: + return am65_cpsw_rxnfc_del_rule(port, rxnfc); + default: + return -EOPNOTSUPP; + } +} + const struct ethtool_ops am65_cpsw_ethtool_ops_slave = { .begin = am65_cpsw_ethtool_op_begin, .complete = am65_cpsw_ethtool_op_complete, @@ -1007,4 +1360,6 @@ const struct ethtool_ops am65_cpsw_ethtool_ops_slave = { .get_mm = am65_cpsw_get_mm, .set_mm = am65_cpsw_set_mm, .get_mm_stats = am65_cpsw_get_mm_stats, + .get_rxnfc = am65_cpsw_get_rxnfc, + .set_rxnfc = am65_cpsw_set_rxnfc, }; diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 07df61f343d3..cdb83ae54656 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -2758,6 +2758,7 @@ am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) return -ENOMEM; } + am65_cpsw_rxnfc_init(port); ndev_priv = netdev_priv(port->ndev); ndev_priv->port = port; ndev_priv->msg_enable = AM65_CPSW_DEBUG; @@ -2870,6 +2871,7 @@ static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) unregister_netdev(port->ndev); free_netdev(port->ndev); port->ndev = NULL; + am65_cpsw_rxnfc_cleanup(port); } } @@ -3172,6 +3174,7 @@ static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, /* clean up ALE table */ cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); + cpsw_ale_policer_reset(cpsw->ale); if (switch_en) { dev_info(cpsw->dev, "Enable switch mode\n"); diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.h b/drivers/net/ethernet/ti/am65-cpsw-nuss.h index 61daa5db12e6..8b83c9a0965d 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.h +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.h @@ -16,6 +16,7 @@ #include #include #include "am65-cpsw-qos.h" +#include "cpsw_ale.h" struct am65_cpts; @@ -40,6 +41,12 @@ struct am65_cpsw_slave_data { struct phylink_config phylink_config; }; +struct am65_cpsw_rxnfc_rule { + struct list_head list; + unsigned int location; + struct cpsw_ale_policer_cfg cfg; +}; + struct am65_cpsw_port { struct am65_cpsw_common *common; struct net_device *ndev; @@ -59,6 +66,11 @@ struct am65_cpsw_port { struct xdp_rxq_info xdp_rxq[AM65_CPSW_MAX_QUEUES]; /* Only for suspend resume context */ u32 vid_context; + /* Classifier flows */ + struct mutex rxnfc_lock; + struct list_head rxnfc_rules; + int rxnfc_count; + int rxnfc_max; }; enum am65_cpsw_tx_buf_type { @@ -229,4 +241,7 @@ int am65_cpsw_nuss_update_tx_rx_chns(struct am65_cpsw_common *common, bool am65_cpsw_port_dev_check(const struct net_device *dev); +void am65_cpsw_rxnfc_init(struct am65_cpsw_port *port); +void am65_cpsw_rxnfc_cleanup(struct am65_cpsw_port *port); + #endif /* AM65_CPSW_NUSS_H_ */ From patchwork Mon May 5 16:26:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 887690 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 848AB270EC1; Mon, 5 May 2025 16:27:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746462428; cv=none; b=IDs+BP1IdLgm9xxXU7u1qJ9Xf7YE1rnVe/9yWZ4+Zk1h3bcat+F7c08wkb5n7jxjkGCZN9lO8I4dMDbOcX0HtFeGvolPp9MtV+AUdGPIr0lvlaQQLnOpISVYU7KmWCH0X/sDO7mxh/fJW4BodFCXWzQMQZu6kWK1FIKh4kO60a0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746462428; c=relaxed/simple; bh=wHh0BxBceQm28qRNNXj5B9KsKZgsI5S+hHvXu32JIJg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HQkytuw2rT+TwHxi17iAhbbPwZdl/sM3Cpa0sPPypZdGA8ZchstokfjAVaFqmnSBN2f142BT8qnM19IVc+uQR9grbjFkun1cBhO838jMh4Y9dI4faXnI2IDRNIZCO9Co42gIoyphYYAtwhrB0OUyY5sN4yNToMTrN6jO495okgc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bRtQFPDR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bRtQFPDR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3E750C4CEE4; Mon, 5 May 2025 16:27:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746462428; bh=wHh0BxBceQm28qRNNXj5B9KsKZgsI5S+hHvXu32JIJg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=bRtQFPDRoj8QVvBhxqqNiNo8hmZjtnt8zNiha/jjf/d5c7m5mnCEGNTdGaDgyDpAI uZ+vkHVORL2TWd/0WdfXHjhKBef33NIZP/YuzB1clKcIAjz1Y/Kmw+rvk7vO9cvjFU CJVacekCqdE/bbYuMFcqAvaP4skaAUJiRMZBooIadeL1VfgiPFy7nMdeKWs9vNjLeZ 9kIoKJoYsGaf9pU/8fpWagnlUUKQB26s2vCY+6xVklrGArM0YHRLr1Tr8+nOfxwNaG 34v3XXJuGDrFVsgF+L4OYpd2LJzCwQ0F96KJqZoiJMvz0YjHVFcSQM1ZiJdx2OMxjp 35CsmxKzl6jNw== From: Roger Quadros Date: Mon, 05 May 2025 19:26:39 +0300 Subject: [PATCH net-next v2 9/9] net: ethernet: ti: am65-cpsw: remove cpsw_ale_classifier_setup_default() Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250505-am65-cpsw-rx-class-v2-9-5359ea025144@kernel.org> References: <20250505-am65-cpsw-rx-class-v2-0-5359ea025144@kernel.org> In-Reply-To: <20250505-am65-cpsw-rx-class-v2-0-5359ea025144@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4075; i=rogerq@kernel.org; h=from:subject:message-id; bh=wHh0BxBceQm28qRNNXj5B9KsKZgsI5S+hHvXu32JIJg=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoGOa7NsXxwdwKprEFRSfDEqqY934bqmxijrX9l AKnU+wEEyGJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaBjmuwAKCRDSWmvTvnYw k33xEADJ8odgtuThHzioSAr/lfpBpypc92cmMCGI5/jCji38P0bh7myevGMdJC+EVO7P/BNFUgR iQJTwwQWcXVNY4EQU14c9KemjfGkZrW+X5vNh7Mx/CCC/XhIv4XR3Et3BJ8N5+bDPJXJ8/mga6+ 57tGR5UDdB8ctOgJsE0sYwYPejxG8Y9tnvhX9DLu/yX7wksy/2/i3ZZnLKS/rYTIdYthUU3Dnnq nj7FEw1UdokU8yhVhBAy2H4rjOiB6Erfg7qua8DiL2hs+PbBZp3USgSFEeSUX1z3AL3RBjjs4g9 VZVoWSb0NabNSPtff/SqLTF1cxuW0ndMecL6BaG4P9h/c5MSkA9wwunw9+vAfP2BMwzNqD5lkAs 9yIbISSNSAX2Y/Xj5e6tFcelMCO7SGz10NHxKPgRaUEhfoPHJahQERLYvgHzt1cYvQ4M+TZ4RLr fFVZQ8Sio0IJ17+Wzm0P/+ScxEl1rMSFt2VDk2bl9HR1L6dKCqo9LFSMYbHSHI+keWfDwn700UA 19MHzxkPWW4s20/MJveXvfLrl5U9BJ+mkarMKLvmR4mizhN2/ToDS04yucvD7vPoKcoXZxSq5Hc jA3yxxjp1mBhxuFyvajI3Tqaii3haKpklXVrmxVxGI8wHay+SluYHbor6amA7EEJune2BoYYtUt AMyJOEJArFKAP3w== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 The RX classifier can now be configured by user using ethtool -N. So drop cpsw_ale_classifier_setup_default(). Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 3 -- drivers/net/ethernet/ti/cpsw_ale.c | 52 -------------------------------- drivers/net/ethernet/ti/cpsw_ale.h | 1 - 3 files changed, 56 deletions(-) diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index cdb83ae54656..0523c81a2a54 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -2497,9 +2497,6 @@ static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) } } - /* setup classifier to route priorities to flows */ - cpsw_ale_classifier_setup_default(common->ale, common->rx_ch_num_flows); - return 0; err_request_irq: diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 4e29702b86ea..85fcd09fd830 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -1695,58 +1695,6 @@ void cpsw_ale_policer_reset(struct cpsw_ale *ale) cpsw_ale_policer_reset_entry(ale, i); } -/* Default classifier is to map 8 user priorities to N receive channels */ -void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch) -{ - int pri, idx; - - /* Reference: - * IEEE802.1Q-2014, Standard for Local and metropolitan area networks - * Table I-2 - Traffic type acronyms - * Table I-3 - Defining traffic types - * Section I.4 Traffic types and priority values, states: - * "0 is thus used both for default priority and for Best Effort, and - * Background is associated with a priority value of 1. This means - * that the value 1 effectively communicates a lower priority than 0." - * - * In the table below, Priority Code Point (PCP) 0 is assigned - * to a higher priority thread than PCP 1 wherever possible. - * The table maps which thread the PCP traffic needs to be - * sent to for a given number of threads (RX channels). Upper threads - * have higher priority. - * e.g. if number of threads is 8 then user priority 0 will map to - * pri_thread_map[8-1][0] i.e. thread 1 - */ - - int pri_thread_map[8][8] = { /* BK,BE,EE,CA,VI,VO,IC,NC */ - { 0, 0, 0, 0, 0, 0, 0, 0, }, - { 0, 0, 0, 0, 1, 1, 1, 1, }, - { 0, 0, 0, 0, 1, 1, 2, 2, }, - { 0, 0, 1, 1, 2, 2, 3, 3, }, - { 0, 0, 1, 1, 2, 2, 3, 4, }, - { 1, 0, 2, 2, 3, 3, 4, 5, }, - { 1, 0, 2, 3, 4, 4, 5, 6, }, - { 1, 0, 2, 3, 4, 5, 6, 7 } }; - - cpsw_ale_policer_reset(ale); - - /* use first 8 classifiers to map 8 (DSCP/PCP) priorities to channels */ - for (pri = 0; pri < 8; pri++) { - idx = pri; - - /* Classifier 'idx' match on priority 'pri' */ - cpsw_ale_policer_read_idx(ale, idx); - regmap_field_write(ale->fields[POL_PRI_VAL], pri); - regmap_field_write(ale->fields[POL_PRI_MEN], 1); - cpsw_ale_policer_write_idx(ale, idx); - - /* Map Classifier 'idx' to thread provided by the map */ - cpsw_ale_policer_thread_idx_enable(ale, idx, - pri_thread_map[num_rx_ch - 1][pri], - 1); - } -} - #define HOST_PORT_NUM 0 /* Clear Policer and associated ALE table entries */ diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index dbc095397389..5c9614730998 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -223,7 +223,6 @@ int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask); void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, bool add); -void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch); void cpsw_ale_policer_reset(struct cpsw_ale *ale); int cpsw_ale_policer_set_entry(struct cpsw_ale *ale, u32 policer_idx, struct cpsw_ale_policer_cfg *cfg);