From patchwork Tue May 6 05:43:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 887882 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40931295509; Tue, 6 May 2025 05:44:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746510261; cv=none; b=OCdp89/2hwABbTYONKJEuJQ1r5cGnZzf237PPs1jRWkABK9oJ+4Fp3/EQD4B2X4Sbc8IHRjI6yM1TpYgoDXidZKG3yeG/nLxTeWiXf+rG+Z0P1w9C2Tqpoyq5onfzmjyLasPZe+RqRaBxj0UFkVJrABLZDRGg/WA7X+CvBrcK48= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746510261; c=relaxed/simple; bh=dj7hW8ZgQnAwcNBQPjqhjJ+Z9E/QQA3KSfq7G5Qk+u8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ACoHoZNTS/L9eqavzoZ4HQ/6HvYvtaplkvHcwymqcalsZrb0WQw3voWwwSsQbu7dXyCrHPHPRQ2FLoaoKXEkhPECoz9CuCbRJLcoWM/JQu/Mac3EGqMtPAsP09A06+PcQIezmKQ6zZCg60nga+ckzAtNoMGDfD8to07bzh8MY/0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BFDf32Jh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BFDf32Jh" Received: by smtp.kernel.org (Postfix) with ESMTPS id BE03CC4CEEF; Tue, 6 May 2025 05:44:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746510260; bh=dj7hW8ZgQnAwcNBQPjqhjJ+Z9E/QQA3KSfq7G5Qk+u8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=BFDf32Jh9LaKV9E2hBNyHcmixw5Klr9Am73NWTku67gTPq2aM3ShaBK5SADdUKj2R fi5sDZqU3Tpe9lufguspc+26sPoxbDXbcybAYOukqA48muzrJtfGyV+QWXrxl1OID+ aCTkswJ2Rmwrz0r9BHYjCKeCNbs4xQbVRZFdgUTOAKFBrD9Uxk5k+fL9zGLJc0TYB1 HAf4+soL9MMTLmpkB/7BHHPreS4iLoGrS+TKjLbsCKvNkokO6mpkMascSxFUJ0am6V LKf/hz+mGeLwDNY3ExlU2+AlKLal4ivB34lh6K1Hi0okT/yC4vFn/raWT6xR56+AE+ bBAxbwhrb4MoA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2790C3ABBE; Tue, 6 May 2025 05:44:20 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 06 May 2025 09:43:33 +0400 Subject: [PATCH v2 1/6] clk: qcom: ipq5018: keep XO clock always on Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250506-ipq5018-cmn-pll-v2-1-c0a9fcced114@outlook.com> References: <20250506-ipq5018-cmn-pll-v2-0-c0a9fcced114@outlook.com> In-Reply-To: <20250506-ipq5018-cmn-pll-v2-0-c0a9fcced114@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746510258; l=5615; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=Y1JlY5oRKJOTEFrLvYYyqkZKWEAjiaHbxNE3QfYsj7s=; b=7CAurtbrS7p+d9AmNJBBdWw47Qgb4EgUhnD0StVBj9e6Zk5wLuUQdqTjmk33RhcD7G9omq0dG XBXKG7O/8QJDQK4vSx9gJexdYrsA2h4YWsS0dZofuiIag9LGG/h8u40 X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The XO clock must not be disabled to avoid the kernel trying to disable the it (when parenting it under the CMN PLL reference clock), else the kernel will panic and the below message will appear in the kernel logs. So let's enable the XO and its source CLK and keep them always on. [ 0.916515] ------------[ cut here ]------------ [ 0.918890] gcc_xo_clk_src status stuck at 'on' [ 0.918944] WARNING: CPU: 0 PID: 8 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x114/0x124 [ 0.927926] Modules linked in: [ 0.936945] CPU: 0 PID: 8 Comm: kworker/0:0 Not tainted 6.6.74 #0 [ 0.939982] Hardware name: Linksys MX2000 (DT) [ 0.946151] Workqueue: pm pm_runtime_work [ 0.950489] pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 0.954566] pc : clk_branch_wait+0x114/0x124 [ 0.961335] lr : clk_branch_wait+0x114/0x124 [ 0.965849] sp : ffffffc08181bb50 [ 0.970101] x29: ffffffc08181bb50 x28: 0000000000000000 x27: 61c8864680b583eb [ 0.973317] x26: ffffff801fec2168 x25: ffffff800000abc0 x24: 0000000000000002 [ 0.980437] x23: ffffffc0809f6fd8 x22: 0000000000000000 x21: ffffffc08044193c [ 0.985276] loop: module loaded [ 0.987554] x20: 0000000000000000 x19: ffffffc081749278 x18: 000000000000007c [ 0.987573] x17: 0000000091706274 x16: 000000001985c4f7 x15: ffffffc0816bbdf0 [ 0.987587] x14: 0000000000000174 x13: 000000000000007c x12: 00000000ffffffea [ 0.987601] x11: 00000000ffffefff x10: ffffffc081713df0 x9 : ffffffc0816bbd98 [ 0.987615] x8 : 0000000000017fe8 x7 : c0000000ffffefff x6 : 0000000000057fa8 [ 1.026268] x5 : 0000000000000fff x4 : 0000000000000000 x3 : ffffffc08181b950 [ 1.033385] x2 : ffffffc0816bbd30 x1 : ffffffc0816bbd30 x0 : 0000000000000023 [ 1.040507] Call trace: [ 1.047618] clk_branch_wait+0x114/0x124 [ 1.049875] clk_branch2_disable+0x2c/0x3c [ 1.054043] clk_core_disable+0x60/0xac [ 1.057948] clk_core_disable+0x68/0xac [ 1.061681] clk_disable+0x30/0x4c [ 1.065499] pm_clk_suspend+0xd4/0xfc [ 1.068971] pm_generic_runtime_suspend+0x2c/0x44 [ 1.072705] __rpm_callback+0x40/0x1bc [ 1.077392] rpm_callback+0x6c/0x78 [ 1.081038] rpm_suspend+0xf0/0x5c0 [ 1.084423] pm_runtime_work+0xf0/0xfc [ 1.087895] process_one_work+0x17c/0x2f8 [ 1.091716] worker_thread+0x2e8/0x4d4 [ 1.095795] kthread+0xdc/0xe0 [ 1.099440] ret_from_fork+0x10/0x20 [ 1.102480] ---[ end trace 0000000000000000 ]--- Signed-off-by: George Moussalem --- drivers/clk/qcom/gcc-ipq5018.c | 50 +++++------------------------------------- 1 file changed, 6 insertions(+), 44 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 70f5dcb96700f55da1fb19fc893d22350a7e63bf..32c3e72429039dfb7adb1e956fba18bd2bc06557 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -1345,38 +1345,6 @@ static struct clk_branch gcc_sleep_clk_src = { }, }; -static struct clk_branch gcc_xo_clk_src = { - .halt_reg = 0x30018, - .clkr = { - .enable_reg = 0x30018, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data) { - .name = "gcc_xo_clk_src", - .parent_data = gcc_xo_data, - .num_parents = ARRAY_SIZE(gcc_xo_data), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_xo_clk = { - .halt_reg = 0x30030, - .clkr = { - .enable_reg = 0x30030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_xo_clk", - .parent_hws = (const struct clk_hw *[]) { - &gcc_xo_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_adss_pwm_clk = { .halt_reg = 0x1f020, .clkr = { @@ -1584,11 +1552,7 @@ static struct clk_branch gcc_cmn_blk_sys_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "gcc_cmn_blk_sys_clk", - .parent_hws = (const struct clk_hw *[]) { - &gcc_xo_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .num_parents = 0, .ops = &clk_branch2_ops, }, }, @@ -2980,11 +2944,7 @@ static struct clk_branch gcc_uniphy_sys_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "gcc_uniphy_sys_clk", - .parent_hws = (const struct clk_hw *[]) { - &gcc_xo_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .num_parents = 0, .ops = &clk_branch2_ops, }, }, @@ -3504,8 +3464,6 @@ static struct clk_regmap *gcc_ipq5018_clks[] = { [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr, [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr, [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr, - [GCC_XO_CLK] = &gcc_xo_clk.clkr, - [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr, [GMAC0_RX_CLK_SRC] = &gmac0_rx_clk_src.clkr, [GMAC0_RX_DIV_CLK_SRC] = &gmac0_rx_div_clk_src.clkr, [GMAC0_TX_CLK_SRC] = &gmac0_tx_clk_src.clkr, @@ -3696,6 +3654,10 @@ static int gcc_ipq5018_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x30018); /* GCC_XO_CLK_SRC */ + qcom_branch_set_clk_en(regmap, 0x30030); /* GCC_XO_CLK */ + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); return qcom_cc_really_probe(&pdev->dev, &ipq5018_desc, regmap); From patchwork Tue May 6 05:43:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 888283 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02A8F283134; Tue, 6 May 2025 05:44:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746510261; cv=none; b=IuxYNnakI8V+9rv61O/MsCyJ5iSO9ThaUIhDLJmtq/tkqXuHsnUMFzZj1PXVPGQAcPvl/b3JpxK4too42ZDhLOXoQX5pHu9FwYQunbYHvcY/FZbbx+IuXOJQxv3UFRAh0TEZZfQNS4xwsRi+y+5olNZPVxIHuRkDdMwAQuAL9Ic= ARC-Message-Signature: i=1; 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b=oQZRTtCYi4tw7YQZ8NXTvn+49Z+EJga0q2LAJi7B5Mkvc97bkgNUBwJROUUfL4Lq6 TqSsSyVI4uqSx2C50MEpec+3ULMTn9ZUSuhbR9rhKcVz70hkpPTbGI5dQoWU4PfPFM uerNcZS/q5XiXnh1uE0P1RZLLzwoHUGIGsT6KbsaFwvaEARcYqyFH7JkFm6zOld/Cf HCgLFvi8ar2qCMmKv9INrIqf7kLzkryHqSWRTopPB7669ZW+Ltw5Zr9jn7kBKQq5jy +zndvPRhKPHKpabKNphQqe4HrEIzP1ciJGtPpoMkz0hrmlt1FCKnM+mPHcEcjVxn7/ bStuyy2jy2/Ng== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF6B4C3ABAC; Tue, 6 May 2025 05:44:20 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 06 May 2025 09:43:34 +0400 Subject: [PATCH v2 2/6] dt-bindings: clock: qcom: ipq5018: remove bindings for XO clock Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250506-ipq5018-cmn-pll-v2-2-c0a9fcced114@outlook.com> References: <20250506-ipq5018-cmn-pll-v2-0-c0a9fcced114@outlook.com> In-Reply-To: <20250506-ipq5018-cmn-pll-v2-0-c0a9fcced114@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746510258; l=916; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=JupKX6iwdtJMe4ecLVTA0mWjAGvKoKV28P3vMGpTlG0=; b=7p+yVQvKj5aQQRuj+czk6aiSi45ggNA8QFh8VJwga282xblu/OE1PGOvTXbw3Bj8u5hJmcLBj J5Cy+BBjW7MDWf5qvb38Bg7e8V4cI2apve30eAPFN79ZcDPH1FwxgBJ X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The XO and its source clock must be always-on and is enabled in the GCC during probe. As such, remove the bindings for them. Signed-off-by: George Moussalem --- include/dt-bindings/clock/qcom,gcc-ipq5018.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq5018.h b/include/dt-bindings/clock/qcom,gcc-ipq5018.h index f3de2fdfeea11f4b8832b75a05e424ca347b3634..d4de5eaffee7b4cb81e0ff2dcbf9e6669c3da8f8 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq5018.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq5018.h @@ -140,8 +140,6 @@ #define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 131 #define GCC_WCSS_DBG_IFC_NTS_CLK 132 #define GCC_WCSS_ECAHB_CLK 133 -#define GCC_XO_CLK 134 -#define GCC_XO_CLK_SRC 135 #define GMAC0_RX_CLK_SRC 136 #define GMAC0_TX_CLK_SRC 137 #define GMAC1_RX_CLK_SRC 138 From patchwork Tue May 6 05:43:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 887883 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14DB127F175; Tue, 6 May 2025 05:44:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746510261; cv=none; b=gi4ZvARcUQ11nZCC2uizhX5WdjOJeN3nvPoTy1VVbS96JB2lYsOm8c/WXjrdrat3woNzZ529uW37AJx8cJHVn2jDl3H24c880cbOA1/OlTygXieCIzpcPZgSo3npCScaHus++HAYNPAtFrgCavV14+urfjriwHR0bM1JhalBDb4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746510261; c=relaxed/simple; bh=z45Mhrm50G2NpvDPKyb5BFCNwuMnJv7rrdU8ii7BY4w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LEmGhQUEmzVkPnGzDu0knZgHAD2VdJbFYheNtPdLweC6VAIzpuycOy7gQLvHSJ5TFWKJHopsj3AQ8Y3rPvSE5veNSOFmaRw/qtfbapMp8fRQb788W4JM/C1JNIF4yOqKLGtV5LSd24GUfjgJetGS6VPUVH2iHWu+mM3UtZk8ue8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WtFl+xv8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WtFl+xv8" Received: by smtp.kernel.org (Postfix) with ESMTPS id D5CABC4CEF0; Tue, 6 May 2025 05:44:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746510260; bh=z45Mhrm50G2NpvDPKyb5BFCNwuMnJv7rrdU8ii7BY4w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WtFl+xv8z/6VRVbe5b/1/wp6FZJEoChJR3qgcSDwQdrrINejPHsIKmnHleJfklTaL uOu1CCe1Jehv1vOekdIgJ4T4dZJh5iMUrfwI/2E1UW+aGUaQ0hWP3g7nhH1MsREOEI vuxuL52wzCb2F6HT6zbS9LmrHeDOah5+fD8nTidAQ4q2QHeDIvFOfj/yIfrT+NZo/U vu49txDiAPRtJa2qORbyx25K5/E3OzEIQmLH6sTvkCb+6oH+1f0t3h8TSJtMvxTbt4 AW6ej7hNKYitCGDHfxfo4MDxWk/nJSd87CxbL86eoUUsKR2jrjwo2Xplox6ZkJdYWa gMFWlUsIEtqUg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB17CC3ABC3; Tue, 6 May 2025 05:44:20 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 06 May 2025 09:43:35 +0400 Subject: [PATCH v2 3/6] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250506-ipq5018-cmn-pll-v2-3-c0a9fcced114@outlook.com> References: <20250506-ipq5018-cmn-pll-v2-0-c0a9fcced114@outlook.com> In-Reply-To: <20250506-ipq5018-cmn-pll-v2-0-c0a9fcced114@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746510258; l=1805; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=8ErFwBb8LXa01ct7/Tl+4mrJDAJ15D3Sw41xcCkSs/4=; b=oA5CQA6Mwh7Ty3WViEfqrAci7NX4dm4nnvnWOgQ/jUopT4a5cT/Du/swtu91VgSnuRJAV7xOm 8Y7tDi4LDaqA/+NtXOqeseDGBlUVwvFAmgF05EuJGV8xpxz7p9c/7SE X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and ethernet (50Mhz) clocks. Signed-off-by: George Moussalem --- .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 + include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml index cb6e09f4247f4b25105b25f4ae746c0b3ef47616..817d51135fbfdf0f518af1007ec7d6b120a91818 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml @@ -24,6 +24,7 @@ description: properties: compatible: enum: + - qcom,ipq5018-cmn-pll - qcom,ipq5424-cmn-pll - qcom,ipq9574-cmn-pll diff --git a/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h new file mode 100644 index 0000000000000000000000000000000000000000..586d1c9b33b374331bef413f543c526212c18494 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H +#define _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H + +/* CMN PLL core clock. */ +#define IPQ5018_CMN_PLL_CLK 0 + +/* The output clocks from CMN PLL of IPQ5018. */ +#define IPQ5018_XO_24MHZ_CLK 1 +#define IPQ5018_SLEEP_32KHZ_CLK 2 +#define IPQ5018_ETH_50MHZ_CLK 3 +#endif From patchwork Tue May 6 05:43:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 887881 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 614E229551C; Tue, 6 May 2025 05:44:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746510261; cv=none; b=KSVjufyI6J+R4krzBXwHHAuSNBO9rNPlAzvA68mXkyBAc9g00ErnKDUSe91u/Bc/XN7IHhDH9Ly2Ogu4pnTHgWEvP/gRfIb8fWEK6/6EUAk3gZbRhhZI3jqJsl34wFeeq4BgNikv4TTaON/5/HRzYhhqqHX9fcvB0viPhtnhGiU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746510261; c=relaxed/simple; bh=oZZPzXRkRK1qwT8QXo+WyiPkT8wvLk9sLQ2Tj8Rhwsc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=M60sJx/4tFOHDksv8RbxaGRNLIF8svZTbz/6AiuaVeJbLO5xIXPWFd99IGlG9rCCPdCC8Ll791zUkDMCz7u/1vAtgrANbEGsMJXl2+gxRRw3zSXx3nQ+YlYIj3sSi3cay1sFqEKiXiGIKgGdx1up+6torN+gjkIngKWY3h+r6ow= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kxZZ6jKE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kxZZ6jKE" Received: by smtp.kernel.org (Postfix) with ESMTPS id DD3D1C4CEF4; Tue, 6 May 2025 05:44:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746510260; bh=oZZPzXRkRK1qwT8QXo+WyiPkT8wvLk9sLQ2Tj8Rhwsc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kxZZ6jKEjLu3J/TvjDFTi1mWqiBy9JC2jawEEd6HcvGG4ZetWoMw8Enl++i9bW9ta I0qzpzEKqYjB1qPmTtl0MInuGP1KivmZ2UwD7wtfFG9B8mTo+/fds6wnbuGNUogp0L 76wETuUZ9aaS7TWU57GVkcRFBt4HGGNOUMchDDN0ZQxAbxzqiyGjF5Svzn9kI/h8X9 adHakzhwFIx6fT8QhJRXf6Ra70MxeHN0pEObsgfXz8R8pcvDQU95vfZ5Ok4GQhslfH zPGMv4nFNrlG7jQErffyJreQNDMmyqkJC19XxetJmMqMHV3sK6ilmvz5eYms7ziQw2 Ms1lz+dx1MMTg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7616C3ABBC; Tue, 6 May 2025 05:44:20 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 06 May 2025 09:43:36 +0400 Subject: [PATCH v2 4/6] clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250506-ipq5018-cmn-pll-v2-4-c0a9fcced114@outlook.com> References: <20250506-ipq5018-cmn-pll-v2-0-c0a9fcced114@outlook.com> In-Reply-To: <20250506-ipq5018-cmn-pll-v2-0-c0a9fcced114@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746510258; l=4181; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=RLCf5CaWa6JRGj1tMwC22OxTx2xTaEIjQUUkGIrSCqw=; b=CK+Io6bobabhxzkFJqjpS4kSr6iNuus3yW3mS3XzztrG48y9lp3tMHgzE++4lSIrx7RsmdvxZ HOJGKGP00WbCNAwuSkjYBBr4f/vt5WuQBvtEHmZtcxbXWYp2K5Ogiof X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The CMN PLL in IPQ5018 SoC supplies fixed clocks to XO, sleep, and the ethernet block. The CMN PLL to the ethernet block must be enabled first by setting a specific register in the TCSR area set in the device tree. Signed-off-by: George Moussalem --- drivers/clk/qcom/ipq-cmn-pll.c | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index b34d6faf67b8dd74402fabdb8dfe5ea52edd52f4..b3d7169c63e5fa7638fee80094a47746a0b6845e 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -50,6 +50,7 @@ #include #include +#include #include #define CMN_PLL_REFCLK_SRC_SELECTION 0x28 @@ -110,16 +111,10 @@ static const struct regmap_config ipq_cmn_pll_regmap_config = { .fast_io = true, }; -static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { - CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), - CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), - CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), - CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), - CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), - CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), - CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), - CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), - CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), +static const struct cmn_pll_fixed_output_clk ipq5018_output_clks[] = { + CLK_PLL_OUTPUT(IPQ5018_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), + CLK_PLL_OUTPUT(IPQ5018_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), + CLK_PLL_OUTPUT(IPQ5018_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL), { /* Sentinel */ } }; @@ -136,6 +131,19 @@ static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = { { /* Sentinel */ } }; +static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { + CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), + CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), + CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), + CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), + CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), + CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), + CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), + { /* Sentinel */ } +}; + /* * CMN PLL has the single parent clock, which supports the several * possible parent clock rates, each parent clock rate is reflected @@ -399,11 +407,11 @@ static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) */ ret = pm_clk_add(dev, "ahb"); if (ret) - return dev_err_probe(dev, ret, "Fail to add AHB clock\n"); + return dev_err_probe(dev, ret, "Failed to add AHB clock\n"); ret = pm_clk_add(dev, "sys"); if (ret) - return dev_err_probe(dev, ret, "Fail to add SYS clock\n"); + return dev_err_probe(dev, ret, "Failed to add SYS clock\n"); ret = pm_runtime_resume_and_get(dev); if (ret) @@ -414,7 +422,7 @@ static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) pm_runtime_put(dev); if (ret) return dev_err_probe(dev, ret, - "Fail to register CMN PLL clocks\n"); + "Failed to register CMN PLL clocks\n"); return 0; } @@ -439,8 +447,9 @@ static const struct dev_pm_ops ipq_cmn_pll_pm_ops = { }; static const struct of_device_id ipq_cmn_pll_clk_ids[] = { - { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks }, + { .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks }, { .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks }, + { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks }, { } }; MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids); From patchwork Tue May 6 05:43:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 888280 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F9C62957BE; Tue, 6 May 2025 05:44:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746510261; cv=none; b=Cvs65TYkBrazaLbrYSCkUowim2b6KC8JJ8lycd2ejzElt7PCl7GeGx5Qqn+3gbKwBJgHQeqg34n9Fcx3584MwLe4NtKV+tku1cDrdl5PYyr0lP7Fuqm6BcAHeExMXgq6Vz5a9IMvRZu9/Yx+SULCnWWp7coedE4KpArh1RXQADM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746510261; 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Tue, 6 May 2025 05:44:20 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 06 May 2025 09:43:37 +0400 Subject: [PATCH v2 5/6] arm64: dts: ipq5018: Add CMN PLL node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250506-ipq5018-cmn-pll-v2-5-c0a9fcced114@outlook.com> References: <20250506-ipq5018-cmn-pll-v2-0-c0a9fcced114@outlook.com> In-Reply-To: <20250506-ipq5018-cmn-pll-v2-0-c0a9fcced114@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746510258; l=2485; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=JG4puk3te0VbG/hCbL1JZAa8YmHtOXbXdjPdx67V0/s=; b=J1Ipn55wgYH4TRNvLfZdY4tP1ymeKf01XpzCsQD0N82+tgRrJlPDP9M01afPFBgredMUfhpWU 4wbBnTXgsmNAc57eGQPY9zvfcbj+VgEsDwDGsNEbXaUzuQ9oukoWFP2 X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Add CMN PLL node for enabling output clocks to the networking hardware blocks on IPQ5018 devices. The reference clock of CMN PLL is routed from XO to the CMN PLL through the internal WiFi block. .XO (48 MHZ) --> WiFi (multiplier/divider)--> 96 MHZ to CMN PLL. Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 8914f2ef0bc47fda243b19174f77ce73fc10757d..6992d164fa965c760ce2738307f6e103d3ff3a20 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -2,12 +2,13 @@ /* * IPQ5018 SoC device tree source * - * Copyright (c) 2023 The Linux Foundation. All rights reserved. + * Copyright (c) 2023-2025 The Linux Foundation. All rights reserved. */ #include -#include #include +#include +#include #include / { @@ -16,6 +17,14 @@ / { #size-cells = <2>; clocks { + ref_96mhz_clk: ref-96mhz-clk { + compatible = "fixed-factor-clock"; + clocks = <&xo_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -25,6 +34,12 @@ xo_board_clk: xo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; + + xo_clk: xo-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; }; cpus { @@ -147,6 +162,20 @@ usbphy0: phy@5b000 { status = "disabled"; }; + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq5018-cmn-pll"; + reg = <0x0009b000 0x800>; + clocks = <&ref_96mhz_clk>, + <&gcc GCC_CMN_BLK_AHB_CLK>, + <&gcc GCC_CMN_BLK_SYS_CLK>; + clock-names = "ref", + "ahb", + "sys"; + #clock-cells = <1>; + assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>; + assigned-clock-rates-u64 = /bits/ 64 <9600000000>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>; From patchwork Tue May 6 05:43:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 888282 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38C942951DE; Tue, 6 May 2025 05:44:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746510261; cv=none; b=PYJXVAC1uoKDIN70yN8R36dCBkDiXGAQyZiOXCU2m+k+pxrH+RXrD+tQOiIWZn0rvWTy7qEVNWGk0u2+YSgnISVlkygoT7epoFZLofZ7eo3feQLALZDauiWh5SdcTjSnjplOaAa/0GAYRV0qAjd4igeBxJghyau/lPBPuX/p5FA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Tue, 6 May 2025 05:44:20 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 06 May 2025 09:43:38 +0400 Subject: [PATCH v2 6/6] arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250506-ipq5018-cmn-pll-v2-6-c0a9fcced114@outlook.com> References: <20250506-ipq5018-cmn-pll-v2-0-c0a9fcced114@outlook.com> In-Reply-To: <20250506-ipq5018-cmn-pll-v2-0-c0a9fcced114@outlook.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Lee Jones , Konrad Dybcio , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1746510258; l=2154; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=rsjsy3sOFV1Bg2dDCftuVKNO8nGOiFRTAbeFFfhHc1c=; b=0VkXT8KgrXJiOeVPwOsCMJkL8WBGzu2Ai1tNRz+xQh1NXvS3hxts5NHZIBfMwvp61k+Qjpx3J heUx4Dl8ppaAg0cOOwbIYbjtjqBnWwBWKJeS82kY8nYamZ5Ue+0fKKf X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output clock 96 MHZ (also being the reference clock of CMN PLL) divided by 4 to the analog block routing channel. Update the xo_board_clk nodes in the board DTS files to use clock-div/clock-mult accordingly. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 3 ++- arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts | 3 ++- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts index 8460b538eb6a3e2d6b971bd9637309809e0c0f0c..abb629678c023a2eb387ebf229f6dd1c30133b19 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -80,5 +80,6 @@ &usbphy0 { }; &xo_board_clk { - clock-frequency = <24000000>; + clock-div = <4>; + clock-mult = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts index 5bb021cb29cd39cb95035bfac1bdbc976439838b..7a25af57749c8e8c9a6a185437886b04b0d99e8e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts @@ -124,5 +124,6 @@ uart_pins: uart-pins-state { }; &xo_board_clk { - clock-frequency = <24000000>; + clock-div = <4>; + clock-mult = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 6992d164fa965c760ce2738307f6e103d3ff3a20..6cd76155534c9933fb2b2762291519e9355aee2f 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -31,7 +31,8 @@ sleep_clk: sleep-clk { }; xo_board_clk: xo-board-clk { - compatible = "fixed-clock"; + compatible = "fixed-factor-clock"; + clocks = <&ref_96mhz_clk>; #clock-cells = <0>; };