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Tue, 6 May 2025 12:31:11 -0700 From: Chris Babroski To: , , CC: , , , Subject: [PATCH v4 1/2] i2c-mlxbf: Add repeated start condition support Date: Tue, 6 May 2025 19:30:58 +0000 Message-ID: <20250506193059.321345-1-cbabroski@nvidia.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468E:EE_|SJ2PR12MB9115:EE_ X-MS-Office365-Filtering-Correlation-Id: a5440eb4-d03e-4526-ea63-08dd8cd49917 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: 01V9Npy0g/8TOms2Vd/IDDb/TeQWeSePMiR4zibH8YwgOKbEb+X4T1FhHiBBCwHNlqdUGwBFXIo4i2T3PaSF+R5roQk3Qhlf3ee8L9JbaaZ0dP6BPZDlMGyBl2fmhCeTFVZwve2fJXxGYYpFg+TeDNKIE5ey3ecQ5MC/2ewKNTMDxco/XTS0RyKwkU0huvwsIiiY2qOSbY35ZQ/PGG1fBNVQC7c/wW3MMd5GWQPTzb1SiukhgVgm13IcDL3cxoUTYtI7r1xle9m/05XkZCzncTCzjNhkRxpzxVGKGWjn2WT8JIlXkYRjnCF/RRyQHOWaT3U6GoMJbzf8+3m1suER5jK4NTbxO1gZ6S5VbdSdXCV/ONSDulx5jQEKX1pDViJW024ThIyJU/aFo8q4egtKVaFVOniDwIM+rGZFNFLu32GkwlFB+Rf9S7jXeXgjeLLGFUS0hCmCRjNhSJa7y86ZXAZoYLHsPOyxHVJwT7uk5moMAYt5IQUSyhSCQkYqIOo/IvlRMhQkUJxFHHKaVzSe0/nG8RAlSjsPK5lqM07O9pfE5w46DH5bJacmKr/4L9BaYqX+oZ7FcEmmV6V3mdqjnrbyI/aj36WN+K0doar14W253u7TdtTrkvEfFdeV29EbwAZLGM5im1VahKhdL2/lUl8OqIOd1UbPQVPe4TphvpNJvZO7ilqtHgWfM9PbUvNJ0YLA4RIZcWEcJhR6EddKIOUTtO8diomuaP2mvd80zmQDkCRVRQYzWFHFvXyWKuRzLs2c34WQTv1xHsYBZI3upTx19MVSNMUFGrGEvYm2FcH6pfAGXGJu+ISVfyaRfU0hBi5LB3MP/lkyt6t0AWaUTdCER9WF5yp9anK2jOO8T20BCL0e2VEVyUPZFEipOw50y6iBJY3fqV/h6QMrFmoa4QpNz+3BEpfMd9dG64qDX2av10XE0Fxwhp09PPFmTp6x8wu52mWdn/A/D/pxMcMDJYk3g+bUOFdkxMfmL3gfSHi4S2KStgztPW/5WKs7qBZNDOfKB0Gv/0FwmcFz2lVPXbYZAJn2ta8cpb88lFF3F2C1Pwc8pacc9K/Obq0wzWz9ML76Q8+Rk4e+CPkgEgaXlT3JE8GFGZtIUDyBG414swGyxBLoXv/0M09aIaP12fAMEI3bpNsdTLTnaoIFun3YQfbkuLsTmsJPobnlyvUVb0X0+XHDfhRHlWOSiowj/6+v4AzdDkt2BpwhmdT4XJznkSBOCZsOYxewZpUtb8o9fZn/N2bCyjJ6fQksOdmiJAkUzApsLASMQ5LmeYLI48B/jCIl+vuzbBtElNYe/jsp7RSPoJkuUBwB1+hOGpWwZfKNiUSb4I2M8m7u1n6UPNoRsyVOvIIdwwZT5uOiyydhh9HPkcUqUGD76IBHmwj235BqkWIZ2wOK9fp8bLMzuKWYLTk/cPhF/5Mh6yj+UuYy1pr1dKFaCsocDppJYhfPvlOwvHGI5hAiHklo/fa6OuIo3QZtNw/HyCQpRN2BRomFAwh8teopKicgknJN7nRqwflj X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 May 2025 19:31:28.3982 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a5440eb4-d03e-4526-ea63-08dd8cd49917 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9115 Add support for SMBus repeated start conditions to the Mellanox I2C driver. This support is specifically enabled for the I2C_FUNC_SMBUS_WRITE_I2C_BLOCK implementation which is required for communication with a specific I2C device on BlueField 3. Signed-off-by: Chris Babroski Reviewed-by: Asmaa Mnebhi Reviewed-by: Khalil Blaiech --- V3 -> V4: Split changes into two separate logical patches V2 -> V3: Cleaned up code and address review comments V1 -> V2: Removed default "Reviewed-by:" tags drivers/i2c/busses/i2c-mlxbf.c | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) base-commit: 0a9b9d17f3a781dea03baca01c835deaa07f7cc3 diff --git a/drivers/i2c/busses/i2c-mlxbf.c b/drivers/i2c/busses/i2c-mlxbf.c index b3a73921ab69..0f5b6a00c1b6 100644 --- a/drivers/i2c/busses/i2c-mlxbf.c +++ b/drivers/i2c/busses/i2c-mlxbf.c @@ -222,7 +222,7 @@ #define MLXBF_I2C_MASTER_ENABLE \ (MLXBF_I2C_MASTER_LOCK_BIT | MLXBF_I2C_MASTER_BUSY_BIT | \ - MLXBF_I2C_MASTER_START_BIT | MLXBF_I2C_MASTER_STOP_BIT) + MLXBF_I2C_MASTER_START_BIT) #define MLXBF_I2C_MASTER_ENABLE_WRITE \ (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_WRITE_BIT) @@ -336,6 +336,7 @@ enum { MLXBF_I2C_F_SMBUS_BLOCK = BIT(5), MLXBF_I2C_F_SMBUS_PEC = BIT(6), MLXBF_I2C_F_SMBUS_PROCESS_CALL = BIT(7), + MLXBF_I2C_F_WRITE_WITHOUT_STOP = BIT(8), }; /* Mellanox BlueField chip type. */ @@ -694,16 +695,19 @@ static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv, } static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave, - u8 len, u8 block_en, u8 pec_en, bool read) + u8 len, u8 block_en, u8 pec_en, bool read, + bool stop) { - u32 command; + u32 command = 0; /* Set Master GW control word. */ + if (stop) + command |= MLXBF_I2C_MASTER_STOP_BIT; if (read) { - command = MLXBF_I2C_MASTER_ENABLE_READ; + command |= MLXBF_I2C_MASTER_ENABLE_READ; command |= rol32(len, MLXBF_I2C_MASTER_READ_SHIFT); } else { - command = MLXBF_I2C_MASTER_ENABLE_WRITE; + command |= MLXBF_I2C_MASTER_ENABLE_WRITE; command |= rol32(len, MLXBF_I2C_MASTER_WRITE_SHIFT); } command |= rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT); @@ -738,9 +742,11 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv, u8 op_idx, data_idx, data_len, write_len, read_len; struct mlxbf_i2c_smbus_operation *operation; u8 read_en, write_en, block_en, pec_en; - u8 slave, flags, addr; + bool stop_after_write = true; + u8 slave, addr; u8 *read_buf; int ret = 0; + u32 flags; if (request->operation_cnt > MLXBF_I2C_SMBUS_MAX_OP_CNT) return -EINVAL; @@ -799,7 +805,16 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv, memcpy(data_desc + data_idx, operation->buffer, operation->length); data_idx += operation->length; + + /* + * The stop condition can be skipped when writing on the bus + * to implement a repeated start condition on the next read + * as required for several SMBus and I2C operations. + */ + if (flags & MLXBF_I2C_F_WRITE_WITHOUT_STOP) + stop_after_write = false; } + /* * We assume that read operations are performed only once per * SMBus transaction. *TBD* protect this statement so it won't @@ -825,7 +840,7 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv, if (write_en) { ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en, - pec_en, 0); + pec_en, 0, stop_after_write); if (ret) goto out_unlock; } @@ -835,7 +850,7 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv, mlxbf_i2c_smbus_write_data(priv, (const u8 *)&addr, 1, MLXBF_I2C_MASTER_DATA_DESC_ADDR, true); ret = mlxbf_i2c_smbus_enable(priv, slave, read_len, block_en, - pec_en, 1); + pec_en, 1, true); if (!ret) { /* Get Master GW data descriptor. */ mlxbf_i2c_smbus_read_data(priv, data_desc, read_len + 1, @@ -940,6 +955,9 @@ mlxbf_i2c_smbus_i2c_block_func(struct mlxbf_i2c_smbus_request *request, request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; request->operation[0].buffer = command; + if (read) + request->operation[0].flags |= MLXBF_I2C_F_WRITE_WITHOUT_STOP; + /* * As specified in the standard, the max number of bytes to read/write * per block operation is 32 bytes. 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 May 2025 19:31:33.9937 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f7455db-7e58-4351-234d-08dd8cd49c6d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9184 Update the I2C bus timing configuration on BlueField to match the configuration recommended and verified by the HW team. I2C block read failures were found on BlueField 3 during communication with a device that requires the use of repeated start conditions. Testing showed that these failures were caused by the I2C transaction getting aborted early due to a short bus "timeout" configuration value. This value determines how long the clock can be held low before the I2C transaction is aborted. Upon further inspection, it was also found that other I2C bus timing configuration values used by the kernel driver do not match the configuration that is recommended by the HW team and used in the BlueField BSP I2C drivers. Signed-off-by: Chris Babroski Reviewed-by: Asmaa Mnebhi Reviewed-by: Khalil Blaiech --- V3 -> V4: Split changes into two separate logical patches V2 -> V3: Cleaned up code and address review comments V1 -> V2: Removed default "Reviewed-by:" tags drivers/i2c/busses/i2c-mlxbf.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/i2c/busses/i2c-mlxbf.c b/drivers/i2c/busses/i2c-mlxbf.c index 0f5b6a00c1b6..3f8b4574f735 100644 --- a/drivers/i2c/busses/i2c-mlxbf.c +++ b/drivers/i2c/busses/i2c-mlxbf.c @@ -196,6 +196,7 @@ #define MLXBF_I2C_MASK_8 GENMASK(7, 0) #define MLXBF_I2C_MASK_16 GENMASK(15, 0) +#define MLXBF_I2C_MASK_32 GENMASK(31, 0) #define MLXBF_I2C_MST_ADDR_OFFSET 0x200 @@ -1192,7 +1193,8 @@ static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv, MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF); - timer = timings->timeout; + timer = mlxbf_i2c_set_timer(priv, timings->timeout, false, + MLXBF_I2C_MASK_32, MLXBF_I2C_SHIFT_0); writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT); } @@ -1202,11 +1204,7 @@ enum mlxbf_i2c_timings_config { MLXBF_I2C_TIMING_CONFIG_1000KHZ, }; -/* - * Note that the mlxbf_i2c_timings->timeout value is not related to the - * bus frequency, it is impacted by the time it takes the driver to - * complete data transmission before transaction abort. - */ +/* Timing values are in nanoseconds */ static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] = { [MLXBF_I2C_TIMING_CONFIG_100KHZ] = { .scl_high = 4810, @@ -1221,8 +1219,8 @@ static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] = { .scl_fall = 50, .hold_data = 300, .buf = 20000, - .thigh_max = 5000, - .timeout = 106500 + .thigh_max = 50000, + .timeout = 35000000 }, [MLXBF_I2C_TIMING_CONFIG_400KHZ] = { .scl_high = 1011, @@ -1237,24 +1235,24 @@ static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] = { .scl_fall = 50, .hold_data = 300, .buf = 20000, - .thigh_max = 5000, - .timeout = 106500 + .thigh_max = 50000, + .timeout = 35000000 }, [MLXBF_I2C_TIMING_CONFIG_1000KHZ] = { - .scl_high = 600, - .scl_low = 1300, + .scl_high = 383, + .scl_low = 460, .hold_start = 600, - .setup_start = 600, - .setup_stop = 600, - .setup_data = 100, + .setup_start = 260, + .setup_stop = 260, + .setup_data = 50, .sda_rise = 50, .sda_fall = 50, .scl_rise = 50, .scl_fall = 50, .hold_data = 300, - .buf = 20000, - .thigh_max = 5000, - .timeout = 106500 + .buf = 500, + .thigh_max = 50000, + .timeout = 35000000 } };