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Tue, 06 May 2025 13:57:39 -0700 (PDT) From: Peter Griffin Date: Tue, 06 May 2025 21:57:27 +0100 Subject: [PATCH v4 1/5] dt-bindings: soc: google: Add gs101-pmu-intr-gen binding documentation Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-1-9f64a2657316@linaro.org> References: <20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-0-9f64a2657316@linaro.org> In-Reply-To: <20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-0-9f64a2657316@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, willmcvicker@google.com, kernel-team@android.com, Peter Griffin , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Add bindings documentation for the Power Management Unit (PMU) interrupt generator. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Peter Griffin --- Changes since v2: - Fix dtschema error "relative path/filename doesn't match actual path or filename" (Robs patch bot) --- .../soc/google/google,gs101-pmu-intr-gen.yaml | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml b/Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml new file mode 100644 index 0000000000000000000000000000000000000000..2be022ca6a7d0780db3163f1b774e4825a9123fb --- /dev/null +++ b/Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/google/google,gs101-pmu-intr-gen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Power Management Unit (PMU) Interrupt Generation + +description: | + PMU interrupt generator for handshaking between PMU through interrupts. + +maintainers: + - Peter Griffin + +properties: + compatible: + items: + - const: google,gs101-pmu-intr-gen + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pmu_intr_gen: syscon@17470000 { + compatible = "google,gs101-pmu-intr-gen", "syscon"; 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Tue, 06 May 2025 13:57:40 -0700 (PDT) From: Peter Griffin Date: Tue, 06 May 2025 21:57:28 +0100 Subject: [PATCH v4 2/5] dt-bindings: soc: samsung: exynos-pmu: gs101: add google,pmu-intr-gen phandle Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-2-9f64a2657316@linaro.org> References: <20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-0-9f64a2657316@linaro.org> In-Reply-To: <20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-0-9f64a2657316@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, willmcvicker@google.com, kernel-team@android.com, Peter Griffin , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA gs101 requires access to the pmu interrupt generation register region which is exposed as a syscon. Update the exynos-pmu bindings documentation to reflect this. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Peter Griffin --- .../devicetree/bindings/soc/samsung/exynos-pmu.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 204da6fe458d2d4bfeee1471ebc5c38247477ae2..3109df43d5028c61cbcaa597e7bd8cb530eafb37 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -129,6 +129,11 @@ properties: description: Node for reboot method + google,pmu-intr-gen-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to PMU interrupt generation interface. + required: - compatible - reg @@ -189,6 +194,16 @@ allOf: properties: dp-phy: false + - if: + properties: + compatible: + contains: + enum: + - google,gs101-pmu + then: + required: + - google,pmu-intr-gen-syscon + examples: - | #include From patchwork Tue May 6 20:57:29 2025 Content-Type: text/plain; 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Tue, 06 May 2025 13:57:42 -0700 (PDT) From: Peter Griffin Date: Tue, 06 May 2025 21:57:29 +0100 Subject: [PATCH v4 3/5] MAINTAINERS: Add google,gs101-pmu-intr-gen.yaml binding file Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-3-9f64a2657316@linaro.org> References: <20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-0-9f64a2657316@linaro.org> In-Reply-To: <20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-0-9f64a2657316@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, willmcvicker@google.com, kernel-team@android.com, Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=799; i=peter.griffin@linaro.org; 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Signed-off-by: Peter Griffin --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index b2c3be5f6131432647dd01f22bbf4bf1c8bde9e6..5b2ec4c2023f39a3dd532ac61f0075a0a1555411 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10118,6 +10118,7 @@ L: linux-samsung-soc@vger.kernel.org S: Maintained C: irc://irc.oftc.net/pixel6-kernel-dev F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +F: Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml F: arch/arm64/boot/dts/exynos/google/ F: drivers/clk/samsung/clk-gs101.c F: drivers/phy/samsung/phy-gs101-ufs.c From patchwork Tue May 6 20:57:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 889005 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0102E1DED57 for ; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Add syscon node for the PMU Interrupt Generation registers. Additionally update the exynos-pmu node to provide a phandle to pmu-intr-gen syscon. These registers are required for CPU hotplug to be functional. Signed-off-by: Peter Griffin --- Changes since v1: * Model pmu-intr-gen as it's own syscon (Krzysztof) --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 91cda7758020563b2c5b5768d8921e87b1f4231c..48c691fd0a3ae430b5d66b402610d23b72b144d7 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1405,6 +1405,7 @@ sysreg_apm: syscon@174204e0 { pmu_system_controller: system-controller@17460000 { compatible = "google,gs101-pmu", "syscon"; reg = <0x17460000 0x10000>; + google,pmu-intr-gen-syscon = <&pmu_intr_gen>; poweroff: syscon-poweroff { compatible = "syscon-poweroff"; @@ -1434,6 +1435,11 @@ reboot-mode { }; }; + pmu_intr_gen: syscon@17470000 { + compatible = "google,gs101-pmu-intr-gen", "syscon"; + reg = <0x17470000 0x10000>; + }; + pinctrl_gpio_alive: pinctrl@174d0000 { compatible = "google,gs101-pinctrl"; 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Tue, 06 May 2025 13:57:44 -0700 (PDT) From: Peter Griffin Date: Tue, 06 May 2025 21:57:31 +0100 Subject: [PATCH v4 5/5] soc: samsung: exynos-pmu: enable CPU hotplug support for gs101 Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-5-9f64a2657316@linaro.org> References: <20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-0-9f64a2657316@linaro.org> In-Reply-To: <20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-0-9f64a2657316@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, willmcvicker@google.com, kernel-team@android.com, Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6461; i=peter.griffin@linaro.org; h=from:subject:message-id; bh=DmhgKVwxaPjv1roKDXteW3FTL4oH33qlI5LJtEP83bI=; b=owEBbQKS/ZANAwAKAc7ouNYCNHK6AcsmYgBoGne/lbKw4I26t2kad3YPe6N0+D1U9nwWjSbiV qxfSIyClViJAjMEAAEKAB0WIQQO/I5vVXh1DVa1SfzO6LjWAjRyugUCaBp3vwAKCRDO6LjWAjRy uvkwD/40C6kd/hz8G7/BRCna/loJnrlliDpXug9hRYnua7k0DIzUhdhVt6G5eWj5vbfW026Vel9 yi76dDm9N4DsM9VxevSVpl3qaUr3Q21qF7Tvl06e/EtiBLKJUwas3SLgiwaGo90dlsyECKjYjYE FNvdOu5u3ep+ZE5r2XrPiEVeyONHR1Jrc25AW0Au6lokRTQoVPNZXx4R1I0iWAAM8Uu7lVyhmal Kps/mBJZSBesMIcZnUR0IYgIgmLUccqlmXEPcS8E2OmmcN0hdKSY8jHcdYFqmKID/X78Wx4Jp+y +QPkpBTIfREDs22QEeKfYIz+EJmRSfOSpgmCB+t556edtpWW9Zhi/Cu/DTMVuZVMAM81XbgbP07 eG+rGtanTx2ezj3ZGpHcTkRMzjn7E5UiCQ9RQL8RB0lA3Ra8CnkXw0kQTa+m1FybTzn1lrxMstL ko0FZ2rMoUuEj+eMG5XaVoIsLAqxsbF3TtJhv8atgDEcqchqxmIENWV8CptTcii0zogpF9AdGlN 8cBbG9VePfp8tx3nb+Q40eZPwtQTrVzTMrrcVj8P1Xi6cHTqef290wsFTV4sBQn8LOZqYzPeFaZ JbgC3J0ZJIDgKGOO2/HAYe8h1ZNsMOQNJQskzv4J7hYOlnAS3dgA7xnLOhjzxALWcG6MRj1TtEo BbBnvwlnAiPhGjw== X-Developer-Key: i=peter.griffin@linaro.org; a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Some additional register writes are required when hotplugging CPUs on gs101, without these the system hangs when hotplugging. Specifically a CPU_INFORM register needs to be programmed with a hint value which is used by the EL3 firmware (el3mon) and the pmu-intr-gen registers need to be programmed. With this patch applied, and corresponding DT update CPU hotplug now works as expected. e.g. echo 0 > /sys/devices/system/cpu/cpu6/online echo 1 > /sys/devices/system/cpu/cpu6/online Note: to maintain compatibility with older DTs that didn't specify pmu-intr-gen phandle only a warning is issued if the syscon can't be obtained. Signed-off-by: Peter Griffin --- Changes in v4: * Fix typo with GS101_GRP1_INTR_BID_CLEAR in gs101_cpuhp_pmu_offline() (Peter) Changes in v2: * Use BIT macro (Kryzstof) * Use gs101_ prefix for cpuhp functions (Kryzstof) * Model pmuintrgen SFR region as it's own syscon (Kryzstof) * Use regmap_update_bits() API (Kryzstof) * Program hint on current processor number (Peter) --- drivers/soc/samsung/exynos-pmu.c | 80 ++++++++++++++++++++++++++++- drivers/soc/samsung/exynos-pmu.h | 1 + include/linux/soc/samsung/exynos-regs-pmu.h | 11 ++++ 3 files changed, 91 insertions(+), 1 deletion(-) diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index c40313886a012304b3f345d5d7369f15713eb857..0915b2457be7f473f09b6030923ba80c2f963427 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -33,6 +34,7 @@ struct exynos_pmu_context { struct device *dev; const struct exynos_pmu_data *pmu_data; struct regmap *pmureg; + struct regmap *pmuintrgen; }; void __iomem *pmu_base_addr; @@ -222,7 +224,8 @@ static const struct regmap_config regmap_smccfg = { }; static const struct exynos_pmu_data gs101_pmu_data = { - .pmu_secure = true + .pmu_secure = true, + .pmu_cpuhp = true, }; /* @@ -326,6 +329,60 @@ struct regmap *exynos_get_pmu_regmap_by_phandle(struct device_node *np, } EXPORT_SYMBOL_GPL(exynos_get_pmu_regmap_by_phandle); +/* + * CPU_INFORM register hint values which are used by + * EL3 firmware (el3mon). + */ +#define CPU_INFORM_CLEAR 0 +#define CPU_INFORM_C2 1 + +static int gs101_cpuhp_pmu_online(unsigned int cpu) +{ + + unsigned int cpuhint = smp_processor_id(); + u32 reg, mask; + + /* clear cpu inform hint */ + regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpuhint), + CPU_INFORM_CLEAR); + + mask = BIT(cpu); + + regmap_update_bits(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_ENABLE, + mask, (0 << cpu)); + + regmap_read(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_UPEND, ®); + + regmap_write(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_CLEAR, + reg & mask); + + return 0; +} + +static int gs101_cpuhp_pmu_offline(unsigned int cpu) +{ + u32 reg, mask; + unsigned int cpuhint = smp_processor_id(); + + /* set cpu inform hint */ + regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpuhint), + CPU_INFORM_C2); + + mask = BIT(cpu); + regmap_update_bits(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_ENABLE, + mask, BIT(cpu)); + + regmap_read(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_UPEND, ®); + regmap_write(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_CLEAR, + reg & mask); + + mask = (BIT(cpu+8)); + regmap_read(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_UPEND, ®); + regmap_write(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_CLEAR, + reg & mask); + return 0; +} + static int exynos_pmu_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -378,6 +435,27 @@ static int exynos_pmu_probe(struct platform_device *pdev) pmu_context->pmureg = regmap; pmu_context->dev = dev; + if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_cpuhp) { + + pmu_context->pmuintrgen = syscon_regmap_lookup_by_phandle(dev->of_node, + "google,pmu-intr-gen-syscon"); + if (IS_ERR(pmu_context->pmuintrgen)) { + /* + * To maintain support for older DTs that didn't specify syscon phandle + * just issue a warning rather than fail to probe. + */ + dev_warn(&pdev->dev, "pmu-intr-gen syscon unavailable\n"); + } else { + cpuhp_setup_state(CPUHP_BP_PREPARE_DYN, + "soc/exynos-pmu:prepare", + gs101_cpuhp_pmu_online, NULL); + + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "soc/exynos-pmu:online", + NULL, gs101_cpuhp_pmu_offline); + } + } + if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_init) pmu_context->pmu_data->pmu_init(); diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h index 0a49a2c9a08ef5bc75670551bdbf6d0a2d3e8ae9..0938bb4fe15f439e2d8bddeec51b6077e79a7e84 100644 --- a/drivers/soc/samsung/exynos-pmu.h +++ b/drivers/soc/samsung/exynos-pmu.h @@ -22,6 +22,7 @@ struct exynos_pmu_data { const struct exynos_pmu_conf *pmu_config; const struct exynos_pmu_conf *pmu_config_extra; bool pmu_secure; + bool pmu_cpuhp; void (*pmu_init)(void); void (*powerdown_conf)(enum sys_powerdown); diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h index cde299a85384a70d04dae49ee9a4e2daa88fbbf6..c82b40035e9fa8fe6a673b829a75a50a707afb1b 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -660,9 +660,20 @@ #define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION (0x32A8) /* For Tensor GS101 */ +/* PMU ALIVE */ #define GS101_SYSIP_DAT0 (0x810) +#define GS101_CPU0_INFORM (0x860) +#define GS101_CPU_INFORM(cpu) \ + (GS101_CPU0_INFORM + (cpu*4)) #define GS101_SYSTEM_CONFIGURATION (0x3A00) #define GS101_PHY_CTRL_USB20 (0x3EB0) #define GS101_PHY_CTRL_USBDP (0x3EB4) +/* PMU INTR GEN */ +#define GS101_GRP1_INTR_BID_UPEND (0x0108) +#define GS101_GRP1_INTR_BID_CLEAR (0x010c) +#define GS101_GRP2_INTR_BID_ENABLE (0x0200) +#define GS101_GRP2_INTR_BID_UPEND (0x0208) +#define GS101_GRP2_INTR_BID_CLEAR (0x020c) + #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */