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Mon, 28 Apr 2025 11:40:53 +0000 (GMT) Received: from epsmgmcp1.samsung.com (unknown [182.195.42.82]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20250428114053epsmtrp1c3098cf5f1ed0408ee08e14b1630b845~6eKSdPa7Q0239602396epsmtrp1q; Mon, 28 Apr 2025 11:40:53 +0000 (GMT) X-AuditID: b6c32a52-40bff70000004c16-2b-680f6945e8f8 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmcp1.samsung.com (Symantec Messaging Gateway) with SMTP id A1.10.19478.5496F086; Mon, 28 Apr 2025 20:40:53 +0900 (KST) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250428114051epsmtip19cfc81298abf833ca6d224db61e5b7c0~6eKQSo-O42852128521epsmtip1b; Mon, 28 Apr 2025 11:40:51 +0000 (GMT) From: Pritam Manohar Sutar To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, sunyeal.hong@samsung.com Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, Pritam Manohar Sutar , stable Subject: [PATCH] clk: samsung: correct clock summary for hsi1 block Date: Mon, 28 Apr 2025 17:20:49 +0530 Message-Id: <20250428115049.2064955-1-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCLMWRmVeSWpSXmKPExsWy7bCSnK5rJn+GQe8iE4sH87axWVz/8pzV 4t6OZewW124sZLc4f34Du8Wmx9dYLT723GO1uLxrDpvFjPP7mCwunnK1eHZvBZvFl58PmC0O v2lntfh3bSOLxafzF9gsmpatZ3IQ8Hh/o5XdY9OqTjaPzUvqPfq2rGL0+LxJLoA1issmJTUn syy1SN8ugSuj40xSwUS+iinXLjE3MN7g7mLk5JAQMJE4suAmM4gtJLCdUeLQrxSIuIzEo2kb WSFsYYmV/56zdzFyAdW8ZZTYdv8FYxcjBwebgKnExD0JIHERgTWMEl37f7GCOMwCy5kkHjZN YgLpFhZwlpiwYw2YzSKgKvHy2gywZl4Be4k1sysgFshL7D94FuwIXgFBiZMzn7CA2MxA8eat s5knMPLNQpKahSS1gJFpFaNoakFxbnpucoGhXnFibnFpXrpecn7uJkZwwGsF7WBctv6v3iFG Jg7GQ4wSHMxKIrxVBvwZQrwpiZVVqUX58UWlOanFhxilOViUxHmVczpThATSE0tSs1NTC1KL YLJMHJxSDUzaCZ3Tw/d7/Z1kuduCWbDl2up5WgfVAiZH7jp2aGlnsY/OcdHVzxZbnFqQFv+0 NIPn0fzZPhrnw90KXlSpnK89eqd9fieb1b0zXO21fV8ffHXNfLvxj7ziy3cOJXubGo+9s2re 9uDqbQX3ZecWP1uW/qLhqlheUmuM3vMoOds5+jucNvz2dN7Z87T8S2Vtl9Cu+BMKy5cJMgre kt554FXBhDe2pSF/NC2rljw9vsbsgVbOlsR50l2379UEXk3NWpf3+EFWh8ofAfedr3d8q/lT krNG+IXN1wsCptccj+078feZYVdVYZLcfKMFNv+8Gur5exX048J8Ta+ZW/+ZUdL1fqKu8dnw Qzu9PezPaj1UYinOSDTUYi4qTgQAzwjlAucCAAA= X-CMS-MailID: 20250428114053epcas5p450f97a4b8e41a1b06606e695e8c19f5f X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250428114053epcas5p450f97a4b8e41a1b06606e695e8c19f5f References: When debugfs is mounted to check clk_summary, 'mout_hsi1_usbdrd_user' shows 400Mhz instead of 40Mhz. Snippet of the clock summary is given as below dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ... mout_hsi1_usbdrd_user 0 0 0 400000000 0 0 50000 Y ... dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ... Hence corrected the clk-tree for the cmu_hsi1 & the corrected clock summary is as mentioned below. dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ... mout_clkcmu_hsi1_usbdrd 0 0 0 400000000 0 0 50000 Y ... dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ... mout_hsi1_usbdrd_user 0 0 0 40000000 0 0 50000 Y ... Fixes: 485e13fe2fb6 ("clk: samsung: add top clock support for ExynosAuto v920 SoC") Cc: stable Signed-off-by: Pritam Manohar Sutar --- drivers/clk/samsung/clk-exynosautov920.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung/clk-exynosautov920.c index dc8d4240f6de..b0561faecfeb 100644 --- a/drivers/clk/samsung/clk-exynosautov920.c +++ b/drivers/clk/samsung/clk-exynosautov920.c @@ -1393,7 +1393,7 @@ static const unsigned long hsi1_clk_regs[] __initconst = { /* List of parent clocks for Muxes in CMU_HSI1 */ PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"}; PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" }; -PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "mout_clkcmu_hsi1_usbdrd" }; +PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_hsi1_usbdrd" }; PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" }; static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = {