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Wed, 07 May 2025 03:10:24 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 5473AOXP006122; Wed, 7 May 2025 03:10:24 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (cse-cd02-lnx.qualcomm.com [10.64.75.246]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 5473AN1g005947 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 May 2025 03:10:24 +0000 Received: by cse-cd02-lnx.ap.qualcomm.com (Postfix, from userid 4438065) id 72E452F3D; Wed, 7 May 2025 11:10:22 +0800 (CST) From: Ziyue Zhang To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dmitry.baryshkov@linaro.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, andersson@kernel.org, konradybcio@kernel.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, quic_qianyu@quicinc.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, Ziyue Zhang Subject: [PATCH v5 1/6] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for sa8775p Date: Wed, 7 May 2025 11:10:14 +0800 Message-Id: <20250507031019.4080541-2-quic_ziyuzhan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250507031019.4080541-1-quic_ziyuzhan@quicinc.com> References: <20250507031019.4080541-1-quic_ziyuzhan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=L9cdQ/T8 c=1 sm=1 tr=0 ts=681acf23 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=tAWiX01tdBucjzfsbJgA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: VqHZ2eVrxvxyoPqdSm3A8yLEwzOQgqY4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA3MDAyNyBTYWx0ZWRfX7KeMtdaP0OJD ryAwGYeA5T/VvbsIgppzbgheZrT20myfJ8idtoSFNOhRuyGTuGUDYDVVKJCCnKbYD7hzFhp02w0 0DaDOZa59PI/aVyJ24TLN9Xjwp9I3MgNQR/mV0XJkrvr9G/6lDG5t+sAgqVNI6wuUEUnwqOVRzC eMQRa7RdHI+A7iRh+v3V+uRYo8tSZN33P/Bamp2sCJ/U16cFmteoFuIn/Xw4L+Gz4ZSx9CIplrC Yc+iOaBMtHZmEcc/SfmVJCQAq+zabNisMOsQW0P5tsLrSSoy2U1lmIaaFnRnCt62ZIhWYKQXEq9 0yxai5jKSmswk6zSZrm5HtJ19iP+dGGsfENhi3NUGcUUVMuCLy44Z3ythzgeb6ihAm3OiQAJ0pf Ty3NFeNvDwvUYBmLSsLP3L+uoFnT9EWU3Gv+SqBZfa3+3tMJ8OmiJb8Dga/NB91AIOnAcfYo X-Proofpoint-ORIG-GUID: VqHZ2eVrxvxyoPqdSm3A8yLEwzOQgqY4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-07_01,2025-05-06_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=999 spamscore=0 suspectscore=0 impostorscore=0 mlxscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505070027 qcs8300 pcie1 phy use the same clocks as sa8775p, in the review comments of qcs8300 patches, gcc aux clock should be removed and replace it with phy_aux clock.So move "qcom,sa8775p-qmp-gen4x4-pcie-phy" compatible from 7 clocks' list to 6 clocks' list to solve the dtb check error. qcs8300 pcie phy only use 6 clocks, so move qcs8300 gen4x2 pcie phy compatible from 7 clocks' list to 6 clocks' list. Signed-off-by: Ziyue Zhang --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 2c6c9296e4c0..a11a7e78636d 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -176,6 +176,8 @@ allOf: contains: enum: - qcom,qcs615-qmp-gen3x1-pcie-phy + - qcom,qcs8300-qmp-gen4x2-pcie-phy + - qcom,sa8775p-qmp-gen4x4-pcie-phy - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy @@ -196,9 +198,7 @@ allOf: compatible: contains: enum: - - qcom,qcs8300-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x2-pcie-phy - - qcom,sa8775p-qmp-gen4x4-pcie-phy then: properties: clocks: From patchwork Wed May 7 03:10:15 2025 Content-Type: text/plain; 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Wed, 07 May 2025 03:10:24 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 5473AO2r006135; Wed, 7 May 2025 03:10:24 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (cse-cd02-lnx.qualcomm.com [10.64.75.246]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 5473AOBR006125 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 May 2025 03:10:24 +0000 Received: by cse-cd02-lnx.ap.qualcomm.com (Postfix, from userid 4438065) id 267EE2F3F; Wed, 7 May 2025 11:10:23 +0800 (CST) From: Ziyue Zhang To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dmitry.baryshkov@linaro.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, andersson@kernel.org, konradybcio@kernel.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, quic_qianyu@quicinc.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, Ziyue Zhang Subject: [PATCH v5 2/6] dt-bindings: PCI: qcom,pcie-sa8775p: document qcs8300 Date: Wed, 7 May 2025 11:10:15 +0800 Message-Id: <20250507031019.4080541-3-quic_ziyuzhan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250507031019.4080541-1-quic_ziyuzhan@quicinc.com> References: <20250507031019.4080541-1-quic_ziyuzhan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: naYzJ3r7232AqcpGp74D6qRF_KxnJ4El X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA3MDAyNyBTYWx0ZWRfX6UoJwPf6sWWn URY/PXYrqLJvbvtkqMmpfb7kWioNoieH/nIQEqNW3fgKsTtEELqqUudIr9/4cXzr+x2DgRtCgGl e0k4cSO2ZTrOldSybM2p4lM7eAuLrM2cy97Q0t7VEaN9iuxFFcZVC/Q6iU4FVSPrrpVU7KbtNJP g3vHjCZsr7BglL4l2pLjnuKJe3b+pUDz5+sh4WePKDaP+K2lxpixb6skSPxUF5f7hf4LCjzN6ly /+LnmBO8vTigJrQLcotL/wpOf7X5U6gKyfSBTpfOGGBEItw6MdHZLLVPwf5f60uj2xod/SbVZ8O rac3bOCpqk1DjeMtN2m17RtLhEbRBSjK51BDYNJ6BPlUqaBXNJ1t3ftc6u14bnGk18NJyXc7eGk Rnxd3hj2QE1rIUOGUlbG07HNWUF4yUMbMROPrcPxYQMEbLQ6UOGrYw7RB8Rjz6SNWjsjuxuG X-Authority-Analysis: v=2.4 cv=dPemmPZb c=1 sm=1 tr=0 ts=681acf23 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=5s6rildDmCdGve1q1wIA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: naYzJ3r7232AqcpGp74D6qRF_KxnJ4El X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-07_01,2025-05-06_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 malwarescore=0 mlxscore=0 clxscore=1011 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505070027 Add compatible for qcs8300 platform, with sa8775p as the fallback. Signed-off-by: Ziyue Zhang --- .../bindings/pci/qcom,pcie-sa8775p.yaml | 26 ++++++++++++++----- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml index efde49d1bef8..154bb60be402 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml @@ -16,7 +16,12 @@ description: properties: compatible: - const: qcom,pcie-sa8775p + oneOf: + - const: qcom,pcie-sa8775p + - items: + - enum: + - qcom,pcie-qcs8300 + - const: qcom,pcie-sa8775p reg: minItems: 6 @@ -45,7 +50,7 @@ properties: interrupts: minItems: 8 - maxItems: 8 + maxItems: 9 interrupt-names: items: @@ -57,13 +62,16 @@ properties: - const: msi5 - const: msi6 - const: msi7 + - const: global resets: - maxItems: 1 + minItems: 1 + maxItems: 2 reset-names: items: - const: pci + - const: link_down required: - interconnects @@ -129,7 +137,8 @@ examples: , , , - ; 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Add PCIe lane equalization preset properties for 8 GT/s and 16GT/s Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 172 +++++++++++++++++++++++++- 1 file changed, 171 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index fe8824477158..b2d4fe59b03d 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -601,7 +601,7 @@ gcc: clock-controller@100000 { #power-domain-cells = <1>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, - <0>, + <&pcie0_phy>, <0>, <0>, <0>, @@ -711,6 +711,176 @@ mmss_noc: interconnect@17a0000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + pcie0: pci@1c00000 { + device_type = "pci"; + compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <0>; + num-lanes = <2>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_0_GDSC>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 + 0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + + status = "disabled"; + + pcie3_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + + /* GEN 4 x2 */ + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + }; + }; + }; + + pcie0_phy: phy@1c04000 { + compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy"; + reg = <0x0 0x01c04000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; 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Wed, 07 May 2025 03:10:28 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 5473AQjN014725; Wed, 7 May 2025 03:10:26 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 46dc7mdwp4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 May 2025 03:10:26 +0000 Received: from APTAIPPMTA01.qualcomm.com (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 5473AQEQ014705; Wed, 7 May 2025 03:10:26 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (cse-cd02-lnx.qualcomm.com [10.64.75.246]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 5473APRD014694 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 May 2025 03:10:26 +0000 Received: by cse-cd02-lnx.ap.qualcomm.com (Postfix, from userid 4438065) id 7F6472F3D; Wed, 7 May 2025 11:10:24 +0800 (CST) From: Ziyue Zhang To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dmitry.baryshkov@linaro.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, andersson@kernel.org, konradybcio@kernel.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, quic_qianyu@quicinc.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, Ziyue Zhang , Konrad Dybcio Subject: [PATCH v5 4/6] arm64: dts: qcom: qcs8300-ride: enable pcie0 interface Date: Wed, 7 May 2025 11:10:17 +0800 Message-Id: <20250507031019.4080541-5-quic_ziyuzhan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250507031019.4080541-1-quic_ziyuzhan@quicinc.com> References: <20250507031019.4080541-1-quic_ziyuzhan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=EOUG00ZC c=1 sm=1 tr=0 ts=681acf24 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=Ukq1jWRXX9In9DvyudYA:9 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: hw6_1St1vxreUZ1TD36bWQEMbvtWiB2Y X-Proofpoint-GUID: hw6_1St1vxreUZ1TD36bWQEMbvtWiB2Y X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA3MDAyNyBTYWx0ZWRfX6QQto7oyq+Z0 GbZ3P3w+p0lgdE640OIJWY09/1Sbj8uK78NDTHrWzUym8t8B5GbZbw4p+GR1XpMvGfpsdK6+tJd 3s1AWRvazRN1MsOeO/7R+kFWvSDu96kL+73SL3TVBenOrrGUf8s/3nzoMHnh1fRZ795aYoGrhBW dJvY31D4z1VySK7mzKxnkbT+hvt/JzEhS+Gr0IUyzs8Hc6x9cp3+OBWE3gbkuluPI1WUjxm0/rI BNAxOo0z6/BXYJI7tnVTTEgs1Jqt6QOry+8xHEsTC+EZv4BuFex6DLE7gmt0w6DX435zIuGBbUs dNnSl21OkEVsMH78BVEUs09lColYxh/jedmN1a1VxCJXrv9caM/HicJxaAxHemi3uqL3nVlAIng p84Ibr9J0YdO/b9Q4/DOzXOjcJQVyMXUF2++tKoc9MtC4QUITGCvdc7WjcGmBdHVx8y2P3Y4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-07_01,2025-05-06_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1011 impostorscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 suspectscore=0 mlxlogscore=960 mlxscore=0 priorityscore=1501 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505070027 Add configurations in devicetree for PCIe0, board related gpios, PMIC regulators, etc for qcs8300-ride board. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 40 +++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index b5c9f89b3435..c3fe3b98b1b6 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -285,6 +285,23 @@ queue3 { }; }; +&pcie0 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -310,6 +327,29 @@ &serdes0 { }; &tlmm { + pcie0_default_state: pcie0-default-state { + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { pins = "gpio5"; From patchwork Wed May 7 03:10:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziyue Zhang X-Patchwork-Id: 888680 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D23321A8F84; Wed, 7 May 2025 03:10:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746587448; cv=none; b=mBbafXZ1UZX/3oMoqoNOalP2sW6+913gCYxBixwQJdcC67PlziBCv2xGta6EsICSqMBfyPe1EENJPYN2tYbZq2cjU8Y6m8wKYsxGFcmER5jUZCPjgiGuGqdkXZyfSJXR/PaSipLB8p3qTNMOZ8BRstjEcZZWkrO1yzjHphinbrU= ARC-Message-Signature: i=1; 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Wed, 7 May 2025 03:10:26 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 46dc7m5yt2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 May 2025 03:10:26 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 5473AQw1006156; Wed, 7 May 2025 03:10:26 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (cse-cd02-lnx.qualcomm.com [10.64.75.246]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 5473AQT0006155 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 May 2025 03:10:26 +0000 Received: by cse-cd02-lnx.ap.qualcomm.com (Postfix, from userid 4438065) id 256252F3F; Wed, 7 May 2025 11:10:25 +0800 (CST) From: Ziyue Zhang To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dmitry.baryshkov@linaro.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, andersson@kernel.org, konradybcio@kernel.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, quic_qianyu@quicinc.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, Ziyue Zhang , Konrad Dybcio Subject: [PATCH v5 5/6] arm64: dts: qcom: qcs8300: enable pcie1 Date: Wed, 7 May 2025 11:10:18 +0800 Message-Id: <20250507031019.4080541-6-quic_ziyuzhan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250507031019.4080541-1-quic_ziyuzhan@quicinc.com> References: <20250507031019.4080541-1-quic_ziyuzhan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=UJPdHDfy c=1 sm=1 tr=0 ts=681acf25 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=K7kricVwaqq8vgrxYV0A:9 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: bTiS3bnM6mQs-Eyjg550wekGKW1kip0P X-Proofpoint-GUID: bTiS3bnM6mQs-Eyjg550wekGKW1kip0P X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA3MDAyNyBTYWx0ZWRfX6f2iQgIGAqmj aW1WaDvICv4mTvYpDcf9lfUYZ0JQc4EdaaMZyfsJYzCY2Tl6J+xey5VEymrxIhzpNd10k69cZ26 zNN05YJPp7L+kLZ5komQwZ4DL3Fz4pM5s1UqM9cFhdNND4pRAKRzAcPX5+rptdldzopKguB0j1R AhJCxCtupEacgdPVrCpblWMaQuvoUeb3I7KeWdsTYwTwE3NehiH3RbKmlUi17mYCZUUerrtX9yp aAx03/t7apFaYqkdlQekiC1TLlAJcQUf2SbtGBd+d+i33jGhzdJtRcGofe6Nw/qslsXj8C8Y7Gp b+gIBdyniqg6iM6eZt3LN8rzsU0BOS/ITQF0o192mIpyT+9CyiOkDoCuY0H6dNgKDHA2RhnX3EW PIVXU8EERp9V9vfmQa3cZdC22bCQznSPx/QjkMtki0E2d/v+uBVcEuZlNqVOmxW11f0Ll8Du X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-07_01,2025-05-06_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 clxscore=1015 phishscore=0 spamscore=0 impostorscore=0 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505070027 Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence. Add PCIe lane equalization preset properties for 8 GT/s and 16GT/s. Acked-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 125 +++++++++++++++++++++++++- 1 file changed, 124 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index b2d4fe59b03d..9917b98f6b6d 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -602,7 +602,7 @@ gcc: clock-controller@100000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie0_phy>, - <0>, + <&pcie1_phy>, <0>, <0>, <0>, @@ -881,6 +881,129 @@ pcie0_phy: phy@1c04000 { status = "disabled"; }; + pcie1: pci@1c10000 { + device_type = "pci"; + compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <1>; + num-lanes = <4>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, + <0x100 &pcie_smmu 0x0081 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_1_GDSC>; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 + 0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + + status = "disabled"; + }; + + pcie1_phy: phy@1c14000 { + compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; + reg = <0x0 0x01c14000 0x0 0x4000>; + + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, + <&gcc GCC_PCIE_1_PHY_AUX_CLK>; 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Reviewed-by: Konrad Dybcio Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 40 +++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index c3fe3b98b1b6..508a1276ed05 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -302,6 +302,23 @@ &pcie0_phy { status = "okay"; }; +&pcie1 { + perst-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -350,6 +367,29 @@ perst-pins { }; }; + pcie1_default_state: pcie1-default-state { + wake-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio22"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { pins = "gpio5";