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Tue, 6 May 2025 21:43:33 -0700 From: Robert Lin To: , , , , CC: , , , , , , Robert Lin Subject: [PATCH v8 1/3] clocksource/drivers/timer-tegra186: add WDIOC_GETTIMELEFT support Date: Wed, 7 May 2025 12:43:09 +0800 Message-ID: <20250507044311.3751033-2-robelin@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250507044311.3751033-1-robelin@nvidia.com> References: <20250507044311.3751033-1-robelin@nvidia.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D8:EE_|CH3PR12MB8725:EE_ X-MS-Office365-Filtering-Correlation-Id: 4d8c7036-92d8-4ceb-bc60-08dd8d21c1b3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: lMGS/pkJzGKJHZ8HdAonCm1nvRHcwiPkGHmKWPmIvyox0WG4xxWZbpUEWIZVxhFMtlPeqcV1chB+Nu0xR+W/d+NlWIQpbhsw6bVxr+wkYaUlmxLp2SonIJmsX5KfcFL2HhjlQYvpiAKpjWCTkKfAmHKAwATFICLQ1afJ6qM1H2XIJUAVGT7Ej4pA3OJ4XZIq/1w13JFhm+D0spzaEmAqBZ6D0rx/90muwhUcbFxcIWhnHjA7+iqstiLV2QYGV/DF5krArqrIb8NEBxTz6YGgyW93LI4E0OMdrf5Q50yS1bcVGyIpbius5rg3qqfvRXGmgxY7x1tts+LVyqTmlHbhcae+Fl6f5gbivZDvM4aF8U0llft9/nEV/ZoWUNAc/eaDB31n1tM3dQoQyIR+IIeilyqH3AA5rzqF/fmvJfagffF+WRoViRjFN6mLKDBJhx4oXCtZ7CkpHEBmhuNfpF+Xqd7k2jVgqruZFq0vCJx55/JXsfxBkpIVx+rbEdPIqBu1qQq4f+uqLC+/8jakxCB9O+eMWMfl0iis/37LYes5ZYJbnHeR7z/i1uYri7qPe/9kaUIG8cFQJMsdX9QbzcBhRI3jyxs8lou0/zj/BSns6/oPzO5vnGztoQUKebi2F3zyEd5N0dCGI8c/9J60qFSo5xZFeoqP+JyO2knuZOdL6FV5z4t9VQoyTfGGqMGa9Cn9SD/HmR2E8chI4rXWhBOcrSMl0tMBmr2ackgJlBBbsxT6QRV0V0fIPXDu0/RyPHXGJCZeAt59wD76RMI+TivUw1NWiBq0g+g4Dh3F3ALos81hKfnrsBsqKcxF52HqmodDpbA9FZr+Fin8LxIQkXyIFMAyXKoD55PXCoSpT5fznq43CVHCmcMG5i7xWSYCefGMzJCYaomJ8braFDJHw7MwbOTleKzxWJhoGQsKhN+P3XHJD+icBnB7IxeQLCdy6JE4oAMDkh2VfYid5W1RfQmQ8HogTvLQbGD7Wvh31QloZyZSHxGKKZlS5G/sfTW6QlMXKsIbLysa8RrV8f18cleslCb0V+lBGIvyONn270SQLZH/v81fF0H02ud/hhIc2y/fOa1DBVeRXqrTflqycOgedPkJUylkOUpSPeatI3hlz0b6TlP8FEwONEUxr50bPnNoxIUdI4btCMQ9JrXu2X+9jutzO68QDvQSbX33lQYkCHgvYH/KhW9QiWP9ycmt2rE0JpKSyArvKYzTTfV/UC0yd1zs3/BC9g2+8iFtxD37mf0tfl6mw4xCgJDQ8xOmMLyuAWAjQZ3++oCyc2qb2b6QGTWxAax7eTP8PVYFp5c4j9n8z9SQJHETHXctbXdWW0EZ+K1EEefxbi1dGe/lYYNVyshm8w5j+dqWCsuAuTNO42iSb3t2SeebRQHP7q05+DDGrLujLg/6P9BQza2bY3rMYwDCSo1Pqyq28Veiq/kOJJCw+loa07WczhqK7wr1R7p001LCs8uP6xbGTszutS04Cf2AiTzb78czIpGCKVm0jrszHdjdkFtNK2pyRgU1+stV X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2025 04:43:47.8302 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d8c7036-92d8-4ceb-bc60-08dd8d21c1b3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8725 From: Pohsun Su This change adds support for WDIOC_GETTIMELEFT so userspace programs can get the number of seconds before system reset by the watchdog timer via ioctl. Signed-off-by: Pohsun Su Signed-off-by: Robert Lin --- drivers/clocksource/timer-tegra186.c | 64 +++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/timer-tegra186.c index ea742889ee06..e3ea6110e6f5 100644 --- a/drivers/clocksource/timer-tegra186.c +++ b/drivers/clocksource/timer-tegra186.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019-2020 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2019-2025 NVIDIA Corporation. All rights reserved. */ +#include #include #include #include @@ -30,6 +31,7 @@ #define TMRSR 0x004 #define TMRSR_INTR_CLR BIT(30) +#define TMRSR_PCV GENMASK(28, 0) #define TMRCSSR 0x008 #define TMRCSSR_SRC_USEC (0 << 0) @@ -46,6 +48,9 @@ #define WDTCR_TIMER_SOURCE_MASK 0xf #define WDTCR_TIMER_SOURCE(x) ((x) & 0xf) +#define WDTSR 0x004 +#define WDTSR_CURRENT_EXPIRATION_COUNT GENMASK(14, 12) + #define WDTCMDR 0x008 #define WDTCMDR_DISABLE_COUNTER BIT(1) #define WDTCMDR_START_COUNTER BIT(0) @@ -235,12 +240,69 @@ static int tegra186_wdt_set_timeout(struct watchdog_device *wdd, return 0; } +static unsigned int tegra186_wdt_get_timeleft(struct watchdog_device *wdd) +{ + struct tegra186_wdt *wdt = to_tegra186_wdt(wdd); + u32 expiration, val; + u64 timeleft; + + if (!watchdog_active(&wdt->base)) { + /* return zero if the watchdog timer is not activated. */ + return 0; + } + + /* + * Reset occurs on the fifth expiration of the + * watchdog timer and so when the watchdog timer is configured, + * the actual value programmed into the counter is 1/5 of the + * timeout value. Once the counter reaches 0, expiration count + * will be increased by 1 and the down counter restarts. + * Hence to get the time left before system reset we must + * combine 2 parts: + * 1. value of the current down counter + * 2. (number of counter expirations remaining) * (timeout/5) + */ + + /* Get the current number of counter expirations. Should be a + * value between 0 and 4 + */ + val = readl_relaxed(wdt->regs + WDTSR); + expiration = FIELD_GET(WDTSR_CURRENT_EXPIRATION_COUNT, val); + if (WARN_ON_ONCE(expiration > 4)) + return 0; + + /* Get the current counter value in microsecond. */ + val = readl_relaxed(wdt->tmr->regs + TMRSR); + timeleft = FIELD_GET(TMRSR_PCV, val); + + /* + * Calculate the time remaining by adding the time for the + * counter value to the time of the counter expirations that + * remain. + */ + timeleft += (((u64)wdt->base.timeout * USEC_PER_SEC) / 5) * (4 - expiration); + + /* + * Convert the current counter value to seconds, + * rounding up to the nearest second. Cast u64 to + * u32 under the assumption that no overflow happens + * when coverting to seconds. + */ + timeleft = DIV_ROUND_CLOSEST_ULL(timeleft, USEC_PER_SEC); + + if (WARN_ON_ONCE(timeleft > U32_MAX)) + return U32_MAX; + + return lower_32_bits(timeleft); +} + static const struct watchdog_ops tegra186_wdt_ops = { .owner = THIS_MODULE, .start = tegra186_wdt_start, .stop = tegra186_wdt_stop, .ping = tegra186_wdt_ping, .set_timeout = tegra186_wdt_set_timeout, + .get_timeleft = tegra186_wdt_get_timeleft, }; static struct tegra186_wdt *tegra186_wdt_create(struct tegra186_timer *tegra, From patchwork Wed May 7 04:43:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Lin X-Patchwork-Id: 888512 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2086.outbound.protection.outlook.com [40.107.102.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 365001D7E5C; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2025 04:43:53.3195 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bdc2bd0f-be37-40e0-9b5d-08dd8d21c4fa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8949 From: Pohsun Su This change removes watchdog self-pinging behavior. The timer irq handler is triggered due to the 1st expiration, the handler disables and enables watchdog but also implicitly clears the expiration count so the count can only be 0 or 1. Since this watchdog supports opened, configured, or pinged by systemd, We remove this behavior or the watchdog may not bark when systemd crashes since the 5th expiration never comes. Signed-off-by: Pohsun Su Signed-off-by: Robert Lin --- drivers/clocksource/timer-tegra186.c | 27 --------------------------- 1 file changed, 27 deletions(-) diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/timer-tegra186.c index e3ea6110e6f5..20685d122b47 100644 --- a/drivers/clocksource/timer-tegra186.c +++ b/drivers/clocksource/timer-tegra186.c @@ -175,9 +175,6 @@ static void tegra186_wdt_enable(struct tegra186_wdt *wdt) value &= ~WDTCR_PERIOD_MASK; value |= WDTCR_PERIOD(1); - /* enable local interrupt for WDT petting */ - value |= WDTCR_LOCAL_INT_ENABLE; - /* enable local FIQ and remote interrupt for debug dump */ if (0) value |= WDTCR_REMOTE_INT_ENABLE | @@ -428,23 +425,10 @@ static int tegra186_timer_usec_init(struct tegra186_timer *tegra) return clocksource_register_hz(&tegra->usec, USEC_PER_SEC); } -static irqreturn_t tegra186_timer_irq(int irq, void *data) -{ - struct tegra186_timer *tegra = data; - - if (watchdog_active(&tegra->wdt->base)) { - tegra186_wdt_disable(tegra->wdt); - tegra186_wdt_enable(tegra->wdt); - } - - return IRQ_HANDLED; -} - static int tegra186_timer_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct tegra186_timer *tegra; - unsigned int irq; int err; tegra = devm_kzalloc(dev, sizeof(*tegra), GFP_KERNEL); @@ -463,8 +447,6 @@ static int tegra186_timer_probe(struct platform_device *pdev) if (err < 0) return err; - irq = err; - /* create a watchdog using a preconfigured timer */ tegra->wdt = tegra186_wdt_create(tegra, 0); if (IS_ERR(tegra->wdt)) { @@ -491,17 +473,8 @@ static int tegra186_timer_probe(struct platform_device *pdev) goto unregister_osc; } - err = devm_request_irq(dev, irq, tegra186_timer_irq, 0, - "tegra186-timer", tegra); - if (err < 0) { - dev_err(dev, "failed to request IRQ#%u: %d\n", irq, err); - goto unregister_usec; - } - return 0; -unregister_usec: - clocksource_unregister(&tegra->usec); unregister_osc: clocksource_unregister(&tegra->osc); unregister_tsc: