From patchwork Thu May 8 06:35:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sirius Wang X-Patchwork-Id: 889022 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C8654B1E45; Thu, 8 May 2025 06:36:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746686163; cv=none; b=Ii2HazqKRVceNCMkBqvsG/OgEGEW6OVysSOKAkg5gDMQdiQJAkOamOHWSZCraiGhEJcWje65y9Cd4BW30RBCyjAoQ8Lrr9ZhJfJphYmqQjffujflMSi3f/LUbh4z5/+Uk9PsRi+4xgcIqe6cB8X5lNN8MeOCnDTTVi/uJJkW+GE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746686163; c=relaxed/simple; bh=nUybPfIJN8nxlB8+l3za+c+gQiaPurdscHuMFvr6DO4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=T+H+wti3uKbf6jYp5FsaKDzraDxlKU8AQ+lXYxHPD5x/+HLZ6vlxuqJ1vZwYXAQ9A7LHAg3O3meKx+zA8bjF1jcZx4Mcv65+A0kdBIAf+xDxLz7IMeW6YdaKmkL5YpKkUt+X25I3Ktx8s1A5ODQB6XCvq5ImxUYmv0g82FciGt4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=QUSjx8Qj; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="QUSjx8Qj" X-UUID: afc9ab5a2bd611f082f7f7ac98dee637-20250508 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=J+k3hUUer1eheTQ5q4p0oNapEKv+llZFBmeNNNPE+z8=; b=QUSjx8QjXcBcFbUTnvERCNfWsHaaNBXDTfH9tym/UjrcKYbdyAT2x5jM24bnAZaM5TtMJzjstypTPEq+3yRTZCarzsnqNL/Kq2mnVDYT39HiR1e1aFg3npD2QmJyK9DJqwNTvg20jfioLHJDrD9W7P6JRETyVwthCp0/9SnzHhY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1, REQID:e1517d43-1ca9-400d-bc5d-0844d04bcae6, IP:0, UR L:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:-5 X-CID-META: VersionHash:0ef645f, CLOUDID:b0b96c80-1eec-4f76-b81b-944fecd9abcd, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: afc9ab5a2bd611f082f7f7ac98dee637-20250508 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2036067457; Thu, 08 May 2025 14:35:52 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Thu, 8 May 2025 14:35:50 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Thu, 8 May 2025 14:35:50 +0800 From: Sirius Wang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Jiri Slaby , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang CC: , , , , , , , Sirius Wang Subject: [PATCH v2 1/3] dt-bindings: arm: Add compatible for MediaTek MT8189 Date: Thu, 8 May 2025 14:35:40 +0800 Message-ID: <20250508063546.289115-2-sirius.wang@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250508063546.289115-1-sirius.wang@mediatek.com> References: <20250508063546.289115-1-sirius.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This commit adds dt-binding documentation for the MediaTek MT8189 reference board. Signed-off-by: Sirius Wang --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index fa1646bc0bac..05e827076a7f 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -372,6 +372,10 @@ properties: - enum: - mediatek,mt8188-evb - const: mediatek,mt8188 + - items: + - enum: + - mediatek,mt8189-evb + - const: mediatek,mt8189 - description: Google Hayato items: - const: google,hayato-rev1 From patchwork Thu May 8 06:35:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sirius Wang X-Patchwork-Id: 888768 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29BD61E2834; Thu, 8 May 2025 06:51:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746687071; cv=none; b=iKTW1nOfRs1viDGJppuWeTzE1H+/oAKzZMBmlAJ+t4aFjTft347OSguWWubZEyHxLbBWqmn2YovXR0lgiIfM9cOSTRLutmm9wh5chd+BOFb40IKy8tKzzUxb0FKfnQRzAbON7gM7nJuXClbpnR0TRO2w3qx0rWzPvzekpjcVbe0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746687071; c=relaxed/simple; bh=n2v0Gmkm4hGwMwg7j7wGFTCELbux8wlLmGTUhIw+LSg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SwCAHW5hXGcqY2d4frkNHo+oNOQ5shW5tKHj11GD1ujQXXkpxcLiYKVYDn7HWL71wQT5YLBeJkXN/lTm7tlW6hQut9N1ase1Y4OPGVU54+ha6hG87ZpHKf3S4FxR+5eSrvsHPq+WhqjVgjKmXW6sFulzZOgRZjl8Rj8y1mu6s5A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=d2R/m738; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="d2R/m738" X-UUID: b1024cf22bd611f0813e4fe1310efc19-20250508 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=DqEocXsXGQ7lTYZ6vfAmK0h2RIid3JxgwK28/Ie6WsA=; b=d2R/m7388Iw0X2G7vEmdR7lFxxPOwplnovsxD6+aFCMFk3Eh+M/xI3iZiGngshjupuNmmm8/rN7w2mOxR8wJmuSFpzWf0eRszXlTKS+bIbSoVFGXZkUh5qDMw5ikFeiDNih3m3/sQhdJZ9y7thieuxUOFTUZRqWQA8NriqL8r30=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1, REQID:d8fbaa33-f653-4150-964a-0c785e957538, IP:0, UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:0ef645f, CLOUDID:1370c9f9-d2be-4f65-b354-0f04e3343627, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: b1024cf22bd611f0813e4fe1310efc19-20250508 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1720980272; Thu, 08 May 2025 14:35:54 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Thu, 8 May 2025 14:35:52 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Thu, 8 May 2025 14:35:52 +0800 From: Sirius Wang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Jiri Slaby , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang CC: , , , , , , , Sirius Wang Subject: [PATCH v2 2/3] dt-bindings: serial: mediatek, uart: Add compatible for MT8189 Date: Thu, 8 May 2025 14:35:41 +0800 Message-ID: <20250508063546.289115-3-sirius.wang@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250508063546.289115-1-sirius.wang@mediatek.com> References: <20250508063546.289115-1-sirius.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add compatible string for serial on MT8189 SoC. Signed-off-by: Sirius Wang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/serial/mediatek,uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml index c55d9a0efa19..fabc22d47cb3 100644 --- a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml +++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml @@ -46,6 +46,7 @@ properties: - mediatek,mt8183-uart - mediatek,mt8186-uart - mediatek,mt8188-uart + - mediatek,mt8189-uart - mediatek,mt8192-uart - mediatek,mt8195-uart - mediatek,mt8365-uart From patchwork Thu May 8 06:35:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sirius Wang X-Patchwork-Id: 888769 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6DA9215771; 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Thu, 08 May 2025 14:35:56 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Thu, 8 May 2025 14:35:54 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Thu, 8 May 2025 14:35:54 +0800 From: Sirius Wang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Jiri Slaby , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang CC: , , , , , , , Sirius Wang Subject: [PATCH v2 3/3] arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile Date: Thu, 8 May 2025 14:35:42 +0800 Message-ID: <20250508063546.289115-4-sirius.wang@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250508063546.289115-1-sirius.wang@mediatek.com> References: <20250508063546.289115-1-sirius.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add mt8189 dts evaluation board and Mafefile Signed-off-by: Sirius Wang --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8189-evb.dts | 20 + arch/arm64/boot/dts/mediatek/mt8189.dtsi | 430 ++++++++++++++++++++ 3 files changed, 451 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 3aa06476c6c0..ad2ac9e1bb79 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8189-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts new file mode 100644 index 000000000000..e5d9ce1b8e61 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Sirius Wang + */ +/dts-v1/; +#include "mt8189.dtsi" + +/ { + model = "MediaTek MT8189 evaluation board"; + compatible = "mediatek,mt8189-evb", "mediatek,mt8189"; + + chosen: chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts/mediatek/mt8189.dtsi new file mode 100644 index 000000000000..50c7a3811e0f --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi @@ -0,0 +1,430 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 MediaTek Inc. + */ + +#include +#include + +/ { + compatible = "mediatek,mt8189"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + clk32k: oscillator-clk32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "clk32k"; + }; + + clk13m: oscillator-clk13m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-mult = <1>; + clock-div = <2>; + clock-output-names = "clk13m"; + }; + + clk26m: oscillator-clk26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk104m: oscillator-clk104m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-mult = <4>; + clock-div = <1>; + clock-output-names = "clk104m"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x000>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <742>; + cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>, + <&cpu_system_vcore>, <&cpu_s2idle>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; + #cooling-cells = <2>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <742>; + cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>, + <&cpu_system_vcore>, <&cpu_s2idle>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; + #cooling-cells = <2>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <742>; + cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>, + <&cpu_system_vcore>, <&cpu_s2idle>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; + #cooling-cells = <2>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <742>; + cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>, + <&cpu_system_vcore>, <&cpu_s2idle>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; + #cooling-cells = <2>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x400>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <742>; + cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>, + <&cpu_system_vcore>, <&cpu_s2idle>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; + #cooling-cells = <2>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x500>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <742>; + cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>, + <&cpu_system_vcore>, <&cpu_s2idle>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; + #cooling-cells = <2>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x600>; + enable-method = "psci"; + clock-frequency = <3000000000>; + capacity-dmips-mhz = <958>; + cpu-idle-states = <&cpu_off_m>, <&cpu_cluster_off_m>, <&cpu_mcusys_off_m>, + <&cpu_system_vcore>, <&cpu_s2idle>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; + #cooling-cells = <2>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x700>; + enable-method = "psci"; + clock-frequency = <3000000000>; + capacity-dmips-mhz = <958>; + cpu-idle-states = <&cpu_off_m>, <&cpu_cluster_off_m>, <&cpu_mcusys_off_m>, + <&cpu_system_vcore>, <&cpu_s2idle>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; + #cooling-cells = <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + core4 { + cpu = <&cpu4>; + }; + core5 { + cpu = <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu6>; + }; + core1 { + cpu = <&cpu7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + cpu_off_l: cpu-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010000>; + local-timer-stop; + entry-latency-us = <97>; + exit-latency-us = <252>; + min-residency-us = <6710>; + }; + + cpu_off_m: cpu-off-m { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010000>; + local-timer-stop; + entry-latency-us = <53>; + exit-latency-us = <143>; + min-residency-us = <2120>; + }; + + cpu_cluster_off_l: cpu-cluster-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010001>; + local-timer-stop; + entry-latency-us = <109>; + exit-latency-us = <325>; + min-residency-us = <6710>; + }; + + cpu_cluster_off_m: cpu-cluster-off-m { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010001>; + local-timer-stop; + entry-latency-us = <59>; + exit-latency-us = <188>; + min-residency-us = <2120>; + }; + + cpu_mcusys_off_l: cpu-mcusys-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x02010007>; + local-timer-stop; + entry-latency-us = <1357>; + exit-latency-us = <835>; + min-residency-us = <6710>; + }; + + cpu_mcusys_off_m: cpu-mcusys-off-m { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x02010007>; + local-timer-stop; + entry-latency-us = <1202>; + exit-latency-us = <679>; + min-residency-us = <2120>; + }; + + cpu_system_vcore: cpu-system-vcore { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x020100ff>; + local-timer-stop; + entry-latency-us = <940>; + exit-latency-us = <3500>; + min-residency-us = <35200>; + }; + + cpu_s2idle: cpu-s2idle { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x020180ff>; + local-timer-stop; + entry-latency-us = <10000>; + exit-latency-us = <10000>; + min-residency-us = <4294967295>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_0>; + cache-unified; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_0>; + cache-unified; + }; + + l3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + memory: memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0xC0000000>; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + + performance: performance-controller@11bc10 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + #performance-domain-cells = <1>; + }; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0xc000000 0 0x40000>, /* distributor */ + <0 0xc040000 0 0x200000>; /* redistributor */ + interrupts = ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu6 &cpu7>; + }; + }; + }; + + uart0: serial@11001000 { + compatible = "mediatek,mt8189-uart", "mediatek,mt6577-uart"; + reg = <0 0x11001000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + }; + + ulposc: oscillator-ulposc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <520000000>; + clock-output-names = "ulposc"; + }; + + ulposc3: oscillator-ulposc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "ulposc3"; + }; +};