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Mon, 12 May 2025 05:05:50 -0700 (PDT) From: Linus Walleij Date: Mon, 12 May 2025 14:05:47 +0200 Subject: [PATCH v3 01/12] ARM: dts: bcm6878: Correct UART0 IRQ number Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250512-bcmbca-peripherals-arm-v3-1-86f97ab4326f@linaro.org> References: <20250512-bcmbca-peripherals-arm-v3-0-86f97ab4326f@linaro.org> In-Reply-To: <20250512-bcmbca-peripherals-arm-v3-0-86f97ab4326f@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , William Zhang , Anand Gore , Kursad Oney , Florian Fainelli , =?utf-8?b?UmFmYcWCIE1p?= =?utf-8?b?xYJlY2tp?= , Broadcom internal kernel review list , Olivia Mackall , Ray Jui , Scott Branden , Florian Fainelli Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-crypto@vger.kernel.org, Linus Walleij X-Mailer: b4 0.14.2 According to the vendor file 6878_intr.h the UART0 has IRQ 92, not 32. Assuming this is a copy-and-paste error. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/broadcom/bcm6878.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/broadcom/bcm6878.dtsi b/arch/arm/boot/dts/broadcom/bcm6878.dtsi index 70cf23a65fdb5ac7ed9eabc986f4ebb4df263c43..43eb678e14d04be487af39c9365186b6fb919cf3 100644 --- a/arch/arm/boot/dts/broadcom/bcm6878.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm6878.dtsi @@ -137,7 +137,7 @@ nandcs: nand@0 { uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&uart_clk>, <&uart_clk>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; From patchwork Mon May 12 12:05:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 889497 Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C617292932 for ; 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Mon, 12 May 2025 05:05:54 -0700 (PDT) Received: from [192.168.1.140] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54fc64bf8a3sm1466033e87.189.2025.05.12.05.05.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 May 2025 05:05:53 -0700 (PDT) From: Linus Walleij Date: Mon, 12 May 2025 14:05:49 +0200 Subject: [PATCH v3 03/12] ARM: dts: bcm6846: Add interrupt to RNG Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250512-bcmbca-peripherals-arm-v3-3-86f97ab4326f@linaro.org> References: <20250512-bcmbca-peripherals-arm-v3-0-86f97ab4326f@linaro.org> In-Reply-To: <20250512-bcmbca-peripherals-arm-v3-0-86f97ab4326f@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , William Zhang , Anand Gore , Kursad Oney , Florian Fainelli , =?utf-8?b?UmFmYcWCIE1p?= =?utf-8?b?xYJlY2tp?= , Broadcom internal kernel review list , Olivia Mackall , Ray Jui , Scott Branden , Florian Fainelli Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-crypto@vger.kernel.org, Linus Walleij X-Mailer: b4 0.14.2 The r200 RNG has an interrupt so let's add it. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/broadcom/bcm6846.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/broadcom/bcm6846.dtsi b/arch/arm/boot/dts/broadcom/bcm6846.dtsi index e0e06af3fe891df3c3d8c2005cf1980d33a7762b..f5591a45d2e4ad64d8f95680aea327771825252b 100644 --- a/arch/arm/boot/dts/broadcom/bcm6846.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm6846.dtsi @@ -196,6 +196,7 @@ uart0: serial@640 { rng@b80 { compatible = "brcm,iproc-rng200"; reg = <0xb80 0x28>; + interrupts = ; }; leds: led-controller@800 { From patchwork Mon May 12 12:05:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 889496 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EAC229293D for ; Mon, 12 May 2025 12:05:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 12 May 2025 05:05:57 -0700 (PDT) Received: from [192.168.1.140] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54fc64bf8a3sm1466033e87.189.2025.05.12.05.05.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 May 2025 05:05:56 -0700 (PDT) From: Linus Walleij Date: Mon, 12 May 2025 14:05:51 +0200 Subject: [PATCH v3 05/12] ARM: dts: bcm6878: Add BCMBCA peripherals Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250512-bcmbca-peripherals-arm-v3-5-86f97ab4326f@linaro.org> References: <20250512-bcmbca-peripherals-arm-v3-0-86f97ab4326f@linaro.org> In-Reply-To: <20250512-bcmbca-peripherals-arm-v3-0-86f97ab4326f@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , William Zhang , Anand Gore , Kursad Oney , Florian Fainelli , =?utf-8?b?UmFmYcWCIE1p?= =?utf-8?b?xYJlY2tp?= , Broadcom internal kernel review list , Olivia Mackall , Ray Jui , Scott Branden , Florian Fainelli Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-crypto@vger.kernel.org, Linus Walleij X-Mailer: b4 0.14.2 All the BCMBCA SoCs share a set of peripherals at 0xff800000, albeit at slightly varying memory locations on the bus and with varying IRQ assignments. Add the first and second watchdog, GPIO, RNG, LED and DMA blocks for the BCM6878 based on the vendor files 6878_map_part.h and 6878_intr.h from the "bcmopen-consumer" code drop. This SoC has up to 256 possible GPIOs due to having 8 registers with 32 GPIOs in each available. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/broadcom/bcm6878.dtsi | 118 ++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/arch/arm/boot/dts/broadcom/bcm6878.dtsi b/arch/arm/boot/dts/broadcom/bcm6878.dtsi index 43eb678e14d04be487af39c9365186b6fb919cf3..dd837bf693905736a7b8ef9cfefea8368e6df6ed 100644 --- a/arch/arm/boot/dts/broadcom/bcm6878.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm6878.dtsi @@ -108,6 +108,111 @@ bus@ff800000 { #size-cells = <1>; ranges = <0 0xff800000 0x800000>; + watchdog@480 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x480 0x10>; + }; + + watchdog@4c0 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x4c0 0x10>; + status = "disabled"; + }; + + /* GPIOs 0 .. 31 */ + gpio0: gpio@500 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x500 0x04>, <0x520 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 32 .. 63 */ + gpio1: gpio@504 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x504 0x04>, <0x524 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 64 .. 95 */ + gpio2: gpio@508 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x508 0x04>, <0x528 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 96 .. 127 */ + gpio3: gpio@50c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x50c 0x04>, <0x52c 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 128 .. 159 */ + gpio4: gpio@510 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x510 0x04>, <0x530 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 160 .. 191 */ + gpio5: gpio@514 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x514 0x04>, <0x534 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 192 .. 223 */ + gpio6: gpio@518 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x518 0x04>, <0x538 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 224 .. 255 */ + gpio7: gpio@51c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x51c 0x04>, <0x53c 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + rng@b80 { + compatible = "brcm,iproc-rng200"; + reg = <0xb80 0x28>; + interrupts = ; + }; + + leds: led-controller@700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63138-leds"; + reg = <0x700 0xdc>; + status = "disabled"; + }; + hsspi: spi@1000 { #address-cells = <1>; #size-cells = <0>; @@ -134,6 +239,19 @@ nandcs: nand@0 { }; }; + pl081_dma: dma-controller@11000 { + compatible = "arm,pl081", "arm,primecell"; + // The magic B105F00D info is missing + arm,primecell-periphid = <0x00041081>; + reg = <0x11000 0x1000>; + interrupts = ; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + clocks = <&periph_clk>; + clock-names = "apb_pclk"; + #dma-cells = <2>; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; From patchwork Mon May 12 12:05:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 889495 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B7AB29293D for ; Mon, 12 May 2025 12:06:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747051564; cv=none; b=ZhGUBlkKjzc6Ms93ueMIKOVr/oaxDvhdQO6Q+Rlln1SuSWVNqPTX1ccWt2UJvf0PjS2Axu/a36NBRBFBYl3uUYGUpTkdHGnhjDtEk21TUyBVHEXq3miumVWaMaESEhLdD2F4LYBegqx7TkYHbC4HsRDyiYcJ92gO3WoAkmmOhPI= ARC-Message-Signature: i=1; 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Mon, 12 May 2025 05:05:59 -0700 (PDT) Received: from [192.168.1.140] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54fc64bf8a3sm1466033e87.189.2025.05.12.05.05.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 May 2025 05:05:59 -0700 (PDT) From: Linus Walleij Date: Mon, 12 May 2025 14:05:53 +0200 Subject: [PATCH v3 07/12] ARM: dts: bcm63148: Add BCMBCA peripherals Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250512-bcmbca-peripherals-arm-v3-7-86f97ab4326f@linaro.org> References: <20250512-bcmbca-peripherals-arm-v3-0-86f97ab4326f@linaro.org> In-Reply-To: <20250512-bcmbca-peripherals-arm-v3-0-86f97ab4326f@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , William Zhang , Anand Gore , Kursad Oney , Florian Fainelli , =?utf-8?b?UmFmYcWCIE1p?= =?utf-8?b?xYJlY2tp?= , Broadcom internal kernel review list , Olivia Mackall , Ray Jui , Scott Branden , Florian Fainelli Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-crypto@vger.kernel.org, Linus Walleij X-Mailer: b4 0.14.2 All the BCMBCA SoCs share a set of peripherals at 0xff800000, albeit at slightly varying memory locations on the bus and with varying IRQ assignments. Add the GPIO, RNG and LED and DMA blocks for the BCM63148 based on the vendor files 63148_map_part.h and 63148_intr.h from the "bcmopen-consumer" code drop. This SoC has up to 160 possible GPIOs due to having 5 registers with 32 GPIOs in each available. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/broadcom/bcm63148.dtsi | 64 ++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm/boot/dts/broadcom/bcm63148.dtsi b/arch/arm/boot/dts/broadcom/bcm63148.dtsi index 53703827ee3fe58ead1dbe70536d7293ad842d0c..e071cddb28fc2888b8f408b4bc275290dd135642 100644 --- a/arch/arm/boot/dts/broadcom/bcm63148.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm63148.dtsi @@ -99,6 +99,62 @@ bus@ff800000 { #size-cells = <1>; ranges = <0 0xfffe8000 0x8000>; + /* GPIOs 0 .. 31 */ + gpio0: gpio@100 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x100 0x04>, <0x114 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 32 .. 63 */ + gpio1: gpio@104 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x104 0x04>, <0x118 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 64 .. 95 */ + gpio2: gpio@108 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x108 0x04>, <0x11c 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 96 .. 127 */ + gpio3: gpio@10c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10c 0x04>, <0x120 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 128 .. 159 */ + gpio4: gpio@110 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x110 0x04>, <0x124 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + rng@300 { + compatible = "brcm,iproc-rng200"; + reg = <0x300 0x28>; + interrupts = ; + }; + uart0: serial@600 { compatible = "brcm,bcm6345-uart"; reg = <0x600 0x20>; @@ -108,6 +164,14 @@ uart0: serial@600 { status = "disabled"; }; + leds: led-controller@700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63138-leds"; + reg = <0x700 0xdc>; + status = "disabled"; + }; + hsspi: spi@1000 { #address-cells = <1>; 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Mon, 12 May 2025 05:06:01 -0700 (PDT) From: Linus Walleij Date: Mon, 12 May 2025 14:05:55 +0200 Subject: [PATCH v3 09/12] ARM64: dts: bcm4908: Add BCMBCA peripherals Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250512-bcmbca-peripherals-arm-v3-9-86f97ab4326f@linaro.org> References: <20250512-bcmbca-peripherals-arm-v3-0-86f97ab4326f@linaro.org> In-Reply-To: <20250512-bcmbca-peripherals-arm-v3-0-86f97ab4326f@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , William Zhang , Anand Gore , Kursad Oney , Florian Fainelli , =?utf-8?b?UmFmYcWCIE1p?= =?utf-8?b?xYJlY2tp?= , Broadcom internal kernel review list , Olivia Mackall , Ray Jui , Scott Branden , Florian Fainelli Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-crypto@vger.kernel.org, Linus Walleij X-Mailer: b4 0.14.2 All the BCMBCA SoCs share a set of peripherals at 0xff800000, albeit at slightly varying memory locations on the bus and with varying IRQ assignments. ARM64 SoCs have additional peripherals at 0xff858000, we extend the peripheral bus range to 0x400000 to cover this area. Add the watchdog, remaining GPIO blocks, RNG, and DMA blocks for the BCM4908 based on the vendor files 4908_map_part.h and 4908_intr.h from the "bcmopen-consumer" code drop. This SoC has up to 320 possible GPIOs due to having 10 registers with 32 GPIOs in each available. Signed-off-by: Linus Walleij --- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 116 ++++++++++++++++++++++- 1 file changed, 113 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi index 613ba7ee43d6489ea0f1490d2fccaf90961b2694..3b7595fd4e81d150278816bbe27e08286cde2ff8 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi @@ -323,11 +323,12 @@ pmb: power-controller@2800c0 { }; }; + /* PERF Peripherals */ bus@ff800000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x00 0x00 0xff800000 0x3000>; + ranges = <0x00 0x00 0xff800000 0x400000>; twd: timer-mfd@400 { compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; @@ -348,13 +349,103 @@ watchdog@28 { }; }; - gpio0: gpio-controller@500 { + /* GPIOs 0 .. 31 */ + gpio0: gpio@500 { compatible = "brcm,bcm6345-gpio"; + reg = <0x500 0x04>, <0x528 0x04>; reg-names = "dirout", "dat"; - reg = <0x500 0x28>, <0x528 0x28>; + gpio-controller; + #gpio-cells = <2>; + }; + + /* GPIOs 32 .. 63 */ + gpio1: gpio@504 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x504 0x04>, <0x52c 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 64 .. 95 */ + gpio2: gpio@508 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x508 0x04>, <0x530 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + /* GPIOs 96 .. 127 */ + gpio3: gpio@50c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x50c 0x04>, <0x534 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 128 .. 159 */ + gpio4: gpio@510 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x510 0x04>, <0x538 0x04>; + reg-names = "dirout", "dat"; gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 160 .. 191 */ + gpio5: gpio@514 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x514 0x04>, <0x53c 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 192 .. 223 */ + gpio6: gpio@518 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x518 0x04>, <0x540 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 224 .. 255 */ + gpio7: gpio@51c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x51c 0x04>, <0x544 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 256 .. 287 */ + gpio8: gpio@520 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x520 0x04>, <0x548 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 288 .. 319 */ + gpio9: gpio@524 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x524 0x04>, <0x54c 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; }; pinctrl@560 { @@ -584,6 +675,12 @@ leds: leds@800 { #size-cells = <0>; }; + rng@b80 { + compatible = "brcm,iproc-rng200"; + reg = <0xb80 0x28>; + interrupts = ; + }; + hsspi: spi@1000 { #address-cells = <1>; #size-cells = <0>; @@ -636,6 +733,19 @@ reset-controller@2644 { #reset-cells = <1>; }; }; + + pl081_dma: dma-controller@59000 { + compatible = "arm,pl081", "arm,primecell"; + // The magic B105F00D info is missing + arm,primecell-periphid = <0x00041081>; + reg = <0x59000 0x1000>; + interrupts = ; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + clocks = <&periph_clk>; + clock-names = "apb_pclk"; + #dma-cells = <2>; + }; }; reboot { From patchwork Mon May 12 12:05:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 889493 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C101293B49 for ; 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Mon, 12 May 2025 05:06:04 -0700 (PDT) Received: from [192.168.1.140] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54fc64bf8a3sm1466033e87.189.2025.05.12.05.06.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 May 2025 05:06:04 -0700 (PDT) From: Linus Walleij Date: Mon, 12 May 2025 14:05:57 +0200 Subject: [PATCH v3 11/12] ARM64: dts: bcm6858: Add BCMBCA peripherals Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250512-bcmbca-peripherals-arm-v3-11-86f97ab4326f@linaro.org> References: <20250512-bcmbca-peripherals-arm-v3-0-86f97ab4326f@linaro.org> In-Reply-To: <20250512-bcmbca-peripherals-arm-v3-0-86f97ab4326f@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , William Zhang , Anand Gore , Kursad Oney , Florian Fainelli , =?utf-8?b?UmFmYcWCIE1p?= =?utf-8?b?xYJlY2tp?= , Broadcom internal kernel review list , Olivia Mackall , Ray Jui , Scott Branden , Florian Fainelli Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-crypto@vger.kernel.org, Linus Walleij X-Mailer: b4 0.14.2 All the BCMBCA SoCs share a set of peripherals at 0xff800000, albeit at slightly varying memory locations on the bus and with varying IRQ assignments. ARM64 SoCs have additional peripherals at 0xff858000. Extend the peripheral window range to 0x400000 and add the DMA controller at offset 0x59000. Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA blocks for the BCM6858 based on the vendor files 6858_map_part.h and 6858_intr.h from the "bcmopen-consumer" code drop. This SoC has up to 256 possible GPIOs due to having 8 registers with 32 GPIOs in each available. Signed-off-by: Linus Walleij --- arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi | 119 ++++++++++++++++++++++- 1 file changed, 118 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi index caeaf428dc15db3089bf4dc62c4a272782c22c3f..c105a734a64897e714ed107e0ddccc5eebd415da 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi @@ -111,11 +111,12 @@ gic: interrupt-controller@1000 { }; }; + /* PERF Peripherals */ bus@ff800000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x62000>; + ranges = <0x0 0x0 0xff800000 0x400000>; twd: timer-mfd@400 { compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; @@ -136,6 +137,86 @@ watchdog@28 { }; }; + /* GPIOs 0 .. 31 */ + gpio0: gpio@500 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x500 0x04>, <0x520 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 32 .. 63 */ + gpio1: gpio@504 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x504 0x04>, <0x524 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 64 .. 95 */ + gpio2: gpio@508 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x508 0x04>, <0x528 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 96 .. 127 */ + gpio3: gpio@50c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x50c 0x04>, <0x52c 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 128 .. 159 */ + gpio4: gpio@510 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x510 0x04>, <0x530 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 160 .. 191 */ + gpio5: gpio@514 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x514 0x04>, <0x534 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 192 .. 223 */ + gpio6: gpio@518 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x518 0x04>, <0x538 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 224 .. 255 */ + gpio7: gpio@51c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x51c 0x04>, <0x53c 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + uart0: serial@640 { compatible = "brcm,bcm6345-uart"; reg = <0x640 0x18>; @@ -145,6 +226,29 @@ uart0: serial@640 { status = "disabled"; }; + uart1: serial@660 { + compatible = "brcm,bcm6345-uart"; + reg = <0x660 0x18>; + interrupts = ; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + + leds: led-controller@800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63138-leds"; + reg = <0x800 0xdc>; + status = "disabled"; + }; + + rng@b80 { + compatible = "brcm,iproc-rng200"; + reg = <0xb80 0x28>; + interrupts = ; + }; + hsspi: spi@1000 { #address-cells = <1>; #size-cells = <0>; @@ -170,5 +274,18 @@ nandcs: nand@0 { reg = <0>; }; }; + + pl081_dma: dma-controller@59000 { + compatible = "arm,pl081", "arm,primecell"; + // The magic B105F00D info is missing + arm,primecell-periphid = <0x00041081>; + reg = <0x59000 0x1000>; + interrupts = ; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + clocks = <&periph_clk>; + clock-names = "apb_pclk"; + #dma-cells = <2>; + }; }; };