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Signed-off-by: Sirius Wang Reviewed-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index fa1646bc0bac..05e827076a7f 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -372,6 +372,10 @@ properties: - enum: - mediatek,mt8188-evb - const: mediatek,mt8188 + - items: + - enum: + - mediatek,mt8189-evb + - const: mediatek,mt8189 - description: Google Hayato items: - const: google,hayato-rev1 From patchwork Mon May 12 11:53:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2lyaXVzIFdhbmcgKOeOi+eak+aYsSk=?= X-Patchwork-Id: 889605 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0554293460; Mon, 12 May 2025 11:54:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747050864; cv=none; b=pYvkzHu7/apiz9ccAqR14mmxd1zqLVKVVWg2cdwjj/qZZ593+BJIVInkZkTj/LkXu2yHczCJe4/hRCQovKnydFQeecMRJ+WOF+VGRhJUyA1Z50iSYAWtohPad39DELxwaQNakG6pt/A7pnW8t4mvbBnIc3irVIevZen4Ri8arYI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747050864; c=relaxed/simple; bh=nK7PIqlBFsQIMmKook3MdxZKJmWErLmya08ExpgM1ko=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=UsMSSimapEkON8vXlWuVqWLnkYrJR/cLwvECg0K3Py7AnPvGvwtcwH3htd0pPdJe3wPhGakBzIUaKzqiS84EafMLGR8N4r3I7p09nU3PcOrq3d/dI3NeIt6GenxWTztHI3i8auTuaDPEkQv7XaolQrCjXNbLYsDoTSpyCpCsa9c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=IVTrF/B7; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="IVTrF/B7" X-UUID: d372e1442f2711f082f7f7ac98dee637-20250512 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=JzR3NkQ2NJIx5O5Q119lnGbLJrIVpzi/qat5rrANbkI=; b=IVTrF/B7thVJkBz8F2BMbvyLT+n1LbrWLKwT24nTCGGeVHd17/3I2e90rnlmFHc6WSH42G7tD5KJLVMB5adtNESP5i2ZWKOFNYsgouJiqQGcKWAzgBmWlqbn1jGpaP9cKHCuqeiEovT8Xsg48CqzL8+OCkdFMe+n5EiCgaOktrk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1, REQID:03d3eb28-d78a-4993-b21e-405e5dca1fbc, IP:0, UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:0ef645f, CLOUDID:f0b09db7-5e6b-4d0f-a080-a5e9cb36bea6, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: d372e1442f2711f082f7f7ac98dee637-20250512 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 590835690; Mon, 12 May 2025 19:54:14 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 12 May 2025 19:54:11 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 12 May 2025 19:54:11 +0800 From: Sirius Wang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Jiri Slaby , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang CC: , , , , , , , Sirius Wang , Conor Dooley Subject: [PATCH v3 2/3] dt-bindings: serial: mediatek, uart: Add compatible for MT8189 Date: Mon, 12 May 2025 19:53:49 +0800 Message-ID: <20250512115355.923342-3-sirius.wang@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250512115355.923342-1-sirius.wang@mediatek.com> References: <20250512115355.923342-1-sirius.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add compatible string for serial on MT8189 SoC. Signed-off-by: Sirius Wang Reviewed-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley --- Documentation/devicetree/bindings/serial/mediatek,uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml index c55d9a0efa19..fabc22d47cb3 100644 --- a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml +++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml @@ -46,6 +46,7 @@ properties: - mediatek,mt8183-uart - mediatek,mt8186-uart - mediatek,mt8188-uart + - mediatek,mt8189-uart - mediatek,mt8192-uart - mediatek,mt8195-uart - mediatek,mt8365-uart From patchwork Mon May 12 11:53:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2lyaXVzIFdhbmcgKOeOi+eak+aYsSk=?= X-Patchwork-Id: 889830 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E222329375A; 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Mon, 12 May 2025 19:54:18 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 12 May 2025 19:54:15 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 12 May 2025 19:54:15 +0800 From: Sirius Wang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Jiri Slaby , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang CC: , , , , , , , Sirius Wang Subject: [PATCH v3 3/3] arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile Date: Mon, 12 May 2025 19:53:50 +0800 Message-ID: <20250512115355.923342-4-sirius.wang@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250512115355.923342-1-sirius.wang@mediatek.com> References: <20250512115355.923342-1-sirius.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add mt8189 dts evaluation board and Mafefile Signed-off-by: Sirius Wang --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8189-evb.dts | 20 + arch/arm64/boot/dts/mediatek/mt8189.dtsi | 427 ++++++++++++++++++++ 3 files changed, 448 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 3aa06476c6c0..ad2ac9e1bb79 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8189-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts new file mode 100644 index 000000000000..e5d9ce1b8e61 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Sirius Wang + */ +/dts-v1/; +#include "mt8189.dtsi" + +/ { + model = "MediaTek MT8189 evaluation board"; + compatible = "mediatek,mt8189-evb", "mediatek,mt8189"; + + chosen: chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts/mediatek/mt8189.dtsi new file mode 100644 index 000000000000..f8794c6fba7b --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi @@ -0,0 +1,427 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 MediaTek Inc. + */ + +#include +#include + +/ { + compatible = "mediatek,mt8189"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + clk32k: oscillator-clk32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "clk32k"; + }; + + clk13m: oscillator-clk13m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-mult = <1>; + clock-div = <2>; + clock-output-names = "clk13m"; + }; + + clk26m: oscillator-clk26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk104m: oscillator-clk104m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-mult = <4>; + clock-div = <1>; + clock-output-names = "clk104m"; + }; + + ulposc: oscillator-ulposc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <520000000>; + clock-output-names = "ulposc"; + }; + + ulposc3: oscillator-ulposc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "ulposc3"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x000>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <742>; + cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>, + <&cpu_system_vcore>, <&cpu_s2idle>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; + #cooling-cells = <2>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <742>; + cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>, + <&cpu_system_vcore>, <&cpu_s2idle>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; + #cooling-cells = <2>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <742>; + cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>, + <&cpu_system_vcore>, <&cpu_s2idle>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; + #cooling-cells = <2>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <742>; + cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>, + <&cpu_system_vcore>, <&cpu_s2idle>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; + #cooling-cells = <2>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x400>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <742>; + cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>, + <&cpu_system_vcore>, <&cpu_s2idle>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; + #cooling-cells = <2>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x500>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <742>; + cpu-idle-states = <&cpu_off_l>, <&cpu_cluster_off_l>, <&cpu_mcusys_off_l>, + <&cpu_system_vcore>, <&cpu_s2idle>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; + #cooling-cells = <2>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x600>; + enable-method = "psci"; + clock-frequency = <3000000000>; + capacity-dmips-mhz = <958>; + cpu-idle-states = <&cpu_off_b>, <&cpu_cluster_off_b>, <&cpu_mcusys_off_b>, + <&cpu_system_vcore>, <&cpu_s2idle>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; + #cooling-cells = <2>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x700>; + enable-method = "psci"; + clock-frequency = <3000000000>; + capacity-dmips-mhz = <958>; + cpu-idle-states = <&cpu_off_b>, <&cpu_cluster_off_b>, <&cpu_mcusys_off_b>, + <&cpu_system_vcore>, <&cpu_s2idle>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; + #cooling-cells = <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + core4 { + cpu = <&cpu4>; + }; + core5 { + cpu = <&cpu5>; + }; + core6 { + cpu = <&cpu6>; + }; + core7 { + cpu = <&cpu7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + cpu_off_l: cpu-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010000>; + local-timer-stop; + entry-latency-us = <97>; + exit-latency-us = <252>; + min-residency-us = <6710>; + }; + + cpu_off_b: cpu-off-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010000>; + local-timer-stop; + entry-latency-us = <53>; + exit-latency-us = <143>; + min-residency-us = <2120>; + }; + + cpu_cluster_off_l: cpu-cluster-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010001>; + local-timer-stop; + entry-latency-us = <109>; + exit-latency-us = <325>; + min-residency-us = <6710>; + }; + + cpu_cluster_off_b: cpu-cluster-off-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010001>; + local-timer-stop; + entry-latency-us = <59>; + exit-latency-us = <188>; + min-residency-us = <2120>; + }; + + cpu_mcusys_off_l: cpu-mcusys-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x02010007>; + local-timer-stop; + entry-latency-us = <1357>; + exit-latency-us = <835>; + min-residency-us = <6710>; + }; + + cpu_mcusys_off_b: cpu-mcusys-off-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x02010007>; + local-timer-stop; + entry-latency-us = <1202>; + exit-latency-us = <679>; + min-residency-us = <2120>; + }; + + cpu_system_vcore: cpu-system-vcore { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x020100ff>; + local-timer-stop; + entry-latency-us = <940>; + exit-latency-us = <3500>; + min-residency-us = <35200>; + }; + + cpu_s2idle: cpu-s2idle { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x020180ff>; + local-timer-stop; + entry-latency-us = <10000>; + exit-latency-us = <10000>; + min-residency-us = <4294967295>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_0>; + cache-unified; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_0>; + cache-unified; + }; + + l3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; + }; + + memory: memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0xC0000000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + + performance: performance-controller@11bc10 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + #performance-domain-cells = <1>; + }; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0xc000000 0 0x40000>, /* distributor */ + <0 0xc040000 0 0x200000>; /* redistributor */ + interrupts = ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu6 &cpu7>; + }; + }; + }; + + uart0: serial@11001000 { + compatible = "mediatek,mt8189-uart", "mediatek,mt6577-uart"; + reg = <0 0x11001000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + }; +};