From patchwork Wed May 14 07:01:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 890011 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF87B204096; Wed, 14 May 2025 07:01:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747206102; cv=none; b=P+EM+EfH/9WqiXuL6mw5cQYdhynY8e9Y1wbPe5c/5yHzlXS+3zTEcdVbA3Tf6igUL282uCCD2MnTxCEQMNikNFscS6WWiRkt2BKHBGWwT54nNoT45JclEjEOvdcvau0n/2mCSjAU1LznFnSk1qpWFfiGFHfrgVxNdQ36keDDor8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747206102; c=relaxed/simple; bh=RhXaG6D10XuprrM2uwXZ+yryGaiW6qQjUHpNKKnNco4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FsbS1hTJumXwrbUnKbSxC0fNZkqObAD3vD2kdoEwLux2rigyyOVjhyZKHNv8No4E+GCyeJL30tbqAYIRESO0QVh7SiriCcRXQO2fj5PTcrZv0CtaiqxOJOU/hGJHEmqrXzPV80Z2e7NtuXYER+we5VbJUpx7bTIiFgjuRJNRXY4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eHwvoObs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eHwvoObs" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4C6A1C4CEEB; Wed, 14 May 2025 07:01:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747206102; bh=RhXaG6D10XuprrM2uwXZ+yryGaiW6qQjUHpNKKnNco4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=eHwvoObsxQY3MpoRSkhPWgLKhUksDEdk1jl8Wa8VmcNU26EGdaEst84a7hA8auT8/ SYLGSnnKnCZhzRpf24kMjECzayANSmpWVojht96wWY1xJe8maAq9edikem9yB8vpVn tgR9NxofW8wTLTeT64O4qACZNZZhg1r78MtvrCoWVQ3Q7PM3ELH+qvd/owQUIT7fo8 55OXG/SV6zpaIl+YnHCJyOm9L6Nsw1sTU3CiKkIlcXGK2Oiiy2napiGFGvrnH530UK yqy9TrePmCrkTKCQPBfqmkko9YRzDnr4ZX1yPb3NIlAcv79HZm1lUMuoiAybuf/rQq k37yTgs4Qhx5Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C497C3ABDE; Wed, 14 May 2025 07:01:42 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 14 May 2025 15:01:30 +0800 Subject: [PATCH 3/8] dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S6 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-s6-s7-pinctrl-v1-3-39d368cad250@amlogic.com> References: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> In-Reply-To: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747206100; l=777; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=SGs48wURMjraERop2ENTKoLj76g7oJ3ublU0QekYvzE=; b=rEqYoaagVtWnwccz+GPoTSGpAh94WJcq+4gnR1fgKV7VHyJeoiV4IoNKYrTVI+RfssOUFjmUS xZt7xPptmWPBGTOn3Rauo5rXQh3GVD6b7ou5ya83Rk7YLBhUHLgUG2I X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Update dt-binding document for pinctrl of Amlogic S6 SoC. Signed-off-by: Xianwei Zhao --- Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml index 96a7c5646c13..61a4685f9748 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -17,6 +17,7 @@ properties: oneOf: - enum: - amlogic,pinctrl-a4 + - amlogic,pinctrl-s6 - amlogic,pinctrl-s7 - items: - enum: From patchwork Wed May 14 07:01:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 890012 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80B161FCFFC; Wed, 14 May 2025 07:01:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747206102; cv=none; b=MJYLH8EOdx7rMd46ED5XhY4fnb1uU7/zMVLSrbRREu8zBYj1fSw73n3EKCT8HIpOfwC+Tc8KVCXkYXPYWCWeWv2hrhRDd5CpebJSIeSVj2P1O1iOVa3BbsV2dDpR3s7v66ct3YNA9YrJo3FO+ChAeOUZLQKaC+oOKW9LzKI5Cvc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747206102; c=relaxed/simple; bh=urScH87aRUYYRU4uMH/UcgcwqDXNvfnULC466CYiu1A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mGWrlicG8UdSkYLOJerFRlRjY5XDBbRgDLFqFDluF4SBNL4gfRXYjpXLMXtQEdnWdNXGujp1Gk0kqzp7T+43DSdx9++T9YAtdg5a724wV+SuSCcN3d8EytwY17bSqgFDQTjpIwPaubeIE1AewWuRfHuozwOwhTXOKCbk9LaJDTQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UNcD5uGQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UNcD5uGQ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 54D4FC4CEF3; Wed, 14 May 2025 07:01:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747206102; bh=urScH87aRUYYRU4uMH/UcgcwqDXNvfnULC466CYiu1A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=UNcD5uGQI9/jVyg8Di29D94BA3lKhnw11VkC391nr75+adpIkN071VF/MsE2+vrA0 +3vu8f0btFQcB+KRwbLqMN03cxrGnEwzPK0w0rSh30VztddhiA73C5rgTxVGTDN0uu OEBbCNDG5H+UDkGePv5de6fRQKWCUDctFhz+E/laIG1sBCTfo9sWn6MLf/1bo5J8uz pxsHx9nqDkU/hJSyVo4isAaxf3+J5Fp+63HutVj2ONwrGePxK0SPD2ht8OGWPNMXP3 PrKw97EuTruCSAvf39BfyK//xCTp1rV4GQdD4S34qIW80Y/Ra37Mo6BEzKGwmIx3+r x1of5bS0L+Ypg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AF4AC3ABDC; Wed, 14 May 2025 07:01:42 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 14 May 2025 15:01:31 +0800 Subject: [PATCH 4/8] pinctrl: meson: a4: remove special data processing Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-s6-s7-pinctrl-v1-4-39d368cad250@amlogic.com> References: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> In-Reply-To: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747206100; l=1982; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=FRMEmxN5zjpQVQOxtUKSm3GQm/lC+q2P8YsijCrDdRM=; b=+6hLKSp0TODk9+4jPyX0PxesuamsmX2QcK+x5esdSc3SYblzTFKWXatB/oAB2U0+Tfv5MEg6X ZWVfF23ZwRGA4BhIn08ObpMSlwTK3z44oHVT+iB42n7EHzbE+Qh2xO9 X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao According to the data specifications of Amlogic's existing SoCs, the function register offset and the bit offset are the same value among various chips. Therefore, general processing can be carried out without the need for private data modification. Drop special data processing. Signed-off-by: Xianwei Zhao --- drivers/pinctrl/meson/pinctrl-amlogic-a4.c | 33 +++--------------------------- 1 file changed, 3 insertions(+), 30 deletions(-) diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c index a76f266b4b94..90d4d10ca10b 100644 --- a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c +++ b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c @@ -50,15 +50,8 @@ struct aml_pio_control { u32 bit_offset[AML_NUM_REG]; }; -struct aml_reg_bit { - u32 bank_id; - u32 reg_offs[AML_NUM_REG]; - u32 bit_offs[AML_NUM_REG]; -}; - struct aml_pctl_data { unsigned int number; - struct aml_reg_bit rb_offs[]; }; struct aml_pmx_func { @@ -843,31 +836,11 @@ static const struct gpio_chip aml_gpio_template = { static void init_bank_register_bit(struct aml_pinctrl *info, struct aml_gpio_bank *bank) { - const struct aml_pctl_data *data = info->data; - const struct aml_reg_bit *aml_rb; - bool def_offs = true; int i; - if (data) { - for (i = 0; i < data->number; i++) { - aml_rb = &data->rb_offs[i]; - if (bank->bank_id == aml_rb->bank_id) { - def_offs = false; - break; - } - } - } - - if (def_offs) { - for (i = 0; i < AML_NUM_REG; i++) { - bank->pc.reg_offset[i] = aml_def_regoffs[i]; - bank->pc.bit_offset[i] = 0; - } - } else { - for (i = 0; i < AML_NUM_REG; i++) { - bank->pc.reg_offset[i] = aml_rb->reg_offs[i]; - bank->pc.bit_offset[i] = aml_rb->bit_offs[i]; - } + for (i = 0; i < AML_NUM_REG; i++) { + bank->pc.reg_offset[i] = aml_def_regoffs[i]; + bank->pc.bit_offset[i] = 0; } } From patchwork Wed May 14 07:01:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 890010 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5AB6205501; Wed, 14 May 2025 07:01:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 14 May 2025 07:01:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747206102; bh=XxBBe3spuxNIwNvzGd15V0aP4uoAqHQtCEDW4+0F0fE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=PuL07YMIvLIcwvYaA82Pg+UT7vYgVvWmFPtRDJB0ZsL+bq4rYbG88KIvw/D4TAh7L 9Drjqjhv1kGP9PudPDctsGi7jo372Z8kGZ6tHkfh45/9FR7VlOuvFyqK6Nu6017ljl t5YdPvN/E8Z9nnMWNKeysBdP+ASWolBGdAkckZ8nWxu4GGkNIi4K92eam13bdWovYk KS9lB5E2OvjCcoGn4av9/uqv58vnKcrHJphu81z+J8nzZh7yQ/tBm+PadS6Q00dl+H fWiZbyB9J4dlcbGlGOR5NEgraqfOa+3rJmPjr4P3AHQEFq5ajd5A6rAUrkPNJbyxPk jbI+urSWBlSgw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 654FFC3ABDD; Wed, 14 May 2025 07:01:42 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 14 May 2025 15:01:33 +0800 Subject: [PATCH 6/8] dts: arm64: amlogic: add S7 pinctrl node Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-s6-s7-pinctrl-v1-6-39d368cad250@amlogic.com> References: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> In-Reply-To: <20250514-s6-s7-pinctrl-v1-0-39d368cad250@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1747206100; l=3124; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=BWdYQqBMaY6QH+w4v+ycYDJAgq8chiBLXYLDSukgN2o=; b=+Ojibt0W9PyMDMcmm+oqePAvJGE6pbyxpns8nJEEzkxJkF5VaeXtMu78lrbksG/xg48gTpqxy NZOAnWHK9uWCvY8S0ChDP7W6uFDlWVeqLO5AQ9CZBpt+/B+MrcC2Txu X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add pinctrl device to support Amlogic S7. Signed-off-by: Xianwei Zhao --- arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 81 +++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi index f0c172681bd1..924f10aff269 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { cpus { @@ -94,6 +95,86 @@ uart_b: serial@7a000 { clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; + + periphs_pinctrl: pinctrl { + compatible = "amlogic,pinctrl-s7"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>; + + gpioz: gpio@c0 { + reg = <0 0xc0 0 0x20>, <0 0x18 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 13>; + }; + + gpiox: gpio@100 { + reg = <0 0x100 0 0x30>, <0 0xc 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; + }; + + gpioh: gpio@140 { + reg = <0 0x140 0 0x20>, <0 0x2c 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 12>; + }; + + gpiod: gpio@180 { + reg = <0 0x180 0 0x20>, <0 0x40 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 12>; + }; + + gpioe: gpio@1c0 { + reg = <0 0x1c0 0 0x20>, <0 0x48 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>; + }; + + gpioc: gpio@200 { + reg = <0 0x200 0 0x20>, <0 0x24 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>; + }; + + gpiob: gpio@240 { + reg = <0 0x240 0 0x20>, <0 0x0 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; + }; + + test_n: gpio@2c0 { + reg = <0 0x2c0 0 0x20>; + reg-names = "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = + <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; + }; + + gpiocc: gpio@300 { + reg = <0 0x300 0 0x20>, <0 0x14 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; + }; + }; }; }; }; From patchwork Wed May 14 07:01:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 890008 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A8F02153EA; Wed, 14 May 2025 07:01:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=ed25519-sha256; t=1747206100; l=3610; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=LQtEhTH+4eGkcgIF+Vwy2luHuUbtEoQ8YiYPmKbSysk=; b=S8+ebZFd/3aLdScnhUNT2oKPoPi/XIvUCU86CBgbhCRKe7b7J6FzLOMCx5QjOuvMj9DIUAUUw Lz+sz4JJ1dwBZz+LtWhw6/woTdNSztnNVqS3qabFwUDOx1uSBwibmHm X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add pinctrl device to support Amlogic S6. Signed-off-by: Xianwei Zhao --- arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi | 97 +++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi index a8c90245c42a..5324079808c4 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { cpus { #address-cells = <2>; @@ -92,6 +93,102 @@ uart_b: serial@7a000 { clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; + + periphs_pinctrl: pinctrl { + compatible = "amlogic,pinctrl-s6"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>; + + gpioz: gpio@c0 { + reg = <0 0xc0 0 0x20>, <0 0x18 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 16>; + }; + + gpiox: gpio@100 { + reg = <0 0x100 0 0x30>, <0 0xc 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; + }; + + gpioh: gpio@140 { + reg = <0 0x140 0 0x20>, <0 0x2c 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 9>; + }; + + gpiod: gpio@180 { + reg = <0 0x180 0 0x20>, <0 0x8 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 7>; + }; + + gpiof: gpio@1a0 { + reg = <0 0x1a0 0 0x20>, <0 0x20 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_F<<8) 5>; + }; + + gpioe: gpio@1c0 { + reg = <0 0x1c0 0 0x20>, <0 0x48 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 3>; + }; + + gpioc: gpio@200 { + reg = <0 0x200 0 0x20>, <0 0x24 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>; + }; + + gpiob: gpio@240 { + reg = <0 0x240 0 0x20>, <0 0x0 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; + }; + + gpioa: gpio@280 { + reg = <0 0x280 0 0x20>, <0 0x40 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_A<<8) 16>; + }; + + test_n: gpio@2c0 { + reg = <0 0x2c0 0 0x20>; + reg-names = "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = + <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; + }; + + gpiocc: gpio@300 { + reg = <0 0x300 0 0x20>, <0 0x14 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; + }; + }; }; }; };