From patchwork Wed May 14 12:04:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 890092 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD9AB224AED; Wed, 14 May 2025 12:04:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747224276; cv=none; b=uwVGEnOCIRUXNxfLByIjAAybs1B7Ad+GZGyqSWGrID5dqLiA5pPeb5UFFrdLeq18M1SmKFRvytei/kSGZUVfrSPgmx53Ry0vt0K0TbiKe40MApNHkwHpp0tfHoHu/xScxbZCbhJ9s+FQh+hTQQCDNi+5kSMOC7/t5dth7P1D/Pk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747224276; c=relaxed/simple; bh=YbtaSFXvEqscgWdaWU4X/6cPyfGpueE1ti1NCjiITjk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IzphKiFmRORlb9uBHBqqc3mi1HCOy039HG6jvTdsd0N1WJQRX68Fm+R6F0U7o1HHgw80EslKRxKyVVsIzendLtOhiErRY67XSVcZvXmALbtZNJTi/vF4Ohz0aeb2AUD5m/600ygt2/jj6zlscPBeX8OsZdWXzpVqTQW5aYxug28= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AX5r23C4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AX5r23C4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8CF32C4CEE9; Wed, 14 May 2025 12:04:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747224275; bh=YbtaSFXvEqscgWdaWU4X/6cPyfGpueE1ti1NCjiITjk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=AX5r23C4h84VDY7k2SjRXXVS+Ez8UA9sMmjHKvknh/YsUHjn5lqod29mgjJsbJtQ7 SAdgVG59qPvHNp6vQYAVz4h5XhxT3PnblqfAggzF1l3iFbi2CU3xuzdtbRzVzpWbOA pl6iLOMDX7HsbBT7C6z/dIADQurDLxUfxKmn3cG4flN7b0S0tSzDw9Pl30oqswz2Ii XXcWn19jbmjlkZ/CvFywOk3xWDx/RdWeraFhj+ESYuYjPIUjH9sRC9VmTDK3JY61R2 2ppiVJTrkZ5tCrON7EmfNtrKssXefS5HfvB+4Qax1s/otsZ/2BRaZZtVOa3zfR/r+5 Y1dCNCa2VmeJQ== From: Roger Quadros Date: Wed, 14 May 2025 15:04:22 +0300 Subject: [PATCH net-next v4 2/9] net: ethernet: ti: cpsw_ale: return ALE index in cpsw_ale_add_vlan() Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-am65-cpsw-rx-class-v4-2-5202d8119241@kernel.org> References: <20250514-am65-cpsw-rx-class-v4-0-5202d8119241@kernel.org> In-Reply-To: <20250514-am65-cpsw-rx-class-v4-0-5202d8119241@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2474; i=rogerq@kernel.org; h=from:subject:message-id; bh=YbtaSFXvEqscgWdaWU4X/6cPyfGpueE1ti1NCjiITjk=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoJIbIi6cIbsAzjH6bHTkh9BchbPkP1lpLK28JF TUjeFraD92JAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaCSGyAAKCRDSWmvTvnYw k5ibD/9y2eBWVHqD5RH5Jmf8Uy2QBH00IA1gQh4M+S9ctcN8VlYe6r7lmLuforULZsBVoyOBi8m ocv0YyLPZfdoIP6oHW51L1bvKkG7lgkGq6wv5mjt7pjQAKum2C/I24Um4EbbwMd1eN+ihINSUJg rIzCYKXhV4WkwLoElQHHFPKHAGFSUSkKCP5mxW1K2mnFoqCDk9toAxgRK/i/TPdoi/HjHXGNSf3 8gxoQ4hMT3XyIgz17/LceAJgUr66Y+ilvT/iIvZrsc4+Ynm1gQfC+9cREgPhAnWzN3lXZ3SkH06 OIl1I8prcT92h0cFD1BdXMs7v9IZ/em/ZPmzXxaTY7zD6gSOBtdqQ28GQ90WqYCrzhOMbgwD6uq aVRaEmqS3Ri7Q0dUBRomDmNA71osD2ow123Jt64gaE0kSIrickQ3nW26nxWPfamv5isr0VPtK4G G3Oc4XIab3pgT7sH3aMjFpQ7gSeBA4Mbcx7yqxVHUlqEdKRrXoIvUFNkIAaMPAgEEVnLZPDr7mg lNb2bIftsSICzfFNA/Dk3m2joXvQcdJ5Sznw707ga50VDEuswb/+Bl34CVLc6suWGlr46aMq5/G ZuY2Bfu7N+qzRm3ZzNbX54+HgYRrsD4Z0HaVCtXy+ZtlkhCNGDh6smIQA2yZs8zU7cAbEwz6Sgc WGFlbbBjz2ObO5Q== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Policer helpers will be interested to know what ALE index was used for the added VLAN entry. So return the ALE index instead of zero on success. Modify existing users to check for less than zero as error case. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw.c | 2 +- drivers/net/ethernet/ti/cpsw_ale.c | 6 +++--- drivers/net/ethernet/ti/cpsw_new.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index a984b7d84e5e..2d23cba557f3 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -1026,7 +1026,7 @@ static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask, unreg_mcast_mask); - if (ret != 0) + if (ret < 0) return ret; ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 7bb63aad7724..0bdc95552410 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -680,7 +680,7 @@ int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag, return -ENOMEM; cpsw_ale_write(ale, idx, ale_entry); - return 0; + return idx; } static void cpsw_ale_vlan_del_modify_int(struct cpsw_ale *ale, u32 *ale_entry, @@ -803,14 +803,14 @@ int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, ret = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members, reg_mcast_members, unreg_mcast_members); - if (ret) { + if (ret < 0) { dev_err(ale->params.dev, "Unable to add vlan\n"); return ret; } dev_dbg(ale->params.dev, "port mask 0x%x untag 0x%x\n", vlan_members, untag_mask); - return ret; + return 0; } void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, diff --git a/drivers/net/ethernet/ti/cpsw_new.c b/drivers/net/ethernet/ti/cpsw_new.c index 5b5b52e4e7a7..1516171352cd 100644 --- a/drivers/net/ethernet/ti/cpsw_new.c +++ b/drivers/net/ethernet/ti/cpsw_new.c @@ -417,7 +417,7 @@ static int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask, unreg_mcast_mask); - if (ret != 0) + if (ret < 0) return ret; ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, From patchwork Wed May 14 12:04:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 890091 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68EE527A45A; Wed, 14 May 2025 12:04:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747224282; cv=none; b=MvxOeNYKttXSyg1o86CYWMvUjo/bzwuXfcYzBab/QbGLKybcUf8m2vvmamgVvlrrSkRkr+pFC4M77Lacp74Tw14/LG4wIW1z3jqQteQo0VdSjN54VDZSwhzX84ztYgXMsoktwDBH+yEBNQ828EmMkL1WDwfcC3Pow2/koAxDVFg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747224282; c=relaxed/simple; bh=7wsQp+uaWY2u0ja4R/dpHDQPnssNtRTBw5npmaUzg0A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=foxgmZcNASBwJ//7KX4eD5RspEWz6JfIPk0YZIY4x59Cc+0QhbYm77NOx/RehzOQsHFwKJHb0HShLHBLCiVPgeeOLFRQtJB5XYgTtTYYNTGTj7Fj78k5kGLSv72yxDVB2UZRLh9WvnSLDp8tZY9GuQlcsxukIzVhhHvLUpU4Jf4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MOHchC2y; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MOHchC2y" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 13872C4CEEF; Wed, 14 May 2025 12:04:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747224281; bh=7wsQp+uaWY2u0ja4R/dpHDQPnssNtRTBw5npmaUzg0A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MOHchC2yoKnD6N2/T8ls9UgCI2vvVGk02/h2HpJoaDcdsmiFsaPQS3AocwqjQP+Sn 6d5Y3BqbZ9sUXIILTpVLEqCaZ0alaz5IK0zoqBPvfpd9zTdyg95IQMNVWm7AnzFWfd AG8vEgXRd7SsyzvAftKg5hcev9Hy/sPFV4qP4K533NVDh3kQp6mRTAuyFhF+q11QQ9 +nSVqXcIKPWu61d80tyRH2h6eYz/n9dRZCz15O4Gu251vv4w0sZs9dvvStJuNeLl4w GxXRootyqVQjr7+Jz13adhRfDFJS4C5z9gWL6G6zc9vGYJGtWUj8bEAe9XUCU7fgjh ELrX2p1PivJcw== From: Roger Quadros Date: Wed, 14 May 2025 15:04:24 +0300 Subject: [PATCH net-next v4 4/9] net: ethernet: ti: cpsw_ale: return ALE index in cpsw_ale_add_ucast() Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-am65-cpsw-rx-class-v4-4-5202d8119241@kernel.org> References: <20250514-am65-cpsw-rx-class-v4-0-5202d8119241@kernel.org> In-Reply-To: <20250514-am65-cpsw-rx-class-v4-0-5202d8119241@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1944; i=rogerq@kernel.org; h=from:subject:message-id; bh=7wsQp+uaWY2u0ja4R/dpHDQPnssNtRTBw5npmaUzg0A=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoJIbJOP4nWFsmWqWu4CgyBKC37Z3H89P3rSEyn q7oyxLVRu6JAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaCSGyQAKCRDSWmvTvnYw kzlbD/4zEnd8HDvHkxxm3C1gkgZpOf4MX37wW+nePovZhMGLQJbo7STPxvHWGczCIQNnrUXzR8o A+PT/KWBLMwgDRd3NhwTOewKTft/s/5tos8fM1+R9kWZ4G9KtOZX1dpcTuP04W2y8zC8PPEVyDE pQ7ph+VAQ4PaOv7dv+tZgorE9lk8uttDwRLetqot8rXmj34OpbufIt7L4R3gMApHv5z5Snnz5Fw LHTsSzBy5JS3QI0Eqf02Zg/hcJ9z2/U2MWe/bdWCgd6usBNpQrd6AYNumstL1CGMgSZqDsozhR7 hzs5Pe2oeKa6PXK/L7SbTvwxr5UbOwbzrIKGi8/RQAeZsrNXUfjQBp1RF+oniqanB6SUIyOodCk Fu79MPtpFIUzo5xepPpw0Vn7g1aMWgz/DYpUh/C2MEgA4dnDiU8O9grjuGhvXJ0rTUliruK9IQR rPlQ2eiDiMLmc9QILZea5FPq72vAPenGunPBsoqUX4e/bmiTFc6cjZKL/4OJ0zySrXnAyU7qJBD WBMlxz3oLIAHn67+SzxmahFmbsoS12xEx2LcsqVzVci41+Ay+ShuD/h4PkDEfjwgiaK7NZ5bfCr s7oKPkouR182BmjAu7FVOdRZI5AXaSd5hRdohsnxRa5wsH9sbNvCL03U2uY1Iv2Da3v5uaZiO4Y KLqOrquaC3ipXSw== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Policer helpers will need to know what ALE index was used for the added unicast entry. So return the ALE index instead of zero on success. Modify existing users to check for less than zero as error case. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw.c | 2 +- drivers/net/ethernet/ti/cpsw_ale.c | 2 +- drivers/net/ethernet/ti/cpsw_new.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 2d23cba557f3..d1abd2fb63c9 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -1031,7 +1031,7 @@ static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, ALE_VLAN, vid); - if (ret != 0) + if (ret < 0) goto clean_vid; ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 952444b0c436..74dc431f1c1b 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -534,7 +534,7 @@ int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port, return -ENOMEM; cpsw_ale_write(ale, idx, ale_entry); - return 0; + return idx; } int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port, diff --git a/drivers/net/ethernet/ti/cpsw_new.c b/drivers/net/ethernet/ti/cpsw_new.c index 1516171352cd..944fa3db94a2 100644 --- a/drivers/net/ethernet/ti/cpsw_new.c +++ b/drivers/net/ethernet/ti/cpsw_new.c @@ -422,7 +422,7 @@ static int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM, ALE_VLAN, vid); - if (ret != 0) + if (ret < 0) goto clean_vid; ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast, From patchwork Wed May 14 12:04:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 890090 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F351327B4E5; Wed, 14 May 2025 12:04:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747224289; cv=none; b=Jw6kFqwE/Xtm+LFVvYud7RePQ6CTOSOirtp0N3lx//USQp0yDF0OXe/98OyrFu+/T7o97UbJB08HX25CHkG6phQ5l8csstDd3sHiix8wN9/Q1THVQNxmITtw4DMC16YEneJKqoEP6p/I7GZGckBj9WjTm+EoLvfacThjhJsitQs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747224289; c=relaxed/simple; bh=yvDolz4DU7x4F3IPiMMAYL9Zyt+CPJcn+6QaEzC3KRo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jJPm2BLyUydJvYItU/Cs6Dl4ni4xDIhKhHe29D3cBb57xxnahwxlrGaqqCSCKjgLT0uo/8uBSHETdAfTeBua73Aq15fDgwaMu2JmNz+VnzVDJmy6X3ffZjLid/QNFBHOMzuq8deBl4cCKp6TlozZ47pNH9tL/B+sbAuwPj4+U7k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=r0PE+S6v; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="r0PE+S6v" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 94939C4CEEF; Wed, 14 May 2025 12:04:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747224288; bh=yvDolz4DU7x4F3IPiMMAYL9Zyt+CPJcn+6QaEzC3KRo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=r0PE+S6vuBKzs5fDzleQptKCho+npyRSCvmk+Pmiged3MUVz9IfoX1/TuJjuNc/SN PQ3YEQYaPuZmNBxZ6qopk549LBp5hx23FS74jrj3fkQgCCHOijlfaDr0xGalbnFSl4 5y858WfBJsa5p8HQSj9yLSXVZU+Wj/lJwSoTzyCbodKUt/ZA347iAaXDFXPa6kbtjS ypc006PJzXdbcmS+5J75B0kWmk2AKt8QFXGGGfnoBQjKqAHZcTssCvTuuxe2Se7f88 FbOJnM/G/bQ9sH0bIRj6774bPGDcmWiua7eMyNV//V/Ds1ek32a5m9e3DsDtwhUZ9M LZV7cWA20sdxw== From: Roger Quadros Date: Wed, 14 May 2025 15:04:26 +0300 Subject: [PATCH net-next v4 6/9] net: ethernet: ti: cpsw_ale: add cpsw_ale_policer_set/clr_entry() Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-am65-cpsw-rx-class-v4-6-5202d8119241@kernel.org> References: <20250514-am65-cpsw-rx-class-v4-0-5202d8119241@kernel.org> In-Reply-To: <20250514-am65-cpsw-rx-class-v4-0-5202d8119241@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4792; i=rogerq@kernel.org; h=from:subject:message-id; bh=yvDolz4DU7x4F3IPiMMAYL9Zyt+CPJcn+6QaEzC3KRo=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoJIbJBiCvNhC78EjKplosWGUYtbOZVUn/ftNmX K0vHPtTQ3iJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaCSGyQAKCRDSWmvTvnYw k1i2D/90CrPQtWzHqzj4mps+pDXAYGTZGYyrYlAt8DSzQfcvYxYh95mkCitqNYJh4hDls6G6aDL orV6jhhN2TZ+jCS9JXytVCgHwk5MCSbh6AFmV5Jq9ApknZh9VceUkJf7jWx30hLQwcMWL9hiCuN xXuV1AcxfeqwRdOSE4nMmmksygFQuuXctgtThNXsv7CUlL2bl6xrFvzGpjYX73QAWm9YGPwCjXi 0jWpdlo1y/JipHvrmX6lghV54EOhQDw1lzyZ4qPXgs08rlP3qiZjy8xpyL4WuNfcJbVTBKCk2HJ grgdgbh/i+g8nGGlc4KLQGT27M9ObCcNw0pAPRj9ksICcZKCEXYxUcECgora42NssT/V4PDUzGo 0+7eeJzNmhZSxE3S2Tbgly/blB4LVRckef4MCYs4SchM3ELRVwo+8tMRnR0g2VJj3Bok+xiXUus w0EpZIpDHMTJcJH+DCLVMwW9I9vAEfbxVO88XWxPGubiMS+88U9M3i8s5k3dhCX2L5On/FZx36a Qp+bGASubx0JMczYkVYpuq07AjqmhPeRrPd2FGHfCu+jLTzBWdnYQcal8I+g0i7+Zlj4566RYF7 ed28puW1M1QWRA02jxjFPx6N89ps1Ozd3FzaDdXRdCBb39SlVBbsBFZpcH4hPq7npjkGnTIm3Zk xSiA8N4ydeYF/Lg== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Add cpsw_ale_policer_set/clr_entry() helpers. So far Raw Ethernet matching based on Source/Destination address and VLAN Priority (PCP) is supported. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw_ale.c | 77 ++++++++++++++++++++++++++++++++++++++ drivers/net/ethernet/ti/cpsw_ale.h | 28 ++++++++++++++ 2 files changed, 105 insertions(+) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 49ea1c00be3d..ce216606d915 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -1746,3 +1746,80 @@ void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch) 1); } } + +#define HOST_PORT_NUM 0 + +/* Clear Policer and associated ALE table entries */ +void cpsw_ale_policer_clr_entry(struct cpsw_ale *ale, u32 policer_idx, + struct cpsw_ale_policer_cfg *cfg) +{ + cpsw_ale_policer_reset_entry(ale, policer_idx); + + /* We do not delete ALE entries that were added in set_entry + * as they might still be in use by the port e.g. VLAN id + * or port MAC address + */ + + /* clear BLOCKED in case we set it */ + if ((cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACSRC) && cfg->drop) + cpsw_ale_add_ucast(ale, cfg->src_addr, HOST_PORT_NUM, 0, 0); + + if ((cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACDST) && cfg->drop) + cpsw_ale_add_ucast(ale, cfg->dst_addr, HOST_PORT_NUM, 0, 0); +} + +int cpsw_ale_policer_set_entry(struct cpsw_ale *ale, u32 policer_idx, + struct cpsw_ale_policer_cfg *cfg) +{ + int ale_idx; + u16 ale_flags = cfg->drop ? ALE_BLOCKED : 0; + + /* A single policer can support multiple match types simultaneously + * There can be only one ALE entry per address + */ + cpsw_ale_policer_reset_entry(ale, policer_idx); + cpsw_ale_policer_read_idx(ale, policer_idx); + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACSRC) { + ale_idx = cpsw_ale_add_ucast(ale, cfg->src_addr, HOST_PORT_NUM, + ale_flags, 0); + if (ale_idx < 0) + return -ENOENT; + + /* update policer entry */ + regmap_field_write(ale->fields[POL_SRC_INDEX], ale_idx); + regmap_field_write(ale->fields[POL_SRC_MEN], 1); + } + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACDST) { + ale_idx = cpsw_ale_add_ucast(ale, cfg->dst_addr, HOST_PORT_NUM, + ale_flags, 0); + if (ale_idx < 0) + return -ENOENT; + + /* update policer entry */ + regmap_field_write(ale->fields[POL_DST_INDEX], ale_idx); + regmap_field_write(ale->fields[POL_DST_MEN], 1); + } + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_OVLAN) { + /* VLAN ID based flow routing not yet working, + * only PCP matching for now + */ + if (cfg->vid > 0) + return -EINVAL; + + regmap_field_write(ale->fields[POL_PRI_VAL], cfg->vlan_prio); + regmap_field_write(ale->fields[POL_PRI_MEN], 1); + } + + cpsw_ale_policer_write_idx(ale, policer_idx); + + /* Map to thread id provided by the config */ + if (!cfg->drop) { + cpsw_ale_policer_thread_idx_enable(ale, policer_idx, + cfg->thread_id, true); + } + + return 0; +} diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index ce59fec75774..11d333bf5a52 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -159,6 +159,30 @@ enum cpsw_ale_port_state { /* Policer */ #define CPSW_ALE_POLICER_ENTRY_WORDS 8 +/* Policer match flags */ +#define CPSW_ALE_POLICER_MATCH_PORT BIT(0) +#define CPSW_ALE_POLICER_MATCH_PRI BIT(1) +#define CPSW_ALE_POLICER_MATCH_OUI BIT(2) +#define CPSW_ALE_POLICER_MATCH_MACDST BIT(3) +#define CPSW_ALE_POLICER_MATCH_MACSRC BIT(4) +#define CPSW_ALE_POLICER_MATCH_OVLAN BIT(5) +#define CPSW_ALE_POLICER_MATCH_IVLAN BIT(6) +#define CPSW_ALE_POLICER_MATCH_ETHTYPE BIT(7) +#define CPSW_ALE_POLICER_MATCH_IPSRC BIT(8) +#define CPSW_ALE_POLICER_MATCH_IPDST BIT(9) + +struct cpsw_ale_policer_cfg { + u32 match_flags; + u16 ether_type; + u16 vid; + u8 vlan_prio; + u8 src_addr[ETH_ALEN]; + u8 dst_addr[ETH_ALEN]; + bool drop; + u64 thread_id; + int port_id; +}; + struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params); void cpsw_ale_start(struct cpsw_ale *ale); @@ -199,5 +223,9 @@ void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, bool add); void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch); void cpsw_ale_policer_reset(struct cpsw_ale *ale); +int cpsw_ale_policer_set_entry(struct cpsw_ale *ale, u32 policer_idx, + struct cpsw_ale_policer_cfg *cfg); +void cpsw_ale_policer_clr_entry(struct cpsw_ale *ale, u32 policer_idx, + struct cpsw_ale_policer_cfg *cfg); #endif From patchwork Wed May 14 12:04:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 890089 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8183127D76A; Wed, 14 May 2025 12:04:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747224295; cv=none; b=NT7Cp2xqv76Q19KbKVlkYqrZ+LmDAl5KxToAgNFqjkdkvsc4Nn8m4oD2ri3SUW76W/uBiAFtKz1fZbNn5XBGqLs7thhWEa9iejcbbzq5rgFQSXoxfhY8xaGUSsxLgof5CMXsevCRkz22LZbDnNDRNIZb3t4SLgQaFzb9gcOt3tc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747224295; c=relaxed/simple; bh=ETc3C9Ve09FV4dP091Lg8o78pkW+mExFHoB0dZG+riU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OPPcKEo4kOC5F2WPMaVpi5hfKnvCD0cP6VuQP1uR7qcTPmhCob4HvlRlAPwyZVYoV161fGp3PZXBFr4EelcIxsHzhSYkrl4O4hhprePZ0MzOr5OhpjDLMcrano0QQQytwFf72uajZIQizGEk8eHo72VkrO1DdM/b7rXANWzQn6U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iddsvVmo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iddsvVmo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 32DD5C4CEEF; Wed, 14 May 2025 12:04:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747224295; bh=ETc3C9Ve09FV4dP091Lg8o78pkW+mExFHoB0dZG+riU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=iddsvVmoyY/3haV6OfNat2tfVWR8PhfY/oH5mQvaYH/KNqZk2zESl0mv11Q7JlJp9 Vf17OJeitN8t0jtnUwKSuH6Iehkbj3EoH+lQqmNhmFv/yMmFiqSkZnbuyE8S6wLsEQ SSgNvCPd9ltT+56JaVROW9C0/4rxEszsZWYVk0shyqV8OJDw4uh1Nxqmao6f/IX0+q YoroTcur+x+WtPbjv/R+UdhS7utv/1+JCjMoeTQ32Fz5CrNmFatlg3V+SYY6LQd/Ej KcUcQZvSNkcSim9wGv0RJRPAMTgVS93QVrdUPkQWLoaoIrv9R082KEeI8SBR89e+54 fM86dx4oIk+/g== From: Roger Quadros Date: Wed, 14 May 2025 15:04:28 +0300 Subject: [PATCH net-next v4 8/9] net: ethernet: ti: am65-cpsw: add network flow classification support Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250514-am65-cpsw-rx-class-v4-8-5202d8119241@kernel.org> References: <20250514-am65-cpsw-rx-class-v4-0-5202d8119241@kernel.org> In-Reply-To: <20250514-am65-cpsw-rx-class-v4-0-5202d8119241@kernel.org> To: Siddharth Vadapalli , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , danishanwar@ti.com Cc: srk@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Roger Quadros X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=13820; i=rogerq@kernel.org; h=from:subject:message-id; bh=ETc3C9Ve09FV4dP091Lg8o78pkW+mExFHoB0dZG+riU=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBoJIbJh54Ue3Un7nlqhUQ2aNzJS2ui5xSf6h8Rz 9fzW+DczL6JAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCaCSGyQAKCRDSWmvTvnYw k1idD/wKpoCVnLFIUq0jW6JbG5JolAR/vh+F1GQ4T4mKdlaBb9Xs1YGX/XabiE+reW/4asQQ/Uc joGZTe4spef3+zUqUSAmAD5I8OMPXDjrGNR+DuBvmYDVw9ogBNoM0uvoNdpxKlCPu1kR5N4Ov9l a3HUydMMyiXNZ0EVC848YcqmloASuTf0+wClefpFtQ4tUYC1K3KI46HpvDHvl/kWRbselXjihAP Aw/o3S9baL8mbjMS/WAg82mGb5WPBoXXxiTsfQNOFmWPlkwk5TXSUYHDAMA4JzvMEi2pezOTdoT e9Cb+bntbxxoMp0k1+OB8BZDtAhu0WYlHwA37U5rhsZdowPadGJuZAZFAdFmfwP5S/d1bL98rOS U597LGxXs5JtYO0yngELpn3rF/Q8PWAKVnaKA5bdl4FuAfQKsV5EtXmFbFXaAsS5nlf0AnjCFG+ 5y70gmSODqQx0xua9FbZ3Yrx8h31HHL/NEOiojLoSUcgdimQKrkVbd339E5LzzRs4ftQXTsg4IT afgRS94hvn9tMzmORGfwrITd32/Y0n2kgf+ZjjKn6542WAQeBorG+1xdqCIwXHMVo/9YM7Eb6jy j9rU2RhZwALmuAkfD0kzcuMhEBxLQc5QAcPyz4MsbkHdzV19+0vF8zj9sQWQIqhFHWIptuh3uzQ BG9tMPQxH0ZyLJw== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Adds support for -N/--config-nfc ethtool command for configuring RX classfiers. Currently only raw Ethernet (flow-type ether) matching is added based on source/destination addresses and VLAN Priority (PCP). The ALE policer engine is used to perform the matching and routing to a specific RX channel. The TRM doesn't mention anything about order of evaluation of the classifier rules however it does mention in [1] "if multiple classifier matches occur, the highest match with thread enable bit set will be used." [1] 3.1.4.6.1.12.3.1 Classifier to CPPI Transmit Flow ID Mapping in AM62x TRM https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/am65-cpsw-ethtool.c | 357 ++++++++++++++++++++++++++++ drivers/net/ethernet/ti/am65-cpsw-nuss.c | 3 + drivers/net/ethernet/ti/am65-cpsw-nuss.h | 15 ++ 3 files changed, 375 insertions(+) diff --git a/drivers/net/ethernet/ti/am65-cpsw-ethtool.c b/drivers/net/ethernet/ti/am65-cpsw-ethtool.c index 9032444435e9..41f4baf06507 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-ethtool.c +++ b/drivers/net/ethernet/ti/am65-cpsw-ethtool.c @@ -970,6 +970,361 @@ static int am65_cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coales return am65_cpsw_set_per_queue_coalesce(ndev, 0, coal); } +#define AM65_CPSW_FLOW_TYPE(f) ((f) & ~(FLOW_EXT | FLOW_MAC_EXT)) + +/* rxnfc_lock must be held */ +static struct am65_cpsw_rxnfc_rule *am65_cpsw_get_rule(struct am65_cpsw_port *port, + int location) +{ + struct am65_cpsw_rxnfc_rule *rule; + + list_for_each_entry(rule, &port->rxnfc_rules, list) { + if (rule->location == location) + return rule; + } + + return NULL; +} + +/* rxnfc_lock must be held */ +static void am65_cpsw_del_rule(struct am65_cpsw_port *port, + struct am65_cpsw_rxnfc_rule *rule) +{ + cpsw_ale_policer_clr_entry(port->common->ale, rule->location, + &rule->cfg); + list_del(&rule->list); + port->rxnfc_count--; + kfree(rule); +} + +/* rxnfc_lock must be held */ +static int am65_cpsw_add_rule(struct am65_cpsw_port *port, + struct am65_cpsw_rxnfc_rule *rule) +{ + struct am65_cpsw_rxnfc_rule *prev = NULL, *cur; + int ret; + + ret = cpsw_ale_policer_set_entry(port->common->ale, rule->location, + &rule->cfg); + if (ret) + return ret; + + list_for_each_entry(cur, &port->rxnfc_rules, list) { + if (cur->location >= rule->location) + break; + prev = cur; + } + + list_add(&rule->list, prev ? &prev->list : &port->rxnfc_rules); + port->rxnfc_count++; + + return 0; +} + +#define ETHER_TYPE_FULL_MASK cpu_to_be16(FIELD_MAX(U16_MAX)) +#define VLAN_TCI_FULL_MASK ETHER_TYPE_FULL_MASK + +static int am65_cpsw_rxnfc_get_rule(struct am65_cpsw_port *port, + struct ethtool_rxnfc *rxnfc) +{ + struct ethtool_rx_flow_spec *fs = &rxnfc->fs; + struct am65_cpsw_rxnfc_rule *rule; + struct cpsw_ale_policer_cfg *cfg; + + mutex_lock(&port->rxnfc_lock); + rule = am65_cpsw_get_rule(port, fs->location); + if (!rule) { + mutex_unlock(&port->rxnfc_lock); + return -ENOENT; + } + + cfg = &rule->cfg; + + /* build flowspec from policer_cfg */ + fs->flow_type = ETHER_FLOW; + fs->ring_cookie = cfg->thread_id; + + /* clear all masks. Seems to be inverted */ + eth_broadcast_addr(fs->m_u.ether_spec.h_dest); + eth_broadcast_addr(fs->m_u.ether_spec.h_source); + fs->m_u.ether_spec.h_proto = ETHER_TYPE_FULL_MASK; + fs->m_ext.vlan_tci = htons(0xFFFF); + fs->m_ext.vlan_etype = ETHER_TYPE_FULL_MASK; + fs->m_ext.data[0] = cpu_to_be32(FIELD_MAX(U32_MAX)); + fs->m_ext.data[1] = cpu_to_be32(FIELD_MAX(U32_MAX)); + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACDST) { + ether_addr_copy(fs->h_u.ether_spec.h_dest, + cfg->dst_addr); + eth_zero_addr(fs->m_u.ether_spec.h_dest); + } + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_MACSRC) { + ether_addr_copy(fs->h_u.ether_spec.h_source, + cfg->src_addr); + eth_zero_addr(fs->m_u.ether_spec.h_source); + } + + if (cfg->match_flags & CPSW_ALE_POLICER_MATCH_OVLAN) { + fs->flow_type |= FLOW_EXT; + fs->h_ext.vlan_tci = htons(FIELD_PREP(VLAN_VID_MASK, cfg->vid) + | FIELD_PREP(VLAN_PRIO_MASK, cfg->vlan_prio)); + fs->m_ext.vlan_tci = 0; + } + + mutex_unlock(&port->rxnfc_lock); + + return 0; +} + +static int am65_cpsw_rxnfc_get_all(struct am65_cpsw_port *port, + struct ethtool_rxnfc *rxnfc, + u32 *rule_locs) +{ + struct am65_cpsw_rxnfc_rule *rule; + int count = 0; + + rxnfc->data = port->rxnfc_max; + mutex_lock(&port->rxnfc_lock); + + list_for_each_entry(rule, &port->rxnfc_rules, list) { + if (count == rxnfc->rule_cnt) { + mutex_unlock(&port->rxnfc_lock); + return -EMSGSIZE; + } + + rule_locs[count] = rule->location; + count++; + } + + mutex_unlock(&port->rxnfc_lock); + rxnfc->rule_cnt = count; + + return 0; +} + +static int am65_cpsw_get_rxnfc(struct net_device *ndev, + struct ethtool_rxnfc *rxnfc, + u32 *rule_locs) +{ + struct am65_cpsw_common *common = am65_ndev_to_common(ndev); + struct am65_cpsw_port *port = am65_ndev_to_port(ndev); + + switch (rxnfc->cmd) { + case ETHTOOL_GRXRINGS: + rxnfc->data = common->rx_ch_num_flows; + return 0; + case ETHTOOL_GRXCLSRLCNT: /* Get RX classification rule count */ + rxnfc->rule_cnt = port->rxnfc_count; + rxnfc->data = port->rxnfc_max; + return 0; + case ETHTOOL_GRXCLSRULE: /* Get RX classification rule */ + return am65_cpsw_rxnfc_get_rule(port, rxnfc); + case ETHTOOL_GRXCLSRLALL: /* Get all RX classification rules */ + return am65_cpsw_rxnfc_get_all(port, rxnfc, rule_locs); + default: + return -EOPNOTSUPP; + } +} + +/* validate the rxnfc rule and convert it to policer config */ +static int am65_cpsw_rxnfc_validate(struct am65_cpsw_port *port, + struct ethtool_rxnfc *rxnfc, + struct cpsw_ale_policer_cfg *cfg) +{ + struct ethtool_rx_flow_spec *fs = &rxnfc->fs; + struct ethhdr *eth_mask; + int flow_type; + + flow_type = AM65_CPSW_FLOW_TYPE(fs->flow_type); + memset(cfg, 0, sizeof(*cfg)); + + if (flow_type & FLOW_RSS) + return -EINVAL; + + if (fs->location == RX_CLS_LOC_ANY || + fs->location >= port->rxnfc_max) + return -EINVAL; + + if (fs->ring_cookie == RX_CLS_FLOW_DISC) + cfg->drop = true; + else if (fs->ring_cookie > AM65_CPSW_MAX_QUEUES) + return -EINVAL; + + cfg->port_id = port->port_id; + cfg->thread_id = fs->ring_cookie; + + switch (flow_type) { + case ETHER_FLOW: + eth_mask = &fs->m_u.ether_spec; + + /* etherType matching is supported by h/w but not yet here */ + if (eth_mask->h_proto) + return -EINVAL; + + /* Only support source matching addresses by full mask */ + if (is_broadcast_ether_addr(eth_mask->h_source)) { + cfg->match_flags |= CPSW_ALE_POLICER_MATCH_MACSRC; + ether_addr_copy(cfg->src_addr, + fs->h_u.ether_spec.h_source); + } + + /* Only support destination matching addresses by full mask */ + if (is_broadcast_ether_addr(eth_mask->h_dest)) { + cfg->match_flags |= CPSW_ALE_POLICER_MATCH_MACDST; + ether_addr_copy(cfg->dst_addr, + fs->h_u.ether_spec.h_dest); + } + + if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { + /* Don't yet support vlan ethertype */ + if (fs->m_ext.vlan_etype) + return -EINVAL; + + if (fs->m_ext.vlan_tci != VLAN_TCI_FULL_MASK) + return -EINVAL; + + cfg->vid = FIELD_GET(VLAN_VID_MASK, + ntohs(fs->h_ext.vlan_tci)); + cfg->vlan_prio = FIELD_GET(VLAN_PRIO_MASK, + ntohs(fs->h_ext.vlan_tci)); + cfg->match_flags |= CPSW_ALE_POLICER_MATCH_OVLAN; + } + + break; + default: + return -EINVAL; + } + + return 0; +} + +/* rxnfc_lock must be held */ +static int am65_cpsw_policer_find_match(struct am65_cpsw_port *port, + struct cpsw_ale_policer_cfg *cfg) +{ + struct am65_cpsw_rxnfc_rule *rule; + int loc = -EINVAL; + + list_for_each_entry(rule, &port->rxnfc_rules, list) { + if (!memcmp(&rule->cfg, cfg, sizeof(*cfg))) { + loc = rule->location; + break; + } + } + + mutex_unlock(&port->rxnfc_lock); + + return loc; +} + +static int am65_cpsw_rxnfc_add_rule(struct am65_cpsw_port *port, + struct ethtool_rxnfc *rxnfc) +{ + struct ethtool_rx_flow_spec *fs = &rxnfc->fs; + struct am65_cpsw_rxnfc_rule *rule; + struct cpsw_ale_policer_cfg cfg; + int loc, ret; + + if (am65_cpsw_rxnfc_validate(port, rxnfc, &cfg)) + return -EINVAL; + + /* need to check if similar rule is already present at another location, + * if yes error out + */ + mutex_lock(&port->rxnfc_lock); + loc = am65_cpsw_policer_find_match(port, &cfg); + if (loc >= 0 && loc != fs->location) { + netdev_info(port->ndev, + "rule already exists in location %d. not adding\n", + loc); + mutex_unlock(&port->rxnfc_lock); + return -EINVAL; + } + + /* delete exisiting rule */ + if (loc >= 0) { + rule = am65_cpsw_get_rule(port, loc); + if (rule) + am65_cpsw_del_rule(port, rule); + } + + rule = kzalloc(sizeof(*rule), GFP_KERNEL); + if (!rule) { + mutex_unlock(&port->rxnfc_lock); + return -ENOMEM; + } + + INIT_LIST_HEAD(&rule->list); + memcpy(&rule->cfg, &cfg, sizeof(cfg)); + rule->location = fs->location; + ret = am65_cpsw_add_rule(port, rule); + if (ret) + kfree(rule); + mutex_unlock(&port->rxnfc_lock); + + return ret; +} + +static int am65_cpsw_rxnfc_del_rule(struct am65_cpsw_port *port, + struct ethtool_rxnfc *rxnfc) +{ + struct ethtool_rx_flow_spec *fs = &rxnfc->fs; + struct am65_cpsw_rxnfc_rule *rule; + + mutex_lock(&port->rxnfc_lock); + rule = am65_cpsw_get_rule(port, fs->location); + if (!rule) { + mutex_unlock(&port->rxnfc_lock); + return -ENOENT; + } + + am65_cpsw_del_rule(port, rule); + /* rule freed in am65_cpsw_del_rule() */ + mutex_unlock(&port->rxnfc_lock); + + return 0; +} + +void am65_cpsw_rxnfc_init(struct am65_cpsw_port *port) +{ + struct cpsw_ale *ale = port->common->ale; + + mutex_init(&port->rxnfc_lock); + INIT_LIST_HEAD(&port->rxnfc_rules); + port->rxnfc_max = ale->params.num_policers; + + /* disable all rules */ + cpsw_ale_policer_reset(ale); +} + +void am65_cpsw_rxnfc_cleanup(struct am65_cpsw_port *port) +{ + struct am65_cpsw_rxnfc_rule *rule, *tmp; + + mutex_lock(&port->rxnfc_lock); + + list_for_each_entry_safe(rule, tmp, &port->rxnfc_rules, list) + am65_cpsw_del_rule(port, rule); + + mutex_unlock(&port->rxnfc_lock); +} + +static int am65_cpsw_set_rxnfc(struct net_device *ndev, + struct ethtool_rxnfc *rxnfc) +{ + struct am65_cpsw_port *port = am65_ndev_to_port(ndev); + + switch (rxnfc->cmd) { + case ETHTOOL_SRXCLSRLINS: + return am65_cpsw_rxnfc_add_rule(port, rxnfc); + case ETHTOOL_SRXCLSRLDEL: + return am65_cpsw_rxnfc_del_rule(port, rxnfc); + default: + return -EOPNOTSUPP; + } +} + const struct ethtool_ops am65_cpsw_ethtool_ops_slave = { .begin = am65_cpsw_ethtool_op_begin, .complete = am65_cpsw_ethtool_op_complete, @@ -1007,4 +1362,6 @@ const struct ethtool_ops am65_cpsw_ethtool_ops_slave = { .get_mm = am65_cpsw_get_mm, .set_mm = am65_cpsw_set_mm, .get_mm_stats = am65_cpsw_get_mm_stats, + .get_rxnfc = am65_cpsw_get_rxnfc, + .set_rxnfc = am65_cpsw_set_rxnfc, }; diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 07df61f343d3..cdb83ae54656 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -2758,6 +2758,7 @@ am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) return -ENOMEM; } + am65_cpsw_rxnfc_init(port); ndev_priv = netdev_priv(port->ndev); ndev_priv->port = port; ndev_priv->msg_enable = AM65_CPSW_DEBUG; @@ -2870,6 +2871,7 @@ static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) unregister_netdev(port->ndev); free_netdev(port->ndev); port->ndev = NULL; + am65_cpsw_rxnfc_cleanup(port); } } @@ -3172,6 +3174,7 @@ static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, /* clean up ALE table */ cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); + cpsw_ale_policer_reset(cpsw->ale); if (switch_en) { dev_info(cpsw->dev, "Enable switch mode\n"); diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.h b/drivers/net/ethernet/ti/am65-cpsw-nuss.h index 61daa5db12e6..8b83c9a0965d 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.h +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.h @@ -16,6 +16,7 @@ #include #include #include "am65-cpsw-qos.h" +#include "cpsw_ale.h" struct am65_cpts; @@ -40,6 +41,12 @@ struct am65_cpsw_slave_data { struct phylink_config phylink_config; }; +struct am65_cpsw_rxnfc_rule { + struct list_head list; + unsigned int location; + struct cpsw_ale_policer_cfg cfg; +}; + struct am65_cpsw_port { struct am65_cpsw_common *common; struct net_device *ndev; @@ -59,6 +66,11 @@ struct am65_cpsw_port { struct xdp_rxq_info xdp_rxq[AM65_CPSW_MAX_QUEUES]; /* Only for suspend resume context */ u32 vid_context; + /* Classifier flows */ + struct mutex rxnfc_lock; + struct list_head rxnfc_rules; + int rxnfc_count; + int rxnfc_max; }; enum am65_cpsw_tx_buf_type { @@ -229,4 +241,7 @@ int am65_cpsw_nuss_update_tx_rx_chns(struct am65_cpsw_common *common, bool am65_cpsw_port_dev_check(const struct net_device *dev); +void am65_cpsw_rxnfc_init(struct am65_cpsw_port *port); +void am65_cpsw_rxnfc_cleanup(struct am65_cpsw_port *port); + #endif /* AM65_CPSW_NUSS_H_ */