From patchwork Thu May 15 21:19:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 890518 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56FB2218AAA; Thu, 15 May 2025 21:20:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344001; cv=none; b=m5WK2NsZZkhFqXZzeZPdCJEL0PzfAMS8425jfXIERSbC7lU8CIkkMTouvUps73TuadB9jkhHhg3DS9kBKlvGrv6CJT36tlDbrWR07uCf8ccUU4VZzhLhomf4kDKqlHTLpoO908HqnTvxUQfD4E4jgDEd5OlMNkpYn1nZ/mzASgM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344001; c=relaxed/simple; bh=ZZPLPFekmqonJmYX/xbKyqOt43jN+w5eM5nlYX4e6+c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BzcqEbcskEi6uKbRLtJIs1E5ikjXXl+RLBkbw6NLKFw95hxYMN/xspJTlAu8XlqmppAeTs8b7RHXMsOqy0u4H9Krsgp41BgQnI4fQDELcaSBt69qgLqaKnHWHm3+wFxb67bkONo9U0yldFQ4mPHDozjmafhyVKnN+vNdKWzHr6s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jZU4IX+7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jZU4IX+7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D4233C4CEF1; Thu, 15 May 2025 21:19:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747344000; bh=ZZPLPFekmqonJmYX/xbKyqOt43jN+w5eM5nlYX4e6+c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jZU4IX+7uYEM2hSyE7J+xtar0A883pyCqJrN0dlvbuCaZ8j9rEzehCtw5ayUWIubl iPHQEYJDowe0E8Emsxe61p36Cu8y6AArAJvXiEauQMB3/g0AFHbHxDE8qsLQUx1Vlf MrfnegcAPmFPoPimZkmppKz7MmswwxvsTeC0sM3X7i22ednQySMa7W7NegvBV7Ddfc +duaTlAGqfztPDHH44HSmaLMeDtjxKx1KPU+YxIsxiA6S4dkdO4/Xk0WZPUwbt63qL xNOWlAO1oOhxdxB0tjhF5/hbhWciJl8ZKyqkOq4h6GPeP626JnsF37SWKLdQ9t6+th pd2IZE1VXEjZA== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan , Bagas Sanjaya Subject: [PATCH v10 01/13] Documentation: x86: Add AMD Hardware Feedback Interface documentation Date: Thu, 15 May 2025 16:19:38 -0500 Message-ID: <20250515211950.3102922-2-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515211950.3102922-1-superm1@kernel.org> References: <20250515211950.3102922-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Introduce a new documentation file, `amd_hfi.rst`, which delves into the implementation details of the AMD Hardware Feedback Interface and its associated driver, `amd_hfi`. This documentation describes how the driver provides hint to the OS scheduling which depends on the capability of core performance and efficiency ranking data. This documentation describes * The design of the driver * How the driver provides hints to the OS scheduling * How the driver interfaces with the kernel for efficiency ranking data. Reviewed-by: Bagas Sanjaya Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- Documentation/arch/x86/amd-hfi.rst | 133 +++++++++++++++++++++++++++++ Documentation/arch/x86/index.rst | 1 + 2 files changed, 134 insertions(+) create mode 100644 Documentation/arch/x86/amd-hfi.rst diff --git a/Documentation/arch/x86/amd-hfi.rst b/Documentation/arch/x86/amd-hfi.rst new file mode 100644 index 0000000000000..8c1799acb6fe6 --- /dev/null +++ b/Documentation/arch/x86/amd-hfi.rst @@ -0,0 +1,133 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================================================== +Hardware Feedback Interface For Hetero Core Scheduling On AMD Platform +====================================================================== + +:Copyright: 2025 Advanced Micro Devices, Inc. All Rights Reserved. + +:Author: Perry Yuan +:Author: Mario Limonciello + +Overview +-------- + +AMD Heterogeneous Core implementations are comprised of more than one +architectural class and CPUs are comprised of cores of various efficiency and +power capabilities: performance-oriented *classic cores* and power-efficient +*dense cores*. As such, power management strategies must be designed to +accommodate the complexities introduced by incorporating different core types. +Heterogeneous systems can also extend to more than two architectural classes +as well. The purpose of the scheduling feedback mechanism is to provide +information to the operating system scheduler in real time such that the +scheduler can direct threads to the optimal core. + +The goal of AMD's heterogeneous architecture is to attain power benefit by +sending background thread to the dense cores while sending high priority +threads to the classic cores. From a performance perspective, sending +background threads to dense cores can free up power headroom and allow the +classic cores to optimally service demanding threads. Furthermore, the area +optimized nature of the dense cores allows for an increasing number of +physical cores. This improved core density will have positive multithreaded +performance impact. + +AMD Heterogeneous Core Driver +----------------------------- + +The ``amd_hfi`` driver delivers the operating system a performance and energy +efficiency capability data for each CPU in the system. The scheduler can use +the ranking data from the HFI driver to make task placement decisions. + +Thread Classification and Ranking Table Interaction +---------------------------------------------------- + +The thread classification is used to select into a ranking table that +describes an efficiency and performance ranking for each classification. + +Threads are classified during runtime into enumerated classes. The classes +represent thread performance/power characteristics that may benefit from +special scheduling behaviors. The below table depicts an example of thread +classification and a preference where a given thread should be scheduled +based on its thread class. The real time thread classification is consumed +by the operating system and is used to inform the scheduler of where the +thread should be placed. + +Thread Classification Example Table +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ++----------+----------------+-------------------------------+---------------------+---------+ +| class ID | Classification | Preferred scheduling behavior | Preemption priority | Counter | ++----------+----------------+-------------------------------+---------------------+---------+ +| 0 | Default | Performant | Highest | | ++----------+----------------+-------------------------------+---------------------+---------+ +| 1 | Non-scalable | Efficient | Lowest | PMCx1A1 | ++----------+----------------+-------------------------------+---------------------+---------+ +| 2 | I/O bound | Efficient | Lowest | PMCx044 | ++----------+----------------+-------------------------------+---------------------+---------+ + +Thread classification is performed by the hardware each time that the thread is switched out. +Threads that don't meet any hardware specified criteria will be classified as "default". + +AMD Hardware Feedback Interface +-------------------------------- + +The Hardware Feedback Interface provides to the operating system information +about the performance and energy efficiency of each CPU in the system. Each +capability is given as a unit-less quantity in the range [0-255]. A higher +performance value indicates higher performance capability, and a higher +efficiency value indicates more efficiency. Energy efficiency and performance +are reported in separate capabilities in the shared memory based ranking table. + +These capabilities may change at runtime as a result of changes in the +operating conditions of the system or the action of external factors. +Power Management FW is responsible for detecting events that would require +a reordering of the performance and efficiency ranking. Table updates would +happen relatively infrequently and occur on the time scale of seconds or more. + +The following events trigger a table update: + * Thermal Stress Events + * Silent Compute + * Extreme Low Battery Scenarios + +The kernel or a userspace policy daemon can use these capabilities to modify +task placement decisions. For instance, if either the performance or energy +capabilities of a given logical processor becomes zero, it is an indication +that the hardware recommends to the operating system to not schedule any tasks +on that processor for performance or energy efficiency reasons, respectively. + +Implementation details for Linux +-------------------------------- + +The implementation of threads scheduling consists of the following steps: + +1. A thread is spawned and scheduled to the ideal core using the default + heterogeneous scheduling policy. +2. The processor profiles thread execution and assigns an enumerated + classification ID. + This classification is communicated to the OS via logical processor + scope MSR. +3. During the thread context switch out the operating system consumes the + workload(WL) classification which resides in a logical processor scope MSR. +4. The OS triggers the hardware to clear its history by writing to an MSR, + after consuming the WL classification and before switching in the new thread. +5. If due to the classification, ranking table, and processor availability, + the thread is not on its ideal processor, the OS will then consider + scheduling the thread on its ideal processor (if available). + +Ranking Table +------------- +The ranking table is a shared memory region that is used to communicate the +performance and energy efficiency capabilities of each CPU in the system. + +The ranking table design includes rankings for each APIC ID in the system and +rankings both for performance and efficiency for each workload classification. + +.. kernel-doc:: drivers/platform/x86/amd/hfi/hfi.c + :doc: amd_shmem_info + +Ranking Table update +--------------------------- +The power management firmware issues an platform interrupt after updating the +ranking table and is ready for the operating system to consume it. CPUs receive +such interrupt and read new ranking table from shared memory which PCCT table +has provided, then ``amd_hfi`` driver parse the new table to provide new +consume data for scheduling decisions. diff --git a/Documentation/arch/x86/index.rst b/Documentation/arch/x86/index.rst index 58a006525ae81..cd9143d623872 100644 --- a/Documentation/arch/x86/index.rst +++ b/Documentation/arch/x86/index.rst @@ -28,6 +28,7 @@ x86-specific Documentation amd-debugging amd-memory-encryption amd_hsmp + amd-hfi tdx pti mds From patchwork Thu May 15 21:19:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 890804 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50DAC28A714; Thu, 15 May 2025 21:20:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344003; cv=none; b=K8ywEPUFSmhJ7yLenPVe2KRbDwprHkdI0HQMBhvC9MF7gSY9jdSxaHXmvn8sVlFNWEfzZEijYWmr5VHf4H3ZVWJ97z6MJlEHGKfRYVBclcsttPbRhBfbpicPuC6SetnKOkbtHwQ/DTCnXyoFttPnAgAdep391V9+hDlhEOCN7pQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344003; c=relaxed/simple; bh=kSO1RcrRmbpu2jI/kFy9WAUOJT0oJZHI8uzfRcQZa8I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RxeiDvrF10T9grjuZ54UZ5V9k5F8upBV7nQizWFyaC+UYVjyjb3JLLm2+6VDMEMLAOkFWlxn8tqbI8YZzrBQvZY8paqR7Rs3tZkCHWSCdyGYyEGao4D4QddZeTILn6bIgET/u244RfBGOKypBuxOnjJ730HSmQGi/sPMbqZjExo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OcHtWql+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OcHtWql+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0184DC4CEED; Thu, 15 May 2025 21:20:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747344002; bh=kSO1RcrRmbpu2jI/kFy9WAUOJT0oJZHI8uzfRcQZa8I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OcHtWql+EvBBv0tnyG08OSm3xGtJfoBSHayrDhn37wGD5EAbhn6EQl6keiXncLkEw 8kPElFjA5B6ZmYArN/p8xrM7LP0nI5F3jo81AmgwehLM1IzW0WL+Y8rM80RxAfaoLl hcy/na+l6wkhgdIb8lpKbWKnzAuHeTNrxJ6nB6YrJKM1wAHXHfV3fj6Ejq2xGSB9+g S+4wUhF/QgnFwpN0argltJhr4CAyGAlOIo/XeBOdE4A/HF44UKQ+3t2gqa5Q88nhB1 f2womG/Ekowb7OjVDaYYHbWgQ5dIVCCYvlmUV5KrAGPw/VypC+KKuBtCD6x2mPbKWu wYLWuUnZDsT4A== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v10 02/13] MAINTAINERS: Add maintainer entry for AMD Hardware Feedback Driver Date: Thu, 15 May 2025 16:19:39 -0500 Message-ID: <20250515211950.3102922-3-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515211950.3102922-1-superm1@kernel.org> References: <20250515211950.3102922-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello Introduce the `amd_hfi` driver into the MAINTAINERS file. The driver will support AMD Heterogeneous Core design which provides hardware feedback to the OS scheduler. Moving forward, Mario will be responsible for the maintenance and Perry will assist on review of patches related to this driver. Signed-off-by: Mario Limonciello --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fa54602b59022..6920afed09e8b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1101,6 +1101,15 @@ F: arch/x86/include/asm/amd/hsmp.h F: arch/x86/include/uapi/asm/amd_hsmp.h F: drivers/platform/x86/amd/hsmp/ +AMD HETERO CORE HARDWARE FEEDBACK DRIVER +M: Mario Limonciello +R: Perry Yuan +L: platform-driver-x86@vger.kernel.org +S: Supported +B: https://gitlab.freedesktop.org/drm/amd/-/issues +F: Documentation/arch/x86/amd-hfi.rst +F: drivers/platform/x86/amd/hfi/ + AMD IOMMU (AMD-VI) M: Joerg Roedel R: Suravee Suthikulpanit From patchwork Thu May 15 21:19:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 890517 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC41628C5DF; Thu, 15 May 2025 21:20:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344004; cv=none; b=o14G95Kot+RNSEDxBfrVom7H3y7ENaqhCbIQTncYAw9fMn9XvSsb7tmznMsLhqGPEgGVPbgXxjHMfCpjdtHFojSA2aN4URsQC5O7KvhGFxXpn/m/VcDiUihSJGuqcUdCpA7ysSLCaYjnfc8FViHqlXks9gmLUxa9NXjpr41suHk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344004; c=relaxed/simple; bh=clP7AkFKKUaIpuy0+IvByQA/4XreAJXjxCjAlqwDY4k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mV7JdM0xfJA9IiHbV1c17OXrB5A3Cztflh/UY9IIcMNMnHkQr1vIpna+kMCl/wcHLU49gAbsGSHM3t09J+xm6h5qAfs/Lz+X+IlFn53YT4yKttXbQyiDyA/n2xonUR/1tTQPs+DJj6qhJjestQCeP29BSCXwkyWGYToAIDUcA2M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ams3THYI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ams3THYI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EA305C4CEF0; Thu, 15 May 2025 21:20:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747344004; bh=clP7AkFKKUaIpuy0+IvByQA/4XreAJXjxCjAlqwDY4k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ams3THYIaBVJ3DU9YFQUgzWa48MT/syXawNxgSrvn51seD9NZA9hG39RUPFd/1Ffa TMu+uQajB5lpVP+8RAnWKF8mrJNkzGVHcOtCefdX4almGu34jNJ8y/6pyT7THrcNUR UGvOrPy+PHd3dKK8M1sXFLFJMMIgD/dF4Rg/lWeW1Jv7Nridw398cDv9lLoeazUsqg uvedWPcgMFg0M5RHX8ANCV+dXdw1wE7Olsqs8+B96ksbMqZN/s5/Lt4+EBhoMiyyvv 3RKg7favEn7msQJveefPnFk61pXgj620maWLBrra+SDdm2czl+QIWEyFaj1ZGMwRu4 RHrPIJGUD8ELQ== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v10 03/13] x86/msr-index: define AMD heterogeneous CPU related MSR Date: Thu, 15 May 2025 16:19:40 -0500 Message-ID: <20250515211950.3102922-4-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515211950.3102922-1-superm1@kernel.org> References: <20250515211950.3102922-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Introduces new MSR registers for AMD hardware feedback support. These registers enable the system to provide workload classification and configuration capabilities. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index b7dded3c81132..8e6db9a9f53c0 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -732,6 +732,11 @@ #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 +/* AMD Hardware Feedback Support MSRs */ +#define AMD_WORKLOAD_CLASS_CONFIG 0xc0000500 +#define AMD_WORKLOAD_CLASS_ID 0xc0000501 +#define AMD_WORKLOAD_HRST 0xc0000502 + /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e From patchwork Thu May 15 21:19:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 890803 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C15B328EA46; Thu, 15 May 2025 21:20:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344006; cv=none; b=fwaDC29PXYYUbNxqslPoNgMPl/aGlXz10cTPWjr1e3qaw3UZlvF8dn0jB8Mp80Oyz/EmnuDTwG1IbBXisbOhqqeUmD3OTCPnP1YqdBf398zeNGJk/Oclw6hp/sov0EF7TEq+4mvs+438CDWvWjNH5a9LZ9Lfq12zbCGEvM53TBs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344006; c=relaxed/simple; bh=h4MElcp+Fb1vokbgwKom+kcbVykn7Y6wWpjvwcJZZoo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gg1Dscdy+pp+XZyS8uJlNL88XsJBXrd3C7JSa9fRnwvAOVw2v/QuMtbYc3T0ShTdbnHixiYAky6slq8LCgWmnbrI9K69/4LFtkLrkfLaZhBsHrDwilXOMiXhA9ZoBBR/aWQ/2WfLxkJxKKXtjVE6uGPeK7kjEpw8THNaezxCbkM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=c8gXcO5B; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="c8gXcO5B" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D1076C4CEED; Thu, 15 May 2025 21:20:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747344006; bh=h4MElcp+Fb1vokbgwKom+kcbVykn7Y6wWpjvwcJZZoo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c8gXcO5Bwpb3JCfFwWU+gkqfHK8uLBeRXmkHb2NH0ykY0mdEJBTW4bM/iwgCk3M39 qPKWYW5f4X+SGVs6G8X9DrPEHoybc2o7/Nd1/fErRhWyC94h4ccuZKIXfMq/eKortl GeEAybsW6kbhbASKYlhqQZF9qMSXC8LG5sqiTtHOTysCZqd/PmIZcDwDrcWVN5rnOf STW5deQCZUDVgIfAIrHb1RBcq8ApRu8Nx+zaDmTEeR2cF6ohg6hZFexIzfZezH95S0 7EvPUniEqIOBdJoMpMvZg5HXgsasJgzaIgHEL645DScvmxE2yA+/q4Ofkbbx7jV4XK +Z8YKMSALGQoA== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan , Shyam Sundar S K Subject: [PATCH v10 04/13] platform/x86: hfi: Introduce AMD Hardware Feedback Interface Driver Date: Thu, 15 May 2025 16:19:41 -0500 Message-ID: <20250515211950.3102922-5-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515211950.3102922-1-superm1@kernel.org> References: <20250515211950.3102922-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan The AMD Heterogeneous core design and Hardware Feedback Interface (HFI) provide behavioral classification and a dynamically updated ranking table for the scheduler to use when choosing cores for tasks. There are two CPU core types defined: `Classic Core` and `Dense Core`. "Classic" cores are the standard performance cores, while "Dense" cores are optimized for area and efficiency. Heterogeneous compute refers to CPU implementations that are comprised of more than one architectural class, each with two capabilities. This means each CPU reports two separate capabilities: "perf" and "eff". Each capability lists all core ranking numbers between 0 and 255, where a higher number represents a higher capability. Heterogeneous systems can also extend to more than two architectural classes. The purpose of the scheduling feedback mechanism is to provide information to the operating system scheduler in real time, allowing the scheduler to direct threads to the optimal core during task scheduling. All core ranking data are provided by the PMFW via a shared memory ranking table, which the driver reads and uses to update core capabilities to the scheduler. When the hardware updates the table, it generates a platform interrupt to notify the OS to read the new ranking table. Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Reviewed-by: Gautham R. Shenoy Reviewed-by: Shyam Sundar S K Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- drivers/platform/x86/amd/Kconfig | 1 + drivers/platform/x86/amd/Makefile | 1 + drivers/platform/x86/amd/hfi/Kconfig | 17 +++ drivers/platform/x86/amd/hfi/Makefile | 7 ++ drivers/platform/x86/amd/hfi/hfi.c | 158 ++++++++++++++++++++++++++ 5 files changed, 184 insertions(+) create mode 100644 drivers/platform/x86/amd/hfi/Kconfig create mode 100644 drivers/platform/x86/amd/hfi/Makefile create mode 100644 drivers/platform/x86/amd/hfi/hfi.c diff --git a/drivers/platform/x86/amd/Kconfig b/drivers/platform/x86/amd/Kconfig index c3e086ea64fc6..589d61ebf726b 100644 --- a/drivers/platform/x86/amd/Kconfig +++ b/drivers/platform/x86/amd/Kconfig @@ -6,6 +6,7 @@ source "drivers/platform/x86/amd/hsmp/Kconfig" source "drivers/platform/x86/amd/pmf/Kconfig" source "drivers/platform/x86/amd/pmc/Kconfig" +source "drivers/platform/x86/amd/hfi/Kconfig" config AMD_3D_VCACHE tristate "AMD 3D V-Cache Performance Optimizer Driver" diff --git a/drivers/platform/x86/amd/Makefile b/drivers/platform/x86/amd/Makefile index c6c40bdcbdedb..645cb569a2949 100644 --- a/drivers/platform/x86/amd/Makefile +++ b/drivers/platform/x86/amd/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_AMD_PMC) += pmc/ obj-$(CONFIG_AMD_HSMP) += hsmp/ obj-$(CONFIG_AMD_PMF) += pmf/ obj-$(CONFIG_AMD_WBRF) += wbrf.o +obj-$(CONFIG_AMD_HFI) += hfi/ diff --git a/drivers/platform/x86/amd/hfi/Kconfig b/drivers/platform/x86/amd/hfi/Kconfig new file mode 100644 index 0000000000000..476e4a9ed67a9 --- /dev/null +++ b/drivers/platform/x86/amd/hfi/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# AMD Hardware Feedback Interface Driver +# + +config AMD_HFI + bool "AMD Hetero Core Hardware Feedback Driver" + depends on ACPI + depends on CPU_SUP_AMD + help + Select this option to enable the AMD Heterogeneous Core Hardware + Feedback Interface. If selected, hardware provides runtime thread + classification guidance to the operating system on the performance and + energy efficiency capabilities of each heterogeneous CPU core. These + capabilities may vary due to the inherent differences in the core types + and can also change as a result of variations in the operating + conditions of the system such as power and thermal limits. diff --git a/drivers/platform/x86/amd/hfi/Makefile b/drivers/platform/x86/amd/hfi/Makefile new file mode 100644 index 0000000000000..672c6ac106e95 --- /dev/null +++ b/drivers/platform/x86/amd/hfi/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# AMD Hardware Feedback Interface Driver +# + +obj-$(CONFIG_AMD_HFI) += amd_hfi.o +amd_hfi-objs := hfi.o diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c new file mode 100644 index 0000000000000..e613bdf027b26 --- /dev/null +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD Hardware Feedback Interface Driver + * + * Copyright (C) 2025 Advanced Micro Devices, Inc. All Rights Reserved. + * + * Authors: Perry Yuan + * Mario Limonciello + */ + +#define pr_fmt(fmt) "amd-hfi: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AMD_HFI_DRIVER "amd_hfi" + +#define AMD_HETERO_CPUID_27 0x80000027 + +static struct platform_device *device; + +struct amd_hfi_data { + const char *name; + struct device *dev; +}; + +struct amd_hfi_classes { + u32 perf; + u32 eff; +}; + +/** + * struct amd_hfi_cpuinfo - HFI workload class info per CPU + * @cpu: cpu index + * @class_index: workload class ID index + * @nr_class: max number of workload class supported + * @amd_hfi_classes: current cpu workload class ranking data + * + * Parameters of a logical processor linked with hardware feedback class. + */ +struct amd_hfi_cpuinfo { + int cpu; + s16 class_index; + u8 nr_class; + struct amd_hfi_classes *amd_hfi_classes; +}; + +static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = -1}; + +static int amd_hfi_alloc_class_data(struct platform_device *pdev) +{ + struct amd_hfi_cpuinfo *hfi_cpuinfo; + struct device *dev = &pdev->dev; + u32 nr_class_id; + int idx; + + nr_class_id = cpuid_eax(AMD_HETERO_CPUID_27); + if (nr_class_id > 255) { + dev_err(dev, "number of supported classes too large: %d\n", + nr_class_id); + return -EINVAL; + } + + for_each_possible_cpu(idx) { + struct amd_hfi_classes *classes; + + classes = devm_kcalloc(dev, + nr_class_id, + sizeof(struct amd_hfi_classes), + GFP_KERNEL); + if (!classes) + return -ENOMEM; + hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, idx); + hfi_cpuinfo->amd_hfi_classes = classes; + hfi_cpuinfo->nr_class = nr_class_id; + } + + return 0; +} + +static const struct acpi_device_id amd_hfi_platform_match[] = { + {"AMDI0104", 0}, + { } +}; +MODULE_DEVICE_TABLE(acpi, amd_hfi_platform_match); + +static int amd_hfi_probe(struct platform_device *pdev) +{ + struct amd_hfi_data *amd_hfi_data; + int ret; + + if (!acpi_match_device(amd_hfi_platform_match, &pdev->dev)) + return -ENODEV; + + amd_hfi_data = devm_kzalloc(&pdev->dev, sizeof(*amd_hfi_data), GFP_KERNEL); + if (!amd_hfi_data) + return -ENOMEM; + + amd_hfi_data->dev = &pdev->dev; + platform_set_drvdata(pdev, amd_hfi_data); + + ret = amd_hfi_alloc_class_data(pdev); + if (ret) + return ret; + + return 0; +} + +static struct platform_driver amd_hfi_driver = { + .driver = { + .name = AMD_HFI_DRIVER, + .owner = THIS_MODULE, + .acpi_match_table = ACPI_PTR(amd_hfi_platform_match), + }, + .probe = amd_hfi_probe, +}; + +static int __init amd_hfi_init(void) +{ + int ret; + + if (acpi_disabled || + !cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES) || + !cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS)) + return -ENODEV; + + device = platform_device_register_simple(AMD_HFI_DRIVER, -1, NULL, 0); + if (IS_ERR(device)) { + pr_err("unable to register HFI platform device\n"); + return PTR_ERR(device); + } + + ret = platform_driver_register(&amd_hfi_driver); + if (ret) + pr_err("failed to register HFI driver\n"); + + return ret; +} + +static __exit void amd_hfi_exit(void) +{ + platform_driver_unregister(&amd_hfi_driver); + platform_device_unregister(device); +} +module_init(amd_hfi_init); +module_exit(amd_hfi_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("AMD Hardware Feedback Interface Driver"); From patchwork Thu May 15 21:19:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 890516 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25F8D27F75F; Thu, 15 May 2025 21:20:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344009; cv=none; b=tciChMTctj4RNbrTnyTCbaUtokNLlRzcz6HrA+B6G1KH3N9HnGIv6T9O8+5UbaFEhyeTVt07dTk09LW2mukb72wStoxuEmhsmfzs4N8NFxcl7FQLmMdCWfPcNgIpIRgGboZrAW1E9S7pR58I+0irpxTVkCQn3DOD9zohsVst69Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344009; c=relaxed/simple; bh=WFDwgAop6UqZBk5ZX6ZLvF4aWnJBlIdA9CTACAPhV6M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WS6KcewHKsDQlLMIpOcznLpcQkcbaXQz2BXWaxXkVg+UNFtoppBjeI2297Rres0iD1tudSjiMV7PjsrRi38EVfXVmZf8kCqfgSSWFiPC0x0iEL0QAYpDXwskFz+jNUeH63IF2gyulJKA4s5Ofi1Gdkoj/QqGBOVtxqCFfxilDe0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AYcBPEia; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AYcBPEia" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E1422C4CEF1; Thu, 15 May 2025 21:20:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747344008; bh=WFDwgAop6UqZBk5ZX6ZLvF4aWnJBlIdA9CTACAPhV6M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AYcBPEiagxrS96vqOrTZQq5+P74c5L43GXiY9KJVAzdELPXpXxCC2fYQu0OOtQjfJ KFMSSzuOsG5XCMpbHX1XPTJNKXun7gtdMPUIYYQeMxKCj6vM87vEIVphaQEOHkYpD4 aFSw+FEi+kCY8rZ5bV29jkuc1xyp2cjfySJFk+b2raqUmzUp+NaY1lf1rVn5qhKk2z gr7R5NPw5PkufMx6LMFUC9/tk+OD0MRezfRUBheBpVYSRRJNdvsNrP6YwospNPECEA sIXlxqUpcT8STZGajGOuWm45D2Ph2O9LYBh4AitK4t59hmwVmPPg+Q8q7jVeK0d532 0Aagoyr6fM6Tw== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan Subject: [PATCH v10 05/13] platform/x86: hfi: parse CPU core ranking data from shared memory Date: Thu, 15 May 2025 16:19:42 -0500 Message-ID: <20250515211950.3102922-6-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515211950.3102922-1-superm1@kernel.org> References: <20250515211950.3102922-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan When `amd_hfi` driver is loaded, it will use PCCT subspace type 4 table to retrieve the shared memory address which contains the CPU core ranking table. This table includes a header that specifies the number of ranking data entries to be parsed and rank each CPU core with the Performance and Energy Efficiency capability as implemented by the CPU power management firmware. Once the table has been parsed, each CPU is assigned a ranking score within its class. Subsequently, when the scheduler selects cores, it chooses from the ranking list based on the assigned scores in each class, thereby ensuring the optimal selection of CPU cores according to their predefined classifications and priorities. Reviewed-by: Ilpo Järvinen Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- drivers/platform/x86/amd/hfi/hfi.c | 197 +++++++++++++++++++++++++++++ 1 file changed, 197 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index e613bdf027b26..17ce5302cb531 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -18,21 +18,71 @@ #include #include #include +#include #include +#include #include #include +#include +#include + +#include + +#include +#include #define AMD_HFI_DRIVER "amd_hfi" +#define AMD_HFI_MAILBOX_COUNT 1 +#define AMD_HETERO_RANKING_TABLE_VER 2 #define AMD_HETERO_CPUID_27 0x80000027 static struct platform_device *device; +/** + * struct amd_shmem_info - Shared memory table for AMD HFI + * + * @header: The PCCT table header including signature, length flags and command. + * @version_number: Version number of the table + * @n_logical_processors: Number of logical processors + * @n_capabilities: Number of ranking dimensions (performance, efficiency, etc) + * @table_update_context: Command being sent over the subspace + * @n_bitmaps: Number of 32-bit bitmaps to enumerate all the APIC IDs + * This is based on the maximum APIC ID enumerated in the system + * @reserved: 24 bit spare + * @table_data: Bit Map(s) of enabled logical processors + * Followed by the ranking data for each logical processor + */ +struct amd_shmem_info { + struct acpi_pcct_ext_pcc_shared_memory header; + u32 version_number :8, + n_logical_processors :8, + n_capabilities :8, + table_update_context :8; + u32 n_bitmaps :8, + reserved :24; + u32 table_data[]; +}; + struct amd_hfi_data { const char *name; struct device *dev; + + /* PCCT table related */ + struct pcc_mbox_chan *pcc_chan; + void __iomem *pcc_comm_addr; + struct acpi_subtable_header *pcct_entry; + struct amd_shmem_info *shmem; }; +/** + * struct amd_hfi_classes - HFI class capabilities per CPU + * @perf: Performance capability + * @eff: Power efficiency capability + * + * Capabilities of a logical processor in the ranking table. These capabilities + * are unitless and specific to each HFI class. + */ struct amd_hfi_classes { u32 perf; u32 eff; @@ -41,21 +91,106 @@ struct amd_hfi_classes { /** * struct amd_hfi_cpuinfo - HFI workload class info per CPU * @cpu: cpu index + * @apic_id: apic id of the current cpu * @class_index: workload class ID index * @nr_class: max number of workload class supported + * @ipcc_scores: ipcc scores for each class * @amd_hfi_classes: current cpu workload class ranking data * * Parameters of a logical processor linked with hardware feedback class. */ struct amd_hfi_cpuinfo { int cpu; + u32 apic_id; s16 class_index; u8 nr_class; + int *ipcc_scores; struct amd_hfi_classes *amd_hfi_classes; }; static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = -1}; +static int find_cpu_index_by_apicid(unsigned int target_apicid) +{ + int cpu_index; + + for_each_possible_cpu(cpu_index) { + struct cpuinfo_x86 *info = &cpu_data(cpu_index); + + if (info->topo.apicid == target_apicid) { + pr_debug("match APIC id %u for CPU index: %d\n", + info->topo.apicid, cpu_index); + return cpu_index; + } + } + + return -ENODEV; +} + +static int amd_hfi_fill_metadata(struct amd_hfi_data *amd_hfi_data) +{ + struct acpi_pcct_ext_pcc_slave *pcct_ext = + (struct acpi_pcct_ext_pcc_slave *)amd_hfi_data->pcct_entry; + void __iomem *pcc_comm_addr; + u32 apic_start = 0; + + pcc_comm_addr = acpi_os_ioremap(amd_hfi_data->pcc_chan->shmem_base_addr, + amd_hfi_data->pcc_chan->shmem_size); + if (!pcc_comm_addr) { + dev_err(amd_hfi_data->dev, "failed to ioremap PCC common region mem\n"); + return -ENOMEM; + } + + memcpy_fromio(amd_hfi_data->shmem, pcc_comm_addr, pcct_ext->length); + iounmap(pcc_comm_addr); + + if (amd_hfi_data->shmem->header.signature != PCC_SIGNATURE) { + dev_err(amd_hfi_data->dev, "invalid signature in shared memory\n"); + return -EINVAL; + } + if (amd_hfi_data->shmem->version_number != AMD_HETERO_RANKING_TABLE_VER) { + dev_err(amd_hfi_data->dev, "invalid version %d\n", amd_hfi_data->shmem->version_number); + return -EINVAL; + } + + for (unsigned int i = 0; i < amd_hfi_data->shmem->n_bitmaps; i++) { + u32 bitmap = amd_hfi_data->shmem->table_data[i]; + + for (unsigned int j = 0; j < BITS_PER_TYPE(u32); j++) { + u32 apic_id = i * BITS_PER_TYPE(u32) + j; + struct amd_hfi_cpuinfo *info; + int cpu_index, apic_index; + + if (!(bitmap & BIT(j))) + continue; + + cpu_index = find_cpu_index_by_apicid(apic_id); + if (cpu_index < 0) { + dev_warn(amd_hfi_data->dev, "APIC ID %u not found\n", apic_id); + continue; + } + + info = per_cpu_ptr(&amd_hfi_cpuinfo, cpu_index); + info->apic_id = apic_id; + + /* Fill the ranking data for each logical processor */ + info = per_cpu_ptr(&amd_hfi_cpuinfo, cpu_index); + apic_index = apic_start * info->nr_class * 2; + for (unsigned int k = 0; k < info->nr_class; k++) { + u32 *table = amd_hfi_data->shmem->table_data + + amd_hfi_data->shmem->n_bitmaps + + i * info->nr_class; + + info->amd_hfi_classes[k].eff = table[apic_index + 2 * k]; + info->amd_hfi_classes[k].perf = table[apic_index + 2 * k + 1]; + } + apic_start++; + } + } + + return 0; +} + static int amd_hfi_alloc_class_data(struct platform_device *pdev) { struct amd_hfi_cpuinfo *hfi_cpuinfo; @@ -72,6 +207,7 @@ static int amd_hfi_alloc_class_data(struct platform_device *pdev) for_each_possible_cpu(idx) { struct amd_hfi_classes *classes; + int *ipcc_scores; classes = devm_kcalloc(dev, nr_class_id, @@ -79,14 +215,71 @@ static int amd_hfi_alloc_class_data(struct platform_device *pdev) GFP_KERNEL); if (!classes) return -ENOMEM; + ipcc_scores = devm_kcalloc(dev, nr_class_id, sizeof(int), GFP_KERNEL); + if (!ipcc_scores) + return -ENOMEM; hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, idx); hfi_cpuinfo->amd_hfi_classes = classes; + hfi_cpuinfo->ipcc_scores = ipcc_scores; hfi_cpuinfo->nr_class = nr_class_id; } return 0; } +static int amd_hfi_metadata_parser(struct platform_device *pdev, + struct amd_hfi_data *amd_hfi_data) +{ + struct acpi_pcct_ext_pcc_slave *pcct_ext; + struct acpi_subtable_header *pcct_entry; + struct mbox_chan *pcc_mbox_channels; + struct acpi_table_header *pcct_tbl; + struct pcc_mbox_chan *pcc_chan; + acpi_status status; + int ret; + + pcc_mbox_channels = devm_kcalloc(&pdev->dev, AMD_HFI_MAILBOX_COUNT, + sizeof(*pcc_mbox_channels), GFP_KERNEL); + if (!pcc_mbox_channels) + return -ENOMEM; + + pcc_chan = devm_kcalloc(&pdev->dev, AMD_HFI_MAILBOX_COUNT, + sizeof(*pcc_chan), GFP_KERNEL); + if (!pcc_chan) + return -ENOMEM; + + status = acpi_get_table(ACPI_SIG_PCCT, 0, &pcct_tbl); + if (ACPI_FAILURE(status) || !pcct_tbl) + return -ENODEV; + + /* get pointer to the first PCC subspace entry */ + pcct_entry = (struct acpi_subtable_header *) ( + (unsigned long)pcct_tbl + sizeof(struct acpi_table_pcct)); + + pcc_chan->mchan = &pcc_mbox_channels[0]; + + amd_hfi_data->pcc_chan = pcc_chan; + amd_hfi_data->pcct_entry = pcct_entry; + pcct_ext = (struct acpi_pcct_ext_pcc_slave *)pcct_entry; + + if (pcct_ext->length <= 0) + return -EINVAL; + + amd_hfi_data->shmem = devm_kzalloc(amd_hfi_data->dev, pcct_ext->length, GFP_KERNEL); + if (!amd_hfi_data->shmem) + return -ENOMEM; + + pcc_chan->shmem_base_addr = pcct_ext->base_address; + pcc_chan->shmem_size = pcct_ext->length; + + /* parse the shared memory info from the PCCT table */ + ret = amd_hfi_fill_metadata(amd_hfi_data); + + acpi_put_table(pcct_tbl); + + return ret; +} + static const struct acpi_device_id amd_hfi_platform_match[] = { {"AMDI0104", 0}, { } @@ -112,6 +305,10 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret) return ret; + ret = amd_hfi_metadata_parser(pdev, amd_hfi_data); + if (ret) + return ret; + return 0; } From patchwork Thu May 15 21:19:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 890802 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B302296737; Thu, 15 May 2025 21:20:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344011; cv=none; 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Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan Subject: [PATCH v10 06/13] platform/x86: hfi: init per-cpu scores for each class Date: Thu, 15 May 2025 16:19:43 -0500 Message-ID: <20250515211950.3102922-7-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515211950.3102922-1-superm1@kernel.org> References: <20250515211950.3102922-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Initialize per cpu score `amd_hfi_ipcc_scores` which store energy score and performance score data for each class. `Classic core` and `Dense core` are ranked according to those values as energy efficiency capability or performance capability. OS scheduler will pick cores from the ranking list on each class ID for the thread which provide the class id got from hardware feedback interface. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- drivers/platform/x86/amd/hfi/hfi.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 17ce5302cb531..f63c6098b7d92 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -227,6 +227,31 @@ static int amd_hfi_alloc_class_data(struct platform_device *pdev) return 0; } +static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) +{ + for (int i = 0; i < hfi_cpuinfo->nr_class; i++) + WRITE_ONCE(hfi_cpuinfo->ipcc_scores[i], + hfi_cpuinfo->amd_hfi_classes[i].perf); + + return 0; +} + +static int update_hfi_ipcc_scores(void) +{ + int cpu; + int ret; + + for_each_possible_cpu(cpu) { + struct amd_hfi_cpuinfo *hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, cpu); + + ret = amd_set_hfi_ipcc_score(hfi_cpuinfo, cpu); + if (ret) + return ret; + } + + return 0; +} + static int amd_hfi_metadata_parser(struct platform_device *pdev, struct amd_hfi_data *amd_hfi_data) { @@ -309,6 +334,10 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret) return ret; + ret = update_hfi_ipcc_scores(); + if (ret) + return ret; + return 0; } From patchwork Thu May 15 21:19:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 890515 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA6D92980C2; Thu, 15 May 2025 21:20:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344012; cv=none; b=Ol+k5/+0qekLBSVdgCXs1lbxrfEzLw+IFRN05dl6nwfU7hbQbNSOST5V/jEJlJdNe0Xsd4xMblzcdv4Eynx4kU0EUEPhLgtY/Xul0J6geg4hVIwtUuRfx0R/YQfTZMJEW5SHwp89OOKeUVLTb612rE78tWNUHl5espyw/M9CRB4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344012; c=relaxed/simple; bh=A0FC2mvV2rPlmta1Mg6wircukWWwgVftb+fTVkaFLqM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EGvKmxhNYKrZKtaiLsBqDFpE+MEeDDzzlLEpFmKIHeL6xuClPghKa+ZVjPYu20GvDhUReVMnDiRp9jQz8iLUlbbC9cDTbrhTgTb+5LSsxoLv8Sj7BYijG0PPH8YB3QdFJtcTVtSFD7xilfygFbweFW1mLnoDpEXM3tWxYQkZKoA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dVi3Hh1d; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dVi3Hh1d" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DF4F0C4CEEF; Thu, 15 May 2025 21:20:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747344012; bh=A0FC2mvV2rPlmta1Mg6wircukWWwgVftb+fTVkaFLqM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dVi3Hh1daGD0ZwXUNT5AfL/HETHw2Q3KdSWknbsEyZDY8TuLPyL9J3Uzwq1DZsHMR Gf8ALU+H2Q4SBtAw3IIjXnWUoOw0sKUPihTwa/2WtlRG1CCUD0vwgt2ls9i/1GFT6M 41NAt3KFq2ZlJ/exT+fMy05gnaC7t9hCQOH0OqW1mgll207/73HK7U7Dj2j2kv9hte dpZ11GimwaydO/BI8QHx/6FcY/LnivNEuiAMvMhK/4gEcM8/u86tjnz7ZJJmws0a3X riA6qN2etcLFNS9WY0wI6Be88+SfsYaa15EKDNQLK0DmwCuU9RzELRswihUpV1HLVI 3FXGNtaDRPKUg== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan Subject: [PATCH v10 07/13] platform/x86: hfi: add online and offline callback support Date: Thu, 15 May 2025 16:19:44 -0500 Message-ID: <20250515211950.3102922-8-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515211950.3102922-1-superm1@kernel.org> References: <20250515211950.3102922-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan There are some firmware parameters that need to be configured when a CPU core is brought online or offline. when CPU is online, it will initialize the workload classification parameters to CPU firmware which will trigger the workload class ID updating function. Once the CPU is going to offline, it will need to disable the workload classification function and clear the history. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- drivers/platform/x86/amd/hfi/hfi.c | 88 ++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index f63c6098b7d92..1472214dc809f 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -92,6 +92,7 @@ struct amd_hfi_classes { * struct amd_hfi_cpuinfo - HFI workload class info per CPU * @cpu: cpu index * @apic_id: apic id of the current cpu + * @cpus: mask of cpus associated with amd_hfi_cpuinfo * @class_index: workload class ID index * @nr_class: max number of workload class supported * @ipcc_scores: ipcc scores for each class @@ -102,6 +103,7 @@ struct amd_hfi_classes { struct amd_hfi_cpuinfo { int cpu; u32 apic_id; + cpumask_var_t cpus; s16 class_index; u8 nr_class; int *ipcc_scores; @@ -110,6 +112,8 @@ struct amd_hfi_cpuinfo { static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = -1}; +static DEFINE_MUTEX(hfi_cpuinfo_lock); + static int find_cpu_index_by_apicid(unsigned int target_apicid) { int cpu_index; @@ -236,6 +240,81 @@ static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) return 0; } +static int amd_hfi_set_state(unsigned int cpu, bool state) +{ + int ret; + + ret = wrmsrq_on_cpu(cpu, AMD_WORKLOAD_CLASS_CONFIG, state ? 1 : 0); + if (ret) + return ret; + + return wrmsrq_on_cpu(cpu, AMD_WORKLOAD_HRST, 0x1); +} + +/** + * amd_hfi_online() - Enable workload classification on @cpu + * @cpu: CPU in which the workload classification will be enabled + * + * Return: 0 on success, negative error code on failure. + */ +static int amd_hfi_online(unsigned int cpu) +{ + struct amd_hfi_cpuinfo *hfi_info = per_cpu_ptr(&amd_hfi_cpuinfo, cpu); + struct amd_hfi_classes *hfi_classes; + int ret; + + if (WARN_ON_ONCE(!hfi_info)) + return -EINVAL; + + /* + * Check if @cpu as an associated, initialized and ranking data must + * be filled. + */ + hfi_classes = hfi_info->amd_hfi_classes; + if (!hfi_classes) + return -EINVAL; + + guard(mutex)(&hfi_cpuinfo_lock); + + if (!zalloc_cpumask_var(&hfi_info->cpus, GFP_KERNEL)) + return -ENOMEM; + + cpumask_set_cpu(cpu, hfi_info->cpus); + + ret = amd_hfi_set_state(cpu, true); + if (ret) + pr_err("WCT enable failed for CPU %u\n", cpu); + + return ret; +} + +/** + * amd_hfi_offline() - Disable workload classification on @cpu + * @cpu: CPU in which the workload classification will be disabled + * + * Remove @cpu from those covered by its HFI instance. + * + * Return: 0 on success, negative error code on failure + */ +static int amd_hfi_offline(unsigned int cpu) +{ + struct amd_hfi_cpuinfo *hfi_info = &per_cpu(amd_hfi_cpuinfo, cpu); + int ret; + + if (WARN_ON_ONCE(!hfi_info)) + return -EINVAL; + + guard(mutex)(&hfi_cpuinfo_lock); + + ret = amd_hfi_set_state(cpu, false); + if (ret) + pr_err("WCT disable failed for CPU %u\n", cpu); + + free_cpumask_var(hfi_info->cpus); + + return ret; +} + static int update_hfi_ipcc_scores(void) { int cpu; @@ -338,6 +417,15 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret) return ret; + /* + * Tasks will already be running at the time this happens. This is + * OK because rankings will be adjusted by the callbacks. + */ + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/amd_hfi:online", + amd_hfi_online, amd_hfi_offline); + if (ret < 0) + return ret; + return 0; } From patchwork Thu May 15 21:19:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 890801 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF4F12882B7; Thu, 15 May 2025 21:20:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344014; cv=none; b=TducJFfq5zZ9dGLtwd/pT8096SQdgKMlRks14p+MndjUHL4O7abyPy81tC8K8gnFMRieJNkbnLh0kJEZNdLobo8Pp14462vKnaqALfM3cgB+1dcXj5MFvVELqvFg87ZYiJ+zwhNNGCM9Zp5IbSwzzmO/LwVVkAgnJIqlVADS5AU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344014; c=relaxed/simple; bh=wxhYEGNpiWIhzH7Mo/pycoZJIumcH7mRdwRvDFsadCM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ez2N13uBjQlc7TMZjP0rAD2EvMBE97FY+Ms6Vjovrt2u3zMCeoBy59hPn+KJf0I5bYIqTWQ+Uwxgd7wxtcMu1ZcwSGVPb4cY9wkouwTPGNoJUU26U+ri4GYDU0XFM6i3ooGuAAuBAD2Ks/+JeNj7wEPYx4TuO1ZlyBV+oykX+iU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TxkWCYLs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TxkWCYLs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EA966C4CEED; Thu, 15 May 2025 21:20:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747344014; bh=wxhYEGNpiWIhzH7Mo/pycoZJIumcH7mRdwRvDFsadCM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TxkWCYLsgHuqMVLL5ezLFOw6ZuF2qHk5Cah2jQYg0g1ulaat/3p5LWEfhPS4nqQey bfKKSFbn4OFs15nZeBOyT5PWzDD+4IMbO0gqk0b3VxIHcHKXvjOe6gmnlUXx4vavwG eu5A30n1x0jzTI/vkef9gbmZ0NzFawLzC6Yre47Ps1lEn82Mzw9zXj6lsijo/H/AsK f1VE90SNEUox3Ghosr7CpgsYuI/X5BHndxbRpTFj7v1BQL79OdreaL6q4kbmUx54Q3 tkgmRl6WFgtwF3hnfKMQRH3gMShIIxdmiV1kaLJ7pZuMLn1PFWOQw0Hj2qVrd4NT3A QyrnBLv7M1QrA== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER), Perry Yuan Subject: [PATCH v10 08/13] platform/x86: hfi: add power management callback Date: Thu, 15 May 2025 16:19:45 -0500 Message-ID: <20250515211950.3102922-9-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515211950.3102922-1-superm1@kernel.org> References: <20250515211950.3102922-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Introduces power management callbacks for the `amd_hfi` driver. Specifically, the `suspend` and `resume` callbacks have been added to handle the necessary operations during system low power states and wake-up. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- drivers/platform/x86/amd/hfi/hfi.c | 33 ++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 1472214dc809f..921e07acf2ff1 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -384,6 +384,38 @@ static int amd_hfi_metadata_parser(struct platform_device *pdev, return ret; } +static int amd_hfi_pm_resume(struct device *dev) +{ + int ret, cpu; + + for_each_online_cpu(cpu) { + ret = amd_hfi_set_state(cpu, true); + if (ret < 0) { + dev_err(dev, "failed to enable workload class config: %d\n", ret); + return ret; + } + } + + return 0; +} + +static int amd_hfi_pm_suspend(struct device *dev) +{ + int ret, cpu; + + for_each_online_cpu(cpu) { + ret = amd_hfi_set_state(cpu, false); + if (ret < 0) { + dev_err(dev, "failed to disable workload class config: %d\n", ret); + return ret; + } + } + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(amd_hfi_pm_ops, amd_hfi_pm_suspend, amd_hfi_pm_resume); + static const struct acpi_device_id amd_hfi_platform_match[] = { {"AMDI0104", 0}, { } @@ -433,6 +465,7 @@ static struct platform_driver amd_hfi_driver = { .driver = { .name = AMD_HFI_DRIVER, .owner = THIS_MODULE, + .pm = &amd_hfi_pm_ops, .acpi_match_table = ACPI_PTR(amd_hfi_platform_match), }, .probe = amd_hfi_probe, From patchwork Thu May 15 21:19:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 890514 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8EAB2980C2; Thu, 15 May 2025 21:20:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344016; cv=none; b=jDc+zhcfigpm0Sqd5lTSHMa1KQiQa29LfTYwVpKXNS9l53yP1NUoj/MNlvmFCoJKRQzoItGlePtYyP7T4fVpL38YZGeyIcxDkuAdq4lzPxpzPearUGMlSBDGSPafUVEnSpvLGzPmuhPuaw+4uLKMJwngc5d+mUesloxfM9Ki8+Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344016; c=relaxed/simple; bh=wNnL8W6bUGlGgnFxf75mSRXIwH84JOfIf/StjigsqEU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IstQdrp5J5hk2/vhDJT2DBzD8WYgxjcwXMxuUHzFaTtsQJb/3T8EEq7L1zN99Hnu/qPkhTLP1VRkInHIecfNQfO8A3z4EtEXB/DEMbyh9atssE40+jlvOY/zvVo7zQmBwYYxs58drwpaqt8ohw5hH41Kup+a6GBtfuODlg+Ralo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=utRktGWo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="utRktGWo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EBD9EC4CEF0; Thu, 15 May 2025 21:20:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747344016; bh=wNnL8W6bUGlGgnFxf75mSRXIwH84JOfIf/StjigsqEU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=utRktGWowgBPaC9dRb7s6b9yYSAYm6/gVc6NAgOk+ESa/XR+bm6Gnu9TdCyZNULU1 pRSs4vT+Rc3gmHPMObvWUui6ckxfjQvzPt8GoHU+ehBz8jmvtA438KmxPO81PvIlbc Qt2bZxspXAjCgENaYOgZuALQj8boYeXAQFQR96yvTAjZq68VlG+YkgEldkK0DAOYTE 2g2elRS89aaOmg+Rj3/ILK4Lrl2hDzNqL5M4WL1EKr+NpHMAoDZMI69T5NAmALePv0 EpuhuR6AT6Mx5Ykbx2ao5pnn+TBYBHsJLCPwAMC5UKoh41zakOiOXcb3Ind2kWjVc3 0sVL7YWNmIlDw== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v10 09/13] x86/process: Clear hardware feedback history for AMD processors Date: Thu, 15 May 2025 16:19:46 -0500 Message-ID: <20250515211950.3102922-10-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515211950.3102922-1-superm1@kernel.org> References: <20250515211950.3102922-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Perry Yuan Incorporate a mechanism within the context switching code to reset the hardware history for AMD processors. Specifically, when a task is switched in, the class ID was read and reset the hardware workload classification history of CPU firmware and then it start to trigger workload classification for the next running thread. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- arch/x86/kernel/process_64.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index f39ff02e498d7..3ceb93b784013 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -707,6 +707,10 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Load the Intel cache allocation PQR MSR. */ resctrl_sched_in(next_p); + /* Reset hw history on AMD CPUs */ + if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS)) + wrmsrl(AMD_WORKLOAD_HRST, 0x1); + return prev_p; } From patchwork Thu May 15 21:19:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 890800 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 184D229C339; Thu, 15 May 2025 21:20:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344019; cv=none; b=VfV+qhA84RXmu0PmxWD932vSxbz51r4/uLFIDIPhFQI1Bph1B0YbB+eYKC5UGbYNgkwJ5B707r1rgWP4u/3vbawC2nPThvemQ1p0SgFcxlrRyX4SGjvczCpDTqgQkK5w/wkaTfiOtjMdiJl9eo+nyW8nz8m/3VgWwJPEOp36bis= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344019; c=relaxed/simple; bh=jwHq1Dgz4Xlf3NTJxaMhCnIsdmCBSmUIMBR+/cZEj8Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aB+D4yzXiBbkl4WarKcOh7+NDQdNBryUapQaOe3jtskjSVyruzC+lOWw0TyVcnX8caokr2ZnXg3gqArgWFDy2rdzO2ax7+Jp21W0xSUhFZIn11RNo10pp3Eu1ygZ+4NDGO0Lt1hS5cy1xgEslaqLgYhLWanDd5nbf/mopCBet0Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PVFb4tf+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PVFb4tf+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D9BC6C4CEF1; Thu, 15 May 2025 21:20:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747344018; bh=jwHq1Dgz4Xlf3NTJxaMhCnIsdmCBSmUIMBR+/cZEj8Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PVFb4tf+h3F0gnbuUp/oWHIV5JfiFqkb4Vkyi7JuU6mWrgo9qFl+t+1HEjdxbhIxh HEB832jQkY/lYyTlerK2fiM0b2IzTNHm7CnizGZlyDkqhpl5hckzkn+/P7BqjahTNg x/h6fPZ4gayc9D1BnynN63yT65nLHcyUddoVq+AKyN4322k+Q4S9VyZzLTfdZZHBmQ 16HzvetqEpVD/BzvnmzgaGBrOKiEIdD57l9fcEi8dtZlWq6VicbkYy76sgJDOYFF/U 5xmRMTzMJP4CPSkE1xTimgl12I+WpOKadAzDqt83D3tui3wdB7mSsHWq/3H8z1qc6X 9XnoZDhWZ4bGg== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v10 10/13] cpufreq/amd-pstate: Disable preferred cores on designs with workload classification Date: Thu, 15 May 2025 16:19:47 -0500 Message-ID: <20250515211950.3102922-11-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515211950.3102922-1-superm1@kernel.org> References: <20250515211950.3102922-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello On designs that have workload classification, it's preferred that the amd-hfi driver is used to provide hints to the scheduler of which cores to use instead of the amd-pstate driver. Reviewed-by: Gautham R. Shenoy Reviewed-by: Perry Yuan Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 66fdc74f13ef4..bdaf2034aaa10 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -801,6 +801,12 @@ static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) /* user disabled or not detected */ if (!amd_pstate_prefcore) return; + /* should use amd-hfi instead */ + if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS) && + IS_ENABLED(CONFIG_AMD_HFI)) { + amd_pstate_prefcore = false; + return; + } cpudata->hw_prefcore = true; From patchwork Thu May 15 21:19:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 890513 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EFF4029C33E; Thu, 15 May 2025 21:20:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344021; cv=none; b=tLGgPWNPy6xHKk7JZ9jZ1kYtpLgRswVVfGvZlCNIt8v8gg/yR+gtMmC8uLSZImussPkDMqHbUtqGbheub7C8ogs2U24xZB28U7S/VkkwPIehgGciOxmercWMoD1VgmXNAHw/BIGjanj6CSCk3pfCLSqpozcDc9HLuJxaNgljICI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344021; c=relaxed/simple; bh=oHtRIsAptTXF54+4BJ34mKmBZlrungbNMyhnHWfvkmQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GxIuhvuQ1vtyjfP0UigplvuJ/LETSvN4Odhr4SXs5RtUy2o0oc+t9NNOit0YuviB7kla3jXs8j/D1URv5UMMqGsPhmWLiD9Z+4oz+j9bjss6S41LGiUqrkSEgehyex9oLzpdsc0Dotk7j5ksTKMXzVHtOvsbSwkZI/X/FS2mqRo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rgqMLdBh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rgqMLdBh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BDCFDC4CEF0; Thu, 15 May 2025 21:20:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747344020; bh=oHtRIsAptTXF54+4BJ34mKmBZlrungbNMyhnHWfvkmQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rgqMLdBh4HHkLxDE2dm7yZzg683Lk4TI5wewdTUI/e2STalfYfOeqKvIlHT6mamkT Lr+L0LFv8hO+CnMs+I7EZba/PpP0RErg6GT82vccAKmKxqbbTleM3UzNaYebQ2zCxr 2DR0J+EO944yTTk2YUfrhMmjKAJdnav9T2tR6FOG+GXOecQzcNYOgvQMQIYcnMC63h u2BmjNZ3xgVGJhablmGJN1rMGxxuViO+83sbbxgoyokVRPyZo5GtICG0R4ZhwlOu51 GjYrox8nFpSSuTmLewLd/I2sII6cEK0P3ExSbScm7F3X9frW2aAufxvBTbEoZRf972 WY0iTKuBmB5iw== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v10 11/13] platform/x86/amd: hfi: Set ITMT priority from ranking data Date: Thu, 15 May 2025 16:19:48 -0500 Message-ID: <20250515211950.3102922-12-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515211950.3102922-1-superm1@kernel.org> References: <20250515211950.3102922-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello The static ranking data that is read at module load should be used to set up the priorities for the cores relative to the performance values. Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- drivers/platform/x86/amd/hfi/Kconfig | 1 + drivers/platform/x86/amd/hfi/hfi.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/Kconfig b/drivers/platform/x86/amd/hfi/Kconfig index 476e4a9ed67a9..75b0f73407047 100644 --- a/drivers/platform/x86/amd/hfi/Kconfig +++ b/drivers/platform/x86/amd/hfi/Kconfig @@ -7,6 +7,7 @@ config AMD_HFI bool "AMD Hetero Core Hardware Feedback Driver" depends on ACPI depends on CPU_SUP_AMD + depends on SCHED_MC_PRIO help Select this option to enable the AMD Heterogeneous Core Hardware Feedback Interface. If selected, hardware provides runtime thread diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 921e07acf2ff1..22a5bf977daf5 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -114,6 +114,12 @@ static DEFINE_PER_CPU(struct amd_hfi_cpuinfo, amd_hfi_cpuinfo) = {.class_index = static DEFINE_MUTEX(hfi_cpuinfo_lock); +static void amd_hfi_sched_itmt_work(struct work_struct *work) +{ + sched_set_itmt_support(); +} +static DECLARE_WORK(sched_amd_hfi_itmt_work, amd_hfi_sched_itmt_work); + static int find_cpu_index_by_apicid(unsigned int target_apicid) { int cpu_index; @@ -237,6 +243,8 @@ static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) WRITE_ONCE(hfi_cpuinfo->ipcc_scores[i], hfi_cpuinfo->amd_hfi_classes[i].perf); + sched_set_itmt_core_prio(hfi_cpuinfo->ipcc_scores[0], cpu); + return 0; } @@ -458,6 +466,8 @@ static int amd_hfi_probe(struct platform_device *pdev) if (ret < 0) return ret; + schedule_work(&sched_amd_hfi_itmt_work); + return 0; } From patchwork Thu May 15 21:19:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 890799 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6CF129CB4C; Thu, 15 May 2025 21:20:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344023; cv=none; b=PZrBfzwDduE2PltEjHb6vp9H8143COAKEawIqKOczcp49tBRFTn27CaYJx4vFC42/ZIZBtV+gN1TnnNm+YidkuZ/xW+DXdVCJioujqkPxFtOhrKZhUNZozD0Jdwt3WfpCMSi3o+UUMcJ8Gz6HSLQfX0QXxCARs3opcrbC9Y6+c4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344023; c=relaxed/simple; bh=9RclwTvkbddnT6kR7d8w74N4/VbFnr277HYosPXZksY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TnIe0mZoYKOTZWryfpLoK1dVVSP8BG8ScqRGOQqFwLkfhgcwQmEbdCuJzNzE/meMOOXQ6HN61A/b9/rX9VhAxhKferEAvG1mtjPw3ZkKzp1UfSEgasqXxn8SZu1OKZzVhzr/CBGrnwiX71MsfA9xFRcQsV9puxujJ6kXiM/OOEg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CK1msQhP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CK1msQhP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A17B1C4CEF1; Thu, 15 May 2025 21:20:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747344022; bh=9RclwTvkbddnT6kR7d8w74N4/VbFnr277HYosPXZksY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CK1msQhPGGTBKz9UcO8D8kLueYoCqxWd+pyIb1Do1abl6LIo6izs9+jGmw89CSQ/t rRa3ck1JhrJIfwDUaH7ZsfaqWixEDApTaX+oR4Pou8dr1lPFyoxjjqK/KM6UAu3N1z zcOWyYE3Wt0zcEs7+Ok1JQxWznJn9xfdScLES2up2eO1AJeO0zZvSJwJ3z2TUcmw5/ tgFucwhec2Lc3+/HJx9OrM17/mNy+9KoNIZhhnk43w11cCcze8oAX4DOJVtNaeame3 71BzofHQPNsTUk/HVWV240bYOvSIyw5pO1ClJJ7VewXGdUQQX1lcWkShMoHqxJsWWk 7r1/Avk7x7qGw== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v10 12/13] platform/x86/amd: hfi: Add debugfs support Date: Thu, 15 May 2025 16:19:49 -0500 Message-ID: <20250515211950.3102922-13-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515211950.3102922-1-superm1@kernel.org> References: <20250515211950.3102922-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello Add a dump of the class and capabilities table to debugfs to assist with debugging scheduler issues. Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- drivers/platform/x86/amd/hfi/hfi.c | 35 ++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 22a5bf977daf5..0d6966f138bc6 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -73,6 +74,8 @@ struct amd_hfi_data { void __iomem *pcc_comm_addr; struct acpi_subtable_header *pcct_entry; struct amd_shmem_info *shmem; + + struct dentry *dbgfs_dir; }; /** @@ -237,6 +240,13 @@ static int amd_hfi_alloc_class_data(struct platform_device *pdev) return 0; } +static void amd_hfi_remove(struct platform_device *pdev) +{ + struct amd_hfi_data *dev = platform_get_drvdata(pdev); + + debugfs_remove_recursive(dev->dbgfs_dir); +} + static int amd_set_hfi_ipcc_score(struct amd_hfi_cpuinfo *hfi_cpuinfo, int cpu) { for (int i = 0; i < hfi_cpuinfo->nr_class; i++) @@ -392,6 +402,26 @@ static int amd_hfi_metadata_parser(struct platform_device *pdev, return ret; } +static int class_capabilities_show(struct seq_file *s, void *unused) +{ + u32 cpu, idx; + + seq_puts(s, "CPU #\tWLC\tPerf\tEff\n"); + for_each_possible_cpu(cpu) { + struct amd_hfi_cpuinfo *hfi_cpuinfo = per_cpu_ptr(&amd_hfi_cpuinfo, cpu); + + seq_printf(s, "%d", cpu); + for (idx = 0; idx < hfi_cpuinfo->nr_class; idx++) { + seq_printf(s, "\t%u\t%u\t%u\n", idx, + hfi_cpuinfo->amd_hfi_classes[idx].perf, + hfi_cpuinfo->amd_hfi_classes[idx].eff); + } + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(class_capabilities); + static int amd_hfi_pm_resume(struct device *dev) { int ret, cpu; @@ -468,6 +498,10 @@ static int amd_hfi_probe(struct platform_device *pdev) schedule_work(&sched_amd_hfi_itmt_work); + amd_hfi_data->dbgfs_dir = debugfs_create_dir("amd_hfi", arch_debugfs_dir); + debugfs_create_file("class_capabilities", 0644, amd_hfi_data->dbgfs_dir, pdev, + &class_capabilities_fops); + return 0; } @@ -479,6 +513,7 @@ static struct platform_driver amd_hfi_driver = { .acpi_match_table = ACPI_PTR(amd_hfi_platform_match), }, .probe = amd_hfi_probe, + .remove = amd_hfi_remove, }; static int __init amd_hfi_init(void) From patchwork Thu May 15 21:19:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 890512 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E98E29DB69; Thu, 15 May 2025 21:20:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344024; cv=none; b=EfheTduqp+q5JYnMnWn5wFhJIET5b969pNjCk6zVkMAyVAfApdBCihaxGFFZKBizGkOHLdVvVTIWnpLkhEjISjjUsF/kTrypU48vmtGU5IccFxAQx7j7tRjwOVkJ7CPzHOUIvFKrfA0OVwfFogmregxwjVxQefOm9ktmmTyC2zA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747344024; c=relaxed/simple; bh=ccxi92/CdYcFz5SRXc75fcFWq7DUZRAtA96LadU0vMs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=my4P3RsIETlE7AO9sxP80OQOkhLWv/5gxSVO3VyWDjKgESVddb8LSbFGLAR+t+3dUXwbaYYCzOmQpVeiDEPUGuch2i++NrBlZWws2ZU//kceGyfqdZyG6r3oSOvlDIftz01sFMcQt9OBYGE1ZXVy8nJcg4AL957O+EZEPCaZwzw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GOZTCYE1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GOZTCYE1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C90BEC4CEE7; Thu, 15 May 2025 21:20:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747344024; bh=ccxi92/CdYcFz5SRXc75fcFWq7DUZRAtA96LadU0vMs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GOZTCYE1AfYxSnTPuiMx3EDc6y/a2uA5klS8tlrZUT+kTUswdV2mpHwHq2PtgCZ2D beD2/4FeQp06ZQGtEqdbeuWVZ+ZMTrBW5jJiaMuEgixFX5CPKyBQt1anoB+RaBO7yN 0B39LvVbQ25TALtekJjBCIGICa8Q0xb9G801WX9SEWofhEgbPlPN2jMMfPrGl3U+Fz Xu3Y3HBREIsStb/Eu4Z1ZmQQdoneTyPpd3glVAQzHIYAP6Xe7hIWsqpUoe/Fb0Prfu JiJDWPTpLQvmVxenU7fFJqIE/z6JwYfdWzEkxLzURnyRL9Y75xkm2OCFrVUxCBVqlc RLRGWTk2EeeLg== From: Mario Limonciello To: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: Mario Limonciello , Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), "H . Peter Anvin" , Jonathan Corbet , Huang Rui , "Gautham R . Shenoy" , "Rafael J . Wysocki" , Viresh Kumar , platform-driver-x86@vger.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-pm@vger.kernel.org (open list:AMD PSTATE DRIVER) Subject: [PATCH v10 13/13] x86/itmt: Add debugfs file to show core priorities Date: Thu, 15 May 2025 16:19:50 -0500 Message-ID: <20250515211950.3102922-14-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250515211950.3102922-1-superm1@kernel.org> References: <20250515211950.3102922-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Mario Limonciello Multiple drivers can report priorities to ITMT. To aid in debugging any issues with the values reported by drivers introduce a debugfs file to read out the values. Signed-off-by: Mario Limonciello --- arch/x86/kernel/itmt.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/x86/kernel/itmt.c b/arch/x86/kernel/itmt.c index 9cea1fc36c18f..243a769fdd97b 100644 --- a/arch/x86/kernel/itmt.c +++ b/arch/x86/kernel/itmt.c @@ -59,6 +59,18 @@ static ssize_t sched_itmt_enabled_write(struct file *filp, return result; } +static int sched_core_priority_show(struct seq_file *s, void *unused) +{ + int cpu; + + seq_puts(s, "CPU #\tPriority\n"); + for_each_possible_cpu(cpu) + seq_printf(s, "%d\t%d\n", cpu, arch_asym_cpu_priority(cpu)); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(sched_core_priority); + static const struct file_operations dfs_sched_itmt_fops = { .read = debugfs_read_file_bool, .write = sched_itmt_enabled_write, @@ -67,6 +79,7 @@ static const struct file_operations dfs_sched_itmt_fops = { }; static struct dentry *dfs_sched_itmt; +static struct dentry *dfs_sched_core_prio; /** * sched_set_itmt_support() - Indicate platform supports ITMT @@ -102,6 +115,14 @@ int sched_set_itmt_support(void) return -ENOMEM; } + dfs_sched_core_prio = debugfs_create_file("sched_core_priority", 0644, + arch_debugfs_dir, NULL, + &sched_core_priority_fops); + if (IS_ERR_OR_NULL(dfs_sched_core_prio)) { + dfs_sched_core_prio = NULL; + return -ENOMEM; + } + sched_itmt_capable = true; sysctl_sched_itmt_enabled = 1; @@ -133,6 +154,8 @@ void sched_clear_itmt_support(void) debugfs_remove(dfs_sched_itmt); dfs_sched_itmt = NULL; + debugfs_remove(dfs_sched_core_prio); + dfs_sched_core_prio = NULL; if (sysctl_sched_itmt_enabled) { /* disable sched_itmt if we are no longer ITMT capable */