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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id d13sm1981397ilo.40.2020.06.11.12.48.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2020 12:48:38 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net v2 1/4] net: ipa: program metadata mask differently Date: Thu, 11 Jun 2020 14:48:30 -0500 Message-Id: <20200611194833.2640177-2-elder@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200611194833.2640177-1-elder@linaro.org> References: <20200611194833.2640177-1-elder@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The way the mask value is programmed for QMAP RX endpoints was based on some wrong assumptions about the way metadata containing the QMAP mux_id value is formatted. The metadata value supplied by the modem is *not* in QMAP format, and in fact contains the mux_id we want in its (big endian) low-order byte. That byte must be written by the IPA into offset 1 of the QMAP header it inserts before the received packet. QMAP TX endpoints *do* use a QMAP header as the metadata sent with each packet. The modem assumes this, and based on that assumes the mux_id is in the second byte. To match those assumptions we must program the modem TX (QMAP) endpoint HDR register to indicate the metadata will be found at offset 0 in the message header. The previous configuration managed to work, but it was not working correctly. This patch fixes a bug whose symptom was receipt of messages containing the wrong QMAP mux_id. In fixing this, get rid of ipa_rmnet_mux_id_metadata_mask(), which was more or less defined so there was a separate place to explain what was happening as we generated the mask value. Instead, put a longer description of how this works above ipa_endpoint_init_hdr(), and define the metadata mask to use as a simple constant. Signed-off-by: Alex Elder --- v2: Added back the static specifier to ipa_endpoint_init_hdr(), as suggested by the kernel test robot . drivers/net/ipa/ipa_endpoint.c | 72 ++++++++++++++++++---------------- 1 file changed, 39 insertions(+), 33 deletions(-) -- 2.25.1 diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 66649a806dd1..2825dca23ec4 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -32,6 +32,9 @@ /* The amount of RX buffer space consumed by standard skb overhead */ #define IPA_RX_BUFFER_OVERHEAD (PAGE_SIZE - SKB_MAX_ORDER(NET_SKB_PAD, 0)) +/* Where to find the QMAP mux_id for a packet within modem-supplied metadata */ +#define IPA_ENDPOINT_QMAP_METADATA_MASK 0x000000ff /* host byte order */ + #define IPA_ENDPOINT_RESET_AGGR_RETRY_MAX 3 #define IPA_AGGR_TIME_LIMIT_DEFAULT 1000 /* microseconds */ @@ -433,6 +436,24 @@ static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint) iowrite32(val, endpoint->ipa->reg_virt + offset); } +/** + * We program QMAP endpoints so each packet received is preceded by a QMAP + * header structure. The QMAP header contains a 1-byte mux_id and 2-byte + * packet size field, and we have the IPA hardware populate both for each + * received packet. The header is configured (in the HDR_EXT register) + * to use big endian format. + * + * The packet size is written into the QMAP header's pkt_len field. That + * location is defined here using the HDR_OFST_PKT_SIZE field. + * + * The mux_id comes from a 4-byte metadata value supplied with each packet + * by the modem. It is *not* a QMAP header, but it does contain the mux_id + * value that we want, in its low-order byte. A bitmask defined in the + * endpoint's METADATA_MASK register defines which byte within the modem + * metadata contains the mux_id. And the OFST_METADATA field programmed + * here indicates where the extracted byte should be placed within the QMAP + * header. + */ static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint) { u32 offset = IPA_REG_ENDP_INIT_HDR_N_OFFSET(endpoint->endpoint_id); @@ -441,25 +462,31 @@ static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint) if (endpoint->data->qmap) { size_t header_size = sizeof(struct rmnet_map_header); + /* We might supply a checksum header after the QMAP header */ if (endpoint->toward_ipa && endpoint->data->checksum) header_size += sizeof(struct rmnet_map_ul_csum_header); - val |= u32_encode_bits(header_size, HDR_LEN_FMASK); - /* metadata is the 4 byte rmnet_map header itself */ - val |= HDR_OFST_METADATA_VALID_FMASK; - val |= u32_encode_bits(0, HDR_OFST_METADATA_FMASK); - /* HDR_ADDITIONAL_CONST_LEN is 0; (IPA->AP only) */ + + /* Define how to fill mux_id in a received QMAP header */ if (!endpoint->toward_ipa) { - u32 size_offset = offsetof(struct rmnet_map_header, - pkt_len); + u32 off; /* Field offset within header */ + /* Where IPA will write the metadata value */ + off = offsetof(struct rmnet_map_header, mux_id); + val |= u32_encode_bits(off, HDR_OFST_METADATA_FMASK); + + /* Where IPA will write the length */ + off = offsetof(struct rmnet_map_header, pkt_len); val |= HDR_OFST_PKT_SIZE_VALID_FMASK; - val |= u32_encode_bits(size_offset, - HDR_OFST_PKT_SIZE_FMASK); + val |= u32_encode_bits(off, HDR_OFST_PKT_SIZE_FMASK); } + /* For QMAP TX, metadata offset is 0 (modem assumes this) */ + val |= HDR_OFST_METADATA_VALID_FMASK; + + /* HDR_ADDITIONAL_CONST_LEN is 0; (RX only) */ /* HDR_A5_MUX is 0 */ /* HDR_LEN_INC_DEAGG_HDR is 0 */ - /* HDR_METADATA_REG_VALID is 0; (AP->IPA only) */ + /* HDR_METADATA_REG_VALID is 0 (TX only) */ } iowrite32(val, endpoint->ipa->reg_virt + offset); @@ -482,28 +509,6 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint) iowrite32(val, endpoint->ipa->reg_virt + offset); } -/** - * Generate a metadata mask value that will select only the mux_id - * field in an rmnet_map header structure. The mux_id is at offset - * 1 byte from the beginning of the structure, but the metadata - * value is treated as a 4-byte unit. So this mask must be computed - * with endianness in mind. Note that ipa_endpoint_init_hdr_metadata_mask() - * will convert this value to the proper byte order. - * - * Marked __always_inline because this is really computing a - * constant value. - */ -static __always_inline __be32 ipa_rmnet_mux_id_metadata_mask(void) -{ - size_t mux_id_offset = offsetof(struct rmnet_map_header, mux_id); - u32 mux_id_mask = 0; - u8 *bytes; - - bytes = (u8 *)&mux_id_mask; - bytes[mux_id_offset] = 0xff; /* mux_id is 1 byte */ - - return cpu_to_be32(mux_id_mask); -} static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint) { @@ -513,8 +518,9 @@ static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint) offset = IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(endpoint_id); + /* Note that HDR_ENDIANNESS indicates big endian header fields */ if (!endpoint->toward_ipa && endpoint->data->qmap) - val = ipa_rmnet_mux_id_metadata_mask(); + val = cpu_to_be32(IPA_ENDPOINT_QMAP_METADATA_MASK); iowrite32(val, endpoint->ipa->reg_virt + offset); } From patchwork Thu Jun 11 19:48:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 187824 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp1692962ilo; Thu, 11 Jun 2020 12:48:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwYK8aEjyvLJ5qyC8wj+OD5b14ACPJM46jE26eHNXdnAbNZl+kL75Siq2XjGCRV4YbeCAdm X-Received: by 2002:a05:6402:1746:: with SMTP id v6mr8581134edx.236.1591904926701; Thu, 11 Jun 2020 12:48:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591904926; cv=none; d=google.com; s=arc-20160816; b=pHIoyyT9VrV8RJOC8EO9nse8r/37KAAXIga0sq4r+Kvcul5ZrZkrBDAchao6UnZIjv 5fMtTMgChUrRbuLpf++E4hMSsop/N/vzohJRnMD3UBPjueF6jgoTD/+F+q0BuFT2sjnz Vh899oFzA7x4faeB1ioZh1YwBw9iDcGUDuh+ViuW6FefhaWjPa3pkWUQIYY2AkMY89rX //YolT/ljwlBDghDRombsCDXYEVYYSh4BYylSPfWPAavz97ENt2gWFBqYhv6DQBBFwDW GuAMLMXDjWRsbstM/UFbvHweJpneiHKdpSVkHBfGmix99l+75iUqWTpcmlUHT4FrqNdV 39+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NjH1etSnlY+P/0B3j0s0VstfhJWLswlmVgehJV9D28o=; b=RlOL7MvTqS35GMj6PyL+OK/IlYCZ8c13je1E4BhXBglLUqwE9tB1kvF3NslxIlhE1R VX7mA9k+oZZA1j+Lw9QDMCLDlQTylzG8t7Dbxayvn3MCg1xP228XJIz0YtvZ4c8ne8eB HWNpnKiOB2v51aD/tDlQ1UQP0s3CvI7zX3KIKY85zX7VZReGikjRAaV2Hf27s0xvryZQ JW9h9154ufOWcHjUx4tKPlWaiwM9q72oSGRP5Xf0l0XQyhurWftz2mhcG/dp0J3cFErD zAFrsgK/eTJzIR0OFIXgd7/X4u2JNBCQTkysUMFDObypCoia2gZDjhD+KSKVnyx8pmQy eYHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SJufooEa; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id d13sm1981397ilo.40.2020.06.11.12.48.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2020 12:48:40 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net v2 2/4] net: ipa: fix modem LAN RX endpoint id Date: Thu, 11 Jun 2020 14:48:31 -0500 Message-Id: <20200611194833.2640177-3-elder@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200611194833.2640177-1-elder@linaro.org> References: <20200611194833.2640177-1-elder@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The endpoint id assigned to the modem LAN RX endpoint for the SC7180 SoC is incorrect. The erroneous value might have been copied from SDM845 and never updated. The correct endpoint id to use for this SoC is 11. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_data-sc7180.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/drivers/net/ipa/ipa_data-sc7180.c b/drivers/net/ipa/ipa_data-sc7180.c index 43faa35ae726..d4c2bc7ad24b 100644 --- a/drivers/net/ipa/ipa_data-sc7180.c +++ b/drivers/net/ipa/ipa_data-sc7180.c @@ -106,7 +106,7 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { [IPA_ENDPOINT_MODEM_LAN_RX] = { .ee_id = GSI_EE_MODEM, .channel_id = 3, - .endpoint_id = 13, + .endpoint_id = 11, .toward_ipa = false, }, [IPA_ENDPOINT_MODEM_AP_TX] = { From patchwork Thu Jun 11 19:48:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 187826 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp1693133ilo; Thu, 11 Jun 2020 12:49:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwUDq38PgNBwJzv5GasP8xLfhLDHHdKijyrUG8k/84RRBl0aoZs90BnzYS/U6JsPFRgNuHp X-Received: by 2002:a17:906:b845:: with SMTP id ga5mr9794390ejb.300.1591904945422; Thu, 11 Jun 2020 12:49:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591904945; cv=none; d=google.com; s=arc-20160816; b=KYWMKgZMlgrZOfnTQtNMuiNt0/0uxorTdj8/nuJ1sbTV2Yammy2e1TgkLrWFQjxNsO TuwdHe/5NmA5Rlp7zQ4GEBi8j/ve3Ey6HTlK6igXFgE8uYKlrskq2UFVLK27Von32IVD 7zJkIxMfMPb/vB/3Mv4TspNuwjgxunA17dw0mw53JKO9Ywo/0cSlA1PE1G+BK+M6Ji9Z CoA2T++r15VVX1UvPwNEdluggnfIPCvS/5uZ2R3YbwWsfNdLKPKESZ6UgL+VyeqysMyP YxqRRNQxKas0MEFRuRyVuxQpkZoeKR6sarawJpjRnEvUi3v490RVOOq0UNONnCQiePxw gCJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=z6jCKhwU+IyQWEVkFQhufn/sexfHuVEEbtYUc9UiYh0=; b=I0K2UxL+37BSMChSh2Rb4evQuO3CTcXosM4vEfafO0XkBMAtK5aUcSh7xF1jd01ah2 VfylFHRmJgvID4C1EJ3aLKKCUZzvr0e2P73+LH3hQuY6JIRO84YccyGr3Q3eFWGp51G1 1yMnaX4WKY8ymU8FZx0W6btWNvUiau+KMa1iD+z5Hlesw+yVXcXdnbJfp1Tb9KT6A5rY 3G/y27SaxwUiNWuoJJAPX8sh9v8t3U0mP0WO70iEP3xDYT7YEBbnG4CcUWohFcxtVeiO H0ltsnDtGBe58KQ8zSuJNhlUV62Op7UbwjhEGgWFzdkPgVAThUNRblncTm/JTv5sm4HE Z+7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ix7sfp+3; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id d13sm1981397ilo.40.2020.06.11.12.48.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2020 12:48:42 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net v2 3/4] net: ipa: program upper nibbles of sequencer type Date: Thu, 11 Jun 2020 14:48:32 -0500 Message-Id: <20200611194833.2640177-4-elder@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200611194833.2640177-1-elder@linaro.org> References: <20200611194833.2640177-1-elder@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The upper two nibbles of the sequencer type were not used for SDM845, and were assumed to be 0. But for SC7180 they are used, and so they must be programmed by ipa_endpoint_init_seq(). Fix this bug. IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP doesn't have a descriptive comment, so add one. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_endpoint.c | 6 ++++-- drivers/net/ipa/ipa_reg.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 2825dca23ec4..bf3e8ced3ee0 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -699,10 +699,12 @@ static void ipa_endpoint_init_seq(struct ipa_endpoint *endpoint) u32 seq_type = endpoint->seq_type; u32 val = 0; + /* Sequencer type is made up of four nibbles */ val |= u32_encode_bits(seq_type & 0xf, HPS_SEQ_TYPE_FMASK); val |= u32_encode_bits((seq_type >> 4) & 0xf, DPS_SEQ_TYPE_FMASK); - /* HPS_REP_SEQ_TYPE is 0 */ - /* DPS_REP_SEQ_TYPE is 0 */ + /* The second two apply to replicated packets */ + val |= u32_encode_bits((seq_type >> 8) & 0xf, HPS_REP_SEQ_TYPE_FMASK); + val |= u32_encode_bits((seq_type >> 12) & 0xf, DPS_REP_SEQ_TYPE_FMASK); iowrite32(val, endpoint->ipa->reg_virt + offset); } diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index 3b8106aa277a..0a688d8c1d7c 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -455,6 +455,8 @@ enum ipa_mode { * second packet processing pass + no decipher + microcontroller * @IPA_SEQ_DMA_DEC: DMA + cipher/decipher * @IPA_SEQ_DMA_COMP_DECOMP: DMA + compression/decompression + * @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP: + * packet processing + no decipher + no uCP + HPS REP DMA parser * @IPA_SEQ_INVALID: invalid sequencer type * * The values defined here are broken into 4-bit nibbles that are written From patchwork Thu Jun 11 19:48:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 187825 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp1693078ilo; Thu, 11 Jun 2020 12:48:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJybX+NaiYwyWu6CFNHedD/Bt9eX9SFtreV63D68YCdXsEQNSOYNDWPoVjqu2aDPkQig5bmj X-Received: by 2002:a17:906:1d56:: with SMTP id o22mr9661051ejh.406.1591904939299; Thu, 11 Jun 2020 12:48:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591904939; cv=none; d=google.com; s=arc-20160816; b=xsHvyeTroXEGE8bvNQfNVEHFQHWZKi8JDCaPI5Jh47FAHdntCc9uXpLp0minTuuJsZ N8tKfZ0tL9bkwP8cfStnjKS1ogBCIbWh9IhPVl8PX9oPhuejtwZGRFwGxq7iOwlmYaFo 4qEswcNOe3LpyRn+niHBw/tERqlHQ9j/FxgHcNHM5QFuyOdFZZ6G7Vitk5mccOWP5uyl sLcxumP/zIgR7Y5w6uAREm60+zxxFSktEN0FhqUG30NAenMBCxxi+TW1oMtNMDvSHjgv cJiIyeIlUPIlyJuK1h46nbSFszikVjEOXVYco0d4SDZzPDQ2V2mPwMxpxzN4NaUPNJtC F2Dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3M1k+rxLR+PwfXAjQ6W5HE8fRS+A5J2ae6KqoLRPPl4=; b=i/a7eZLBIQY5FlSfShKaSoA8VRVjQVtoO3QdOIikOGmvDMHArNhTuseVJCXLXjj0vF wpyxPYqZrJYkiQD8paFUxt1v7unODGu1+0CpkMXboAY39MY/HOyd6ZgEj2ywSjXusl7/ uJCPlxIVMuebXo4pjUKIXGgoHw9zMYnClMHD6VOBGawZUhNM9b/DM3Ftmit+NVq/3M3U E4fjIYfojZF9y3/qSJT/Mkeb0Dat50oZtDQsxYMuXwjBBnaBp96E3dGmkj/XVa8YBOnt YNKozY3TeFaJCmgWpimPpQLNU1eZdtLxr7Ci4V4FzoxiIO4JjMXBEJOF+CQGHlRYUBOM DV1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OFFmH6uo; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id d13sm1981397ilo.40.2020.06.11.12.48.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2020 12:48:43 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net v2 4/4] net: ipa: header pad field only valid for AP->modem endpoint Date: Thu, 11 Jun 2020 14:48:33 -0500 Message-Id: <20200611194833.2640177-5-elder@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200611194833.2640177-1-elder@linaro.org> References: <20200611194833.2640177-1-elder@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Only QMAP endpoints should be configured to find a pad size field within packet headers. They are found in the first byte of the QMAP header (and the hardware fills only the 6 bits in that byte that constitute the pad_len field). The RMNet driver assumes the pad_len field is valid for received packets, so we want to ensure the pad_len field is filled in that case. That driver also assumes the length in the QMAP header includes the pad bytes. The RMNet driver does *not* pad the packets it sends, so the pad_len field can be ignored. Fix ipa_endpoint_init_hdr_ext() so it only marks the pad field offset valid for QMAP RX endpoints, and in that case indicates that the length field in the header includes the pad bytes. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_endpoint.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index bf3e8ced3ee0..9f50d0d11704 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -467,7 +467,7 @@ static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint) header_size += sizeof(struct rmnet_map_ul_csum_header); val |= u32_encode_bits(header_size, HDR_LEN_FMASK); - /* Define how to fill mux_id in a received QMAP header */ + /* Define how to fill fields in a received QMAP header */ if (!endpoint->toward_ipa) { u32 off; /* Field offset within header */ @@ -499,10 +499,21 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint) u32 val = 0; val |= HDR_ENDIANNESS_FMASK; /* big endian */ - val |= HDR_TOTAL_LEN_OR_PAD_VALID_FMASK; - /* HDR_TOTAL_LEN_OR_PAD is 0 (pad, not total_len) */ + + /* A QMAP header contains a 6 bit pad field at offset 0. The RMNet + * driver assumes this field is meaningful in packets it receives, + * and assumes the header's payload length includes that padding. + * The RMNet driver does *not* pad packets it sends, however, so + * the pad field (although 0) should be ignored. + */ + if (endpoint->data->qmap && !endpoint->toward_ipa) { + val |= HDR_TOTAL_LEN_OR_PAD_VALID_FMASK; + /* HDR_TOTAL_LEN_OR_PAD is 0 (pad, not total_len) */ + val |= HDR_PAYLOAD_LEN_INC_PADDING_FMASK; + /* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0 */ + } + /* HDR_PAYLOAD_LEN_INC_PADDING is 0 */ - /* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0 */ if (!endpoint->toward_ipa) val |= u32_encode_bits(pad_align, HDR_PAD_TO_ALIGNMENT_FMASK);